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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3254 | Serge | 1 | //#include "../bitmap.h" |
| 2 | |||
| 3 | #include |
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| 4 | #include |
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| 5 | |||
| 6 | #include "sna.h" |
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| 7 | |||
| 3263 | Serge | 8 | #include |
| 9 | |||
| 10 | static struct sna_fb sna_fb; |
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| 11 | |||
| 3258 | Serge | 12 | typedef struct __attribute__((packed)) |
| 13 | { |
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| 14 | unsigned handle; |
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| 15 | unsigned io_code; |
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| 16 | void *input; |
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| 17 | int inp_size; |
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| 18 | void *output; |
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| 19 | int out_size; |
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| 20 | }ioctl_t; |
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| 3254 | Serge | 21 | |
| 3258 | Serge | 22 | |
| 23 | static int call_service(ioctl_t *io) |
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| 24 | { |
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| 25 | int retval; |
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| 26 | |||
| 27 | asm volatile("int $0x40" |
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| 28 | :"=a"(retval) |
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| 29 | :"a"(68),"b"(17),"c"(io) |
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| 30 | :"memory","cc"); |
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| 31 | |||
| 32 | return retval; |
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| 33 | }; |
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| 34 | |||
| 3266 | Serge | 35 | static inline void get_proc_info(char *info) |
| 36 | { |
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| 37 | __asm__ __volatile__( |
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| 38 | "int $0x40" |
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| 39 | : |
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| 40 | :"a"(9), "b"(info), "c"(-1)); |
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| 41 | } |
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| 42 | |||
| 3254 | Serge | 43 | const struct intel_device_info * |
| 44 | intel_detect_chipset(struct pci_device *pci); |
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| 45 | |||
| 46 | //struct kgem_bo *create_bo(bitmap_t *bitmap); |
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| 47 | |||
| 48 | static bool sna_solid_cache_init(struct sna *sna); |
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| 49 | |||
| 50 | struct sna *sna_device; |
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| 51 | |||
| 3258 | Serge | 52 | static void no_render_reset(struct sna *sna) |
| 53 | { |
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| 54 | (void)sna; |
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| 55 | } |
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| 56 | |||
| 3254 | Serge | 57 | void no_render_init(struct sna *sna) |
| 58 | { |
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| 59 | struct sna_render *render = &sna->render; |
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| 60 | |||
| 61 | memset (render,0, sizeof (*render)); |
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| 62 | |||
| 63 | render->prefer_gpu = PREFER_GPU_BLT; |
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| 64 | |||
| 65 | render->vertices = render->vertex_data; |
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| 66 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
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| 67 | |||
| 68 | // render->composite = no_render_composite; |
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| 69 | |||
| 70 | // render->copy_boxes = no_render_copy_boxes; |
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| 71 | // render->copy = no_render_copy; |
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| 72 | |||
| 73 | // render->fill_boxes = no_render_fill_boxes; |
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| 74 | // render->fill = no_render_fill; |
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| 75 | // render->fill_one = no_render_fill_one; |
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| 76 | // render->clear = no_render_clear; |
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| 77 | |||
| 3258 | Serge | 78 | render->reset = no_render_reset; |
| 3263 | Serge | 79 | // render->flush = no_render_flush; |
| 3254 | Serge | 80 | // render->fini = no_render_fini; |
| 81 | |||
| 82 | // sna->kgem.context_switch = no_render_context_switch; |
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| 83 | // sna->kgem.retire = no_render_retire; |
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| 84 | |||
| 3258 | Serge | 85 | if (sna->kgem.gen >= 60) |
| 3254 | Serge | 86 | sna->kgem.ring = KGEM_RENDER; |
| 87 | |||
| 88 | sna_vertex_init(sna); |
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| 89 | } |
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| 90 | |||
| 91 | void sna_vertex_init(struct sna *sna) |
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| 92 | { |
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| 93 | // pthread_mutex_init(&sna->render.lock, NULL); |
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| 94 | // pthread_cond_init(&sna->render.wait, NULL); |
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| 95 | sna->render.active = 0; |
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| 96 | } |
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| 97 | |||
| 98 | bool sna_accel_init(struct sna *sna) |
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| 99 | { |
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| 100 | const char *backend; |
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| 101 | |||
| 102 | // list_init(&sna->deferred_free); |
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| 103 | // list_init(&sna->dirty_pixmaps); |
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| 104 | // list_init(&sna->active_pixmaps); |
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| 105 | // list_init(&sna->inactive_clock[0]); |
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| 106 | // list_init(&sna->inactive_clock[1]); |
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| 107 | |||
| 108 | // sna_accel_install_timers(sna); |
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| 109 | |||
| 110 | |||
| 111 | backend = "no"; |
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| 112 | no_render_init(sna); |
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| 113 | |||
| 114 | if (sna->info->gen >= 0100) { |
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| 115 | /* } else if (sna->info->gen >= 070) { |
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| 116 | if (gen7_render_init(sna)) |
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| 117 | backend = "IvyBridge"; */ |
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| 118 | } else if (sna->info->gen >= 060) { |
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| 119 | if (gen6_render_init(sna)) |
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| 120 | backend = "SandyBridge"; |
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| 121 | /* } else if (sna->info->gen >= 050) { |
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| 122 | if (gen5_render_init(sna)) |
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| 123 | backend = "Ironlake"; |
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| 124 | } else if (sna->info->gen >= 040) { |
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| 125 | if (gen4_render_init(sna)) |
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| 126 | backend = "Broadwater/Crestline"; |
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| 127 | } else if (sna->info->gen >= 030) { |
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| 128 | if (gen3_render_init(sna)) |
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| 129 | backend = "gen3"; |
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| 130 | } else if (sna->info->gen >= 020) { |
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| 131 | if (gen2_render_init(sna)) |
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| 132 | backend = "gen2"; */ |
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| 133 | } |
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| 134 | |||
| 135 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
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| 136 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
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| 137 | |||
| 138 | kgem_reset(&sna->kgem); |
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| 139 | |||
| 140 | // if (!sna_solid_cache_init(sna)) |
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| 141 | // return false; |
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| 142 | |||
| 143 | sna_device = sna; |
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| 144 | |||
| 145 | |||
| 3263 | Serge | 146 | return kgem_init_fb(&sna->kgem, &sna_fb); |
| 3254 | Serge | 147 | } |
| 148 | |||
| 149 | int sna_init(uint32_t service) |
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| 150 | { |
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| 151 | ioctl_t io; |
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| 152 | |||
| 153 | static struct pci_device device; |
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| 154 | struct sna *sna; |
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| 155 | |||
| 156 | DBG(("%s\n", __FUNCTION__)); |
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| 157 | |||
| 158 | sna = malloc(sizeof(struct sna)); |
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| 159 | if (sna == NULL) |
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| 160 | return false; |
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| 161 | |||
| 162 | io.handle = service; |
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| 3256 | Serge | 163 | io.io_code = SRV_GET_PCI_INFO; |
| 3254 | Serge | 164 | io.input = &device; |
| 165 | io.inp_size = sizeof(device); |
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| 166 | io.output = NULL; |
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| 167 | io.out_size = 0; |
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| 168 | |||
| 169 | if (call_service(&io)!=0) |
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| 170 | return false; |
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| 171 | |||
| 172 | sna->PciInfo = &device; |
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| 173 | |||
| 174 | sna->info = intel_detect_chipset(sna->PciInfo); |
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| 175 | |||
| 176 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
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| 177 | /* |
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| 178 | if (!xf86ReturnOptValBool(sna->Options, |
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| 179 | OPTION_RELAXED_FENCING, |
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| 180 | sna->kgem.has_relaxed_fencing)) { |
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| 181 | xf86DrvMsg(scrn->scrnIndex, |
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| 182 | sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
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| 183 | "Disabling use of relaxed fencing\n"); |
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| 184 | sna->kgem.has_relaxed_fencing = 0; |
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| 185 | } |
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| 186 | if (!xf86ReturnOptValBool(sna->Options, |
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| 187 | OPTION_VMAP, |
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| 188 | sna->kgem.has_vmap)) { |
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| 189 | xf86DrvMsg(scrn->scrnIndex, |
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| 190 | sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
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| 191 | "Disabling use of vmap\n"); |
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| 192 | sna->kgem.has_vmap = 0; |
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| 193 | } |
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| 194 | */ |
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| 195 | |||
| 196 | /* Disable tiling by default */ |
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| 197 | sna->tiling = SNA_TILING_DISABLE; |
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| 198 | |||
| 199 | /* Default fail-safe value of 75 Hz */ |
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| 200 | // sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
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| 201 | |||
| 202 | sna->flags = 0; |
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| 203 | |||
| 204 | return sna_accel_init(sna); |
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| 205 | } |
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| 206 | |||
| 207 | #if 0 |
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| 208 | |||
| 209 | static bool sna_solid_cache_init(struct sna *sna) |
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| 210 | { |
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| 211 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 212 | |||
| 213 | DBG(("%s\n", __FUNCTION__)); |
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| 214 | |||
| 215 | cache->cache_bo = |
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| 216 | kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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| 217 | if (!cache->cache_bo) |
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| 218 | return FALSE; |
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| 219 | |||
| 220 | /* |
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| 221 | * Initialise [0] with white since it is very common and filling the |
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| 222 | * zeroth slot simplifies some of the checks. |
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| 223 | */ |
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| 224 | cache->color[0] = 0xffffffff; |
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| 225 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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| 226 | cache->bo[0]->pitch = 4; |
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| 227 | cache->dirty = 1; |
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| 228 | cache->size = 1; |
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| 229 | cache->last = 0; |
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| 230 | |||
| 231 | return TRUE; |
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| 232 | } |
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| 233 | |||
| 234 | void |
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| 235 | sna_render_flush_solid(struct sna *sna) |
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| 236 | { |
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| 237 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 238 | |||
| 239 | DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
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| 240 | assert(cache->dirty); |
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| 241 | assert(cache->size); |
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| 242 | |||
| 243 | kgem_bo_write(&sna->kgem, cache->cache_bo, |
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| 244 | cache->color, cache->size*sizeof(uint32_t)); |
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| 245 | cache->dirty = 0; |
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| 246 | cache->last = 0; |
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| 247 | } |
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| 248 | |||
| 249 | static void |
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| 250 | sna_render_finish_solid(struct sna *sna, bool force) |
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| 251 | { |
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| 252 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 253 | int i; |
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| 254 | |||
| 255 | DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
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| 256 | force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
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| 257 | |||
| 258 | if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
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| 259 | return; |
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| 260 | |||
| 261 | if (cache->dirty) |
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| 262 | sna_render_flush_solid(sna); |
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| 263 | |||
| 264 | for (i = 0; i < cache->size; i++) { |
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| 265 | if (cache->bo[i] == NULL) |
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| 266 | continue; |
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| 267 | |||
| 268 | kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
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| 269 | cache->bo[i] = NULL; |
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| 270 | } |
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| 271 | kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
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| 272 | |||
| 273 | DBG(("sna_render_finish_solid reset\n")); |
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| 274 | |||
| 275 | cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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| 276 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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| 277 | cache->bo[0]->pitch = 4; |
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| 278 | if (force) |
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| 279 | cache->size = 1; |
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| 280 | } |
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| 281 | |||
| 282 | |||
| 283 | struct kgem_bo * |
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| 284 | sna_render_get_solid(struct sna *sna, uint32_t color) |
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| 285 | { |
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| 286 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 287 | int i; |
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| 288 | |||
| 289 | DBG(("%s: %08x\n", __FUNCTION__, color)); |
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| 290 | |||
| 291 | // if ((color & 0xffffff) == 0) /* alpha only */ |
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| 292 | // return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
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| 293 | |||
| 294 | if (color == 0xffffffff) { |
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| 295 | DBG(("%s(white)\n", __FUNCTION__)); |
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| 296 | return kgem_bo_reference(cache->bo[0]); |
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| 297 | } |
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| 298 | |||
| 299 | if (cache->color[cache->last] == color) { |
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| 300 | DBG(("sna_render_get_solid(%d) = %x (last)\n", |
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| 301 | cache->last, color)); |
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| 302 | return kgem_bo_reference(cache->bo[cache->last]); |
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| 303 | } |
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| 304 | |||
| 305 | for (i = 1; i < cache->size; i++) { |
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| 306 | if (cache->color[i] == color) { |
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| 307 | if (cache->bo[i] == NULL) { |
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| 308 | DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
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| 309 | i, color)); |
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| 310 | goto create; |
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| 311 | } else { |
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| 312 | DBG(("sna_render_get_solid(%d) = %x (old)\n", |
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| 313 | i, color)); |
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| 314 | goto done; |
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| 315 | } |
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| 316 | } |
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| 317 | } |
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| 318 | |||
| 319 | sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
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| 320 | |||
| 321 | i = cache->size++; |
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| 322 | cache->color[i] = color; |
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| 323 | cache->dirty = 1; |
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| 324 | DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
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| 325 | |||
| 326 | create: |
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| 327 | cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
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| 328 | i*sizeof(uint32_t), sizeof(uint32_t)); |
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| 329 | cache->bo[i]->pitch = 4; |
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| 330 | |||
| 331 | done: |
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| 332 | cache->last = i; |
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| 333 | return kgem_bo_reference(cache->bo[i]); |
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| 334 | } |
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| 335 | |||
| 336 | #endif |
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| 337 | |||
| 338 | |||
| 3263 | Serge | 339 | int sna_blit_copy(bitmap_t *src_bitmap, int dst_x, int dst_y, |
| 340 | int w, int h, int src_x, int src_y) |
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| 3254 | Serge | 341 | |
| 342 | { |
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| 343 | struct sna_copy_op copy; |
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| 3263 | Serge | 344 | struct _Pixmap src, dst; |
| 345 | struct kgem_bo *src_bo; |
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| 3254 | Serge | 346 | |
| 3266 | Serge | 347 | char proc_info[1024]; |
| 348 | int winx, winy; |
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| 349 | |||
| 350 | get_proc_info(proc_info); |
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| 351 | |||
| 352 | winx = *(uint32_t*)(proc_info+34); |
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| 353 | winy = *(uint32_t*)(proc_info+38); |
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| 354 | |||
| 3263 | Serge | 355 | memset(&src, 0, sizeof(src)); |
| 356 | memset(&dst, 0, sizeof(dst)); |
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| 3254 | Serge | 357 | |
| 3263 | Serge | 358 | src.drawable.bitsPerPixel = 32; |
| 359 | src.drawable.width = src_bitmap->width; |
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| 360 | src.drawable.height = src_bitmap->height; |
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| 3254 | Serge | 361 | |
| 3263 | Serge | 362 | dst.drawable.bitsPerPixel = 32; |
| 363 | dst.drawable.width = sna_fb.width; |
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| 364 | dst.drawable.height = sna_fb.height; |
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| 3254 | Serge | 365 | |
| 366 | memset(©, 0, sizeof(copy)); |
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| 367 | |||
| 3263 | Serge | 368 | src_bo = (struct kgem_bo*)src_bitmap->handle; |
| 369 | |||
| 370 | if( sna_device->render.copy(sna_device, GXcopy, |
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| 371 | &src, src_bo, |
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| 372 | &dst, sna_fb.fb_bo, ©) ) |
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| 373 | { |
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| 3266 | Serge | 374 | copy.blt(sna_device, ©, src_x, src_y, w, h, winx+dst_x, winy+dst_y); |
| 3254 | Serge | 375 | copy.done(sna_device, ©); |
| 3263 | Serge | 376 | } |
| 3254 | Serge | 377 | |
| 3263 | Serge | 378 | kgem_submit(&sna_device->kgem); |
| 3254 | Serge | 379 | |
| 3263 | Serge | 380 | // __asm__ __volatile__("int3"); |
| 3254 | Serge | 381 | |
| 382 | }; |
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| 383 | |||
| 3263 | Serge | 384 | int sna_create_bitmap(bitmap_t *bitmap) |
| 385 | { |
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| 386 | struct kgem_bo *bo; |
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| 3254 | Serge | 387 | |
| 3263 | Serge | 388 | bo = kgem_create_2d(&sna_device->kgem, bitmap->width, bitmap->height, |
| 389 | 32,I915_TILING_NONE, CREATE_CPU_MAP); |
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| 390 | |||
| 391 | if(bo == NULL) |
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| 392 | goto err_1; |
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| 393 | |||
| 394 | void *map = kgem_bo_map(&sna_device->kgem, bo); |
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| 395 | if(map == NULL) |
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| 396 | goto err_2; |
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| 397 | |||
| 398 | bitmap->handle = (uint32_t)bo; |
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| 399 | bitmap->pitch = bo->pitch; |
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| 400 | bitmap->data = map; |
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| 401 | |||
| 402 | return 0; |
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| 403 | |||
| 404 | err_2: |
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| 405 | kgem_bo_destroy(&sna_device->kgem, bo); |
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| 406 | |||
| 407 | err_1: |
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| 408 | return -1; |
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| 3266 | Serge | 409 | |
| 3263 | Serge | 410 | }; |
| 3266 | Serge | 411 | |
| 412 | void sna_lock_bitmap(bitmap_t *bitmap) |
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| 413 | { |
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| 414 | struct kgem_bo *bo; |
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| 415 | |||
| 416 | bo = (struct kgem_bo *)bitmap->handle; |
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| 417 | |||
| 418 | kgem_bo_sync__cpu(&sna_device->kgem, bo); |
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| 419 | |||
| 420 | }; |
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| 421 | |||
| 422 | |||
| 423 | |||
| 3254 | Serge | 424 | /* |
| 425 | |||
| 426 | int sna_blit_tex(bitmap_t *dst_bitmap, int dst_x, int dst_y, |
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| 427 | int w, int h, bitmap_t *src_bitmap, int src_x, int src_y, |
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| 428 | bitmap_t *mask_bitmap) |
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| 429 | |||
| 430 | { |
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| 431 | struct sna_composite_op cop; |
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| 432 | batchbuffer_t execbuffer; |
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| 433 | BoxRec box; |
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| 434 | |||
| 435 | struct kgem_bo src_bo, mask_bo, dst_bo; |
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| 436 | |||
| 437 | memset(&cop, 0, sizeof(cop)); |
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| 438 | memset(&execbuffer, 0, sizeof(execbuffer)); |
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| 439 | memset(&src_bo, 0, sizeof(src_bo)); |
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| 440 | memset(&dst_bo, 0, sizeof(dst_bo)); |
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| 441 | memset(&mask_bo, 0, sizeof(mask_bo)); |
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| 442 | |||
| 443 | src_bo.gaddr = src_bitmap->gaddr; |
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| 444 | src_bo.pitch = src_bitmap->pitch; |
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| 445 | src_bo.tiling = 0; |
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| 446 | |||
| 447 | dst_bo.gaddr = dst_bitmap->gaddr; |
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| 448 | dst_bo.pitch = dst_bitmap->pitch; |
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| 449 | dst_bo.tiling = 0; |
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| 450 | |||
| 451 | mask_bo.gaddr = mask_bitmap->gaddr; |
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| 452 | mask_bo.pitch = mask_bitmap->pitch; |
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| 453 | mask_bo.tiling = 0; |
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| 454 | |||
| 455 | box.x1 = dst_x; |
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| 456 | box.y1 = dst_y; |
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| 457 | box.x2 = dst_x+w; |
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| 458 | box.y2 = dst_y+h; |
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| 459 | |||
| 460 | sna_device->render.composite(sna_device, 0, |
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| 461 | src_bitmap, &src_bo, |
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| 462 | mask_bitmap, &mask_bo, |
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| 463 | dst_bitmap, &dst_bo, |
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| 464 | src_x, src_y, |
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| 465 | src_x, src_y, |
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| 466 | dst_x, dst_y, |
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| 467 | w, h, &cop); |
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| 468 | |||
| 469 | cop.box(sna_device, &cop, &box); |
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| 470 | cop.done(sna_device, &cop); |
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| 471 | |||
| 472 | INIT_LIST_HEAD(&execbuffer.objects); |
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| 473 | list_add_tail(&src_bitmap->obj->exec_list, &execbuffer.objects); |
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| 474 | list_add_tail(&mask_bitmap->obj->exec_list, &execbuffer.objects); |
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| 475 | |||
| 476 | _kgem_submit(&sna_device->kgem, &execbuffer); |
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| 477 | |||
| 478 | }; |
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| 479 | |||
| 480 | */ |
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| 481 | |||
| 482 | static const struct intel_device_info intel_generic_info = { |
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| 483 | .gen = -1, |
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| 484 | }; |
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| 485 | |||
| 486 | static const struct intel_device_info intel_i915_info = { |
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| 487 | .gen = 030, |
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| 488 | }; |
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| 489 | static const struct intel_device_info intel_i945_info = { |
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| 490 | .gen = 031, |
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| 491 | }; |
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| 492 | |||
| 493 | static const struct intel_device_info intel_g33_info = { |
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| 494 | .gen = 033, |
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| 495 | }; |
||
| 496 | |||
| 497 | static const struct intel_device_info intel_i965_info = { |
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| 498 | .gen = 040, |
||
| 499 | }; |
||
| 500 | |||
| 501 | static const struct intel_device_info intel_g4x_info = { |
||
| 502 | .gen = 045, |
||
| 503 | }; |
||
| 504 | |||
| 505 | static const struct intel_device_info intel_ironlake_info = { |
||
| 506 | .gen = 050, |
||
| 507 | }; |
||
| 508 | |||
| 509 | static const struct intel_device_info intel_sandybridge_info = { |
||
| 510 | .gen = 060, |
||
| 511 | }; |
||
| 512 | |||
| 513 | static const struct intel_device_info intel_ivybridge_info = { |
||
| 514 | .gen = 070, |
||
| 515 | }; |
||
| 516 | |||
| 517 | static const struct intel_device_info intel_valleyview_info = { |
||
| 518 | .gen = 071, |
||
| 519 | }; |
||
| 520 | |||
| 521 | static const struct intel_device_info intel_haswell_info = { |
||
| 522 | .gen = 075, |
||
| 523 | }; |
||
| 524 | |||
| 525 | #define INTEL_DEVICE_MATCH(d,i) \ |
||
| 526 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
||
| 527 | |||
| 528 | |||
| 529 | static const struct pci_id_match intel_device_match[] = { |
||
| 530 | |||
| 531 | |||
| 532 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), |
||
| 533 | INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), |
||
| 534 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), |
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| 535 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ), |
||
| 536 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ), |
||
| 537 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ), |
||
| 538 | |||
| 539 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), |
||
| 540 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), |
||
| 541 | INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), |
||
| 542 | INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), |
||
| 543 | /* Another marketing win: Q35 is another g33 device not a gen4 part |
||
| 544 | * like its G35 brethren. |
||
| 545 | */ |
||
| 546 | INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), |
||
| 547 | |||
| 548 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), |
||
| 549 | INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), |
||
| 550 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), |
||
| 551 | INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), |
||
| 552 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), |
||
| 553 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), |
||
| 554 | |||
| 555 | INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), |
||
| 556 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), |
||
| 557 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), |
||
| 558 | INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), |
||
| 559 | INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), |
||
| 560 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), |
||
| 561 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), |
||
| 562 | |||
| 563 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), |
||
| 564 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), |
||
| 565 | |||
| 566 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), |
||
| 567 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), |
||
| 568 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), |
||
| 569 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), |
||
| 570 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), |
||
| 571 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), |
||
| 572 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), |
||
| 573 | |||
| 574 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), |
||
| 575 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), |
||
| 576 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), |
||
| 577 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), |
||
| 578 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), |
||
| 579 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), |
||
| 580 | |||
| 581 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), |
||
| 582 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), |
||
| 583 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), |
||
| 584 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), |
||
| 585 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), |
||
| 586 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), |
||
| 587 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), |
||
| 588 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), |
||
| 589 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), |
||
| 590 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), |
||
| 591 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), |
||
| 592 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), |
||
| 593 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), |
||
| 594 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), |
||
| 595 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), |
||
| 596 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), |
||
| 597 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), |
||
| 598 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), |
||
| 599 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), |
||
| 600 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), |
||
| 601 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), |
||
| 602 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), |
||
| 603 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), |
||
| 604 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), |
||
| 605 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), |
||
| 606 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), |
||
| 607 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), |
||
| 608 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), |
||
| 609 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), |
||
| 610 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), |
||
| 611 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), |
||
| 612 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), |
||
| 613 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), |
||
| 614 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), |
||
| 615 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), |
||
| 616 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), |
||
| 617 | |||
| 618 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), |
||
| 619 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |
||
| 620 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), |
||
| 621 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), |
||
| 622 | |||
| 623 | INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), |
||
| 624 | |||
| 625 | { 0, 0, 0 }, |
||
| 626 | }; |
||
| 627 | |||
| 628 | const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
||
| 629 | { |
||
| 630 | while(list->device_id) |
||
| 631 | { |
||
| 632 | if(dev==list->device_id) |
||
| 633 | return list; |
||
| 634 | list++; |
||
| 635 | } |
||
| 636 | return NULL; |
||
| 637 | } |
||
| 638 | |||
| 639 | const struct intel_device_info * |
||
| 640 | intel_detect_chipset(struct pci_device *pci) |
||
| 641 | { |
||
| 642 | const struct pci_id_match *ent = NULL; |
||
| 643 | const char *name = NULL; |
||
| 644 | int i; |
||
| 645 | |||
| 646 | ent = PciDevMatch(pci->device_id, intel_device_match); |
||
| 647 | |||
| 648 | if(ent != NULL) |
||
| 649 | return (const struct intel_device_info*)ent->match_data; |
||
| 650 | else |
||
| 651 | return &intel_generic_info; |
||
| 652 | |||
| 653 | #if 0 |
||
| 654 | for (i = 0; intel_chipsets[i].name != NULL; i++) { |
||
| 655 | if (DEVICE_ID(pci) == intel_chipsets[i].token) { |
||
| 656 | name = intel_chipsets[i].name; |
||
| 657 | break; |
||
| 658 | } |
||
| 659 | } |
||
| 660 | if (name == NULL) { |
||
| 661 | xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); |
||
| 662 | name = "unknown"; |
||
| 663 | } else { |
||
| 664 | xf86DrvMsg(scrn->scrnIndex, from, |
||
| 665 | "Integrated Graphics Chipset: Intel(R) %s\n", |
||
| 666 | name); |
||
| 667 | } |
||
| 668 | |||
| 669 | scrn->chipset = name; |
||
| 670 | #endif |
||
| 671 | |||
| 672 | } |
||
| 673 | |||
| 674 | |||
| 3258 | Serge | 675 | int drmIoctl(int fd, unsigned long request, void *arg) |
| 676 | { |
||
| 677 | ioctl_t io; |
||
| 3254 | Serge | 678 | |
| 3258 | Serge | 679 | io.handle = fd; |
| 680 | io.io_code = request; |
||
| 681 | io.input = arg; |
||
| 682 | io.inp_size = 64; |
||
| 683 | io.output = NULL; |
||
| 684 | io.out_size = 0; |
||
| 3254 | Serge | 685 | |
| 3258 | Serge | 686 | return call_service(&io); |
| 687 | } |
||
| 688 |