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Rev | Author | Line No. | Line |
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3254 | Serge | 1 | //#include "../bitmap.h" |
2 | |||
3 | #include |
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4 | #include |
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5 | |||
6 | #include "sna.h" |
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7 | |||
3263 | Serge | 8 | #include |
9 | |||
10 | static struct sna_fb sna_fb; |
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11 | |||
3258 | Serge | 12 | typedef struct __attribute__((packed)) |
13 | { |
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14 | unsigned handle; |
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15 | unsigned io_code; |
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16 | void *input; |
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17 | int inp_size; |
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18 | void *output; |
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19 | int out_size; |
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20 | }ioctl_t; |
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3254 | Serge | 21 | |
3258 | Serge | 22 | |
23 | static int call_service(ioctl_t *io) |
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24 | { |
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25 | int retval; |
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26 | |||
27 | asm volatile("int $0x40" |
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28 | :"=a"(retval) |
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29 | :"a"(68),"b"(17),"c"(io) |
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30 | :"memory","cc"); |
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31 | |||
32 | return retval; |
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33 | }; |
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34 | |||
3254 | Serge | 35 | const struct intel_device_info * |
36 | intel_detect_chipset(struct pci_device *pci); |
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37 | |||
38 | //struct kgem_bo *create_bo(bitmap_t *bitmap); |
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39 | |||
40 | static bool sna_solid_cache_init(struct sna *sna); |
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41 | |||
42 | struct sna *sna_device; |
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43 | |||
3258 | Serge | 44 | static void no_render_reset(struct sna *sna) |
45 | { |
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46 | (void)sna; |
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47 | } |
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48 | |||
3254 | Serge | 49 | void no_render_init(struct sna *sna) |
50 | { |
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51 | struct sna_render *render = &sna->render; |
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52 | |||
53 | memset (render,0, sizeof (*render)); |
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54 | |||
55 | render->prefer_gpu = PREFER_GPU_BLT; |
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56 | |||
57 | render->vertices = render->vertex_data; |
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58 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
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59 | |||
60 | // render->composite = no_render_composite; |
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61 | |||
62 | // render->copy_boxes = no_render_copy_boxes; |
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63 | // render->copy = no_render_copy; |
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64 | |||
65 | // render->fill_boxes = no_render_fill_boxes; |
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66 | // render->fill = no_render_fill; |
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67 | // render->fill_one = no_render_fill_one; |
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68 | // render->clear = no_render_clear; |
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69 | |||
3258 | Serge | 70 | render->reset = no_render_reset; |
3263 | Serge | 71 | // render->flush = no_render_flush; |
3254 | Serge | 72 | // render->fini = no_render_fini; |
73 | |||
74 | // sna->kgem.context_switch = no_render_context_switch; |
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75 | // sna->kgem.retire = no_render_retire; |
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76 | |||
3258 | Serge | 77 | if (sna->kgem.gen >= 60) |
3254 | Serge | 78 | sna->kgem.ring = KGEM_RENDER; |
79 | |||
80 | sna_vertex_init(sna); |
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81 | } |
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82 | |||
83 | void sna_vertex_init(struct sna *sna) |
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84 | { |
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85 | // pthread_mutex_init(&sna->render.lock, NULL); |
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86 | // pthread_cond_init(&sna->render.wait, NULL); |
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87 | sna->render.active = 0; |
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88 | } |
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89 | |||
90 | bool sna_accel_init(struct sna *sna) |
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91 | { |
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92 | const char *backend; |
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93 | |||
94 | // list_init(&sna->deferred_free); |
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95 | // list_init(&sna->dirty_pixmaps); |
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96 | // list_init(&sna->active_pixmaps); |
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97 | // list_init(&sna->inactive_clock[0]); |
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98 | // list_init(&sna->inactive_clock[1]); |
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99 | |||
100 | // sna_accel_install_timers(sna); |
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101 | |||
102 | |||
103 | backend = "no"; |
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104 | no_render_init(sna); |
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105 | |||
106 | if (sna->info->gen >= 0100) { |
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107 | /* } else if (sna->info->gen >= 070) { |
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108 | if (gen7_render_init(sna)) |
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109 | backend = "IvyBridge"; */ |
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110 | } else if (sna->info->gen >= 060) { |
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111 | if (gen6_render_init(sna)) |
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112 | backend = "SandyBridge"; |
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113 | /* } else if (sna->info->gen >= 050) { |
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114 | if (gen5_render_init(sna)) |
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115 | backend = "Ironlake"; |
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116 | } else if (sna->info->gen >= 040) { |
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117 | if (gen4_render_init(sna)) |
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118 | backend = "Broadwater/Crestline"; |
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119 | } else if (sna->info->gen >= 030) { |
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120 | if (gen3_render_init(sna)) |
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121 | backend = "gen3"; |
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122 | } else if (sna->info->gen >= 020) { |
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123 | if (gen2_render_init(sna)) |
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124 | backend = "gen2"; */ |
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125 | } |
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126 | |||
127 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
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128 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
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129 | |||
130 | kgem_reset(&sna->kgem); |
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131 | |||
132 | // if (!sna_solid_cache_init(sna)) |
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133 | // return false; |
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134 | |||
135 | sna_device = sna; |
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136 | |||
137 | |||
3263 | Serge | 138 | return kgem_init_fb(&sna->kgem, &sna_fb); |
3254 | Serge | 139 | } |
140 | |||
141 | int sna_init(uint32_t service) |
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142 | { |
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143 | ioctl_t io; |
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144 | |||
145 | static struct pci_device device; |
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146 | struct sna *sna; |
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147 | |||
148 | DBG(("%s\n", __FUNCTION__)); |
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149 | |||
150 | sna = malloc(sizeof(struct sna)); |
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151 | if (sna == NULL) |
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152 | return false; |
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153 | |||
154 | io.handle = service; |
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3256 | Serge | 155 | io.io_code = SRV_GET_PCI_INFO; |
3254 | Serge | 156 | io.input = &device; |
157 | io.inp_size = sizeof(device); |
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158 | io.output = NULL; |
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159 | io.out_size = 0; |
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160 | |||
161 | if (call_service(&io)!=0) |
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162 | return false; |
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163 | |||
164 | sna->PciInfo = &device; |
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165 | |||
166 | sna->info = intel_detect_chipset(sna->PciInfo); |
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167 | |||
168 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
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169 | /* |
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170 | if (!xf86ReturnOptValBool(sna->Options, |
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171 | OPTION_RELAXED_FENCING, |
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172 | sna->kgem.has_relaxed_fencing)) { |
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173 | xf86DrvMsg(scrn->scrnIndex, |
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174 | sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
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175 | "Disabling use of relaxed fencing\n"); |
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176 | sna->kgem.has_relaxed_fencing = 0; |
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177 | } |
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178 | if (!xf86ReturnOptValBool(sna->Options, |
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179 | OPTION_VMAP, |
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180 | sna->kgem.has_vmap)) { |
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181 | xf86DrvMsg(scrn->scrnIndex, |
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182 | sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
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183 | "Disabling use of vmap\n"); |
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184 | sna->kgem.has_vmap = 0; |
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185 | } |
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186 | */ |
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187 | |||
188 | /* Disable tiling by default */ |
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189 | sna->tiling = SNA_TILING_DISABLE; |
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190 | |||
191 | /* Default fail-safe value of 75 Hz */ |
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192 | // sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
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193 | |||
194 | sna->flags = 0; |
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195 | |||
196 | return sna_accel_init(sna); |
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197 | } |
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198 | |||
199 | #if 0 |
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200 | |||
201 | static bool sna_solid_cache_init(struct sna *sna) |
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202 | { |
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203 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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204 | |||
205 | DBG(("%s\n", __FUNCTION__)); |
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206 | |||
207 | cache->cache_bo = |
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208 | kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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209 | if (!cache->cache_bo) |
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210 | return FALSE; |
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211 | |||
212 | /* |
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213 | * Initialise [0] with white since it is very common and filling the |
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214 | * zeroth slot simplifies some of the checks. |
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215 | */ |
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216 | cache->color[0] = 0xffffffff; |
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217 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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218 | cache->bo[0]->pitch = 4; |
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219 | cache->dirty = 1; |
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220 | cache->size = 1; |
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221 | cache->last = 0; |
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222 | |||
223 | return TRUE; |
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224 | } |
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225 | |||
226 | void |
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227 | sna_render_flush_solid(struct sna *sna) |
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228 | { |
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229 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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230 | |||
231 | DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
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232 | assert(cache->dirty); |
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233 | assert(cache->size); |
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234 | |||
235 | kgem_bo_write(&sna->kgem, cache->cache_bo, |
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236 | cache->color, cache->size*sizeof(uint32_t)); |
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237 | cache->dirty = 0; |
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238 | cache->last = 0; |
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239 | } |
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240 | |||
241 | static void |
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242 | sna_render_finish_solid(struct sna *sna, bool force) |
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243 | { |
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244 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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245 | int i; |
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246 | |||
247 | DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
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248 | force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
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249 | |||
250 | if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
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251 | return; |
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252 | |||
253 | if (cache->dirty) |
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254 | sna_render_flush_solid(sna); |
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255 | |||
256 | for (i = 0; i < cache->size; i++) { |
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257 | if (cache->bo[i] == NULL) |
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258 | continue; |
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259 | |||
260 | kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
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261 | cache->bo[i] = NULL; |
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262 | } |
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263 | kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
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264 | |||
265 | DBG(("sna_render_finish_solid reset\n")); |
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266 | |||
267 | cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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268 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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269 | cache->bo[0]->pitch = 4; |
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270 | if (force) |
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271 | cache->size = 1; |
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272 | } |
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273 | |||
274 | |||
275 | struct kgem_bo * |
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276 | sna_render_get_solid(struct sna *sna, uint32_t color) |
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277 | { |
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278 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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279 | int i; |
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280 | |||
281 | DBG(("%s: %08x\n", __FUNCTION__, color)); |
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282 | |||
283 | // if ((color & 0xffffff) == 0) /* alpha only */ |
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284 | // return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
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285 | |||
286 | if (color == 0xffffffff) { |
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287 | DBG(("%s(white)\n", __FUNCTION__)); |
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288 | return kgem_bo_reference(cache->bo[0]); |
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289 | } |
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290 | |||
291 | if (cache->color[cache->last] == color) { |
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292 | DBG(("sna_render_get_solid(%d) = %x (last)\n", |
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293 | cache->last, color)); |
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294 | return kgem_bo_reference(cache->bo[cache->last]); |
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295 | } |
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296 | |||
297 | for (i = 1; i < cache->size; i++) { |
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298 | if (cache->color[i] == color) { |
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299 | if (cache->bo[i] == NULL) { |
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300 | DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
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301 | i, color)); |
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302 | goto create; |
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303 | } else { |
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304 | DBG(("sna_render_get_solid(%d) = %x (old)\n", |
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305 | i, color)); |
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306 | goto done; |
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307 | } |
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308 | } |
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309 | } |
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310 | |||
311 | sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
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312 | |||
313 | i = cache->size++; |
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314 | cache->color[i] = color; |
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315 | cache->dirty = 1; |
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316 | DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
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317 | |||
318 | create: |
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319 | cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
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320 | i*sizeof(uint32_t), sizeof(uint32_t)); |
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321 | cache->bo[i]->pitch = 4; |
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322 | |||
323 | done: |
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324 | cache->last = i; |
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325 | return kgem_bo_reference(cache->bo[i]); |
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326 | } |
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327 | |||
328 | #endif |
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329 | |||
330 | |||
3263 | Serge | 331 | int sna_blit_copy(bitmap_t *src_bitmap, int dst_x, int dst_y, |
332 | int w, int h, int src_x, int src_y) |
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3254 | Serge | 333 | |
334 | { |
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335 | struct sna_copy_op copy; |
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3263 | Serge | 336 | struct _Pixmap src, dst; |
337 | struct kgem_bo *src_bo; |
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3254 | Serge | 338 | |
3263 | Serge | 339 | memset(&src, 0, sizeof(src)); |
340 | memset(&dst, 0, sizeof(dst)); |
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3254 | Serge | 341 | |
3263 | Serge | 342 | src.drawable.bitsPerPixel = 32; |
343 | src.drawable.width = src_bitmap->width; |
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344 | src.drawable.height = src_bitmap->height; |
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3254 | Serge | 345 | |
3263 | Serge | 346 | dst.drawable.bitsPerPixel = 32; |
347 | dst.drawable.width = sna_fb.width; |
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348 | dst.drawable.height = sna_fb.height; |
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3254 | Serge | 349 | |
350 | memset(©, 0, sizeof(copy)); |
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351 | |||
3263 | Serge | 352 | src_bo = (struct kgem_bo*)src_bitmap->handle; |
353 | |||
354 | if( sna_device->render.copy(sna_device, GXcopy, |
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355 | &src, src_bo, |
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356 | &dst, sna_fb.fb_bo, ©) ) |
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357 | { |
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3254 | Serge | 358 | copy.blt(sna_device, ©, src_x, src_y, w, h, dst_x, dst_y); |
359 | copy.done(sna_device, ©); |
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3263 | Serge | 360 | } |
3254 | Serge | 361 | |
3263 | Serge | 362 | kgem_submit(&sna_device->kgem); |
3254 | Serge | 363 | |
3263 | Serge | 364 | // __asm__ __volatile__("int3"); |
3254 | Serge | 365 | |
366 | }; |
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367 | |||
3263 | Serge | 368 | int sna_create_bitmap(bitmap_t *bitmap) |
369 | { |
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370 | struct kgem_bo *bo; |
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3254 | Serge | 371 | |
3263 | Serge | 372 | bo = kgem_create_2d(&sna_device->kgem, bitmap->width, bitmap->height, |
373 | 32,I915_TILING_NONE, CREATE_CPU_MAP); |
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374 | |||
375 | if(bo == NULL) |
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376 | goto err_1; |
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377 | |||
378 | void *map = kgem_bo_map(&sna_device->kgem, bo); |
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379 | if(map == NULL) |
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380 | goto err_2; |
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381 | |||
382 | bitmap->handle = (uint32_t)bo; |
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383 | bitmap->pitch = bo->pitch; |
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384 | bitmap->data = map; |
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385 | |||
386 | return 0; |
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387 | |||
388 | err_2: |
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389 | kgem_bo_destroy(&sna_device->kgem, bo); |
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390 | |||
391 | err_1: |
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392 | return -1; |
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393 | }; |
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3254 | Serge | 394 | /* |
395 | |||
396 | int sna_blit_tex(bitmap_t *dst_bitmap, int dst_x, int dst_y, |
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397 | int w, int h, bitmap_t *src_bitmap, int src_x, int src_y, |
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398 | bitmap_t *mask_bitmap) |
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399 | |||
400 | { |
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401 | struct sna_composite_op cop; |
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402 | batchbuffer_t execbuffer; |
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403 | BoxRec box; |
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404 | |||
405 | struct kgem_bo src_bo, mask_bo, dst_bo; |
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406 | |||
407 | memset(&cop, 0, sizeof(cop)); |
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408 | memset(&execbuffer, 0, sizeof(execbuffer)); |
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409 | memset(&src_bo, 0, sizeof(src_bo)); |
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410 | memset(&dst_bo, 0, sizeof(dst_bo)); |
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411 | memset(&mask_bo, 0, sizeof(mask_bo)); |
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412 | |||
413 | src_bo.gaddr = src_bitmap->gaddr; |
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414 | src_bo.pitch = src_bitmap->pitch; |
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415 | src_bo.tiling = 0; |
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416 | |||
417 | dst_bo.gaddr = dst_bitmap->gaddr; |
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418 | dst_bo.pitch = dst_bitmap->pitch; |
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419 | dst_bo.tiling = 0; |
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420 | |||
421 | mask_bo.gaddr = mask_bitmap->gaddr; |
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422 | mask_bo.pitch = mask_bitmap->pitch; |
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423 | mask_bo.tiling = 0; |
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424 | |||
425 | box.x1 = dst_x; |
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426 | box.y1 = dst_y; |
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427 | box.x2 = dst_x+w; |
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428 | box.y2 = dst_y+h; |
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429 | |||
430 | sna_device->render.composite(sna_device, 0, |
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431 | src_bitmap, &src_bo, |
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432 | mask_bitmap, &mask_bo, |
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433 | dst_bitmap, &dst_bo, |
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434 | src_x, src_y, |
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435 | src_x, src_y, |
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436 | dst_x, dst_y, |
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437 | w, h, &cop); |
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438 | |||
439 | cop.box(sna_device, &cop, &box); |
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440 | cop.done(sna_device, &cop); |
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441 | |||
442 | INIT_LIST_HEAD(&execbuffer.objects); |
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443 | list_add_tail(&src_bitmap->obj->exec_list, &execbuffer.objects); |
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444 | list_add_tail(&mask_bitmap->obj->exec_list, &execbuffer.objects); |
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445 | |||
446 | _kgem_submit(&sna_device->kgem, &execbuffer); |
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447 | |||
448 | }; |
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449 | |||
450 | */ |
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451 | |||
452 | static const struct intel_device_info intel_generic_info = { |
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453 | .gen = -1, |
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454 | }; |
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455 | |||
456 | static const struct intel_device_info intel_i915_info = { |
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457 | .gen = 030, |
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458 | }; |
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459 | static const struct intel_device_info intel_i945_info = { |
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460 | .gen = 031, |
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461 | }; |
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462 | |||
463 | static const struct intel_device_info intel_g33_info = { |
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464 | .gen = 033, |
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465 | }; |
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466 | |||
467 | static const struct intel_device_info intel_i965_info = { |
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468 | .gen = 040, |
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469 | }; |
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470 | |||
471 | static const struct intel_device_info intel_g4x_info = { |
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472 | .gen = 045, |
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473 | }; |
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474 | |||
475 | static const struct intel_device_info intel_ironlake_info = { |
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476 | .gen = 050, |
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477 | }; |
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478 | |||
479 | static const struct intel_device_info intel_sandybridge_info = { |
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480 | .gen = 060, |
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481 | }; |
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482 | |||
483 | static const struct intel_device_info intel_ivybridge_info = { |
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484 | .gen = 070, |
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485 | }; |
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486 | |||
487 | static const struct intel_device_info intel_valleyview_info = { |
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488 | .gen = 071, |
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489 | }; |
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490 | |||
491 | static const struct intel_device_info intel_haswell_info = { |
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492 | .gen = 075, |
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493 | }; |
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494 | |||
495 | #define INTEL_DEVICE_MATCH(d,i) \ |
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496 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
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497 | |||
498 | |||
499 | static const struct pci_id_match intel_device_match[] = { |
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500 | |||
501 | |||
502 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), |
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503 | INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), |
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504 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), |
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505 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ), |
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506 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ), |
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507 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ), |
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508 | |||
509 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), |
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510 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), |
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511 | INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), |
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512 | INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), |
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513 | /* Another marketing win: Q35 is another g33 device not a gen4 part |
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514 | * like its G35 brethren. |
||
515 | */ |
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516 | INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), |
||
517 | |||
518 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), |
||
519 | INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), |
||
520 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), |
||
521 | INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), |
||
522 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), |
||
523 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), |
||
524 | |||
525 | INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), |
||
526 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), |
||
527 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), |
||
528 | INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), |
||
529 | INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), |
||
530 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), |
||
531 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), |
||
532 | |||
533 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), |
||
534 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), |
||
535 | |||
536 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), |
||
537 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), |
||
538 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), |
||
539 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), |
||
540 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), |
||
541 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), |
||
542 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), |
||
543 | |||
544 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), |
||
545 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), |
||
546 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), |
||
547 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), |
||
548 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), |
||
549 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), |
||
550 | |||
551 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), |
||
552 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), |
||
553 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), |
||
554 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), |
||
555 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), |
||
556 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), |
||
557 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), |
||
558 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), |
||
559 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), |
||
560 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), |
||
561 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), |
||
562 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), |
||
563 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), |
||
564 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), |
||
565 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), |
||
566 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), |
||
567 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), |
||
568 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), |
||
569 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), |
||
570 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), |
||
571 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), |
||
572 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), |
||
573 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), |
||
574 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), |
||
575 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), |
||
576 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), |
||
577 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), |
||
578 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), |
||
579 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), |
||
580 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), |
||
581 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), |
||
582 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), |
||
583 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), |
||
584 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), |
||
585 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), |
||
586 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), |
||
587 | |||
588 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), |
||
589 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |
||
590 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), |
||
591 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), |
||
592 | |||
593 | INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), |
||
594 | |||
595 | { 0, 0, 0 }, |
||
596 | }; |
||
597 | |||
598 | const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
||
599 | { |
||
600 | while(list->device_id) |
||
601 | { |
||
602 | if(dev==list->device_id) |
||
603 | return list; |
||
604 | list++; |
||
605 | } |
||
606 | return NULL; |
||
607 | } |
||
608 | |||
609 | const struct intel_device_info * |
||
610 | intel_detect_chipset(struct pci_device *pci) |
||
611 | { |
||
612 | const struct pci_id_match *ent = NULL; |
||
613 | const char *name = NULL; |
||
614 | int i; |
||
615 | |||
616 | ent = PciDevMatch(pci->device_id, intel_device_match); |
||
617 | |||
618 | if(ent != NULL) |
||
619 | return (const struct intel_device_info*)ent->match_data; |
||
620 | else |
||
621 | return &intel_generic_info; |
||
622 | |||
623 | #if 0 |
||
624 | for (i = 0; intel_chipsets[i].name != NULL; i++) { |
||
625 | if (DEVICE_ID(pci) == intel_chipsets[i].token) { |
||
626 | name = intel_chipsets[i].name; |
||
627 | break; |
||
628 | } |
||
629 | } |
||
630 | if (name == NULL) { |
||
631 | xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); |
||
632 | name = "unknown"; |
||
633 | } else { |
||
634 | xf86DrvMsg(scrn->scrnIndex, from, |
||
635 | "Integrated Graphics Chipset: Intel(R) %s\n", |
||
636 | name); |
||
637 | } |
||
638 | |||
639 | scrn->chipset = name; |
||
640 | #endif |
||
641 | |||
642 | } |
||
643 | |||
644 | |||
3258 | Serge | 645 | int drmIoctl(int fd, unsigned long request, void *arg) |
646 | { |
||
647 | ioctl_t io; |
||
3254 | Serge | 648 | |
3258 | Serge | 649 | io.handle = fd; |
650 | io.io_code = request; |
||
651 | io.input = arg; |
||
652 | io.inp_size = 64; |
||
653 | io.output = NULL; |
||
654 | io.out_size = 0; |
||
3254 | Serge | 655 | |
3258 | Serge | 656 | return call_service(&io); |
657 | }><>><>>> |
||
658 |