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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3254 | Serge | 1 | //#include "../bitmap.h" |
| 2 | |||
| 3 | #include |
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| 4 | #include |
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| 5 | |||
| 6 | #include "sna.h" |
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| 7 | |||
| 3258 | Serge | 8 | typedef struct __attribute__((packed)) |
| 9 | { |
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| 10 | unsigned handle; |
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| 11 | unsigned io_code; |
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| 12 | void *input; |
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| 13 | int inp_size; |
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| 14 | void *output; |
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| 15 | int out_size; |
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| 16 | }ioctl_t; |
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| 3254 | Serge | 17 | |
| 3258 | Serge | 18 | |
| 19 | static int call_service(ioctl_t *io) |
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| 20 | { |
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| 21 | int retval; |
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| 22 | |||
| 23 | asm volatile("int $0x40" |
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| 24 | :"=a"(retval) |
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| 25 | :"a"(68),"b"(17),"c"(io) |
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| 26 | :"memory","cc"); |
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| 27 | |||
| 28 | return retval; |
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| 29 | }; |
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| 30 | |||
| 3254 | Serge | 31 | const struct intel_device_info * |
| 32 | intel_detect_chipset(struct pci_device *pci); |
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| 33 | |||
| 34 | //struct kgem_bo *create_bo(bitmap_t *bitmap); |
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| 35 | |||
| 36 | static bool sna_solid_cache_init(struct sna *sna); |
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| 37 | |||
| 38 | struct sna *sna_device; |
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| 39 | |||
| 3258 | Serge | 40 | static void no_render_reset(struct sna *sna) |
| 41 | { |
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| 42 | (void)sna; |
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| 43 | } |
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| 44 | |||
| 3254 | Serge | 45 | void no_render_init(struct sna *sna) |
| 46 | { |
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| 47 | struct sna_render *render = &sna->render; |
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| 48 | |||
| 49 | memset (render,0, sizeof (*render)); |
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| 50 | |||
| 51 | render->prefer_gpu = PREFER_GPU_BLT; |
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| 52 | |||
| 53 | render->vertices = render->vertex_data; |
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| 54 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
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| 55 | |||
| 56 | // render->composite = no_render_composite; |
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| 57 | |||
| 58 | // render->copy_boxes = no_render_copy_boxes; |
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| 59 | // render->copy = no_render_copy; |
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| 60 | |||
| 61 | // render->fill_boxes = no_render_fill_boxes; |
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| 62 | // render->fill = no_render_fill; |
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| 63 | // render->fill_one = no_render_fill_one; |
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| 64 | // render->clear = no_render_clear; |
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| 65 | |||
| 3258 | Serge | 66 | render->reset = no_render_reset; |
| 67 | render->flush = no_render_flush; |
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| 3254 | Serge | 68 | // render->fini = no_render_fini; |
| 69 | |||
| 70 | // sna->kgem.context_switch = no_render_context_switch; |
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| 71 | // sna->kgem.retire = no_render_retire; |
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| 72 | |||
| 3258 | Serge | 73 | if (sna->kgem.gen >= 60) |
| 3254 | Serge | 74 | sna->kgem.ring = KGEM_RENDER; |
| 75 | |||
| 76 | sna_vertex_init(sna); |
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| 77 | } |
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| 78 | |||
| 79 | void sna_vertex_init(struct sna *sna) |
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| 80 | { |
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| 81 | // pthread_mutex_init(&sna->render.lock, NULL); |
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| 82 | // pthread_cond_init(&sna->render.wait, NULL); |
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| 83 | sna->render.active = 0; |
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| 84 | } |
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| 85 | |||
| 86 | bool sna_accel_init(struct sna *sna) |
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| 87 | { |
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| 88 | const char *backend; |
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| 89 | |||
| 90 | // list_init(&sna->deferred_free); |
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| 91 | // list_init(&sna->dirty_pixmaps); |
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| 92 | // list_init(&sna->active_pixmaps); |
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| 93 | // list_init(&sna->inactive_clock[0]); |
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| 94 | // list_init(&sna->inactive_clock[1]); |
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| 95 | |||
| 96 | // sna_accel_install_timers(sna); |
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| 97 | |||
| 98 | |||
| 99 | backend = "no"; |
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| 100 | no_render_init(sna); |
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| 101 | |||
| 102 | if (sna->info->gen >= 0100) { |
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| 103 | /* } else if (sna->info->gen >= 070) { |
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| 104 | if (gen7_render_init(sna)) |
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| 105 | backend = "IvyBridge"; */ |
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| 106 | } else if (sna->info->gen >= 060) { |
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| 107 | if (gen6_render_init(sna)) |
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| 108 | backend = "SandyBridge"; |
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| 109 | /* } else if (sna->info->gen >= 050) { |
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| 110 | if (gen5_render_init(sna)) |
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| 111 | backend = "Ironlake"; |
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| 112 | } else if (sna->info->gen >= 040) { |
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| 113 | if (gen4_render_init(sna)) |
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| 114 | backend = "Broadwater/Crestline"; |
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| 115 | } else if (sna->info->gen >= 030) { |
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| 116 | if (gen3_render_init(sna)) |
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| 117 | backend = "gen3"; |
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| 118 | } else if (sna->info->gen >= 020) { |
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| 119 | if (gen2_render_init(sna)) |
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| 120 | backend = "gen2"; */ |
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| 121 | } |
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| 122 | |||
| 123 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
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| 124 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
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| 125 | |||
| 126 | kgem_reset(&sna->kgem); |
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| 127 | |||
| 128 | // if (!sna_solid_cache_init(sna)) |
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| 129 | // return false; |
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| 130 | |||
| 131 | sna_device = sna; |
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| 132 | #if 0 |
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| 133 | { |
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| 134 | struct kgem_bo *screen_bo; |
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| 135 | bitmap_t screen; |
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| 136 | |||
| 137 | screen.pitch = 1024*4; |
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| 138 | screen.gaddr = 0; |
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| 139 | screen.width = 1024; |
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| 140 | screen.height = 768; |
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| 141 | screen.obj = (void*)-1; |
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| 142 | |||
| 143 | screen_bo = create_bo(&screen); |
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| 144 | |||
| 145 | sna->render.clear(sna, &screen, screen_bo); |
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| 146 | } |
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| 147 | #endif |
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| 148 | |||
| 149 | return true; |
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| 150 | } |
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| 151 | |||
| 152 | int sna_init(uint32_t service) |
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| 153 | { |
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| 154 | ioctl_t io; |
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| 155 | |||
| 156 | static struct pci_device device; |
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| 157 | struct sna *sna; |
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| 158 | |||
| 159 | DBG(("%s\n", __FUNCTION__)); |
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| 160 | |||
| 161 | sna = malloc(sizeof(struct sna)); |
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| 162 | if (sna == NULL) |
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| 163 | return false; |
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| 164 | |||
| 165 | io.handle = service; |
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| 3256 | Serge | 166 | io.io_code = SRV_GET_PCI_INFO; |
| 3254 | Serge | 167 | io.input = &device; |
| 168 | io.inp_size = sizeof(device); |
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| 169 | io.output = NULL; |
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| 170 | io.out_size = 0; |
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| 171 | |||
| 172 | if (call_service(&io)!=0) |
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| 173 | return false; |
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| 174 | |||
| 175 | sna->PciInfo = &device; |
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| 176 | |||
| 177 | sna->info = intel_detect_chipset(sna->PciInfo); |
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| 178 | |||
| 179 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
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| 180 | /* |
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| 181 | if (!xf86ReturnOptValBool(sna->Options, |
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| 182 | OPTION_RELAXED_FENCING, |
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| 183 | sna->kgem.has_relaxed_fencing)) { |
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| 184 | xf86DrvMsg(scrn->scrnIndex, |
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| 185 | sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
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| 186 | "Disabling use of relaxed fencing\n"); |
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| 187 | sna->kgem.has_relaxed_fencing = 0; |
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| 188 | } |
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| 189 | if (!xf86ReturnOptValBool(sna->Options, |
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| 190 | OPTION_VMAP, |
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| 191 | sna->kgem.has_vmap)) { |
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| 192 | xf86DrvMsg(scrn->scrnIndex, |
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| 193 | sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
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| 194 | "Disabling use of vmap\n"); |
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| 195 | sna->kgem.has_vmap = 0; |
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| 196 | } |
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| 197 | */ |
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| 198 | |||
| 199 | /* Disable tiling by default */ |
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| 200 | sna->tiling = SNA_TILING_DISABLE; |
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| 201 | |||
| 202 | /* Default fail-safe value of 75 Hz */ |
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| 203 | // sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
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| 204 | |||
| 205 | sna->flags = 0; |
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| 206 | |||
| 207 | return sna_accel_init(sna); |
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| 208 | } |
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| 209 | |||
| 210 | #if 0 |
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| 211 | |||
| 212 | static bool sna_solid_cache_init(struct sna *sna) |
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| 213 | { |
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| 214 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 215 | |||
| 216 | DBG(("%s\n", __FUNCTION__)); |
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| 217 | |||
| 218 | cache->cache_bo = |
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| 219 | kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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| 220 | if (!cache->cache_bo) |
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| 221 | return FALSE; |
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| 222 | |||
| 223 | /* |
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| 224 | * Initialise [0] with white since it is very common and filling the |
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| 225 | * zeroth slot simplifies some of the checks. |
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| 226 | */ |
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| 227 | cache->color[0] = 0xffffffff; |
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| 228 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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| 229 | cache->bo[0]->pitch = 4; |
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| 230 | cache->dirty = 1; |
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| 231 | cache->size = 1; |
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| 232 | cache->last = 0; |
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| 233 | |||
| 234 | return TRUE; |
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| 235 | } |
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| 236 | |||
| 237 | void |
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| 238 | sna_render_flush_solid(struct sna *sna) |
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| 239 | { |
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| 240 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 241 | |||
| 242 | DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
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| 243 | assert(cache->dirty); |
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| 244 | assert(cache->size); |
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| 245 | |||
| 246 | kgem_bo_write(&sna->kgem, cache->cache_bo, |
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| 247 | cache->color, cache->size*sizeof(uint32_t)); |
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| 248 | cache->dirty = 0; |
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| 249 | cache->last = 0; |
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| 250 | } |
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| 251 | |||
| 252 | static void |
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| 253 | sna_render_finish_solid(struct sna *sna, bool force) |
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| 254 | { |
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| 255 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 256 | int i; |
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| 257 | |||
| 258 | DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
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| 259 | force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
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| 260 | |||
| 261 | if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
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| 262 | return; |
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| 263 | |||
| 264 | if (cache->dirty) |
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| 265 | sna_render_flush_solid(sna); |
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| 266 | |||
| 267 | for (i = 0; i < cache->size; i++) { |
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| 268 | if (cache->bo[i] == NULL) |
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| 269 | continue; |
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| 270 | |||
| 271 | kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
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| 272 | cache->bo[i] = NULL; |
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| 273 | } |
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| 274 | kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
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| 275 | |||
| 276 | DBG(("sna_render_finish_solid reset\n")); |
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| 277 | |||
| 278 | cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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| 279 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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| 280 | cache->bo[0]->pitch = 4; |
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| 281 | if (force) |
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| 282 | cache->size = 1; |
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| 283 | } |
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| 284 | |||
| 285 | |||
| 286 | struct kgem_bo * |
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| 287 | sna_render_get_solid(struct sna *sna, uint32_t color) |
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| 288 | { |
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| 289 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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| 290 | int i; |
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| 291 | |||
| 292 | DBG(("%s: %08x\n", __FUNCTION__, color)); |
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| 293 | |||
| 294 | // if ((color & 0xffffff) == 0) /* alpha only */ |
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| 295 | // return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
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| 296 | |||
| 297 | if (color == 0xffffffff) { |
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| 298 | DBG(("%s(white)\n", __FUNCTION__)); |
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| 299 | return kgem_bo_reference(cache->bo[0]); |
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| 300 | } |
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| 301 | |||
| 302 | if (cache->color[cache->last] == color) { |
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| 303 | DBG(("sna_render_get_solid(%d) = %x (last)\n", |
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| 304 | cache->last, color)); |
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| 305 | return kgem_bo_reference(cache->bo[cache->last]); |
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| 306 | } |
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| 307 | |||
| 308 | for (i = 1; i < cache->size; i++) { |
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| 309 | if (cache->color[i] == color) { |
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| 310 | if (cache->bo[i] == NULL) { |
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| 311 | DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
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| 312 | i, color)); |
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| 313 | goto create; |
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| 314 | } else { |
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| 315 | DBG(("sna_render_get_solid(%d) = %x (old)\n", |
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| 316 | i, color)); |
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| 317 | goto done; |
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| 318 | } |
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| 319 | } |
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| 320 | } |
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| 321 | |||
| 322 | sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
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| 323 | |||
| 324 | i = cache->size++; |
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| 325 | cache->color[i] = color; |
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| 326 | cache->dirty = 1; |
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| 327 | DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
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| 328 | |||
| 329 | create: |
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| 330 | cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
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| 331 | i*sizeof(uint32_t), sizeof(uint32_t)); |
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| 332 | cache->bo[i]->pitch = 4; |
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| 333 | |||
| 334 | done: |
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| 335 | cache->last = i; |
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| 336 | return kgem_bo_reference(cache->bo[i]); |
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| 337 | } |
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| 338 | |||
| 339 | #endif |
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| 340 | |||
| 341 | |||
| 342 | int sna_blit_copy(uint32_t dst_bitmap, int dst_x, int dst_y, |
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| 343 | int w, int h, uint32_t src_bitmap, int src_x, int src_y) |
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| 344 | |||
| 345 | { |
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| 346 | struct sna_copy_op copy; |
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| 347 | struct kgem_bo src_bo, dst_bo; |
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| 348 | |||
| 349 | memset(&src_bo, 0, sizeof(src_bo)); |
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| 350 | memset(&dst_bo, 0, sizeof(dst_bo)); |
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| 351 | |||
| 352 | // src_bo.gaddr = src_bitmap->gaddr; |
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| 353 | // src_bo.pitch = src_bitmap->pitch; |
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| 354 | // src_bo.tiling = 0; |
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| 355 | |||
| 356 | // dst_bo.gaddr = dst_bitmap->gaddr; |
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| 357 | // dst_bo.pitch = dst_bitmap->pitch; |
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| 358 | // dst_bo.tiling = 0; |
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| 359 | |||
| 360 | memset(©, 0, sizeof(copy)); |
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| 361 | |||
| 362 | sna_device->render.copy(sna_device, GXcopy, NULL, &src_bo, NULL, &dst_bo, ©); |
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| 363 | copy.blt(sna_device, ©, src_x, src_y, w, h, dst_x, dst_y); |
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| 364 | copy.done(sna_device, ©); |
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| 365 | |||
| 366 | |||
| 367 | |||
| 368 | // _kgem_submit(&sna_device->kgem, &execbuffer); |
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| 369 | |||
| 370 | }; |
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| 371 | |||
| 372 | |||
| 373 | /* |
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| 374 | |||
| 375 | int sna_blit_tex(bitmap_t *dst_bitmap, int dst_x, int dst_y, |
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| 376 | int w, int h, bitmap_t *src_bitmap, int src_x, int src_y, |
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| 377 | bitmap_t *mask_bitmap) |
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| 378 | |||
| 379 | { |
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| 380 | struct sna_composite_op cop; |
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| 381 | batchbuffer_t execbuffer; |
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| 382 | BoxRec box; |
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| 383 | |||
| 384 | struct kgem_bo src_bo, mask_bo, dst_bo; |
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| 385 | |||
| 386 | memset(&cop, 0, sizeof(cop)); |
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| 387 | memset(&execbuffer, 0, sizeof(execbuffer)); |
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| 388 | memset(&src_bo, 0, sizeof(src_bo)); |
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| 389 | memset(&dst_bo, 0, sizeof(dst_bo)); |
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| 390 | memset(&mask_bo, 0, sizeof(mask_bo)); |
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| 391 | |||
| 392 | src_bo.gaddr = src_bitmap->gaddr; |
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| 393 | src_bo.pitch = src_bitmap->pitch; |
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| 394 | src_bo.tiling = 0; |
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| 395 | |||
| 396 | dst_bo.gaddr = dst_bitmap->gaddr; |
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| 397 | dst_bo.pitch = dst_bitmap->pitch; |
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| 398 | dst_bo.tiling = 0; |
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| 399 | |||
| 400 | mask_bo.gaddr = mask_bitmap->gaddr; |
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| 401 | mask_bo.pitch = mask_bitmap->pitch; |
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| 402 | mask_bo.tiling = 0; |
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| 403 | |||
| 404 | box.x1 = dst_x; |
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| 405 | box.y1 = dst_y; |
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| 406 | box.x2 = dst_x+w; |
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| 407 | box.y2 = dst_y+h; |
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| 408 | |||
| 409 | sna_device->render.composite(sna_device, 0, |
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| 410 | src_bitmap, &src_bo, |
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| 411 | mask_bitmap, &mask_bo, |
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| 412 | dst_bitmap, &dst_bo, |
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| 413 | src_x, src_y, |
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| 414 | src_x, src_y, |
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| 415 | dst_x, dst_y, |
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| 416 | w, h, &cop); |
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| 417 | |||
| 418 | cop.box(sna_device, &cop, &box); |
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| 419 | cop.done(sna_device, &cop); |
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| 420 | |||
| 421 | INIT_LIST_HEAD(&execbuffer.objects); |
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| 422 | list_add_tail(&src_bitmap->obj->exec_list, &execbuffer.objects); |
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| 423 | list_add_tail(&mask_bitmap->obj->exec_list, &execbuffer.objects); |
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| 424 | |||
| 425 | _kgem_submit(&sna_device->kgem, &execbuffer); |
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| 426 | |||
| 427 | }; |
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| 428 | |||
| 429 | */ |
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| 430 | |||
| 431 | static const struct intel_device_info intel_generic_info = { |
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| 432 | .gen = -1, |
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| 433 | }; |
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| 434 | |||
| 435 | static const struct intel_device_info intel_i915_info = { |
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| 436 | .gen = 030, |
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| 437 | }; |
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| 438 | static const struct intel_device_info intel_i945_info = { |
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| 439 | .gen = 031, |
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| 440 | }; |
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| 441 | |||
| 442 | static const struct intel_device_info intel_g33_info = { |
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| 443 | .gen = 033, |
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| 444 | }; |
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| 445 | |||
| 446 | static const struct intel_device_info intel_i965_info = { |
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| 447 | .gen = 040, |
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| 448 | }; |
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| 449 | |||
| 450 | static const struct intel_device_info intel_g4x_info = { |
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| 451 | .gen = 045, |
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| 452 | }; |
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| 453 | |||
| 454 | static const struct intel_device_info intel_ironlake_info = { |
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| 455 | .gen = 050, |
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| 456 | }; |
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| 457 | |||
| 458 | static const struct intel_device_info intel_sandybridge_info = { |
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| 459 | .gen = 060, |
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| 460 | }; |
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| 461 | |||
| 462 | static const struct intel_device_info intel_ivybridge_info = { |
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| 463 | .gen = 070, |
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| 464 | }; |
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| 465 | |||
| 466 | static const struct intel_device_info intel_valleyview_info = { |
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| 467 | .gen = 071, |
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| 468 | }; |
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| 469 | |||
| 470 | static const struct intel_device_info intel_haswell_info = { |
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| 471 | .gen = 075, |
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| 472 | }; |
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| 473 | |||
| 474 | #define INTEL_DEVICE_MATCH(d,i) \ |
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| 475 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
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| 476 | |||
| 477 | |||
| 478 | static const struct pci_id_match intel_device_match[] = { |
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| 479 | |||
| 480 | |||
| 481 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), |
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| 482 | INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), |
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| 483 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), |
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| 484 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ), |
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| 485 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ), |
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| 486 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ), |
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| 487 | |||
| 488 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), |
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| 489 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), |
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| 490 | INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), |
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| 491 | INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), |
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| 492 | /* Another marketing win: Q35 is another g33 device not a gen4 part |
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| 493 | * like its G35 brethren. |
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| 494 | */ |
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| 495 | INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), |
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| 496 | |||
| 497 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), |
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| 498 | INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), |
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| 499 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), |
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| 500 | INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), |
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| 501 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), |
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| 502 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), |
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| 503 | |||
| 504 | INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), |
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| 505 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), |
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| 506 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), |
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| 507 | INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), |
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| 508 | INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), |
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| 509 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), |
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| 510 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), |
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| 511 | |||
| 512 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), |
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| 513 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), |
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| 514 | |||
| 515 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), |
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| 516 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), |
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| 517 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), |
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| 518 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), |
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| 519 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), |
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| 520 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), |
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| 521 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), |
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| 522 | |||
| 523 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), |
||
| 524 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), |
||
| 525 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), |
||
| 526 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), |
||
| 527 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), |
||
| 528 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), |
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| 529 | |||
| 530 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), |
||
| 531 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), |
||
| 532 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), |
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| 533 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), |
||
| 534 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), |
||
| 535 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), |
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| 536 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), |
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| 537 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), |
||
| 538 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), |
||
| 539 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), |
||
| 540 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), |
||
| 541 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), |
||
| 542 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), |
||
| 543 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), |
||
| 544 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), |
||
| 545 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), |
||
| 546 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), |
||
| 547 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), |
||
| 548 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), |
||
| 549 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), |
||
| 550 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), |
||
| 551 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), |
||
| 552 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), |
||
| 553 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), |
||
| 554 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), |
||
| 555 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), |
||
| 556 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), |
||
| 557 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), |
||
| 558 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), |
||
| 559 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), |
||
| 560 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), |
||
| 561 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), |
||
| 562 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), |
||
| 563 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), |
||
| 564 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), |
||
| 565 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), |
||
| 566 | |||
| 567 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), |
||
| 568 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |
||
| 569 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), |
||
| 570 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), |
||
| 571 | |||
| 572 | INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), |
||
| 573 | |||
| 574 | { 0, 0, 0 }, |
||
| 575 | }; |
||
| 576 | |||
| 577 | const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
||
| 578 | { |
||
| 579 | while(list->device_id) |
||
| 580 | { |
||
| 581 | if(dev==list->device_id) |
||
| 582 | return list; |
||
| 583 | list++; |
||
| 584 | } |
||
| 585 | return NULL; |
||
| 586 | } |
||
| 587 | |||
| 588 | const struct intel_device_info * |
||
| 589 | intel_detect_chipset(struct pci_device *pci) |
||
| 590 | { |
||
| 591 | const struct pci_id_match *ent = NULL; |
||
| 592 | const char *name = NULL; |
||
| 593 | int i; |
||
| 594 | |||
| 595 | ent = PciDevMatch(pci->device_id, intel_device_match); |
||
| 596 | |||
| 597 | if(ent != NULL) |
||
| 598 | return (const struct intel_device_info*)ent->match_data; |
||
| 599 | else |
||
| 600 | return &intel_generic_info; |
||
| 601 | |||
| 602 | #if 0 |
||
| 603 | for (i = 0; intel_chipsets[i].name != NULL; i++) { |
||
| 604 | if (DEVICE_ID(pci) == intel_chipsets[i].token) { |
||
| 605 | name = intel_chipsets[i].name; |
||
| 606 | break; |
||
| 607 | } |
||
| 608 | } |
||
| 609 | if (name == NULL) { |
||
| 610 | xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); |
||
| 611 | name = "unknown"; |
||
| 612 | } else { |
||
| 613 | xf86DrvMsg(scrn->scrnIndex, from, |
||
| 614 | "Integrated Graphics Chipset: Intel(R) %s\n", |
||
| 615 | name); |
||
| 616 | } |
||
| 617 | |||
| 618 | scrn->chipset = name; |
||
| 619 | #endif |
||
| 620 | |||
| 621 | } |
||
| 622 | |||
| 623 | |||
| 3258 | Serge | 624 | int drmIoctl(int fd, unsigned long request, void *arg) |
| 625 | { |
||
| 626 | ioctl_t io; |
||
| 3254 | Serge | 627 | |
| 3258 | Serge | 628 | io.handle = fd; |
| 629 | io.io_code = request; |
||
| 630 | io.input = arg; |
||
| 631 | io.inp_size = 64; |
||
| 632 | io.output = NULL; |
||
| 633 | io.out_size = 0; |
||
| 3254 | Serge | 634 | |
| 3258 | Serge | 635 | return call_service(&io); |
| 636 | } |
||
| 637 |