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Rev | Author | Line No. | Line |
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3254 | Serge | 1 | #ifndef INTEL_DRIVER_H |
2 | #define INTEL_DRIVER_H |
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3 | |||
4 | #define INTEL_VERSION 4000 |
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5 | #define INTEL_NAME "intel" |
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6 | #define INTEL_DRIVER_NAME "intel" |
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7 | |||
8 | #define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR |
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9 | #define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR |
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10 | #define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL |
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11 | |||
12 | #define PCI_CHIP_I810 0x7121 |
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13 | #define PCI_CHIP_I810_DC100 0x7123 |
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14 | #define PCI_CHIP_I810_E 0x7125 |
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15 | #define PCI_CHIP_I815 0x1132 |
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16 | |||
17 | #define PCI_CHIP_I830_M 0x3577 |
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18 | #define PCI_CHIP_845_G 0x2562 |
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19 | #define PCI_CHIP_I854 0x358E |
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20 | #define PCI_CHIP_I855_GM 0x3582 |
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21 | #define PCI_CHIP_I865_G 0x2572 |
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22 | |||
23 | #define PCI_CHIP_I915_G 0x2582 |
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24 | #define PCI_CHIP_I915_GM 0x2592 |
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25 | #define PCI_CHIP_E7221_G 0x258A |
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26 | #define PCI_CHIP_I945_G 0x2772 |
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27 | #define PCI_CHIP_I945_GM 0x27A2 |
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28 | #define PCI_CHIP_I945_GME 0x27AE |
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29 | #define PCI_CHIP_PINEVIEW_M 0xA011 |
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30 | #define PCI_CHIP_PINEVIEW_G 0xA001 |
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4251 | Serge | 31 | #define PCI_CHIP_Q35_G 0x29B2 |
32 | #define PCI_CHIP_G33_G 0x29C2 |
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33 | #define PCI_CHIP_Q33_G 0x29D2 |
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3254 | Serge | 34 | |
35 | #define PCI_CHIP_G35_G 0x2982 |
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36 | #define PCI_CHIP_I965_Q 0x2992 |
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37 | #define PCI_CHIP_I965_G 0x29A2 |
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38 | #define PCI_CHIP_I946_GZ 0x2972 |
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39 | #define PCI_CHIP_I965_GM 0x2A02 |
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40 | #define PCI_CHIP_I965_GME 0x2A12 |
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41 | #define PCI_CHIP_GM45_GM 0x2A42 |
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42 | #define PCI_CHIP_G45_E_G 0x2E02 |
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43 | #define PCI_CHIP_G45_G 0x2E22 |
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44 | #define PCI_CHIP_Q45_G 0x2E12 |
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45 | #define PCI_CHIP_G41_G 0x2E32 |
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46 | #define PCI_CHIP_B43_G 0x2E42 |
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47 | #define PCI_CHIP_B43_G1 0x2E92 |
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48 | |||
49 | #define PCI_CHIP_IRONLAKE_D_G 0x0042 |
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50 | #define PCI_CHIP_IRONLAKE_M_G 0x0046 |
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51 | |||
52 | #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 |
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53 | #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 |
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54 | #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 |
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55 | #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 |
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56 | #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 |
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57 | #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 |
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58 | #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A |
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59 | |||
60 | #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 |
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61 | #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 |
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62 | #define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152 |
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63 | #define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162 |
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64 | #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a |
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65 | #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a |
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66 | |||
67 | #define PCI_CHIP_HASWELL_D_GT1 0x0402 |
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68 | #define PCI_CHIP_HASWELL_D_GT2 0x0412 |
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4251 | Serge | 69 | #define PCI_CHIP_HASWELL_D_GT3 0x0422 |
3254 | Serge | 70 | #define PCI_CHIP_HASWELL_M_GT1 0x0406 |
71 | #define PCI_CHIP_HASWELL_M_GT2 0x0416 |
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4251 | Serge | 72 | #define PCI_CHIP_HASWELL_M_GT3 0x0426 |
3254 | Serge | 73 | #define PCI_CHIP_HASWELL_S_GT1 0x040A |
74 | #define PCI_CHIP_HASWELL_S_GT2 0x041A |
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4251 | Serge | 75 | #define PCI_CHIP_HASWELL_S_GT3 0x042A |
76 | #define PCI_CHIP_HASWELL_B_GT1 0x040B |
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77 | #define PCI_CHIP_HASWELL_B_GT2 0x041B |
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78 | #define PCI_CHIP_HASWELL_B_GT3 0x042B |
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79 | #define PCI_CHIP_HASWELL_E_GT1 0x040E |
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80 | #define PCI_CHIP_HASWELL_E_GT2 0x041E |
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81 | #define PCI_CHIP_HASWELL_E_GT3 0x042E |
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82 | |||
3254 | Serge | 83 | #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 |
84 | #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 |
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4251 | Serge | 85 | #define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22 |
3254 | Serge | 86 | #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 |
87 | #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 |
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4251 | Serge | 88 | #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 |
3254 | Serge | 89 | #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A |
90 | #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A |
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4251 | Serge | 91 | #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A |
92 | #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B |
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93 | #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B |
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94 | #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B |
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95 | #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E |
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96 | #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E |
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97 | #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E |
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3254 | Serge | 98 | |
4251 | Serge | 99 | #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 |
100 | #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 |
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101 | #define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22 |
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102 | #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 |
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103 | #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 |
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104 | #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 |
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105 | #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A |
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106 | #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A |
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107 | #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A |
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108 | #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B |
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109 | #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B |
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110 | #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B |
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111 | #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E |
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112 | #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E |
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113 | #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E |
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3254 | Serge | 114 | |
115 | struct intel_device_info { |
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116 | int gen; |
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117 | }; |
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118 | |||
119 | //void intel_detect_chipset(ScrnInfoPtr scrn, |
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120 | // EntityInfoPtr ent, |
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121 | // struct pci_device *pci); |
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122 | |||
123 | |||
124 | #endif /* INTEL_DRIVER_H */ |