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Rev | Author | Line No. | Line |
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3254 | Serge | 1 | |
2 | |||
3 | LAST_3D_OTHER, |
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4 | LAST_3D_VIDEO, |
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5 | LAST_3D_RENDER, |
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6 | LAST_3D_ROTATION |
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7 | }; |
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8 | |||
9 | |||
10 | |||
11 | |||
12 | |||
13 | |||
14 | #define RENDER_BATCH I915_EXEC_RENDER |
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15 | |||
16 | |||
17 | unsigned int current_batch; |
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18 | |||
19 | dri_bufmgr *bufmgr; |
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20 | |||
21 | uint32_t batch_ptr[4096]; |
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22 | |||
23 | unsigned int batch_used; |
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24 | /** Position in batch_ptr at the start of the current BEGIN_BATCH */ |
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25 | unsigned int batch_emit_start; |
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26 | /** Number of bytes to be emitted in the current BEGIN_BATCH. */ |
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27 | uint32_t batch_emitting; |
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28 | dri_bo *batch_bo, *last_batch_bo[2]; |
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29 | /** Whether we're in a section of code that can't tolerate flushing */ |
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30 | Bool in_batch_atomic; |
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31 | /** Ending batch_used that was verified by intel_start_batch_atomic() */ |
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32 | int batch_atomic_limit; |
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33 | struct list batch_pixmaps; |
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34 | drm_intel_bo *wa_scratch_bo; |
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35 | |||
36 | unsigned int tiling; |
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37 | |||
38 | #define INTEL_TILING_FB 0x1 |
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39 | |||
40 | #define INTEL_TILING_3D 0x4 |
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41 | #define INTEL_TILING_ALL (~0) |
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42 | |||
43 | Bool has_relaxed_fencing; |
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44 | |||
45 | int Chipset; |
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46 | |||
47 | unsigned int BR[20]; |
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48 | |||
49 | void (*vertex_flush) (struct intel_screen_private *intel); |
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50 | |||
51 | void (*batch_commit_notify) (struct intel_screen_private *intel); |
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52 | |||
53 | Bool need_sync; |
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54 | |||
55 | int accel_pixmap_offset_alignment; |
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56 | |||
57 | int accel_max_y; |
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58 | int max_bo_size; |
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59 | int max_gtt_map_size; |
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60 | int max_tiling_size; |
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61 | |||
62 | struct { |
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63 | |||
64 | drm_intel_bo *gen4_sf_bo; |
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65 | drm_intel_bo *gen4_wm_packed_bo; |
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66 | drm_intel_bo *gen4_wm_planar_bo; |
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67 | drm_intel_bo *gen4_cc_bo; |
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68 | drm_intel_bo *gen4_cc_vp_bo; |
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69 | drm_intel_bo *gen4_sampler_bo; |
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70 | drm_intel_bo *gen4_sip_kernel_bo; |
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71 | drm_intel_bo *wm_prog_packed_bo; |
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72 | drm_intel_bo *wm_prog_planar_bo; |
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73 | drm_intel_bo *gen6_blend_bo; |
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74 | drm_intel_bo *gen6_depth_stencil_bo; |
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75 | } video; |
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76 | |||
77 | /* Render accel state */ |
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78 | |||
79 | /** Transform pointers for src/mask, or NULL if identity */ |
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80 | PictTransform *transform[2]; |
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81 | |||
82 | PixmapPtr render_source, render_mask, render_dest; |
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83 | |||
84 | Bool needs_3d_invariant; |
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85 | Bool needs_render_state_emit; |
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86 | Bool needs_render_vertex_emit; |
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87 | |||
88 | /* i830 render accel state */ |
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89 | |||
90 | uint32_t cblend, ablend, s8_blendctl; |
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91 | |||
92 | /* i915 render accel state */ |
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93 | |||
94 | uint32_t mapstate[6]; |
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95 | uint32_t samplerstate[6]; |
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96 | |||
97 | struct { |
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98 | |||
99 | uint32_t dst_format; |
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100 | } i915_render_state; |
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101 | |||
102 | struct { |
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103 | |||
104 | int drawrect; |
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105 | uint32_t blend; |
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106 | dri_bo *samplers; |
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107 | dri_bo *kernel; |
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108 | } gen6_render_state; |
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109 | |||
110 | uint32_t prim_offset; |
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111 | |||
112 | int srcX, int srcY, |
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113 | int maskX, int maskY, |
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114 | int dstX, int dstY, |
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115 | int w, int h); |
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116 | int floats_per_vertex; |
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117 | int last_floats_per_vertex; |
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118 | uint16_t vertex_offset; |
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119 | uint16_t vertex_count; |
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120 | uint16_t vertex_index; |
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121 | uint16_t vertex_used; |
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122 | uint32_t vertex_id; |
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123 | float vertex_ptr[4*1024]; |
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124 | dri_bo *vertex_bo; |
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125 | |||
126 | uint8_t surface_data[16*1024]; |
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127 | |||
128 | uint16_t surface_table; |
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129 | uint32_t surface_reloc; |
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130 | dri_bo *surface_bo; |
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131 | |||
132 | /* 965 render acceleration state */ |
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133 | |||
134 | |||
135 | Bool use_pageflipping; |
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136 | |||
137 | Bool force_fallback; |
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138 | Bool has_kernel_flush; |
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139 | Bool needs_flush; |
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140 | |||
141 | enum last_3d last_3d; |
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142 | |||
143 | /** |
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144 | |||
145 | */ |
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146 | Bool fallback_debug; |
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147 | unsigned debug_flush; |
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148 | Bool has_prime_vmap_flush; |
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149 | } intel_screen_private; |
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150 |