Rev 3258 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
3254 | Serge | 1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
||
3 | * All Rights Reserved. |
||
4 | * |
||
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
6 | * copy of this software and associated documentation files (the |
||
7 | * "Software"), to deal in the Software without restriction, including |
||
8 | * without limitation the rights to use, copy, modify, merge, publish, |
||
9 | * distribute, sub license, and/or sell copies of the Software, and to |
||
10 | * permit persons to whom the Software is furnished to do so, subject to |
||
11 | * the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice (including the |
||
14 | * next paragraph) shall be included in all copies or substantial portions |
||
15 | * of the Software. |
||
16 | * |
||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
||
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
||
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
||
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
||
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
||
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
||
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
||
24 | * |
||
25 | */ |
||
26 | |||
27 | #ifndef _I915_DRM_H_ |
||
28 | #define _I915_DRM_H_ |
||
29 | |||
30 | #include "drm.h" |
||
31 | |||
32 | /* Please note that modifications to all structs defined here are |
||
33 | * subject to backwards-compatibility constraints. |
||
34 | */ |
||
35 | |||
36 | |||
37 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
||
38 | */ |
||
39 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
||
40 | * of chars for next/prev indices */ |
||
41 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 |
||
42 | |||
43 | typedef struct _drm_i915_init { |
||
44 | enum { |
||
45 | I915_INIT_DMA = 0x01, |
||
46 | I915_CLEANUP_DMA = 0x02, |
||
47 | I915_RESUME_DMA = 0x03 |
||
48 | } func; |
||
49 | unsigned int mmio_offset; |
||
50 | int sarea_priv_offset; |
||
51 | unsigned int ring_start; |
||
52 | unsigned int ring_end; |
||
53 | unsigned int ring_size; |
||
54 | unsigned int front_offset; |
||
55 | unsigned int back_offset; |
||
56 | unsigned int depth_offset; |
||
57 | unsigned int w; |
||
58 | unsigned int h; |
||
59 | unsigned int pitch; |
||
60 | unsigned int pitch_bits; |
||
61 | unsigned int back_pitch; |
||
62 | unsigned int depth_pitch; |
||
63 | unsigned int cpp; |
||
64 | unsigned int chipset; |
||
65 | } drm_i915_init_t; |
||
66 | |||
67 | typedef struct _drm_i915_sarea { |
||
68 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
||
69 | int last_upload; /* last time texture was uploaded */ |
||
70 | int last_enqueue; /* last time a buffer was enqueued */ |
||
71 | int last_dispatch; /* age of the most recently dispatched buffer */ |
||
72 | int ctxOwner; /* last context to upload state */ |
||
73 | int texAge; |
||
74 | int pf_enabled; /* is pageflipping allowed? */ |
||
75 | int pf_active; |
||
76 | int pf_current_page; /* which buffer is being displayed? */ |
||
77 | int perf_boxes; /* performance boxes to be displayed */ |
||
78 | int width, height; /* screen size in pixels */ |
||
79 | |||
80 | drm_handle_t front_handle; |
||
81 | int front_offset; |
||
82 | int front_size; |
||
83 | |||
84 | drm_handle_t back_handle; |
||
85 | int back_offset; |
||
86 | int back_size; |
||
87 | |||
88 | drm_handle_t depth_handle; |
||
89 | int depth_offset; |
||
90 | int depth_size; |
||
91 | |||
92 | drm_handle_t tex_handle; |
||
93 | int tex_offset; |
||
94 | int tex_size; |
||
95 | int log_tex_granularity; |
||
96 | int pitch; |
||
97 | int rotation; /* 0, 90, 180 or 270 */ |
||
98 | int rotated_offset; |
||
99 | int rotated_size; |
||
100 | int rotated_pitch; |
||
101 | int virtualX, virtualY; |
||
102 | |||
103 | unsigned int front_tiled; |
||
104 | unsigned int back_tiled; |
||
105 | unsigned int depth_tiled; |
||
106 | unsigned int rotated_tiled; |
||
107 | unsigned int rotated2_tiled; |
||
108 | |||
109 | int pipeA_x; |
||
110 | int pipeA_y; |
||
111 | int pipeA_w; |
||
112 | int pipeA_h; |
||
113 | int pipeB_x; |
||
114 | int pipeB_y; |
||
115 | int pipeB_w; |
||
116 | int pipeB_h; |
||
117 | |||
118 | /* fill out some space for old userspace triple buffer */ |
||
119 | drm_handle_t unused_handle; |
||
120 | __u32 unused1, unused2, unused3; |
||
121 | |||
122 | /* buffer object handles for static buffers. May change |
||
123 | * over the lifetime of the client. |
||
124 | */ |
||
125 | __u32 front_bo_handle; |
||
126 | __u32 back_bo_handle; |
||
127 | __u32 unused_bo_handle; |
||
128 | __u32 depth_bo_handle; |
||
129 | |||
130 | } drm_i915_sarea_t; |
||
131 | |||
132 | /* due to userspace building against these headers we need some compat here */ |
||
133 | #define planeA_x pipeA_x |
||
134 | #define planeA_y pipeA_y |
||
135 | #define planeA_w pipeA_w |
||
136 | #define planeA_h pipeA_h |
||
137 | #define planeB_x pipeB_x |
||
138 | #define planeB_y pipeB_y |
||
139 | #define planeB_w pipeB_w |
||
140 | #define planeB_h pipeB_h |
||
141 | |||
142 | /* Flags for perf_boxes |
||
143 | */ |
||
144 | #define I915_BOX_RING_EMPTY 0x1 |
||
145 | #define I915_BOX_FLIP 0x2 |
||
146 | #define I915_BOX_WAIT 0x4 |
||
147 | #define I915_BOX_TEXTURE_LOAD 0x8 |
||
148 | #define I915_BOX_LOST_CONTEXT 0x10 |
||
149 | |||
150 | /* I915 specific ioctls |
||
151 | * The device specific ioctl range is 0x40 to 0x79. |
||
152 | */ |
||
153 | #define DRM_I915_INIT 0x00 |
||
154 | #define DRM_I915_FLUSH 0x01 |
||
155 | #define DRM_I915_FLIP 0x02 |
||
156 | #define DRM_I915_BATCHBUFFER 0x03 |
||
157 | #define DRM_I915_IRQ_EMIT 0x04 |
||
158 | #define DRM_I915_IRQ_WAIT 0x05 |
||
159 | #define DRM_I915_GETPARAM 0x06 |
||
160 | #define DRM_I915_SETPARAM 0x07 |
||
161 | #define DRM_I915_ALLOC 0x08 |
||
162 | #define DRM_I915_FREE 0x09 |
||
163 | #define DRM_I915_INIT_HEAP 0x0a |
||
164 | #define DRM_I915_CMDBUFFER 0x0b |
||
165 | #define DRM_I915_DESTROY_HEAP 0x0c |
||
166 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
||
167 | #define DRM_I915_GET_VBLANK_PIPE 0x0e |
||
168 | #define DRM_I915_VBLANK_SWAP 0x0f |
||
169 | #define DRM_I915_HWS_ADDR 0x11 |
||
170 | #define DRM_I915_GEM_INIT 0x13 |
||
171 | #define DRM_I915_GEM_EXECBUFFER 0x14 |
||
172 | #define DRM_I915_GEM_PIN 0x15 |
||
173 | #define DRM_I915_GEM_UNPIN 0x16 |
||
174 | #define DRM_I915_GEM_BUSY 0x17 |
||
175 | #define DRM_I915_GEM_THROTTLE 0x18 |
||
176 | #define DRM_I915_GEM_ENTERVT 0x19 |
||
177 | #define DRM_I915_GEM_LEAVEVT 0x1a |
||
178 | #define DRM_I915_GEM_CREATE 0x1b |
||
179 | #define DRM_I915_GEM_PREAD 0x1c |
||
180 | #define DRM_I915_GEM_PWRITE 0x1d |
||
181 | #define DRM_I915_GEM_MMAP 0x1e |
||
182 | #define DRM_I915_GEM_SET_DOMAIN 0x1f |
||
183 | #define DRM_I915_GEM_SW_FINISH 0x20 |
||
184 | #define DRM_I915_GEM_SET_TILING 0x21 |
||
185 | #define DRM_I915_GEM_GET_TILING 0x22 |
||
186 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
||
187 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
||
188 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
||
189 | #define DRM_I915_GEM_MADVISE 0x26 |
||
190 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
||
191 | #define DRM_I915_OVERLAY_ATTRS 0x28 |
||
192 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
||
193 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
||
194 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
||
195 | #define DRM_I915_GEM_WAIT 0x2c |
||
196 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
||
197 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
||
198 | #define DRM_I915_GEM_SET_CACHEING 0x2f |
||
199 | #define DRM_I915_GEM_GET_CACHEING 0x30 |
||
200 | #define DRM_I915_REG_READ 0x31 |
||
201 | |||
3258 | Serge | 202 | #define DRM_IOCTL_I915_INIT |
203 | #define DRM_IOCTL_I915_FLUSH |
||
204 | #define DRM_IOCTL_I915_FLIP |
||
205 | #define DRM_IOCTL_I915_BATCHBUFFER |
||
206 | #define DRM_IOCTL_I915_IRQ_EMIT |
||
207 | #define DRM_IOCTL_I915_IRQ_WAIT |
||
208 | #define DRM_IOCTL_I915_GETPARAM SRV_GET_PARAM |
||
209 | #define DRM_IOCTL_I915_SETPARAM |
||
210 | #define DRM_IOCTL_I915_ALLOC |
||
211 | #define DRM_IOCTL_I915_FREE |
||
212 | #define DRM_IOCTL_I915_INIT_HEAP |
||
213 | #define DRM_IOCTL_I915_CMDBUFFER |
||
214 | #define DRM_IOCTL_I915_DESTROY_HEAP |
||
215 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE |
||
216 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE |
||
217 | #define DRM_IOCTL_I915_VBLANK_SWAP |
||
218 | #define DRM_IOCTL_I915_HWS_ADDR |
||
219 | #define DRM_IOCTL_I915_GEM_INIT |
||
220 | #define DRM_IOCTL_I915_GEM_EXECBUFFER |
||
3263 | Serge | 221 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2 |
3258 | Serge | 222 | #define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN |
223 | #define DRM_IOCTL_I915_GEM_UNPIN |
||
224 | #define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY |
||
225 | #define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHEING |
||
226 | #define DRM_IOCTL_I915_GEM_GET_CACHEING |
||
3263 | Serge | 227 | #define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE |
3258 | Serge | 228 | #define DRM_IOCTL_I915_GEM_ENTERVT |
229 | #define DRM_IOCTL_I915_GEM_LEAVEVT |
||
230 | #define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE |
||
231 | #define DRM_IOCTL_I915_GEM_PREAD |
||
232 | #define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE |
||
233 | #define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP |
||
234 | #define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT |
||
235 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN |
||
236 | #define DRM_IOCTL_I915_GEM_SW_FINISH |
||
237 | #define DRM_IOCTL_I915_GEM_SET_TILING |
||
238 | #define DRM_IOCTL_I915_GEM_GET_TILING |
||
239 | #define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE |
||
240 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID |
||
241 | #define DRM_IOCTL_I915_GEM_MADVISE |
||
242 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE |
||
243 | #define DRM_IOCTL_I915_OVERLAY_ATTRS |
||
244 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY |
||
245 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY |
||
246 | #define DRM_IOCTL_I915_GEM_WAIT |
||
247 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE |
||
248 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY |
||
249 | #define DRM_IOCTL_I915_REG_READ |
||
3254 | Serge | 250 | |
251 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
||
252 | * on the security mechanisms provided by hardware. |
||
253 | */ |
||
254 | typedef struct drm_i915_batchbuffer { |
||
255 | int start; /* agp offset */ |
||
256 | int used; /* nr bytes in use */ |
||
257 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
||
258 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
||
259 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
||
260 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
||
261 | } drm_i915_batchbuffer_t; |
||
262 | |||
263 | /* As above, but pass a pointer to userspace buffer which can be |
||
264 | * validated by the kernel prior to sending to hardware. |
||
265 | */ |
||
266 | typedef struct _drm_i915_cmdbuffer { |
||
267 | char *buf; /* pointer to userspace command buffer */ |
||
268 | int sz; /* nr bytes in buf */ |
||
269 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
||
270 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
||
271 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
||
272 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
||
273 | } drm_i915_cmdbuffer_t; |
||
274 | |||
275 | /* Userspace can request & wait on irq's: |
||
276 | */ |
||
277 | typedef struct drm_i915_irq_emit { |
||
278 | int *irq_seq; |
||
279 | } drm_i915_irq_emit_t; |
||
280 | |||
281 | typedef struct drm_i915_irq_wait { |
||
282 | int irq_seq; |
||
283 | } drm_i915_irq_wait_t; |
||
284 | |||
285 | /* Ioctl to query kernel params: |
||
286 | */ |
||
287 | #define I915_PARAM_IRQ_ACTIVE 1 |
||
288 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 |
||
289 | #define I915_PARAM_LAST_DISPATCH 3 |
||
290 | #define I915_PARAM_CHIPSET_ID 4 |
||
291 | #define I915_PARAM_HAS_GEM 5 |
||
292 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
||
293 | #define I915_PARAM_HAS_OVERLAY 7 |
||
294 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
||
295 | #define I915_PARAM_HAS_EXECBUF2 9 |
||
296 | #define I915_PARAM_HAS_BSD 10 |
||
297 | #define I915_PARAM_HAS_BLT 11 |
||
298 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
||
299 | #define I915_PARAM_HAS_COHERENT_RINGS 13 |
||
300 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
||
301 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
||
302 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
||
303 | #define I915_PARAM_HAS_LLC 17 |
||
304 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 |
||
305 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
||
306 | |||
307 | typedef struct drm_i915_getparam { |
||
308 | int param; |
||
309 | int *value; |
||
310 | } drm_i915_getparam_t; |
||
311 | |||
312 | /* Ioctl to set kernel params: |
||
313 | */ |
||
314 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
||
315 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
||
316 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
||
317 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
||
318 | |||
319 | typedef struct drm_i915_setparam { |
||
320 | int param; |
||
321 | int value; |
||
322 | } drm_i915_setparam_t; |
||
323 | |||
324 | /* A memory manager for regions of shared memory: |
||
325 | */ |
||
326 | #define I915_MEM_REGION_AGP 1 |
||
327 | |||
328 | typedef struct drm_i915_mem_alloc { |
||
329 | int region; |
||
330 | int alignment; |
||
331 | int size; |
||
332 | int *region_offset; /* offset from start of fb or agp */ |
||
333 | } drm_i915_mem_alloc_t; |
||
334 | |||
335 | typedef struct drm_i915_mem_free { |
||
336 | int region; |
||
337 | int region_offset; |
||
338 | } drm_i915_mem_free_t; |
||
339 | |||
340 | typedef struct drm_i915_mem_init_heap { |
||
341 | int region; |
||
342 | int size; |
||
343 | int start; |
||
344 | } drm_i915_mem_init_heap_t; |
||
345 | |||
346 | /* Allow memory manager to be torn down and re-initialized (eg on |
||
347 | * rotate): |
||
348 | */ |
||
349 | typedef struct drm_i915_mem_destroy_heap { |
||
350 | int region; |
||
351 | } drm_i915_mem_destroy_heap_t; |
||
352 | |||
353 | /* Allow X server to configure which pipes to monitor for vblank signals |
||
354 | */ |
||
355 | #define DRM_I915_VBLANK_PIPE_A 1 |
||
356 | #define DRM_I915_VBLANK_PIPE_B 2 |
||
357 | |||
358 | typedef struct drm_i915_vblank_pipe { |
||
359 | int pipe; |
||
360 | } drm_i915_vblank_pipe_t; |
||
361 | |||
362 | /* Schedule buffer swap at given vertical blank: |
||
363 | */ |
||
364 | typedef struct drm_i915_vblank_swap { |
||
365 | drm_drawable_t drawable; |
||
366 | enum drm_vblank_seq_type seqtype; |
||
367 | unsigned int sequence; |
||
368 | } drm_i915_vblank_swap_t; |
||
369 | |||
370 | typedef struct drm_i915_hws_addr { |
||
371 | __u64 addr; |
||
372 | } drm_i915_hws_addr_t; |
||
373 | |||
374 | struct drm_i915_gem_init { |
||
375 | /** |
||
376 | * Beginning offset in the GTT to be managed by the DRM memory |
||
377 | * manager. |
||
378 | */ |
||
379 | __u64 gtt_start; |
||
380 | /** |
||
381 | * Ending offset in the GTT to be managed by the DRM memory |
||
382 | * manager. |
||
383 | */ |
||
384 | __u64 gtt_end; |
||
385 | }; |
||
386 | |||
387 | struct drm_i915_gem_create { |
||
388 | /** |
||
389 | * Requested size for the object. |
||
390 | * |
||
391 | * The (page-aligned) allocated size for the object will be returned. |
||
392 | */ |
||
393 | __u64 size; |
||
394 | /** |
||
395 | * Returned handle for the object. |
||
396 | * |
||
397 | * Object handles are nonzero. |
||
398 | */ |
||
399 | __u32 handle; |
||
400 | __u32 pad; |
||
401 | }; |
||
402 | |||
403 | struct drm_i915_gem_pread { |
||
404 | /** Handle for the object being read. */ |
||
405 | __u32 handle; |
||
406 | __u32 pad; |
||
407 | /** Offset into the object to read from */ |
||
408 | __u64 offset; |
||
409 | /** Length of data to read */ |
||
410 | __u64 size; |
||
411 | /** |
||
412 | * Pointer to write the data into. |
||
413 | * |
||
414 | * This is a fixed-size type for 32/64 compatibility. |
||
415 | */ |
||
416 | __u64 data_ptr; |
||
417 | }; |
||
418 | |||
419 | struct drm_i915_gem_pwrite { |
||
420 | /** Handle for the object being written to. */ |
||
421 | __u32 handle; |
||
422 | __u32 pad; |
||
423 | /** Offset into the object to write to */ |
||
424 | __u64 offset; |
||
425 | /** Length of data to write */ |
||
426 | __u64 size; |
||
427 | /** |
||
428 | * Pointer to read the data from. |
||
429 | * |
||
430 | * This is a fixed-size type for 32/64 compatibility. |
||
431 | */ |
||
432 | __u64 data_ptr; |
||
433 | }; |
||
434 | |||
435 | struct drm_i915_gem_mmap { |
||
436 | /** Handle for the object being mapped. */ |
||
437 | __u32 handle; |
||
438 | __u32 pad; |
||
439 | /** Offset in the object to map. */ |
||
440 | __u64 offset; |
||
441 | /** |
||
442 | * Length of data to map. |
||
443 | * |
||
444 | * The value will be page-aligned. |
||
445 | */ |
||
446 | __u64 size; |
||
447 | /** |
||
448 | * Returned pointer the data was mapped at. |
||
449 | * |
||
450 | * This is a fixed-size type for 32/64 compatibility. |
||
451 | */ |
||
452 | __u64 addr_ptr; |
||
453 | }; |
||
454 | |||
455 | struct drm_i915_gem_mmap_gtt { |
||
456 | /** Handle for the object being mapped. */ |
||
457 | __u32 handle; |
||
458 | __u32 pad; |
||
459 | /** |
||
460 | * Fake offset to use for subsequent mmap call |
||
461 | * |
||
462 | * This is a fixed-size type for 32/64 compatibility. |
||
463 | */ |
||
464 | __u64 offset; |
||
465 | }; |
||
466 | |||
467 | struct drm_i915_gem_set_domain { |
||
468 | /** Handle for the object */ |
||
469 | __u32 handle; |
||
470 | |||
471 | /** New read domains */ |
||
472 | __u32 read_domains; |
||
473 | |||
474 | /** New write domain */ |
||
475 | __u32 write_domain; |
||
476 | }; |
||
477 | |||
478 | struct drm_i915_gem_sw_finish { |
||
479 | /** Handle for the object */ |
||
480 | __u32 handle; |
||
481 | }; |
||
482 | |||
483 | struct drm_i915_gem_relocation_entry { |
||
484 | /** |
||
485 | * Handle of the buffer being pointed to by this relocation entry. |
||
486 | * |
||
487 | * It's appealing to make this be an index into the mm_validate_entry |
||
488 | * list to refer to the buffer, but this allows the driver to create |
||
489 | * a relocation list for state buffers and not re-write it per |
||
490 | * exec using the buffer. |
||
491 | */ |
||
492 | __u32 target_handle; |
||
493 | |||
494 | /** |
||
495 | * Value to be added to the offset of the target buffer to make up |
||
496 | * the relocation entry. |
||
497 | */ |
||
498 | __u32 delta; |
||
499 | |||
500 | /** Offset in the buffer the relocation entry will be written into */ |
||
501 | __u64 offset; |
||
502 | |||
503 | /** |
||
504 | * Offset value of the target buffer that the relocation entry was last |
||
505 | * written as. |
||
506 | * |
||
507 | * If the buffer has the same offset as last time, we can skip syncing |
||
508 | * and writing the relocation. This value is written back out by |
||
509 | * the execbuffer ioctl when the relocation is written. |
||
510 | */ |
||
511 | __u64 presumed_offset; |
||
512 | |||
513 | /** |
||
514 | * Target memory domains read by this operation. |
||
515 | */ |
||
516 | __u32 read_domains; |
||
517 | |||
518 | /** |
||
519 | * Target memory domains written by this operation. |
||
520 | * |
||
521 | * Note that only one domain may be written by the whole |
||
522 | * execbuffer operation, so that where there are conflicts, |
||
523 | * the application will get -EINVAL back. |
||
524 | */ |
||
525 | __u32 write_domain; |
||
526 | }; |
||
527 | |||
528 | /** @{ |
||
529 | * Intel memory domains |
||
530 | * |
||
531 | * Most of these just align with the various caches in |
||
532 | * the system and are used to flush and invalidate as |
||
533 | * objects end up cached in different domains. |
||
534 | */ |
||
535 | /** CPU cache */ |
||
536 | #define I915_GEM_DOMAIN_CPU 0x00000001 |
||
537 | /** Render cache, used by 2D and 3D drawing */ |
||
538 | #define I915_GEM_DOMAIN_RENDER 0x00000002 |
||
539 | /** Sampler cache, used by texture engine */ |
||
540 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
||
541 | /** Command queue, used to load batch buffers */ |
||
542 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 |
||
543 | /** Instruction cache, used by shader programs */ |
||
544 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
||
545 | /** Vertex address cache */ |
||
546 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 |
||
547 | /** GTT domain - aperture and scanout */ |
||
548 | #define I915_GEM_DOMAIN_GTT 0x00000040 |
||
549 | /** @} */ |
||
550 | |||
551 | struct drm_i915_gem_exec_object { |
||
552 | /** |
||
553 | * User's handle for a buffer to be bound into the GTT for this |
||
554 | * operation. |
||
555 | */ |
||
556 | __u32 handle; |
||
557 | |||
558 | /** Number of relocations to be performed on this buffer */ |
||
559 | __u32 relocation_count; |
||
560 | /** |
||
561 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
||
562 | * the relocations to be performed in this buffer. |
||
563 | */ |
||
564 | __u64 relocs_ptr; |
||
565 | |||
566 | /** Required alignment in graphics aperture */ |
||
567 | __u64 alignment; |
||
568 | |||
569 | /** |
||
570 | * Returned value of the updated offset of the object, for future |
||
571 | * presumed_offset writes. |
||
572 | */ |
||
573 | __u64 offset; |
||
574 | }; |
||
575 | |||
576 | struct drm_i915_gem_execbuffer { |
||
577 | /** |
||
578 | * List of buffers to be validated with their relocations to be |
||
579 | * performend on them. |
||
580 | * |
||
581 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. |
||
582 | * |
||
583 | * These buffers must be listed in an order such that all relocations |
||
584 | * a buffer is performing refer to buffers that have already appeared |
||
585 | * in the validate list. |
||
586 | */ |
||
587 | __u64 buffers_ptr; |
||
588 | __u32 buffer_count; |
||
589 | |||
590 | /** Offset in the batchbuffer to start execution from. */ |
||
591 | __u32 batch_start_offset; |
||
592 | /** Bytes used in batchbuffer from batch_start_offset */ |
||
593 | __u32 batch_len; |
||
594 | __u32 DR1; |
||
595 | __u32 DR4; |
||
596 | __u32 num_cliprects; |
||
597 | /** This is a struct drm_clip_rect *cliprects */ |
||
598 | __u64 cliprects_ptr; |
||
599 | }; |
||
600 | |||
601 | struct drm_i915_gem_exec_object2 { |
||
602 | /** |
||
603 | * User's handle for a buffer to be bound into the GTT for this |
||
604 | * operation. |
||
605 | */ |
||
606 | __u32 handle; |
||
607 | |||
608 | /** Number of relocations to be performed on this buffer */ |
||
609 | __u32 relocation_count; |
||
610 | /** |
||
611 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
||
612 | * the relocations to be performed in this buffer. |
||
613 | */ |
||
614 | __u64 relocs_ptr; |
||
615 | |||
616 | /** Required alignment in graphics aperture */ |
||
617 | __u64 alignment; |
||
618 | |||
619 | /** |
||
620 | * Returned value of the updated offset of the object, for future |
||
621 | * presumed_offset writes. |
||
622 | */ |
||
623 | __u64 offset; |
||
624 | |||
625 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
||
626 | __u64 flags; |
||
627 | __u64 rsvd1; |
||
628 | __u64 rsvd2; |
||
629 | }; |
||
630 | |||
631 | struct drm_i915_gem_execbuffer2 { |
||
632 | /** |
||
633 | * List of gem_exec_object2 structs |
||
634 | */ |
||
635 | __u64 buffers_ptr; |
||
636 | __u32 buffer_count; |
||
637 | |||
638 | /** Offset in the batchbuffer to start execution from. */ |
||
639 | __u32 batch_start_offset; |
||
640 | /** Bytes used in batchbuffer from batch_start_offset */ |
||
641 | __u32 batch_len; |
||
642 | __u32 DR1; |
||
643 | __u32 DR4; |
||
644 | __u32 num_cliprects; |
||
645 | /** This is a struct drm_clip_rect *cliprects */ |
||
646 | __u64 cliprects_ptr; |
||
647 | #define I915_EXEC_RING_MASK (7<<0) |
||
648 | #define I915_EXEC_DEFAULT (0<<0) |
||
649 | #define I915_EXEC_RENDER (1<<0) |
||
650 | #define I915_EXEC_BSD (2<<0) |
||
651 | #define I915_EXEC_BLT (3<<0) |
||
652 | |||
653 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. |
||
654 | * Gen6+ only supports relative addressing to dynamic state (default) and |
||
655 | * absolute addressing. |
||
656 | * |
||
657 | * These flags are ignored for the BSD and BLT rings. |
||
658 | */ |
||
659 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
||
660 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
||
661 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
||
662 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
||
663 | __u64 flags; |
||
664 | __u64 rsvd1; /* now used for context info */ |
||
665 | __u64 rsvd2; |
||
666 | }; |
||
667 | |||
668 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
||
669 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
||
670 | |||
671 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
||
672 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
||
673 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
||
674 | #define i915_execbuffer2_get_context_id(eb2) \ |
||
675 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
||
676 | |||
677 | struct drm_i915_gem_pin { |
||
678 | /** Handle of the buffer to be pinned. */ |
||
679 | __u32 handle; |
||
680 | __u32 pad; |
||
681 | |||
682 | /** alignment required within the aperture */ |
||
683 | __u64 alignment; |
||
684 | |||
685 | /** Returned GTT offset of the buffer. */ |
||
686 | __u64 offset; |
||
687 | }; |
||
688 | |||
689 | struct drm_i915_gem_unpin { |
||
690 | /** Handle of the buffer to be unpinned. */ |
||
691 | __u32 handle; |
||
692 | __u32 pad; |
||
693 | }; |
||
694 | |||
695 | struct drm_i915_gem_busy { |
||
696 | /** Handle of the buffer to check for busy */ |
||
697 | __u32 handle; |
||
698 | |||
699 | /** Return busy status (1 if busy, 0 if idle). |
||
700 | * The high word is used to indicate on which rings the object |
||
701 | * currently resides: |
||
702 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
||
703 | */ |
||
704 | __u32 busy; |
||
705 | }; |
||
706 | |||
707 | #define I915_CACHEING_NONE 0 |
||
708 | #define I915_CACHEING_CACHED 1 |
||
709 | |||
710 | struct drm_i915_gem_cacheing { |
||
711 | /** |
||
712 | * Handle of the buffer to set/get the cacheing level of. */ |
||
713 | __u32 handle; |
||
714 | |||
715 | /** |
||
716 | * Cacheing level to apply or return value |
||
717 | * |
||
718 | * bits0-15 are for generic cacheing control (i.e. the above defined |
||
719 | * values). bits16-31 are reserved for platform-specific variations |
||
720 | * (e.g. l3$ caching on gen7). */ |
||
721 | __u32 cacheing; |
||
722 | }; |
||
723 | |||
724 | #define I915_TILING_NONE 0 |
||
725 | #define I915_TILING_X 1 |
||
726 | #define I915_TILING_Y 2 |
||
727 | |||
728 | #define I915_BIT_6_SWIZZLE_NONE 0 |
||
729 | #define I915_BIT_6_SWIZZLE_9 1 |
||
730 | #define I915_BIT_6_SWIZZLE_9_10 2 |
||
731 | #define I915_BIT_6_SWIZZLE_9_11 3 |
||
732 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
||
733 | /* Not seen by userland */ |
||
734 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
||
735 | /* Seen by userland. */ |
||
736 | #define I915_BIT_6_SWIZZLE_9_17 6 |
||
737 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
||
738 | |||
739 | struct drm_i915_gem_set_tiling { |
||
740 | /** Handle of the buffer to have its tiling state updated */ |
||
741 | __u32 handle; |
||
742 | |||
743 | /** |
||
744 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
||
745 | * I915_TILING_Y). |
||
746 | * |
||
747 | * This value is to be set on request, and will be updated by the |
||
748 | * kernel on successful return with the actual chosen tiling layout. |
||
749 | * |
||
750 | * The tiling mode may be demoted to I915_TILING_NONE when the system |
||
751 | * has bit 6 swizzling that can't be managed correctly by GEM. |
||
752 | * |
||
753 | * Buffer contents become undefined when changing tiling_mode. |
||
754 | */ |
||
755 | __u32 tiling_mode; |
||
756 | |||
757 | /** |
||
758 | * Stride in bytes for the object when in I915_TILING_X or |
||
759 | * I915_TILING_Y. |
||
760 | */ |
||
761 | __u32 stride; |
||
762 | |||
763 | /** |
||
764 | * Returned address bit 6 swizzling required for CPU access through |
||
765 | * mmap mapping. |
||
766 | */ |
||
767 | __u32 swizzle_mode; |
||
768 | }; |
||
769 | |||
770 | struct drm_i915_gem_get_tiling { |
||
771 | /** Handle of the buffer to get tiling state for. */ |
||
772 | __u32 handle; |
||
773 | |||
774 | /** |
||
775 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
||
776 | * I915_TILING_Y). |
||
777 | */ |
||
778 | __u32 tiling_mode; |
||
779 | |||
780 | /** |
||
781 | * Returned address bit 6 swizzling required for CPU access through |
||
782 | * mmap mapping. |
||
783 | */ |
||
784 | __u32 swizzle_mode; |
||
785 | }; |
||
786 | |||
787 | struct drm_i915_gem_get_aperture { |
||
788 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
||
789 | __u64 aper_size; |
||
790 | |||
791 | /** |
||
792 | * Available space in the aperture used by i915_gem_execbuffer, in |
||
793 | * bytes |
||
794 | */ |
||
795 | __u64 aper_available_size; |
||
796 | }; |
||
797 | |||
798 | struct drm_i915_get_pipe_from_crtc_id { |
||
799 | /** ID of CRTC being requested **/ |
||
800 | __u32 crtc_id; |
||
801 | |||
802 | /** pipe of requested CRTC **/ |
||
803 | __u32 pipe; |
||
804 | }; |
||
805 | |||
806 | #define I915_MADV_WILLNEED 0 |
||
807 | #define I915_MADV_DONTNEED 1 |
||
808 | #define __I915_MADV_PURGED 2 /* internal state */ |
||
809 | |||
810 | struct drm_i915_gem_madvise { |
||
811 | /** Handle of the buffer to change the backing store advice */ |
||
812 | __u32 handle; |
||
813 | |||
814 | /* Advice: either the buffer will be needed again in the near future, |
||
815 | * or wont be and could be discarded under memory pressure. |
||
816 | */ |
||
817 | __u32 madv; |
||
818 | |||
819 | /** Whether the backing store still exists. */ |
||
820 | __u32 retained; |
||
821 | }; |
||
822 | |||
823 | /* flags */ |
||
824 | #define I915_OVERLAY_TYPE_MASK 0xff |
||
825 | #define I915_OVERLAY_YUV_PLANAR 0x01 |
||
826 | #define I915_OVERLAY_YUV_PACKED 0x02 |
||
827 | #define I915_OVERLAY_RGB 0x03 |
||
828 | |||
829 | #define I915_OVERLAY_DEPTH_MASK 0xff00 |
||
830 | #define I915_OVERLAY_RGB24 0x1000 |
||
831 | #define I915_OVERLAY_RGB16 0x2000 |
||
832 | #define I915_OVERLAY_RGB15 0x3000 |
||
833 | #define I915_OVERLAY_YUV422 0x0100 |
||
834 | #define I915_OVERLAY_YUV411 0x0200 |
||
835 | #define I915_OVERLAY_YUV420 0x0300 |
||
836 | #define I915_OVERLAY_YUV410 0x0400 |
||
837 | |||
838 | #define I915_OVERLAY_SWAP_MASK 0xff0000 |
||
839 | #define I915_OVERLAY_NO_SWAP 0x000000 |
||
840 | #define I915_OVERLAY_UV_SWAP 0x010000 |
||
841 | #define I915_OVERLAY_Y_SWAP 0x020000 |
||
842 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
||
843 | |||
844 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 |
||
845 | #define I915_OVERLAY_ENABLE 0x01000000 |
||
846 | |||
847 | struct drm_intel_overlay_put_image { |
||
848 | /* various flags and src format description */ |
||
849 | __u32 flags; |
||
850 | /* source picture description */ |
||
851 | __u32 bo_handle; |
||
852 | /* stride values and offsets are in bytes, buffer relative */ |
||
853 | __u16 stride_Y; /* stride for packed formats */ |
||
854 | __u16 stride_UV; |
||
855 | __u32 offset_Y; /* offset for packet formats */ |
||
856 | __u32 offset_U; |
||
857 | __u32 offset_V; |
||
858 | /* in pixels */ |
||
859 | __u16 src_width; |
||
860 | __u16 src_height; |
||
861 | /* to compensate the scaling factors for partially covered surfaces */ |
||
862 | __u16 src_scan_width; |
||
863 | __u16 src_scan_height; |
||
864 | /* output crtc description */ |
||
865 | __u32 crtc_id; |
||
866 | __u16 dst_x; |
||
867 | __u16 dst_y; |
||
868 | __u16 dst_width; |
||
869 | __u16 dst_height; |
||
870 | }; |
||
871 | |||
872 | /* flags */ |
||
873 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
||
874 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
||
875 | struct drm_intel_overlay_attrs { |
||
876 | __u32 flags; |
||
877 | __u32 color_key; |
||
878 | __s32 brightness; |
||
879 | __u32 contrast; |
||
880 | __u32 saturation; |
||
881 | __u32 gamma0; |
||
882 | __u32 gamma1; |
||
883 | __u32 gamma2; |
||
884 | __u32 gamma3; |
||
885 | __u32 gamma4; |
||
886 | __u32 gamma5; |
||
887 | }; |
||
888 | |||
889 | /* |
||
890 | * Intel sprite handling |
||
891 | * |
||
892 | * Color keying works with a min/mask/max tuple. Both source and destination |
||
893 | * color keying is allowed. |
||
894 | * |
||
895 | * Source keying: |
||
896 | * Sprite pixels within the min & max values, masked against the color channels |
||
897 | * specified in the mask field, will be transparent. All other pixels will |
||
898 | * be displayed on top of the primary plane. For RGB surfaces, only the min |
||
899 | * and mask fields will be used; ranged compares are not allowed. |
||
900 | * |
||
901 | * Destination keying: |
||
902 | * Primary plane pixels that match the min value, masked against the color |
||
903 | * channels specified in the mask field, will be replaced by corresponding |
||
904 | * pixels from the sprite plane. |
||
905 | * |
||
906 | * Note that source & destination keying are exclusive; only one can be |
||
907 | * active on a given plane. |
||
908 | */ |
||
909 | |||
910 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
||
911 | #define I915_SET_COLORKEY_DESTINATION (1<<1) |
||
912 | #define I915_SET_COLORKEY_SOURCE (1<<2) |
||
913 | struct drm_intel_sprite_colorkey { |
||
914 | __u32 plane_id; |
||
915 | __u32 min_value; |
||
916 | __u32 channel_mask; |
||
917 | __u32 max_value; |
||
918 | __u32 flags; |
||
919 | }; |
||
920 | |||
921 | struct drm_i915_gem_wait { |
||
922 | /** Handle of BO we shall wait on */ |
||
923 | __u32 bo_handle; |
||
924 | __u32 flags; |
||
925 | /** Number of nanoseconds to wait, Returns time remaining. */ |
||
926 | __s64 timeout_ns; |
||
927 | }; |
||
928 | |||
929 | struct drm_i915_gem_context_create { |
||
930 | /* output: id of new context*/ |
||
931 | __u32 ctx_id; |
||
932 | __u32 pad; |
||
933 | }; |
||
934 | |||
935 | struct drm_i915_gem_context_destroy { |
||
936 | __u32 ctx_id; |
||
937 | __u32 pad; |
||
938 | }; |
||
939 | |||
940 | struct drm_i915_reg_read { |
||
941 | __u64 offset; |
||
942 | __u64 val; /* Return value */ |
||
943 | }; |
||
944 | #endif /* _I915_DRM_H_ */2) |