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3291 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | |||
28 | #ifndef GEN4_RENDER_H |
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29 | #define GEN4_RENDER_H |
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30 | |||
31 | #define GEN4_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ |
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32 | ((Pipeline) << 27) | \ |
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33 | ((Opcode) << 24) | \ |
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34 | ((Subopcode) << 16)) |
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35 | |||
36 | #define GEN4_URB_FENCE GEN4_3D(0, 0, 0) |
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37 | #define GEN4_CS_URB_STATE GEN4_3D(0, 0, 1) |
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38 | #define GEN4_CONSTANT_BUFFER GEN4_3D(0, 0, 2) |
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39 | #define GEN4_STATE_PREFETCH GEN4_3D(0, 0, 3) |
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40 | |||
41 | #define GEN4_STATE_BASE_ADDRESS GEN4_3D(0, 1, 1) |
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42 | #define GEN4_STATE_SIP GEN4_3D(0, 1, 2) |
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43 | #define GEN4_PIPELINE_SELECT GEN4_3D(0, 1, 4) |
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44 | |||
45 | #define NEW_PIPELINE_SELECT GEN4_3D(1, 1, 4) |
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46 | |||
47 | #define GEN4_MEDIA_STATE_POINTERS GEN4_3D(2, 0, 0) |
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48 | #define GEN4_MEDIA_OBJECT GEN4_3D(2, 1, 0) |
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49 | |||
50 | #define GEN4_3DSTATE_PIPELINED_POINTERS GEN4_3D(3, 0, 0) |
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51 | #define GEN4_3DSTATE_BINDING_TABLE_POINTERS GEN4_3D(3, 0, 1) |
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52 | |||
53 | #define GEN4_3DSTATE_VERTEX_BUFFERS GEN4_3D(3, 0, 8) |
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54 | #define GEN4_3DSTATE_VERTEX_ELEMENTS GEN4_3D(3, 0, 9) |
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55 | #define GEN4_3DSTATE_INDEX_BUFFER GEN4_3D(3, 0, 0xa) |
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56 | #define GEN4_3DSTATE_VF_STATISTICS GEN4_3D(3, 0, 0xb) |
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57 | |||
58 | #define GEN4_3DSTATE_DRAWING_RECTANGLE GEN4_3D(3, 1, 0) |
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59 | #define GEN4_3DSTATE_CONSTANT_COLOR GEN4_3D(3, 1, 1) |
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60 | #define GEN4_3DSTATE_SAMPLER_PALETTE_LOAD GEN4_3D(3, 1, 2) |
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61 | #define GEN4_3DSTATE_CHROMA_KEY GEN4_3D(3, 1, 4) |
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62 | #define GEN4_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 1, 5) |
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63 | # define GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 |
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64 | # define GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 |
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65 | |||
66 | #define GEN4_3DSTATE_POLY_STIPPLE_OFFSET GEN4_3D(3, 1, 6) |
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67 | #define GEN4_3DSTATE_POLY_STIPPLE_PATTERN GEN4_3D(3, 1, 7) |
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68 | #define GEN4_3DSTATE_LINE_STIPPLE GEN4_3D(3, 1, 8) |
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69 | #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN4_3D(3, 1, 9) |
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70 | /* These two are BLC and CTG only, not BW or CL */ |
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71 | #define GEN4_3DSTATE_AA_LINE_PARAMS GEN4_3D(3, 1, 0xa) |
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72 | #define GEN4_3DSTATE_GS_SVB_INDEX GEN4_3D(3, 1, 0xb) |
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73 | |||
74 | #define GEN4_PIPE_CONTROL GEN4_3D(3, 2, 0) |
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75 | |||
76 | #define GEN4_3DPRIMITIVE GEN4_3D(3, 3, 0) |
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77 | |||
78 | #define GEN4_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 1, 0x10) |
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79 | /* DW1 */ |
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80 | # define GEN4_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) |
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81 | |||
82 | #define PIPELINE_SELECT_3D 0 |
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83 | #define PIPELINE_SELECT_MEDIA 1 |
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84 | |||
85 | #define UF0_CS_REALLOC (1 << 13) |
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86 | #define UF0_VFE_REALLOC (1 << 12) |
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87 | #define UF0_SF_REALLOC (1 << 11) |
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88 | #define UF0_CLIP_REALLOC (1 << 10) |
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89 | #define UF0_GS_REALLOC (1 << 9) |
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90 | #define UF0_VS_REALLOC (1 << 8) |
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91 | #define UF1_CLIP_FENCE_SHIFT 20 |
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92 | #define UF1_GS_FENCE_SHIFT 10 |
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93 | #define UF1_VS_FENCE_SHIFT 0 |
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94 | #define UF2_CS_FENCE_SHIFT 20 |
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95 | #define UF2_VFE_FENCE_SHIFT 10 |
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96 | #define UF2_SF_FENCE_SHIFT 0 |
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97 | |||
98 | /* for GEN4_STATE_BASE_ADDRESS */ |
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99 | #define BASE_ADDRESS_MODIFY (1 << 0) |
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100 | |||
101 | /* for GEN4_3DSTATE_PIPELINED_POINTERS */ |
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102 | #define GEN4_GS_DISABLE 0 |
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103 | #define GEN4_GS_ENABLE 1 |
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104 | #define GEN4_CLIP_DISABLE 0 |
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105 | #define GEN4_CLIP_ENABLE 1 |
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106 | |||
107 | /* for GEN4_PIPE_CONTROL */ |
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108 | #define GEN4_PIPE_CONTROL_NOWRITE (0 << 14) |
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109 | #define GEN4_PIPE_CONTROL_WRITE_QWORD (1 << 14) |
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110 | #define GEN4_PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
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111 | #define GEN4_PIPE_CONTROL_WRITE_TIME (3 << 14) |
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112 | #define GEN4_PIPE_CONTROL_DEPTH_STALL (1 << 13) |
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113 | #define GEN4_PIPE_CONTROL_WC_FLUSH (1 << 12) |
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114 | #define GEN4_PIPE_CONTROL_IS_FLUSH (1 << 11) |
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115 | #define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) |
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116 | #define GEN4_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
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117 | #define GEN4_PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
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118 | #define GEN4_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
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119 | #define GEN4_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
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120 | |||
121 | /* VERTEX_BUFFER_STATE Structure */ |
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122 | #define VB0_BUFFER_INDEX_SHIFT 27 |
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123 | #define VB0_VERTEXDATA (0 << 26) |
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124 | #define VB0_INSTANCEDATA (1 << 26) |
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125 | #define VB0_BUFFER_PITCH_SHIFT 0 |
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126 | |||
127 | /* VERTEX_ELEMENT_STATE Structure */ |
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128 | #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 |
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129 | #define VE0_VALID (1 << 26) |
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130 | #define VE0_FORMAT_SHIFT 16 |
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131 | #define VE0_OFFSET_SHIFT 0 |
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132 | #define VE1_VFCOMPONENT_0_SHIFT 28 |
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133 | #define VE1_VFCOMPONENT_1_SHIFT 24 |
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134 | #define VE1_VFCOMPONENT_2_SHIFT 20 |
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135 | #define VE1_VFCOMPONENT_3_SHIFT 16 |
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136 | #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 |
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137 | |||
138 | /* 3DPRIMITIVE bits */ |
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139 | #define GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) |
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140 | #define GEN4_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) |
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141 | /* Primitive types are in gen4_defines.h */ |
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142 | #define GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT 10 |
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143 | |||
144 | #define GEN4_SVG_CTL 0x7400 |
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145 | |||
146 | #define GEN4_SVG_CTL_GS_BA (0 << 8) |
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147 | #define GEN4_SVG_CTL_SS_BA (1 << 8) |
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148 | #define GEN4_SVG_CTL_IO_BA (2 << 8) |
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149 | #define GEN4_SVG_CTL_GS_AUB (3 << 8) |
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150 | #define GEN4_SVG_CTL_IO_AUB (4 << 8) |
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151 | #define GEN4_SVG_CTL_SIP (5 << 8) |
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152 | |||
153 | #define GEN4_SVG_RDATA 0x7404 |
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154 | #define GEN4_SVG_WORK_CTL 0x7408 |
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155 | |||
156 | #define GEN4_VF_CTL 0x7500 |
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157 | |||
158 | #define GEN4_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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159 | #define GEN4_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) |
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160 | #define GEN4_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) |
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161 | #define GEN4_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) |
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162 | #define GEN4_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) |
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163 | #define GEN4_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) |
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164 | #define GEN4_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) |
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165 | #define GEN4_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) |
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166 | #define GEN4_VF_CTL_SNAPSHOT_ENABLE (1 << 0) |
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167 | |||
168 | #define GEN4_VF_STRG_VAL 0x7504 |
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169 | #define GEN4_VF_STR_VL_OVR 0x7508 |
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170 | #define GEN4_VF_VC_OVR 0x750c |
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171 | #define GEN4_VF_STR_PSKIP 0x7510 |
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172 | #define GEN4_VF_MAX_PRIM 0x7514 |
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173 | #define GEN4_VF_RDATA 0x7518 |
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174 | |||
175 | #define GEN4_VS_CTL 0x7600 |
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176 | #define GEN4_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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177 | #define GEN4_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) |
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178 | #define GEN4_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) |
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179 | #define GEN4_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) |
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180 | #define GEN4_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) |
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181 | #define GEN4_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
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182 | #define GEN4_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
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183 | #define GEN4_VS_CTL_SNAPSHOT_ENABLE (1 << 0) |
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184 | |||
185 | #define GEN4_VS_STRG_VAL 0x7604 |
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186 | #define GEN4_VS_RDATA 0x7608 |
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187 | |||
188 | #define GEN4_SF_CTL 0x7b00 |
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189 | #define GEN4_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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190 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) |
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191 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) |
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192 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) |
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193 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) |
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194 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) |
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195 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) |
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196 | #define GEN4_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) |
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197 | #define GEN4_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) |
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198 | #define GEN4_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) |
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199 | #define GEN4_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) |
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200 | #define GEN4_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
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201 | #define GEN4_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
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202 | #define GEN4_SF_CTL_SNAPSHOT_ENABLE (1 << 0) |
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203 | |||
204 | #define GEN4_SF_STRG_VAL 0x7b04 |
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205 | #define GEN4_SF_RDATA 0x7b18 |
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206 | |||
207 | #define GEN4_WIZ_CTL 0x7c00 |
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208 | #define GEN4_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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209 | #define GEN4_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 |
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210 | #define GEN4_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) |
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211 | #define GEN4_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) |
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212 | #define GEN4_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) |
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213 | #define GEN4_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) |
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214 | #define GEN4_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) |
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215 | #define GEN4_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) |
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216 | #define GEN4_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) |
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217 | #define GEN4_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
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218 | #define GEN4_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
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219 | #define GEN4_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) |
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220 | |||
221 | #define GEN4_WIZ_STRG_VAL 0x7c04 |
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222 | #define GEN4_WIZ_RDATA 0x7c18 |
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223 | |||
224 | #define GEN4_TS_CTL 0x7e00 |
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225 | #define GEN4_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
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226 | #define GEN4_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) |
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227 | #define GEN4_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) |
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228 | #define GEN4_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) |
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229 | #define GEN4_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) |
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230 | #define GEN4_TS_CTL_SNAPSHOT_ENABLE (1 << 0) |
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231 | |||
232 | #define GEN4_TS_STRG_VAL 0x7e04 |
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233 | #define GEN4_TS_RDATA 0x7e08 |
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234 | |||
235 | #define GEN4_TD_CTL 0x8000 |
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236 | #define GEN4_TD_CTL_MUX_SHIFT 8 |
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237 | #define GEN4_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) |
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238 | #define GEN4_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) |
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239 | #define GEN4_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) |
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240 | #define GEN4_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) |
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241 | #define GEN4_TD_CTL_BREAKPOINT_ENABLE (1 << 2) |
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242 | #define GEN4_TD_CTL2 0x8004 |
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243 | #define GEN4_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) |
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244 | #define GEN4_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) |
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245 | #define GEN4_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) |
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246 | #define GEN4_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 |
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247 | #define GEN4_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) |
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248 | #define GEN4_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) |
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249 | #define GEN4_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) |
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250 | #define GEN4_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) |
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251 | #define GEN4_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) |
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252 | #define GEN4_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) |
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253 | #define GEN4_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) |
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254 | #define GEN4_TD_VF_VS_EMSK 0x8008 |
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255 | #define GEN4_TD_GS_EMSK 0x800c |
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256 | #define GEN4_TD_CLIP_EMSK 0x8010 |
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257 | #define GEN4_TD_SF_EMSK 0x8014 |
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258 | #define GEN4_TD_WIZ_EMSK 0x8018 |
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259 | #define GEN4_TD_0_6_EHTRG_VAL 0x801c |
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260 | #define GEN4_TD_0_7_EHTRG_VAL 0x8020 |
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261 | #define GEN4_TD_0_6_EHTRG_MSK 0x8024 |
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262 | #define GEN4_TD_0_7_EHTRG_MSK 0x8028 |
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263 | #define GEN4_TD_RDATA 0x802c |
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264 | #define GEN4_TD_TS_EMSK 0x8030 |
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265 | |||
266 | #define GEN4_EU_CTL 0x8800 |
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267 | #define GEN4_EU_CTL_SELECT_SHIFT 16 |
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268 | #define GEN4_EU_CTL_DATA_MUX_SHIFT 8 |
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269 | #define GEN4_EU_ATT_0 0x8810 |
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270 | #define GEN4_EU_ATT_1 0x8814 |
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271 | #define GEN4_EU_ATT_DATA_0 0x8820 |
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272 | #define GEN4_EU_ATT_DATA_1 0x8824 |
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273 | #define GEN4_EU_ATT_CLR_0 0x8830 |
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274 | #define GEN4_EU_ATT_CLR_1 0x8834 |
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275 | #define GEN4_EU_RDATA 0x8840 |
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276 | |||
277 | /* 3D state: |
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278 | */ |
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279 | #define _3DOP_3DSTATE_PIPELINED 0x0 |
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280 | #define _3DOP_3DSTATE_NONPIPELINED 0x1 |
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281 | #define _3DOP_3DCONTROL 0x2 |
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282 | #define _3DOP_3DPRIMITIVE 0x3 |
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283 | |||
284 | #define _3DSTATE_PIPELINED_POINTERS 0x00 |
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285 | #define _3DSTATE_BINDING_TABLE_POINTERS 0x01 |
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286 | #define _3DSTATE_VERTEX_BUFFERS 0x08 |
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287 | #define _3DSTATE_VERTEX_ELEMENTS 0x09 |
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288 | #define _3DSTATE_INDEX_BUFFER 0x0A |
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289 | #define _3DSTATE_VF_STATISTICS 0x0B |
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290 | #define _3DSTATE_DRAWING_RECTANGLE 0x00 |
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291 | #define _3DSTATE_CONSTANT_COLOR 0x01 |
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292 | #define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 |
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293 | #define _3DSTATE_CHROMA_KEY 0x04 |
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294 | #define _3DSTATE_DEPTH_BUFFER 0x05 |
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295 | #define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 |
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296 | #define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 |
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297 | #define _3DSTATE_LINE_STIPPLE 0x08 |
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298 | #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 |
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299 | #define _3DCONTROL 0x00 |
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300 | #define _3DPRIMITIVE 0x00 |
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301 | |||
302 | #define _3DPRIM_POINTLIST 0x01 |
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303 | #define _3DPRIM_LINELIST 0x02 |
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304 | #define _3DPRIM_LINESTRIP 0x03 |
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305 | #define _3DPRIM_TRILIST 0x04 |
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306 | #define _3DPRIM_TRISTRIP 0x05 |
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307 | #define _3DPRIM_TRIFAN 0x06 |
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308 | #define _3DPRIM_QUADLIST 0x07 |
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309 | #define _3DPRIM_QUADSTRIP 0x08 |
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310 | #define _3DPRIM_LINELIST_ADJ 0x09 |
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311 | #define _3DPRIM_LINESTRIP_ADJ 0x0A |
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312 | #define _3DPRIM_TRILIST_ADJ 0x0B |
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313 | #define _3DPRIM_TRISTRIP_ADJ 0x0C |
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314 | #define _3DPRIM_TRISTRIP_REVERSE 0x0D |
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315 | #define _3DPRIM_POLYGON 0x0E |
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316 | #define _3DPRIM_RECTLIST 0x0F |
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317 | #define _3DPRIM_LINELOOP 0x10 |
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318 | #define _3DPRIM_POINTLIST_BF 0x11 |
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319 | #define _3DPRIM_LINESTRIP_CONT 0x12 |
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320 | #define _3DPRIM_LINESTRIP_BF 0x13 |
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321 | #define _3DPRIM_LINESTRIP_CONT_BF 0x14 |
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322 | #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 |
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323 | |||
324 | #define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 |
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325 | #define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 |
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326 | |||
327 | #define GEN4_ANISORATIO_2 0 |
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328 | #define GEN4_ANISORATIO_4 1 |
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329 | #define GEN4_ANISORATIO_6 2 |
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330 | #define GEN4_ANISORATIO_8 3 |
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331 | #define GEN4_ANISORATIO_10 4 |
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332 | #define GEN4_ANISORATIO_12 5 |
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333 | #define GEN4_ANISORATIO_14 6 |
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334 | #define GEN4_ANISORATIO_16 7 |
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335 | |||
336 | #define GEN4_BLENDFACTOR_ONE 0x1 |
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337 | #define GEN4_BLENDFACTOR_SRC_COLOR 0x2 |
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338 | #define GEN4_BLENDFACTOR_SRC_ALPHA 0x3 |
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339 | #define GEN4_BLENDFACTOR_DST_ALPHA 0x4 |
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340 | #define GEN4_BLENDFACTOR_DST_COLOR 0x5 |
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341 | #define GEN4_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 |
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342 | #define GEN4_BLENDFACTOR_CONST_COLOR 0x7 |
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343 | #define GEN4_BLENDFACTOR_CONST_ALPHA 0x8 |
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344 | #define GEN4_BLENDFACTOR_SRC1_COLOR 0x9 |
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345 | #define GEN4_BLENDFACTOR_SRC1_ALPHA 0x0A |
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346 | #define GEN4_BLENDFACTOR_ZERO 0x11 |
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347 | #define GEN4_BLENDFACTOR_INV_SRC_COLOR 0x12 |
||
348 | #define GEN4_BLENDFACTOR_INV_SRC_ALPHA 0x13 |
||
349 | #define GEN4_BLENDFACTOR_INV_DST_ALPHA 0x14 |
||
350 | #define GEN4_BLENDFACTOR_INV_DST_COLOR 0x15 |
||
351 | #define GEN4_BLENDFACTOR_INV_CONST_COLOR 0x17 |
||
352 | #define GEN4_BLENDFACTOR_INV_CONST_ALPHA 0x18 |
||
353 | #define GEN4_BLENDFACTOR_INV_SRC1_COLOR 0x19 |
||
354 | #define GEN4_BLENDFACTOR_INV_SRC1_ALPHA 0x1A |
||
355 | |||
356 | #define GEN4_BLENDFUNCTION_ADD 0 |
||
357 | #define GEN4_BLENDFUNCTION_SUBTRACT 1 |
||
358 | #define GEN4_BLENDFUNCTION_REVERSE_SUBTRACT 2 |
||
359 | #define GEN4_BLENDFUNCTION_MIN 3 |
||
360 | #define GEN4_BLENDFUNCTION_MAX 4 |
||
361 | |||
362 | #define GEN4_ALPHATEST_FORMAT_UNORM8 0 |
||
363 | #define GEN4_ALPHATEST_FORMAT_FLOAT32 1 |
||
364 | |||
365 | #define GEN4_CHROMAKEY_KILL_ON_ANY_MATCH 0 |
||
366 | #define GEN4_CHROMAKEY_REPLACE_BLACK 1 |
||
367 | |||
368 | #define GEN4_CLIP_API_OGL 0 |
||
369 | #define GEN4_CLIP_API_DX 1 |
||
370 | |||
371 | #define GEN4_CLIPMODE_NORMAL 0 |
||
372 | #define GEN4_CLIPMODE_CLIP_ALL 1 |
||
373 | #define GEN4_CLIPMODE_CLIP_NON_REJECTED 2 |
||
374 | #define GEN4_CLIPMODE_REJECT_ALL 3 |
||
375 | #define GEN4_CLIPMODE_ACCEPT_ALL 4 |
||
376 | |||
377 | #define GEN4_CLIP_NDCSPACE 0 |
||
378 | #define GEN4_CLIP_SCREENSPACE 1 |
||
379 | |||
380 | #define GEN4_COMPAREFUNCTION_ALWAYS 0 |
||
381 | #define GEN4_COMPAREFUNCTION_NEVER 1 |
||
382 | #define GEN4_COMPAREFUNCTION_LESS 2 |
||
383 | #define GEN4_COMPAREFUNCTION_EQUAL 3 |
||
384 | #define GEN4_COMPAREFUNCTION_LEQUAL 4 |
||
385 | #define GEN4_COMPAREFUNCTION_GREATER 5 |
||
386 | #define GEN4_COMPAREFUNCTION_NOTEQUAL 6 |
||
387 | #define GEN4_COMPAREFUNCTION_GEQUAL 7 |
||
388 | |||
389 | #define GEN4_COVERAGE_PIXELS_HALF 0 |
||
390 | #define GEN4_COVERAGE_PIXELS_1 1 |
||
391 | #define GEN4_COVERAGE_PIXELS_2 2 |
||
392 | #define GEN4_COVERAGE_PIXELS_4 3 |
||
393 | |||
394 | #define GEN4_CULLMODE_BOTH 0 |
||
395 | #define GEN4_CULLMODE_NONE 1 |
||
396 | #define GEN4_CULLMODE_FRONT 2 |
||
397 | #define GEN4_CULLMODE_BACK 3 |
||
398 | |||
399 | #define GEN4_DEFAULTCOLOR_R8G8B8A8_UNORM 0 |
||
400 | #define GEN4_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 |
||
401 | |||
402 | #define GEN4_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 |
||
403 | #define GEN4_DEPTHFORMAT_D32_FLOAT 1 |
||
404 | #define GEN4_DEPTHFORMAT_D24_UNORM_S8_UINT 2 |
||
405 | #define GEN4_DEPTHFORMAT_D16_UNORM 5 |
||
406 | |||
407 | #define GEN4_FLOATING_POINT_IEEE_754 0 |
||
408 | #define GEN4_FLOATING_POINT_NON_IEEE_754 1 |
||
409 | |||
410 | #define GEN4_FRONTWINDING_CW 0 |
||
411 | #define GEN4_FRONTWINDING_CCW 1 |
||
412 | |||
413 | #define GEN4_INDEX_BYTE 0 |
||
414 | #define GEN4_INDEX_WORD 1 |
||
415 | #define GEN4_INDEX_DWORD 2 |
||
416 | |||
417 | #define GEN4_LOGICOPFUNCTION_CLEAR 0 |
||
418 | #define GEN4_LOGICOPFUNCTION_NOR 1 |
||
419 | #define GEN4_LOGICOPFUNCTION_AND_INVERTED 2 |
||
420 | #define GEN4_LOGICOPFUNCTION_COPY_INVERTED 3 |
||
421 | #define GEN4_LOGICOPFUNCTION_AND_REVERSE 4 |
||
422 | #define GEN4_LOGICOPFUNCTION_INVERT 5 |
||
423 | #define GEN4_LOGICOPFUNCTION_XOR 6 |
||
424 | #define GEN4_LOGICOPFUNCTION_NAND 7 |
||
425 | #define GEN4_LOGICOPFUNCTION_AND 8 |
||
426 | #define GEN4_LOGICOPFUNCTION_EQUIV 9 |
||
427 | #define GEN4_LOGICOPFUNCTION_NOOP 10 |
||
428 | #define GEN4_LOGICOPFUNCTION_OR_INVERTED 11 |
||
429 | #define GEN4_LOGICOPFUNCTION_COPY 12 |
||
430 | #define GEN4_LOGICOPFUNCTION_OR_REVERSE 13 |
||
431 | #define GEN4_LOGICOPFUNCTION_OR 14 |
||
432 | #define GEN4_LOGICOPFUNCTION_SET 15 |
||
433 | |||
434 | #define GEN4_MAPFILTER_NEAREST 0x0 |
||
435 | #define GEN4_MAPFILTER_LINEAR 0x1 |
||
436 | #define GEN4_MAPFILTER_ANISOTROPIC 0x2 |
||
437 | |||
438 | #define GEN4_MIPFILTER_NONE 0 |
||
439 | #define GEN4_MIPFILTER_NEAREST 1 |
||
440 | #define GEN4_MIPFILTER_LINEAR 3 |
||
441 | |||
442 | #define GEN4_POLYGON_FRONT_FACING 0 |
||
443 | #define GEN4_POLYGON_BACK_FACING 1 |
||
444 | |||
445 | #define GEN4_PREFILTER_ALWAYS 0x0 |
||
446 | #define GEN4_PREFILTER_NEVER 0x1 |
||
447 | #define GEN4_PREFILTER_LESS 0x2 |
||
448 | #define GEN4_PREFILTER_EQUAL 0x3 |
||
449 | #define GEN4_PREFILTER_LEQUAL 0x4 |
||
450 | #define GEN4_PREFILTER_GREATER 0x5 |
||
451 | #define GEN4_PREFILTER_NOTEQUAL 0x6 |
||
452 | #define GEN4_PREFILTER_GEQUAL 0x7 |
||
453 | |||
454 | #define GEN4_PROVOKING_VERTEX_0 0 |
||
455 | #define GEN4_PROVOKING_VERTEX_1 1 |
||
456 | #define GEN4_PROVOKING_VERTEX_2 2 |
||
457 | |||
458 | #define GEN4_RASTRULE_UPPER_LEFT 0 |
||
459 | #define GEN4_RASTRULE_UPPER_RIGHT 1 |
||
460 | |||
461 | #define GEN4_RENDERTARGET_CLAMPRANGE_UNORM 0 |
||
462 | #define GEN4_RENDERTARGET_CLAMPRANGE_SNORM 1 |
||
463 | #define GEN4_RENDERTARGET_CLAMPRANGE_FORMAT 2 |
||
464 | |||
465 | #define GEN4_STENCILOP_KEEP 0 |
||
466 | #define GEN4_STENCILOP_ZERO 1 |
||
467 | #define GEN4_STENCILOP_REPLACE 2 |
||
468 | #define GEN4_STENCILOP_INCRSAT 3 |
||
469 | #define GEN4_STENCILOP_DECRSAT 4 |
||
470 | #define GEN4_STENCILOP_INCR 5 |
||
471 | #define GEN4_STENCILOP_DECR 6 |
||
472 | #define GEN4_STENCILOP_INVERT 7 |
||
473 | |||
474 | #define GEN4_SURFACE_MIPMAPLAYOUT_BELOW 0 |
||
475 | #define GEN4_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
||
476 | |||
477 | #define GEN4_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 |
||
478 | #define GEN4_SURFACEFORMAT_R32G32B32A32_SINT 0x001 |
||
479 | #define GEN4_SURFACEFORMAT_R32G32B32A32_UINT 0x002 |
||
480 | #define GEN4_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 |
||
481 | #define GEN4_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 |
||
482 | #define GEN4_SURFACEFORMAT_R64G64_FLOAT 0x005 |
||
483 | #define GEN4_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 |
||
484 | #define GEN4_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 |
||
485 | #define GEN4_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 |
||
486 | #define GEN4_SURFACEFORMAT_R32G32B32_FLOAT 0x040 |
||
487 | #define GEN4_SURFACEFORMAT_R32G32B32_SINT 0x041 |
||
488 | #define GEN4_SURFACEFORMAT_R32G32B32_UINT 0x042 |
||
489 | #define GEN4_SURFACEFORMAT_R32G32B32_UNORM 0x043 |
||
490 | #define GEN4_SURFACEFORMAT_R32G32B32_SNORM 0x044 |
||
491 | #define GEN4_SURFACEFORMAT_R32G32B32_SSCALED 0x045 |
||
492 | #define GEN4_SURFACEFORMAT_R32G32B32_USCALED 0x046 |
||
493 | #define GEN4_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 |
||
494 | #define GEN4_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 |
||
495 | #define GEN4_SURFACEFORMAT_R16G16B16A16_SINT 0x082 |
||
496 | #define GEN4_SURFACEFORMAT_R16G16B16A16_UINT 0x083 |
||
497 | #define GEN4_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 |
||
498 | #define GEN4_SURFACEFORMAT_R32G32_FLOAT 0x085 |
||
499 | #define GEN4_SURFACEFORMAT_R32G32_SINT 0x086 |
||
500 | #define GEN4_SURFACEFORMAT_R32G32_UINT 0x087 |
||
501 | #define GEN4_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 |
||
502 | #define GEN4_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 |
||
503 | #define GEN4_SURFACEFORMAT_L32A32_FLOAT 0x08A |
||
504 | #define GEN4_SURFACEFORMAT_R32G32_UNORM 0x08B |
||
505 | #define GEN4_SURFACEFORMAT_R32G32_SNORM 0x08C |
||
506 | #define GEN4_SURFACEFORMAT_R64_FLOAT 0x08D |
||
507 | #define GEN4_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E |
||
508 | #define GEN4_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F |
||
509 | #define GEN4_SURFACEFORMAT_A32X32_FLOAT 0x090 |
||
510 | #define GEN4_SURFACEFORMAT_L32X32_FLOAT 0x091 |
||
511 | #define GEN4_SURFACEFORMAT_I32X32_FLOAT 0x092 |
||
512 | #define GEN4_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 |
||
513 | #define GEN4_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 |
||
514 | #define GEN4_SURFACEFORMAT_R32G32_SSCALED 0x095 |
||
515 | #define GEN4_SURFACEFORMAT_R32G32_USCALED 0x096 |
||
516 | #define GEN4_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 |
||
517 | #define GEN4_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 |
||
518 | #define GEN4_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 |
||
519 | #define GEN4_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 |
||
520 | #define GEN4_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 |
||
521 | #define GEN4_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 |
||
522 | #define GEN4_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 |
||
523 | #define GEN4_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 |
||
524 | #define GEN4_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 |
||
525 | #define GEN4_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA |
||
526 | #define GEN4_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB |
||
527 | #define GEN4_SURFACEFORMAT_R16G16_UNORM 0x0CC |
||
528 | #define GEN4_SURFACEFORMAT_R16G16_SNORM 0x0CD |
||
529 | #define GEN4_SURFACEFORMAT_R16G16_SINT 0x0CE |
||
530 | #define GEN4_SURFACEFORMAT_R16G16_UINT 0x0CF |
||
531 | #define GEN4_SURFACEFORMAT_R16G16_FLOAT 0x0D0 |
||
532 | #define GEN4_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 |
||
533 | #define GEN4_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 |
||
534 | #define GEN4_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 |
||
535 | #define GEN4_SURFACEFORMAT_R32_SINT 0x0D6 |
||
536 | #define GEN4_SURFACEFORMAT_R32_UINT 0x0D7 |
||
537 | #define GEN4_SURFACEFORMAT_R32_FLOAT 0x0D8 |
||
538 | #define GEN4_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 |
||
539 | #define GEN4_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA |
||
540 | #define GEN4_SURFACEFORMAT_L16A16_UNORM 0x0DF |
||
541 | #define GEN4_SURFACEFORMAT_I24X8_UNORM 0x0E0 |
||
542 | #define GEN4_SURFACEFORMAT_L24X8_UNORM 0x0E1 |
||
543 | #define GEN4_SURFACEFORMAT_A24X8_UNORM 0x0E2 |
||
544 | #define GEN4_SURFACEFORMAT_I32_FLOAT 0x0E3 |
||
545 | #define GEN4_SURFACEFORMAT_L32_FLOAT 0x0E4 |
||
546 | #define GEN4_SURFACEFORMAT_A32_FLOAT 0x0E5 |
||
547 | #define GEN4_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 |
||
548 | #define GEN4_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA |
||
549 | #define GEN4_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB |
||
550 | #define GEN4_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC |
||
551 | #define GEN4_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED |
||
552 | #define GEN4_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE |
||
553 | #define GEN4_SURFACEFORMAT_L16A16_FLOAT 0x0F0 |
||
554 | #define GEN4_SURFACEFORMAT_R32_UNORM 0x0F1 |
||
555 | #define GEN4_SURFACEFORMAT_R32_SNORM 0x0F2 |
||
556 | #define GEN4_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 |
||
557 | #define GEN4_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 |
||
558 | #define GEN4_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 |
||
559 | #define GEN4_SURFACEFORMAT_R16G16_SSCALED 0x0F6 |
||
560 | #define GEN4_SURFACEFORMAT_R16G16_USCALED 0x0F7 |
||
561 | #define GEN4_SURFACEFORMAT_R32_SSCALED 0x0F8 |
||
562 | #define GEN4_SURFACEFORMAT_R32_USCALED 0x0F9 |
||
563 | #define GEN4_SURFACEFORMAT_B5G6R5_UNORM 0x100 |
||
564 | #define GEN4_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 |
||
565 | #define GEN4_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 |
||
566 | #define GEN4_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 |
||
567 | #define GEN4_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 |
||
568 | #define GEN4_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 |
||
569 | #define GEN4_SURFACEFORMAT_R8G8_UNORM 0x106 |
||
570 | #define GEN4_SURFACEFORMAT_R8G8_SNORM 0x107 |
||
571 | #define GEN4_SURFACEFORMAT_R8G8_SINT 0x108 |
||
572 | #define GEN4_SURFACEFORMAT_R8G8_UINT 0x109 |
||
573 | #define GEN4_SURFACEFORMAT_R16_UNORM 0x10A |
||
574 | #define GEN4_SURFACEFORMAT_R16_SNORM 0x10B |
||
575 | #define GEN4_SURFACEFORMAT_R16_SINT 0x10C |
||
576 | #define GEN4_SURFACEFORMAT_R16_UINT 0x10D |
||
577 | #define GEN4_SURFACEFORMAT_R16_FLOAT 0x10E |
||
578 | #define GEN4_SURFACEFORMAT_I16_UNORM 0x111 |
||
579 | #define GEN4_SURFACEFORMAT_L16_UNORM 0x112 |
||
580 | #define GEN4_SURFACEFORMAT_A16_UNORM 0x113 |
||
581 | #define GEN4_SURFACEFORMAT_L8A8_UNORM 0x114 |
||
582 | #define GEN4_SURFACEFORMAT_I16_FLOAT 0x115 |
||
583 | #define GEN4_SURFACEFORMAT_L16_FLOAT 0x116 |
||
584 | #define GEN4_SURFACEFORMAT_A16_FLOAT 0x117 |
||
585 | #define GEN4_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 |
||
586 | #define GEN4_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A |
||
587 | #define GEN4_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B |
||
588 | #define GEN4_SURFACEFORMAT_R8G8_SSCALED 0x11C |
||
589 | #define GEN4_SURFACEFORMAT_R8G8_USCALED 0x11D |
||
590 | #define GEN4_SURFACEFORMAT_R16_SSCALED 0x11E |
||
591 | #define GEN4_SURFACEFORMAT_R16_USCALED 0x11F |
||
592 | #define GEN4_SURFACEFORMAT_R8_UNORM 0x140 |
||
593 | #define GEN4_SURFACEFORMAT_R8_SNORM 0x141 |
||
594 | #define GEN4_SURFACEFORMAT_R8_SINT 0x142 |
||
595 | #define GEN4_SURFACEFORMAT_R8_UINT 0x143 |
||
596 | #define GEN4_SURFACEFORMAT_A8_UNORM 0x144 |
||
597 | #define GEN4_SURFACEFORMAT_I8_UNORM 0x145 |
||
598 | #define GEN4_SURFACEFORMAT_L8_UNORM 0x146 |
||
599 | #define GEN4_SURFACEFORMAT_P4A4_UNORM 0x147 |
||
600 | #define GEN4_SURFACEFORMAT_A4P4_UNORM 0x148 |
||
601 | #define GEN4_SURFACEFORMAT_R8_SSCALED 0x149 |
||
602 | #define GEN4_SURFACEFORMAT_R8_USCALED 0x14A |
||
603 | #define GEN4_SURFACEFORMAT_R1_UINT 0x181 |
||
604 | #define GEN4_SURFACEFORMAT_YCRCB_NORMAL 0x182 |
||
605 | #define GEN4_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 |
||
606 | #define GEN4_SURFACEFORMAT_BC1_UNORM 0x186 |
||
607 | #define GEN4_SURFACEFORMAT_BC2_UNORM 0x187 |
||
608 | #define GEN4_SURFACEFORMAT_BC3_UNORM 0x188 |
||
609 | #define GEN4_SURFACEFORMAT_BC4_UNORM 0x189 |
||
610 | #define GEN4_SURFACEFORMAT_BC5_UNORM 0x18A |
||
611 | #define GEN4_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B |
||
612 | #define GEN4_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C |
||
613 | #define GEN4_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D |
||
614 | #define GEN4_SURFACEFORMAT_MONO8 0x18E |
||
615 | #define GEN4_SURFACEFORMAT_YCRCB_SWAPUV 0x18F |
||
616 | #define GEN4_SURFACEFORMAT_YCRCB_SWAPY 0x190 |
||
617 | #define GEN4_SURFACEFORMAT_DXT1_RGB 0x191 |
||
618 | #define GEN4_SURFACEFORMAT_FXT1 0x192 |
||
619 | #define GEN4_SURFACEFORMAT_R8G8B8_UNORM 0x193 |
||
620 | #define GEN4_SURFACEFORMAT_R8G8B8_SNORM 0x194 |
||
621 | #define GEN4_SURFACEFORMAT_R8G8B8_SSCALED 0x195 |
||
622 | #define GEN4_SURFACEFORMAT_R8G8B8_USCALED 0x196 |
||
623 | #define GEN4_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 |
||
624 | #define GEN4_SURFACEFORMAT_R64G64B64_FLOAT 0x198 |
||
625 | #define GEN4_SURFACEFORMAT_BC4_SNORM 0x199 |
||
626 | #define GEN4_SURFACEFORMAT_BC5_SNORM 0x19A |
||
627 | #define GEN4_SURFACEFORMAT_R16G16B16_UNORM 0x19C |
||
628 | #define GEN4_SURFACEFORMAT_R16G16B16_SNORM 0x19D |
||
629 | #define GEN4_SURFACEFORMAT_R16G16B16_SSCALED 0x19E |
||
630 | #define GEN4_SURFACEFORMAT_R16G16B16_USCALED 0x19F |
||
631 | |||
632 | #define GEN4_SURFACERETURNFORMAT_FLOAT32 0 |
||
633 | #define GEN4_SURFACERETURNFORMAT_S1 1 |
||
634 | |||
635 | #define GEN4_SURFACE_1D 0 |
||
636 | #define GEN4_SURFACE_2D 1 |
||
637 | #define GEN4_SURFACE_3D 2 |
||
638 | #define GEN4_SURFACE_CUBE 3 |
||
639 | #define GEN4_SURFACE_BUFFER 4 |
||
640 | #define GEN4_SURFACE_NULL 7 |
||
641 | |||
642 | #define GEN4_BORDER_COLOR_MODE_DEFAULT 0 |
||
643 | #define GEN4_BORDER_COLOR_MODE_LEGACY 1 |
||
644 | |||
645 | #define GEN4_TEXCOORDMODE_WRAP 0 |
||
646 | #define GEN4_TEXCOORDMODE_MIRROR 1 |
||
647 | #define GEN4_TEXCOORDMODE_CLAMP 2 |
||
648 | #define GEN4_TEXCOORDMODE_CUBE 3 |
||
649 | #define GEN4_TEXCOORDMODE_CLAMP_BORDER 4 |
||
650 | #define GEN4_TEXCOORDMODE_MIRROR_ONCE 5 |
||
651 | |||
652 | #define GEN4_THREAD_PRIORITY_NORMAL 0 |
||
653 | #define GEN4_THREAD_PRIORITY_HIGH 1 |
||
654 | |||
655 | #define GEN4_TILEWALK_XMAJOR 0 |
||
656 | #define GEN4_TILEWALK_YMAJOR 1 |
||
657 | |||
658 | #define GEN4_VERTEX_SUBPIXEL_PRECISION_8BITS 0 |
||
659 | #define GEN4_VERTEX_SUBPIXEL_PRECISION_4BITS 1 |
||
660 | |||
661 | #define GEN4_VERTEXBUFFER_ACCESS_VERTEXDATA 0 |
||
662 | #define GEN4_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 |
||
663 | |||
664 | #define VFCOMPONENT_NOSTORE 0 |
||
665 | #define VFCOMPONENT_STORE_SRC 1 |
||
666 | #define VFCOMPONENT_STORE_0 2 |
||
667 | #define VFCOMPONENT_STORE_1_FLT 3 |
||
668 | #define VFCOMPONENT_STORE_1_INT 4 |
||
669 | #define VFCOMPONENT_STORE_VID 5 |
||
670 | #define VFCOMPONENT_STORE_IID 6 |
||
671 | #define VFCOMPONENT_STORE_PID 7 |
||
672 | |||
673 | |||
674 | /* Execution Unit (EU) defines |
||
675 | */ |
||
676 | |||
677 | #define GEN4_ALIGN_1 0 |
||
678 | #define GEN4_ALIGN_16 1 |
||
679 | |||
680 | #define GEN4_ADDRESS_DIRECT 0 |
||
681 | #define GEN4_ADDRESS_REGISTER_INDIRECT_REGISTER 1 |
||
682 | |||
683 | #define GEN4_CHANNEL_X 0 |
||
684 | #define GEN4_CHANNEL_Y 1 |
||
685 | #define GEN4_CHANNEL_Z 2 |
||
686 | #define GEN4_CHANNEL_W 3 |
||
687 | |||
688 | #define GEN4_COMPRESSION_NONE 0 |
||
689 | #define GEN4_COMPRESSION_2NDHALF 1 |
||
690 | #define GEN4_COMPRESSION_COMPRESSED 2 |
||
691 | |||
692 | #define GEN4_CONDITIONAL_NONE 0 |
||
693 | #define GEN4_CONDITIONAL_Z 1 |
||
694 | #define GEN4_CONDITIONAL_NZ 2 |
||
695 | #define GEN4_CONDITIONAL_EQ 1 /* Z */ |
||
696 | #define GEN4_CONDITIONAL_NEQ 2 /* NZ */ |
||
697 | #define GEN4_CONDITIONAL_G 3 |
||
698 | #define GEN4_CONDITIONAL_GE 4 |
||
699 | #define GEN4_CONDITIONAL_L 5 |
||
700 | #define GEN4_CONDITIONAL_LE 6 |
||
701 | #define GEN4_CONDITIONAL_C 7 |
||
702 | #define GEN4_CONDITIONAL_O 8 |
||
703 | |||
704 | #define GEN4_DEBUG_NONE 0 |
||
705 | #define GEN4_DEBUG_BREAKPOINT 1 |
||
706 | |||
707 | #define GEN4_DEPENDENCY_NORMAL 0 |
||
708 | #define GEN4_DEPENDENCY_NOTCLEARED 1 |
||
709 | #define GEN4_DEPENDENCY_NOTCHECKED 2 |
||
710 | #define GEN4_DEPENDENCY_DISABLE 3 |
||
711 | |||
712 | #define GEN4_EXECUTE_1 0 |
||
713 | #define GEN4_EXECUTE_2 1 |
||
714 | #define GEN4_EXECUTE_4 2 |
||
715 | #define GEN4_EXECUTE_8 3 |
||
716 | #define GEN4_EXECUTE_16 4 |
||
717 | #define GEN4_EXECUTE_32 5 |
||
718 | |||
719 | #define GEN4_HORIZONTAL_STRIDE_0 0 |
||
720 | #define GEN4_HORIZONTAL_STRIDE_1 1 |
||
721 | #define GEN4_HORIZONTAL_STRIDE_2 2 |
||
722 | #define GEN4_HORIZONTAL_STRIDE_4 3 |
||
723 | |||
724 | #define GEN4_INSTRUCTION_NORMAL 0 |
||
725 | #define GEN4_INSTRUCTION_SATURATE 1 |
||
726 | |||
727 | #define _MASK_ENABLE 0 |
||
728 | #define _MASK_DISABLE 1 |
||
729 | |||
730 | #define GEN4_OPCODE_MOV 1 |
||
731 | #define GEN4_OPCODE_SEL 2 |
||
732 | #define GEN4_OPCODE_NOT 4 |
||
733 | #define GEN4_OPCODE_AND 5 |
||
734 | #define GEN4_OPCODE_OR 6 |
||
735 | #define GEN4_OPCODE_XOR 7 |
||
736 | #define GEN4_OPCODE_SHR 8 |
||
737 | #define GEN4_OPCODE_SHL 9 |
||
738 | #define GEN4_OPCODE_RSR 10 |
||
739 | #define GEN4_OPCODE_RSL 11 |
||
740 | #define GEN4_OPCODE_ASR 12 |
||
741 | #define GEN4_OPCODE_CMP 16 |
||
742 | #define GEN4_OPCODE_JMPI 32 |
||
743 | #define GEN4_OPCODE_IF 34 |
||
744 | #define GEN4_OPCODE_IFF 35 |
||
745 | #define GEN4_OPCODE_ELSE 36 |
||
746 | #define GEN4_OPCODE_ENDIF 37 |
||
747 | #define GEN4_OPCODE_DO 38 |
||
748 | #define GEN4_OPCODE_WHILE 39 |
||
749 | #define GEN4_OPCODE_BREAK 40 |
||
750 | #define GEN4_OPCODE_CONTINUE 41 |
||
751 | #define GEN4_OPCODE_HALT 42 |
||
752 | #define GEN4_OPCODE_MSAVE 44 |
||
753 | #define GEN4_OPCODE_MRESTORE 45 |
||
754 | #define GEN4_OPCODE_PUSH 46 |
||
755 | #define GEN4_OPCODE_POP 47 |
||
756 | #define GEN4_OPCODE_WAIT 48 |
||
757 | #define GEN4_OPCODE_SEND 49 |
||
758 | #define GEN4_OPCODE_ADD 64 |
||
759 | #define GEN4_OPCODE_MUL 65 |
||
760 | #define GEN4_OPCODE_AVG 66 |
||
761 | #define GEN4_OPCODE_FRC 67 |
||
762 | #define GEN4_OPCODE_RNDU 68 |
||
763 | #define GEN4_OPCODE_RNDD 69 |
||
764 | #define GEN4_OPCODE_RNDE 70 |
||
765 | #define GEN4_OPCODE_RNDZ 71 |
||
766 | #define GEN4_OPCODE_MAC 72 |
||
767 | #define GEN4_OPCODE_MACH 73 |
||
768 | #define GEN4_OPCODE_LZD 74 |
||
769 | #define GEN4_OPCODE_SAD2 80 |
||
770 | #define GEN4_OPCODE_SADA2 81 |
||
771 | #define GEN4_OPCODE_DP4 84 |
||
772 | #define GEN4_OPCODE_DPH 85 |
||
773 | #define GEN4_OPCODE_DP3 86 |
||
774 | #define GEN4_OPCODE_DP2 87 |
||
775 | #define GEN4_OPCODE_DPA2 88 |
||
776 | #define GEN4_OPCODE_LINE 89 |
||
777 | #define GEN4_OPCODE_NOP 126 |
||
778 | |||
779 | #define GEN4_PREDICATE_NONE 0 |
||
780 | #define GEN4_PREDICATE_NORMAL 1 |
||
781 | #define GEN4_PREDICATE_ALIGN1_ANYV 2 |
||
782 | #define GEN4_PREDICATE_ALIGN1_ALLV 3 |
||
783 | #define GEN4_PREDICATE_ALIGN1_ANY2H 4 |
||
784 | #define GEN4_PREDICATE_ALIGN1_ALL2H 5 |
||
785 | #define GEN4_PREDICATE_ALIGN1_ANY4H 6 |
||
786 | #define GEN4_PREDICATE_ALIGN1_ALL4H 7 |
||
787 | #define GEN4_PREDICATE_ALIGN1_ANY8H 8 |
||
788 | #define GEN4_PREDICATE_ALIGN1_ALL8H 9 |
||
789 | #define GEN4_PREDICATE_ALIGN1_ANY16H 10 |
||
790 | #define GEN4_PREDICATE_ALIGN1_ALL16H 11 |
||
791 | #define GEN4_PREDICATE_ALIGN16_REPLICATE_X 2 |
||
792 | #define GEN4_PREDICATE_ALIGN16_REPLICATE_Y 3 |
||
793 | #define GEN4_PREDICATE_ALIGN16_REPLICATE_Z 4 |
||
794 | #define GEN4_PREDICATE_ALIGN16_REPLICATE_W 5 |
||
795 | #define GEN4_PREDICATE_ALIGN16_ANY4H 6 |
||
796 | #define GEN4_PREDICATE_ALIGN16_ALL4H 7 |
||
797 | |||
798 | #define GEN4_ARCHITECTURE_REGISTER_FILE 0 |
||
799 | #define GEN4_GENERAL_REGISTER_FILE 1 |
||
800 | #define GEN4_MESSAGE_REGISTER_FILE 2 |
||
801 | #define GEN4_IMMEDIATE_VALUE 3 |
||
802 | |||
803 | #define GEN4_REGISTER_TYPE_UD 0 |
||
804 | #define GEN4_REGISTER_TYPE_D 1 |
||
805 | #define GEN4_REGISTER_TYPE_UW 2 |
||
806 | #define GEN4_REGISTER_TYPE_W 3 |
||
807 | #define GEN4_REGISTER_TYPE_UB 4 |
||
808 | #define GEN4_REGISTER_TYPE_B 5 |
||
809 | #define GEN4_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ |
||
810 | #define GEN4_REGISTER_TYPE_HF 6 |
||
811 | #define GEN4_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ |
||
812 | #define GEN4_REGISTER_TYPE_F 7 |
||
813 | |||
814 | #define GEN4_ARF_NULL 0x00 |
||
815 | #define GEN4_ARF_ADDRESS 0x10 |
||
816 | #define GEN4_ARF_ACCUMULATOR 0x20 |
||
817 | #define GEN4_ARF_FLAG 0x30 |
||
818 | #define GEN4_ARF_MASK 0x40 |
||
819 | #define GEN4_ARF_MASK_STACK 0x50 |
||
820 | #define GEN4_ARF_MASK_STACK_DEPTH 0x60 |
||
821 | #define GEN4_ARF_STATE 0x70 |
||
822 | #define GEN4_ARF_CONTROL 0x80 |
||
823 | #define GEN4_ARF_NOTIFICATION_COUNT 0x90 |
||
824 | #define GEN4_ARF_IP 0xA0 |
||
825 | |||
826 | #define GEN4_AMASK 0 |
||
827 | #define GEN4_IMASK 1 |
||
828 | #define GEN4_LMASK 2 |
||
829 | #define GEN4_CMASK 3 |
||
830 | |||
831 | |||
832 | |||
833 | #define GEN4_THREAD_NORMAL 0 |
||
834 | #define GEN4_THREAD_ATOMIC 1 |
||
835 | #define GEN4_THREAD_SWITCH 2 |
||
836 | |||
837 | #define GEN4_VERTICAL_STRIDE_0 0 |
||
838 | #define GEN4_VERTICAL_STRIDE_1 1 |
||
839 | #define GEN4_VERTICAL_STRIDE_2 2 |
||
840 | #define GEN4_VERTICAL_STRIDE_4 3 |
||
841 | #define GEN4_VERTICAL_STRIDE_8 4 |
||
842 | #define GEN4_VERTICAL_STRIDE_16 5 |
||
843 | #define GEN4_VERTICAL_STRIDE_32 6 |
||
844 | #define GEN4_VERTICAL_STRIDE_64 7 |
||
845 | #define GEN4_VERTICAL_STRIDE_128 8 |
||
846 | #define GEN4_VERTICAL_STRIDE_256 9 |
||
847 | #define GEN4_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF |
||
848 | |||
849 | #define GEN4_WIDTH_1 0 |
||
850 | #define GEN4_WIDTH_2 1 |
||
851 | #define GEN4_WIDTH_4 2 |
||
852 | #define GEN4_WIDTH_8 3 |
||
853 | #define GEN4_WIDTH_16 4 |
||
854 | |||
855 | #define GEN4_STATELESS_BUFFER_BOUNDARY_1K 0 |
||
856 | #define GEN4_STATELESS_BUFFER_BOUNDARY_2K 1 |
||
857 | #define GEN4_STATELESS_BUFFER_BOUNDARY_4K 2 |
||
858 | #define GEN4_STATELESS_BUFFER_BOUNDARY_8K 3 |
||
859 | #define GEN4_STATELESS_BUFFER_BOUNDARY_16K 4 |
||
860 | #define GEN4_STATELESS_BUFFER_BOUNDARY_32K 5 |
||
861 | #define GEN4_STATELESS_BUFFER_BOUNDARY_64K 6 |
||
862 | #define GEN4_STATELESS_BUFFER_BOUNDARY_128K 7 |
||
863 | #define GEN4_STATELESS_BUFFER_BOUNDARY_256K 8 |
||
864 | #define GEN4_STATELESS_BUFFER_BOUNDARY_512K 9 |
||
865 | #define GEN4_STATELESS_BUFFER_BOUNDARY_1M 10 |
||
866 | #define GEN4_STATELESS_BUFFER_BOUNDARY_2M 11 |
||
867 | |||
868 | #define GEN4_POLYGON_FACING_FRONT 0 |
||
869 | #define GEN4_POLYGON_FACING_BACK 1 |
||
870 | |||
871 | #define GEN4_MESSAGE_TARGET_NULL 0 |
||
872 | #define GEN4_MESSAGE_TARGET_MATH 1 |
||
873 | #define GEN4_MESSAGE_TARGET_SAMPLER 2 |
||
874 | #define GEN4_MESSAGE_TARGET_GATEWAY 3 |
||
875 | #define GEN4_MESSAGE_TARGET_DATAPORT_READ 4 |
||
876 | #define GEN4_MESSAGE_TARGET_DATAPORT_WRITE 5 |
||
877 | #define GEN4_MESSAGE_TARGET_URB 6 |
||
878 | #define GEN4_MESSAGE_TARGET_THREAD_SPAWNER 7 |
||
879 | |||
880 | #define GEN4_SAMPLER_RETURN_FORMAT_FLOAT32 0 |
||
881 | #define GEN4_SAMPLER_RETURN_FORMAT_UINT32 2 |
||
882 | #define GEN4_SAMPLER_RETURN_FORMAT_SINT32 3 |
||
883 | |||
884 | #define GEN4_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 |
||
885 | #define GEN4_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 |
||
886 | #define GEN4_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 |
||
887 | #define GEN4_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 |
||
888 | #define GEN4_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 |
||
889 | #define GEN4_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 |
||
890 | #define GEN4_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 |
||
891 | #define GEN4_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 |
||
892 | #define GEN4_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 |
||
893 | #define GEN4_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 |
||
894 | #define GEN4_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 |
||
895 | #define GEN4_SAMPLER_MESSAGE_SIMD8_RESINFO 2 |
||
896 | #define GEN4_SAMPLER_MESSAGE_SIMD16_RESINFO 2 |
||
897 | #define GEN4_SAMPLER_MESSAGE_SIMD4X2_LD 3 |
||
898 | #define GEN4_SAMPLER_MESSAGE_SIMD8_LD 3 |
||
899 | #define GEN4_SAMPLER_MESSAGE_SIMD16_LD 3 |
||
900 | |||
901 | #define GEN4_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 |
||
902 | #define GEN4_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 |
||
903 | #define GEN4_DATAPORT_OWORD_BLOCK_2_OWORDS 2 |
||
904 | #define GEN4_DATAPORT_OWORD_BLOCK_4_OWORDS 3 |
||
905 | #define GEN4_DATAPORT_OWORD_BLOCK_8_OWORDS 4 |
||
906 | |||
907 | #define GEN4_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 |
||
908 | #define GEN4_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 |
||
909 | |||
910 | #define GEN4_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 |
||
911 | #define GEN4_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 |
||
912 | |||
913 | #define GEN4_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 |
||
914 | #define GEN4_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 |
||
915 | #define GEN4_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 |
||
916 | #define GEN4_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 |
||
917 | |||
918 | #define GEN4_DATAPORT_READ_TARGET_DATA_CACHE 0 |
||
919 | #define GEN4_DATAPORT_READ_TARGET_RENDER_CACHE 1 |
||
920 | #define GEN4_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 |
||
921 | |||
922 | #define GEN4_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 |
||
923 | #define GEN4_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 |
||
924 | #define GEN4_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 |
||
925 | #define GEN4_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 |
||
926 | #define GEN4_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 |
||
927 | |||
928 | #define GEN4_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 |
||
929 | #define GEN4_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 |
||
930 | #define GEN4_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 |
||
931 | #define GEN4_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 |
||
932 | #define GEN4_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 |
||
933 | #define GEN4_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 |
||
934 | #define GEN4_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 |
||
935 | |||
936 | #define GEN4_MATH_FUNCTION_INV 1 |
||
937 | #define GEN4_MATH_FUNCTION_LOG 2 |
||
938 | #define GEN4_MATH_FUNCTION_EXP 3 |
||
939 | #define GEN4_MATH_FUNCTION_SQRT 4 |
||
940 | #define GEN4_MATH_FUNCTION_RSQ 5 |
||
941 | #define GEN4_MATH_FUNCTION_SIN 6 /* was 7 */ |
||
942 | #define GEN4_MATH_FUNCTION_COS 7 /* was 8 */ |
||
943 | #define GEN4_MATH_FUNCTION_SINCOS 8 /* was 6 */ |
||
944 | #define GEN4_MATH_FUNCTION_TAN 9 |
||
945 | #define GEN4_MATH_FUNCTION_POW 10 |
||
946 | #define GEN4_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 |
||
947 | #define GEN4_MATH_FUNCTION_INT_DIV_QUOTIENT 12 |
||
948 | #define GEN4_MATH_FUNCTION_INT_DIV_REMAINDER 13 |
||
949 | |||
950 | #define GEN4_MATH_INTEGER_UNSIGNED 0 |
||
951 | #define GEN4_MATH_INTEGER_SIGNED 1 |
||
952 | |||
953 | #define GEN4_MATH_PRECISION_FULL 0 |
||
954 | #define GEN4_MATH_PRECISION_PARTIAL 1 |
||
955 | |||
956 | #define GEN4_MATH_SATURATE_NONE 0 |
||
957 | #define GEN4_MATH_SATURATE_SATURATE 1 |
||
958 | |||
959 | #define GEN4_MATH_DATA_VECTOR 0 |
||
960 | #define GEN4_MATH_DATA_SCALAR 1 |
||
961 | |||
962 | #define GEN4_URB_OPCODE_WRITE 0 |
||
963 | |||
964 | #define GEN4_URB_SWIZZLE_NONE 0 |
||
965 | #define GEN4_URB_SWIZZLE_INTERLEAVE 1 |
||
966 | #define GEN4_URB_SWIZZLE_TRANSPOSE 2 |
||
967 | |||
968 | #define GEN4_SCRATCH_SPACE_SIZE_1K 0 |
||
969 | #define GEN4_SCRATCH_SPACE_SIZE_2K 1 |
||
970 | #define GEN4_SCRATCH_SPACE_SIZE_4K 2 |
||
971 | #define GEN4_SCRATCH_SPACE_SIZE_8K 3 |
||
972 | #define GEN4_SCRATCH_SPACE_SIZE_16K 4 |
||
973 | #define GEN4_SCRATCH_SPACE_SIZE_32K 5 |
||
974 | #define GEN4_SCRATCH_SPACE_SIZE_64K 6 |
||
975 | #define GEN4_SCRATCH_SPACE_SIZE_128K 7 |
||
976 | #define GEN4_SCRATCH_SPACE_SIZE_256K 8 |
||
977 | #define GEN4_SCRATCH_SPACE_SIZE_512K 9 |
||
978 | #define GEN4_SCRATCH_SPACE_SIZE_1M 10 |
||
979 | #define GEN4_SCRATCH_SPACE_SIZE_2M 11 |
||
980 | |||
981 | |||
982 | |||
983 | |||
984 | #define CMD_URB_FENCE 0x6000 |
||
985 | #define CMD_CONST_BUFFER_STATE 0x6001 |
||
986 | #define CMD_CONST_BUFFER 0x6002 |
||
987 | |||
988 | #define CMD_STATE_BASE_ADDRESS 0x6101 |
||
989 | #define CMD_STATE_INSN_POINTER 0x6102 |
||
990 | #define CMD_PIPELINE_SELECT 0x6104 |
||
991 | |||
992 | #define CMD_PIPELINED_STATE_POINTERS 0x7800 |
||
993 | #define CMD_BINDING_TABLE_PTRS 0x7801 |
||
994 | #define CMD_VERTEX_BUFFER 0x7808 |
||
995 | #define CMD_VERTEX_ELEMENT 0x7809 |
||
996 | #define CMD_INDEX_BUFFER 0x780a |
||
997 | #define CMD_VF_STATISTICS 0x780b |
||
998 | |||
999 | #define CMD_DRAW_RECT 0x7900 |
||
1000 | #define CMD_BLEND_CONSTANT_COLOR 0x7901 |
||
1001 | #define CMD_CHROMA_KEY 0x7904 |
||
1002 | #define CMD_DEPTH_BUFFER 0x7905 |
||
1003 | #define CMD_POLY_STIPPLE_OFFSET 0x7906 |
||
1004 | #define CMD_POLY_STIPPLE_PATTERN 0x7907 |
||
1005 | #define CMD_LINE_STIPPLE_PATTERN 0x7908 |
||
1006 | #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908 |
||
1007 | |||
1008 | #define CMD_PIPE_CONTROL 0x7a00 |
||
1009 | |||
1010 | #define CMD_3D_PRIM 0x7b00 |
||
1011 | |||
1012 | #define CMD_MI_FLUSH 0x0200 |
||
1013 | |||
1014 | |||
1015 | /* Various values from the R0 vertex header: |
||
1016 | */ |
||
1017 | #define R02_PRIM_END 0x1 |
||
1018 | #define R02_PRIM_START 0x2 |
||
1019 | |||
1020 | /* media pipeline */ |
||
1021 | |||
1022 | #define GEN4_VFE_MODE_GENERIC 0x0 |
||
1023 | #define GEN4_VFE_MODE_VLD_MPEG2 0x1 |
||
1024 | #define GEN4_VFE_MODE_IS 0x2 |
||
1025 | #define GEN4_VFE_MODE_AVC_MC 0x4 |
||
1026 | #define GEN4_VFE_MODE_AVC_IT 0x7 |
||
1027 | #define GEN4_VFE_MODE_VC1_IT 0xB |
||
1028 | |||
1029 | #define GEN4_VFE_DEBUG_COUNTER_FREE 0 |
||
1030 | #define GEN4_VFE_DEBUG_COUNTER_FROZEN 1 |
||
1031 | #define GEN4_VFE_DEBUG_COUNTER_ONCE 2 |
||
1032 | #define GEN4_VFE_DEBUG_COUNTER_ALWAYS 3 |
||
1033 | |||
1034 | /* VLD_STATE */ |
||
1035 | #define GEN4_MPEG_TOP_FIELD 1 |
||
1036 | #define GEN4_MPEG_BOTTOM_FIELD 2 |
||
1037 | #define GEN4_MPEG_FRAME 3 |
||
1038 | #define GEN4_MPEG_QSCALE_LINEAR 0 |
||
1039 | #define GEN4_MPEG_QSCALE_NONLINEAR 1 |
||
1040 | #define GEN4_MPEG_ZIGZAG_SCAN 0 |
||
1041 | #define GEN4_MPEG_ALTER_VERTICAL_SCAN 1 |
||
1042 | #define GEN4_MPEG_I_PICTURE 1 |
||
1043 | #define GEN4_MPEG_P_PICTURE 2 |
||
1044 | #define GEN4_MPEG_B_PICTURE 3 |
||
1045 | |||
1046 | /* Command packets: |
||
1047 | */ |
||
1048 | struct header |
||
1049 | { |
||
1050 | unsigned int length:16; |
||
1051 | unsigned int opcode:16; |
||
1052 | }; |
||
1053 | |||
1054 | |||
1055 | union header_union |
||
1056 | { |
||
1057 | struct header bits; |
||
1058 | unsigned int dword; |
||
1059 | }; |
||
1060 | |||
1061 | struct gen4_3d_control |
||
1062 | { |
||
1063 | struct |
||
1064 | { |
||
1065 | unsigned int length:8; |
||
1066 | unsigned int notify_enable:1; |
||
1067 | unsigned int pad:3; |
||
1068 | unsigned int wc_flush_enable:1; |
||
1069 | unsigned int depth_stall_enable:1; |
||
1070 | unsigned int operation:2; |
||
1071 | unsigned int opcode:16; |
||
1072 | } header; |
||
1073 | |||
1074 | struct |
||
1075 | { |
||
1076 | unsigned int pad:2; |
||
1077 | unsigned int dest_addr_type:1; |
||
1078 | unsigned int dest_addr:29; |
||
1079 | } dest; |
||
1080 | |||
1081 | unsigned int dword2; |
||
1082 | unsigned int dword3; |
||
1083 | }; |
||
1084 | |||
1085 | |||
1086 | struct gen4_3d_primitive |
||
1087 | { |
||
1088 | struct |
||
1089 | { |
||
1090 | unsigned int length:8; |
||
1091 | unsigned int pad:2; |
||
1092 | unsigned int topology:5; |
||
1093 | unsigned int indexed:1; |
||
1094 | unsigned int opcode:16; |
||
1095 | } header; |
||
1096 | |||
1097 | unsigned int verts_per_instance; |
||
1098 | unsigned int start_vert_location; |
||
1099 | unsigned int instance_count; |
||
1100 | unsigned int start_instance_location; |
||
1101 | unsigned int base_vert_location; |
||
1102 | }; |
||
1103 | |||
1104 | /* These seem to be passed around as function args, so it works out |
||
1105 | * better to keep them as #defines: |
||
1106 | */ |
||
1107 | #define GEN4_FLUSH_READ_CACHE 0x1 |
||
1108 | #define GEN4_FLUSH_STATE_CACHE 0x2 |
||
1109 | #define GEN4_INHIBIT_FLUSH_RENDER_CACHE 0x4 |
||
1110 | #define GEN4_FLUSH_SNAPSHOT_COUNTERS 0x8 |
||
1111 | |||
1112 | struct gen4_mi_flush |
||
1113 | { |
||
1114 | unsigned int flags:4; |
||
1115 | unsigned int pad:12; |
||
1116 | unsigned int opcode:16; |
||
1117 | }; |
||
1118 | |||
1119 | struct gen4_vf_statistics |
||
1120 | { |
||
1121 | unsigned int statistics_enable:1; |
||
1122 | unsigned int pad:15; |
||
1123 | unsigned int opcode:16; |
||
1124 | }; |
||
1125 | |||
1126 | |||
1127 | |||
1128 | struct gen4_binding_table_pointers |
||
1129 | { |
||
1130 | struct header header; |
||
1131 | unsigned int vs; |
||
1132 | unsigned int gs; |
||
1133 | unsigned int clp; |
||
1134 | unsigned int sf; |
||
1135 | unsigned int wm; |
||
1136 | }; |
||
1137 | |||
1138 | |||
1139 | struct gen4_blend_constant_color |
||
1140 | { |
||
1141 | struct header header; |
||
1142 | float blend_constant_color[4]; |
||
1143 | }; |
||
1144 | |||
1145 | |||
1146 | struct gen4_depthbuffer |
||
1147 | { |
||
1148 | union header_union header; |
||
1149 | |||
1150 | union { |
||
1151 | struct { |
||
1152 | unsigned int pitch:18; |
||
1153 | unsigned int format:3; |
||
1154 | unsigned int pad:4; |
||
1155 | unsigned int depth_offset_disable:1; |
||
1156 | unsigned int tile_walk:1; |
||
1157 | unsigned int tiled_surface:1; |
||
1158 | unsigned int pad2:1; |
||
1159 | unsigned int surface_type:3; |
||
1160 | } bits; |
||
1161 | unsigned int dword; |
||
1162 | } dword1; |
||
1163 | |||
1164 | unsigned int dword2_base_addr; |
||
1165 | |||
1166 | union { |
||
1167 | struct { |
||
1168 | unsigned int pad:1; |
||
1169 | unsigned int mipmap_layout:1; |
||
1170 | unsigned int lod:4; |
||
1171 | unsigned int width:13; |
||
1172 | unsigned int height:13; |
||
1173 | } bits; |
||
1174 | unsigned int dword; |
||
1175 | } dword3; |
||
1176 | |||
1177 | union { |
||
1178 | struct { |
||
1179 | unsigned int pad:12; |
||
1180 | unsigned int min_array_element:9; |
||
1181 | unsigned int depth:11; |
||
1182 | } bits; |
||
1183 | unsigned int dword; |
||
1184 | } dword4; |
||
1185 | }; |
||
1186 | |||
1187 | struct gen4_drawrect |
||
1188 | { |
||
1189 | struct header header; |
||
1190 | unsigned int xmin:16; |
||
1191 | unsigned int ymin:16; |
||
1192 | unsigned int xmax:16; |
||
1193 | unsigned int ymax:16; |
||
1194 | unsigned int xorg:16; |
||
1195 | unsigned int yorg:16; |
||
1196 | }; |
||
1197 | |||
1198 | |||
1199 | |||
1200 | |||
1201 | struct gen4_global_depth_offset_clamp |
||
1202 | { |
||
1203 | struct header header; |
||
1204 | float depth_offset_clamp; |
||
1205 | }; |
||
1206 | |||
1207 | struct gen4_indexbuffer |
||
1208 | { |
||
1209 | union { |
||
1210 | struct |
||
1211 | { |
||
1212 | unsigned int length:8; |
||
1213 | unsigned int index_format:2; |
||
1214 | unsigned int cut_index_enable:1; |
||
1215 | unsigned int pad:5; |
||
1216 | unsigned int opcode:16; |
||
1217 | } bits; |
||
1218 | unsigned int dword; |
||
1219 | |||
1220 | } header; |
||
1221 | |||
1222 | unsigned int buffer_start; |
||
1223 | unsigned int buffer_end; |
||
1224 | }; |
||
1225 | |||
1226 | |||
1227 | struct gen4_line_stipple |
||
1228 | { |
||
1229 | struct header header; |
||
1230 | |||
1231 | struct |
||
1232 | { |
||
1233 | unsigned int pattern:16; |
||
1234 | unsigned int pad:16; |
||
1235 | } bits0; |
||
1236 | |||
1237 | struct |
||
1238 | { |
||
1239 | unsigned int repeat_count:9; |
||
1240 | unsigned int pad:7; |
||
1241 | unsigned int inverse_repeat_count:16; |
||
1242 | } bits1; |
||
1243 | }; |
||
1244 | |||
1245 | |||
1246 | struct gen4_pipelined_state_pointers |
||
1247 | { |
||
1248 | struct header header; |
||
1249 | |||
1250 | struct { |
||
1251 | unsigned int pad:5; |
||
1252 | unsigned int offset:27; |
||
1253 | } vs; |
||
1254 | |||
1255 | struct |
||
1256 | { |
||
1257 | unsigned int enable:1; |
||
1258 | unsigned int pad:4; |
||
1259 | unsigned int offset:27; |
||
1260 | } gs; |
||
1261 | |||
1262 | struct |
||
1263 | { |
||
1264 | unsigned int enable:1; |
||
1265 | unsigned int pad:4; |
||
1266 | unsigned int offset:27; |
||
1267 | } clp; |
||
1268 | |||
1269 | struct |
||
1270 | { |
||
1271 | unsigned int pad:5; |
||
1272 | unsigned int offset:27; |
||
1273 | } sf; |
||
1274 | |||
1275 | struct |
||
1276 | { |
||
1277 | unsigned int pad:5; |
||
1278 | unsigned int offset:27; |
||
1279 | } wm; |
||
1280 | |||
1281 | struct |
||
1282 | { |
||
1283 | unsigned int pad:5; |
||
1284 | unsigned int offset:27; /* KW: check me! */ |
||
1285 | } cc; |
||
1286 | }; |
||
1287 | |||
1288 | |||
1289 | struct gen4_polygon_stipple_offset |
||
1290 | { |
||
1291 | struct header header; |
||
1292 | |||
1293 | struct { |
||
1294 | unsigned int y_offset:5; |
||
1295 | unsigned int pad:3; |
||
1296 | unsigned int x_offset:5; |
||
1297 | unsigned int pad0:19; |
||
1298 | } bits0; |
||
1299 | }; |
||
1300 | |||
1301 | |||
1302 | |||
1303 | struct gen4_polygon_stipple |
||
1304 | { |
||
1305 | struct header header; |
||
1306 | unsigned int stipple[32]; |
||
1307 | }; |
||
1308 | |||
1309 | |||
1310 | |||
1311 | struct gen4_pipeline_select |
||
1312 | { |
||
1313 | struct |
||
1314 | { |
||
1315 | unsigned int pipeline_select:1; |
||
1316 | unsigned int pad:15; |
||
1317 | unsigned int opcode:16; |
||
1318 | } header; |
||
1319 | }; |
||
1320 | |||
1321 | |||
1322 | struct gen4_pipe_control |
||
1323 | { |
||
1324 | struct |
||
1325 | { |
||
1326 | unsigned int length:8; |
||
1327 | unsigned int notify_enable:1; |
||
1328 | unsigned int pad:2; |
||
1329 | unsigned int instruction_state_cache_flush_enable:1; |
||
1330 | unsigned int write_cache_flush_enable:1; |
||
1331 | unsigned int depth_stall_enable:1; |
||
1332 | unsigned int post_sync_operation:2; |
||
1333 | |||
1334 | unsigned int opcode:16; |
||
1335 | } header; |
||
1336 | |||
1337 | struct |
||
1338 | { |
||
1339 | unsigned int pad:2; |
||
1340 | unsigned int dest_addr_type:1; |
||
1341 | unsigned int dest_addr:29; |
||
1342 | } bits1; |
||
1343 | |||
1344 | unsigned int data0; |
||
1345 | unsigned int data1; |
||
1346 | }; |
||
1347 | |||
1348 | |||
1349 | struct gen4_urb_fence |
||
1350 | { |
||
1351 | struct |
||
1352 | { |
||
1353 | unsigned int length:8; |
||
1354 | unsigned int vs_realloc:1; |
||
1355 | unsigned int gs_realloc:1; |
||
1356 | unsigned int clp_realloc:1; |
||
1357 | unsigned int sf_realloc:1; |
||
1358 | unsigned int vfe_realloc:1; |
||
1359 | unsigned int cs_realloc:1; |
||
1360 | unsigned int pad:2; |
||
1361 | unsigned int opcode:16; |
||
1362 | } header; |
||
1363 | |||
1364 | struct |
||
1365 | { |
||
1366 | unsigned int vs_fence:10; |
||
1367 | unsigned int gs_fence:10; |
||
1368 | unsigned int clp_fence:10; |
||
1369 | unsigned int pad:2; |
||
1370 | } bits0; |
||
1371 | |||
1372 | struct |
||
1373 | { |
||
1374 | unsigned int sf_fence:10; |
||
1375 | unsigned int vf_fence:10; |
||
1376 | unsigned int cs_fence:10; |
||
1377 | unsigned int pad:2; |
||
1378 | } bits1; |
||
1379 | }; |
||
1380 | |||
1381 | struct gen4_constant_buffer_state /* previously gen4_command_streamer */ |
||
1382 | { |
||
1383 | struct header header; |
||
1384 | |||
1385 | struct |
||
1386 | { |
||
1387 | unsigned int nr_urb_entries:3; |
||
1388 | unsigned int pad:1; |
||
1389 | unsigned int urb_entry_size:5; |
||
1390 | unsigned int pad0:23; |
||
1391 | } bits0; |
||
1392 | }; |
||
1393 | |||
1394 | struct gen4_constant_buffer |
||
1395 | { |
||
1396 | struct |
||
1397 | { |
||
1398 | unsigned int length:8; |
||
1399 | unsigned int valid:1; |
||
1400 | unsigned int pad:7; |
||
1401 | unsigned int opcode:16; |
||
1402 | } header; |
||
1403 | |||
1404 | struct |
||
1405 | { |
||
1406 | unsigned int buffer_length:6; |
||
1407 | unsigned int buffer_address:26; |
||
1408 | } bits0; |
||
1409 | }; |
||
1410 | |||
1411 | struct gen4_state_base_address |
||
1412 | { |
||
1413 | struct header header; |
||
1414 | |||
1415 | struct |
||
1416 | { |
||
1417 | unsigned int modify_enable:1; |
||
1418 | unsigned int pad:4; |
||
1419 | unsigned int general_state_address:27; |
||
1420 | } bits0; |
||
1421 | |||
1422 | struct |
||
1423 | { |
||
1424 | unsigned int modify_enable:1; |
||
1425 | unsigned int pad:4; |
||
1426 | unsigned int surface_state_address:27; |
||
1427 | } bits1; |
||
1428 | |||
1429 | struct |
||
1430 | { |
||
1431 | unsigned int modify_enable:1; |
||
1432 | unsigned int pad:4; |
||
1433 | unsigned int indirect_object_state_address:27; |
||
1434 | } bits2; |
||
1435 | |||
1436 | struct |
||
1437 | { |
||
1438 | unsigned int modify_enable:1; |
||
1439 | unsigned int pad:11; |
||
1440 | unsigned int general_state_upper_bound:20; |
||
1441 | } bits3; |
||
1442 | |||
1443 | struct |
||
1444 | { |
||
1445 | unsigned int modify_enable:1; |
||
1446 | unsigned int pad:11; |
||
1447 | unsigned int indirect_object_state_upper_bound:20; |
||
1448 | } bits4; |
||
1449 | }; |
||
1450 | |||
1451 | struct gen4_state_prefetch |
||
1452 | { |
||
1453 | struct header header; |
||
1454 | |||
1455 | struct |
||
1456 | { |
||
1457 | unsigned int prefetch_count:3; |
||
1458 | unsigned int pad:3; |
||
1459 | unsigned int prefetch_pointer:26; |
||
1460 | } bits0; |
||
1461 | }; |
||
1462 | |||
1463 | struct gen4_system_instruction_pointer |
||
1464 | { |
||
1465 | struct header header; |
||
1466 | |||
1467 | struct |
||
1468 | { |
||
1469 | unsigned int pad:4; |
||
1470 | unsigned int system_instruction_pointer:28; |
||
1471 | } bits0; |
||
1472 | }; |
||
1473 | |||
1474 | |||
1475 | |||
1476 | |||
1477 | /* State structs for the various fixed function units: |
||
1478 | */ |
||
1479 | |||
1480 | |||
1481 | struct thread0 |
||
1482 | { |
||
1483 | unsigned int pad0:1; |
||
1484 | unsigned int grf_reg_count:3; |
||
1485 | unsigned int pad1:2; |
||
1486 | unsigned int kernel_start_pointer:26; |
||
1487 | }; |
||
1488 | |||
1489 | struct thread1 |
||
1490 | { |
||
1491 | unsigned int ext_halt_exception_enable:1; |
||
1492 | unsigned int sw_exception_enable:1; |
||
1493 | unsigned int mask_stack_exception_enable:1; |
||
1494 | unsigned int timeout_exception_enable:1; |
||
1495 | unsigned int illegal_op_exception_enable:1; |
||
1496 | unsigned int pad0:3; |
||
1497 | unsigned int depth_coef_urb_read_offset:6; /* WM only */ |
||
1498 | unsigned int pad1:2; |
||
1499 | unsigned int floating_point_mode:1; |
||
1500 | unsigned int thread_priority:1; |
||
1501 | unsigned int binding_table_entry_count:8; |
||
1502 | unsigned int pad3:5; |
||
1503 | unsigned int single_program_flow:1; |
||
1504 | }; |
||
1505 | |||
1506 | struct thread2 |
||
1507 | { |
||
1508 | unsigned int per_thread_scratch_space:4; |
||
1509 | unsigned int pad0:6; |
||
1510 | unsigned int scratch_space_base_pointer:22; |
||
1511 | }; |
||
1512 | |||
1513 | |||
1514 | struct thread3 |
||
1515 | { |
||
1516 | unsigned int dispatch_grf_start_reg:4; |
||
1517 | unsigned int urb_entry_read_offset:6; |
||
1518 | unsigned int pad0:1; |
||
1519 | unsigned int urb_entry_read_length:6; |
||
1520 | unsigned int pad1:1; |
||
1521 | unsigned int const_urb_entry_read_offset:6; |
||
1522 | unsigned int pad2:1; |
||
1523 | unsigned int const_urb_entry_read_length:6; |
||
1524 | unsigned int pad3:1; |
||
1525 | }; |
||
1526 | |||
1527 | |||
1528 | |||
1529 | struct gen4_clip_unit_state |
||
1530 | { |
||
1531 | struct thread0 thread0; |
||
1532 | struct thread1 thread1; |
||
1533 | struct thread2 thread2; |
||
1534 | struct thread3 thread3; |
||
1535 | |||
1536 | struct |
||
1537 | { |
||
1538 | unsigned int pad0:9; |
||
1539 | unsigned int gs_output_stats:1; /* not always */ |
||
1540 | unsigned int stats_enable:1; |
||
1541 | unsigned int nr_urb_entries:7; |
||
1542 | unsigned int pad1:1; |
||
1543 | unsigned int urb_entry_allocation_size:5; |
||
1544 | unsigned int pad2:1; |
||
1545 | unsigned int max_threads:6; /* may be less */ |
||
1546 | unsigned int pad3:1; |
||
1547 | } thread4; |
||
1548 | |||
1549 | struct |
||
1550 | { |
||
1551 | unsigned int pad0:13; |
||
1552 | unsigned int clip_mode:3; |
||
1553 | unsigned int userclip_enable_flags:8; |
||
1554 | unsigned int userclip_must_clip:1; |
||
1555 | unsigned int pad1:1; |
||
1556 | unsigned int guard_band_enable:1; |
||
1557 | unsigned int viewport_z_clip_enable:1; |
||
1558 | unsigned int viewport_xy_clip_enable:1; |
||
1559 | unsigned int vertex_position_space:1; |
||
1560 | unsigned int api_mode:1; |
||
1561 | unsigned int pad2:1; |
||
1562 | } clip5; |
||
1563 | |||
1564 | struct |
||
1565 | { |
||
1566 | unsigned int pad0:5; |
||
1567 | unsigned int clipper_viewport_state_ptr:27; |
||
1568 | } clip6; |
||
1569 | |||
1570 | |||
1571 | float viewport_xmin; |
||
1572 | float viewport_xmax; |
||
1573 | float viewport_ymin; |
||
1574 | float viewport_ymax; |
||
1575 | }; |
||
1576 | |||
1577 | |||
1578 | |||
1579 | struct gen4_cc_unit_state |
||
1580 | { |
||
1581 | struct |
||
1582 | { |
||
1583 | unsigned int pad0:3; |
||
1584 | unsigned int bf_stencil_pass_depth_pass_op:3; |
||
1585 | unsigned int bf_stencil_pass_depth_fail_op:3; |
||
1586 | unsigned int bf_stencil_fail_op:3; |
||
1587 | unsigned int bf_stencil_func:3; |
||
1588 | unsigned int bf_stencil_enable:1; |
||
1589 | unsigned int pad1:2; |
||
1590 | unsigned int stencil_write_enable:1; |
||
1591 | unsigned int stencil_pass_depth_pass_op:3; |
||
1592 | unsigned int stencil_pass_depth_fail_op:3; |
||
1593 | unsigned int stencil_fail_op:3; |
||
1594 | unsigned int stencil_func:3; |
||
1595 | unsigned int stencil_enable:1; |
||
1596 | } cc0; |
||
1597 | |||
1598 | |||
1599 | struct |
||
1600 | { |
||
1601 | unsigned int bf_stencil_ref:8; |
||
1602 | unsigned int stencil_write_mask:8; |
||
1603 | unsigned int stencil_test_mask:8; |
||
1604 | unsigned int stencil_ref:8; |
||
1605 | } cc1; |
||
1606 | |||
1607 | |||
1608 | struct |
||
1609 | { |
||
1610 | unsigned int logicop_enable:1; |
||
1611 | unsigned int pad0:10; |
||
1612 | unsigned int depth_write_enable:1; |
||
1613 | unsigned int depth_test_function:3; |
||
1614 | unsigned int depth_test:1; |
||
1615 | unsigned int bf_stencil_write_mask:8; |
||
1616 | unsigned int bf_stencil_test_mask:8; |
||
1617 | } cc2; |
||
1618 | |||
1619 | |||
1620 | struct |
||
1621 | { |
||
1622 | unsigned int pad0:8; |
||
1623 | unsigned int alpha_test_func:3; |
||
1624 | unsigned int alpha_test:1; |
||
1625 | unsigned int blend_enable:1; |
||
1626 | unsigned int ia_blend_enable:1; |
||
1627 | unsigned int pad1:1; |
||
1628 | unsigned int alpha_test_format:1; |
||
1629 | unsigned int pad2:16; |
||
1630 | } cc3; |
||
1631 | |||
1632 | struct |
||
1633 | { |
||
1634 | unsigned int pad0:5; |
||
1635 | unsigned int cc_viewport_state_offset:27; |
||
1636 | } cc4; |
||
1637 | |||
1638 | struct |
||
1639 | { |
||
1640 | unsigned int pad0:2; |
||
1641 | unsigned int ia_dest_blend_factor:5; |
||
1642 | unsigned int ia_src_blend_factor:5; |
||
1643 | unsigned int ia_blend_function:3; |
||
1644 | unsigned int statistics_enable:1; |
||
1645 | unsigned int logicop_func:4; |
||
1646 | unsigned int pad1:11; |
||
1647 | unsigned int dither_enable:1; |
||
1648 | } cc5; |
||
1649 | |||
1650 | struct |
||
1651 | { |
||
1652 | unsigned int clamp_post_alpha_blend:1; |
||
1653 | unsigned int clamp_pre_alpha_blend:1; |
||
1654 | unsigned int clamp_range:2; |
||
1655 | unsigned int pad0:11; |
||
1656 | unsigned int y_dither_offset:2; |
||
1657 | unsigned int x_dither_offset:2; |
||
1658 | unsigned int dest_blend_factor:5; |
||
1659 | unsigned int src_blend_factor:5; |
||
1660 | unsigned int blend_function:3; |
||
1661 | } cc6; |
||
1662 | |||
1663 | struct { |
||
1664 | union { |
||
1665 | float f; |
||
1666 | unsigned char ub[4]; |
||
1667 | } alpha_ref; |
||
1668 | } cc7; |
||
1669 | }; |
||
1670 | |||
1671 | |||
1672 | |||
1673 | struct gen4_sf_unit_state |
||
1674 | { |
||
1675 | struct thread0 thread0; |
||
1676 | struct { |
||
1677 | unsigned int pad0:7; |
||
1678 | unsigned int sw_exception_enable:1; |
||
1679 | unsigned int pad1:3; |
||
1680 | unsigned int mask_stack_exception_enable:1; |
||
1681 | unsigned int pad2:1; |
||
1682 | unsigned int illegal_op_exception_enable:1; |
||
1683 | unsigned int pad3:2; |
||
1684 | unsigned int floating_point_mode:1; |
||
1685 | unsigned int thread_priority:1; |
||
1686 | unsigned int binding_table_entry_count:8; |
||
1687 | unsigned int pad4:5; |
||
1688 | unsigned int single_program_flow:1; |
||
1689 | } sf1; |
||
1690 | |||
1691 | struct thread2 thread2; |
||
1692 | struct thread3 thread3; |
||
1693 | |||
1694 | struct |
||
1695 | { |
||
1696 | unsigned int pad0:10; |
||
1697 | unsigned int stats_enable:1; |
||
1698 | unsigned int nr_urb_entries:7; |
||
1699 | unsigned int pad1:1; |
||
1700 | unsigned int urb_entry_allocation_size:5; |
||
1701 | unsigned int pad2:1; |
||
1702 | unsigned int max_threads:6; |
||
1703 | unsigned int pad3:1; |
||
1704 | } thread4; |
||
1705 | |||
1706 | struct |
||
1707 | { |
||
1708 | unsigned int front_winding:1; |
||
1709 | unsigned int viewport_transform:1; |
||
1710 | unsigned int pad0:3; |
||
1711 | unsigned int sf_viewport_state_offset:27; |
||
1712 | } sf5; |
||
1713 | |||
1714 | struct |
||
1715 | { |
||
1716 | unsigned int pad0:9; |
||
1717 | unsigned int dest_org_vbias:4; |
||
1718 | unsigned int dest_org_hbias:4; |
||
1719 | unsigned int scissor:1; |
||
1720 | unsigned int disable_2x2_trifilter:1; |
||
1721 | unsigned int disable_zero_pix_trifilter:1; |
||
1722 | unsigned int point_rast_rule:2; |
||
1723 | unsigned int line_endcap_aa_region_width:2; |
||
1724 | unsigned int line_width:4; |
||
1725 | unsigned int fast_scissor_disable:1; |
||
1726 | unsigned int cull_mode:2; |
||
1727 | unsigned int aa_enable:1; |
||
1728 | } sf6; |
||
1729 | |||
1730 | struct |
||
1731 | { |
||
1732 | unsigned int point_size:11; |
||
1733 | unsigned int use_point_size_state:1; |
||
1734 | unsigned int subpixel_precision:1; |
||
1735 | unsigned int sprite_point:1; |
||
1736 | unsigned int pad0:11; |
||
1737 | unsigned int trifan_pv:2; |
||
1738 | unsigned int linestrip_pv:2; |
||
1739 | unsigned int tristrip_pv:2; |
||
1740 | unsigned int line_last_pixel_enable:1; |
||
1741 | } sf7; |
||
1742 | |||
1743 | }; |
||
1744 | |||
1745 | |||
1746 | struct gen4_gs_unit_state |
||
1747 | { |
||
1748 | struct thread0 thread0; |
||
1749 | struct thread1 thread1; |
||
1750 | struct thread2 thread2; |
||
1751 | struct thread3 thread3; |
||
1752 | |||
1753 | struct |
||
1754 | { |
||
1755 | unsigned int pad0:10; |
||
1756 | unsigned int stats_enable:1; |
||
1757 | unsigned int nr_urb_entries:7; |
||
1758 | unsigned int pad1:1; |
||
1759 | unsigned int urb_entry_allocation_size:5; |
||
1760 | unsigned int pad2:1; |
||
1761 | unsigned int max_threads:1; |
||
1762 | unsigned int pad3:6; |
||
1763 | } thread4; |
||
1764 | |||
1765 | struct |
||
1766 | { |
||
1767 | unsigned int sampler_count:3; |
||
1768 | unsigned int pad0:2; |
||
1769 | unsigned int sampler_state_pointer:27; |
||
1770 | } gs5; |
||
1771 | |||
1772 | |||
1773 | struct |
||
1774 | { |
||
1775 | unsigned int max_vp_index:4; |
||
1776 | unsigned int pad0:26; |
||
1777 | unsigned int reorder_enable:1; |
||
1778 | unsigned int pad1:1; |
||
1779 | } gs6; |
||
1780 | }; |
||
1781 | |||
1782 | |||
1783 | struct gen4_vs_unit_state |
||
1784 | { |
||
1785 | struct thread0 thread0; |
||
1786 | struct thread1 thread1; |
||
1787 | struct thread2 thread2; |
||
1788 | struct thread3 thread3; |
||
1789 | |||
1790 | struct |
||
1791 | { |
||
1792 | unsigned int pad0:10; |
||
1793 | unsigned int stats_enable:1; |
||
1794 | unsigned int nr_urb_entries:7; |
||
1795 | unsigned int pad1:1; |
||
1796 | unsigned int urb_entry_allocation_size:5; |
||
1797 | unsigned int pad2:1; |
||
1798 | unsigned int max_threads:4; |
||
1799 | unsigned int pad3:3; |
||
1800 | } thread4; |
||
1801 | |||
1802 | struct |
||
1803 | { |
||
1804 | unsigned int sampler_count:3; |
||
1805 | unsigned int pad0:2; |
||
1806 | unsigned int sampler_state_pointer:27; |
||
1807 | } vs5; |
||
1808 | |||
1809 | struct |
||
1810 | { |
||
1811 | unsigned int vs_enable:1; |
||
1812 | unsigned int vert_cache_disable:1; |
||
1813 | unsigned int pad0:30; |
||
1814 | } vs6; |
||
1815 | }; |
||
1816 | |||
1817 | |||
1818 | struct gen4_wm_unit_state |
||
1819 | { |
||
1820 | struct thread0 thread0; |
||
1821 | struct thread1 thread1; |
||
1822 | struct thread2 thread2; |
||
1823 | struct thread3 thread3; |
||
1824 | |||
1825 | struct { |
||
1826 | unsigned int stats_enable:1; |
||
1827 | unsigned int pad0:1; |
||
1828 | unsigned int sampler_count:3; |
||
1829 | unsigned int sampler_state_pointer:27; |
||
1830 | } wm4; |
||
1831 | |||
1832 | struct |
||
1833 | { |
||
1834 | unsigned int enable_8_pix:1; |
||
1835 | unsigned int enable_16_pix:1; |
||
1836 | unsigned int enable_32_pix:1; |
||
1837 | unsigned int pad0:7; |
||
1838 | unsigned int legacy_global_depth_bias:1; |
||
1839 | unsigned int line_stipple:1; |
||
1840 | unsigned int depth_offset:1; |
||
1841 | unsigned int polygon_stipple:1; |
||
1842 | unsigned int line_aa_region_width:2; |
||
1843 | unsigned int line_endcap_aa_region_width:2; |
||
1844 | unsigned int early_depth_test:1; |
||
1845 | unsigned int thread_dispatch_enable:1; |
||
1846 | unsigned int program_uses_depth:1; |
||
1847 | unsigned int program_computes_depth:1; |
||
1848 | unsigned int program_uses_killpixel:1; |
||
1849 | unsigned int legacy_line_rast: 1; |
||
1850 | unsigned int transposed_urb_read:1; |
||
1851 | unsigned int max_threads:7; |
||
1852 | } wm5; |
||
1853 | |||
1854 | float global_depth_offset_constant; |
||
1855 | float global_depth_offset_scale; |
||
1856 | |||
1857 | struct { |
||
1858 | unsigned int pad0:1; |
||
1859 | unsigned int grf_reg_count_1:3; |
||
1860 | unsigned int pad1:2; |
||
1861 | unsigned int kernel_start_pointer_1:26; |
||
1862 | } wm8; |
||
1863 | |||
1864 | struct { |
||
1865 | unsigned int pad0:1; |
||
1866 | unsigned int grf_reg_count_2:3; |
||
1867 | unsigned int pad1:2; |
||
1868 | unsigned int kernel_start_pointer_2:26; |
||
1869 | } wm9; |
||
1870 | |||
1871 | struct { |
||
1872 | unsigned int pad0:1; |
||
1873 | unsigned int grf_reg_count_3:3; |
||
1874 | unsigned int pad1:2; |
||
1875 | unsigned int kernel_start_pointer_3:26; |
||
1876 | } wm10; |
||
1877 | }; |
||
1878 | |||
1879 | struct gen4_wm_unit_state_padded { |
||
1880 | struct gen4_wm_unit_state state; |
||
1881 | char pad[64 - sizeof(struct gen4_wm_unit_state)]; |
||
1882 | }; |
||
1883 | |||
1884 | /* The hardware supports two different modes for border color. The |
||
1885 | * default (OpenGL) mode uses floating-point color channels, while the |
||
1886 | * legacy mode uses 4 bytes. |
||
1887 | * |
||
1888 | * More significantly, the legacy mode respects the components of the |
||
1889 | * border color for channels not present in the source, (whereas the |
||
1890 | * default mode will ignore the border color's alpha channel and use |
||
1891 | * alpha==1 for an RGB source, for example). |
||
1892 | * |
||
1893 | * The legacy mode matches the semantics specified by the Render |
||
1894 | * extension. |
||
1895 | */ |
||
1896 | struct gen4_sampler_default_border_color { |
||
1897 | float color[4]; |
||
1898 | }; |
||
1899 | |||
1900 | struct gen4_sampler_legacy_border_color { |
||
1901 | uint8_t color[4]; |
||
1902 | }; |
||
1903 | |||
1904 | struct gen4_sampler_state |
||
1905 | { |
||
1906 | |||
1907 | struct |
||
1908 | { |
||
1909 | unsigned int shadow_function:3; |
||
1910 | unsigned int lod_bias:11; |
||
1911 | unsigned int min_filter:3; |
||
1912 | unsigned int mag_filter:3; |
||
1913 | unsigned int mip_filter:2; |
||
1914 | unsigned int base_level:5; |
||
1915 | unsigned int pad:1; |
||
1916 | unsigned int lod_preclamp:1; |
||
1917 | unsigned int border_color_mode:1; |
||
1918 | unsigned int pad0:1; |
||
1919 | unsigned int disable:1; |
||
1920 | } ss0; |
||
1921 | |||
1922 | struct |
||
1923 | { |
||
1924 | unsigned int r_wrap_mode:3; |
||
1925 | unsigned int t_wrap_mode:3; |
||
1926 | unsigned int s_wrap_mode:3; |
||
1927 | unsigned int pad:3; |
||
1928 | unsigned int max_lod:10; |
||
1929 | unsigned int min_lod:10; |
||
1930 | } ss1; |
||
1931 | |||
1932 | |||
1933 | struct |
||
1934 | { |
||
1935 | unsigned int pad:5; |
||
1936 | unsigned int border_color_pointer:27; |
||
1937 | } ss2; |
||
1938 | |||
1939 | struct |
||
1940 | { |
||
1941 | unsigned int pad:19; |
||
1942 | unsigned int max_aniso:3; |
||
1943 | unsigned int chroma_key_mode:1; |
||
1944 | unsigned int chroma_key_index:2; |
||
1945 | unsigned int chroma_key_enable:1; |
||
1946 | unsigned int monochrome_filter_width:3; |
||
1947 | unsigned int monochrome_filter_height:3; |
||
1948 | } ss3; |
||
1949 | }; |
||
1950 | |||
1951 | |||
1952 | struct gen4_clipper_viewport |
||
1953 | { |
||
1954 | float xmin; |
||
1955 | float xmax; |
||
1956 | float ymin; |
||
1957 | float ymax; |
||
1958 | }; |
||
1959 | |||
1960 | struct gen4_cc_viewport |
||
1961 | { |
||
1962 | float min_depth; |
||
1963 | float max_depth; |
||
1964 | }; |
||
1965 | |||
1966 | struct gen4_sf_viewport |
||
1967 | { |
||
1968 | struct { |
||
1969 | float m00; |
||
1970 | float m11; |
||
1971 | float m22; |
||
1972 | float m30; |
||
1973 | float m31; |
||
1974 | float m32; |
||
1975 | } viewport; |
||
1976 | |||
1977 | struct { |
||
1978 | short xmin; |
||
1979 | short ymin; |
||
1980 | short xmax; |
||
1981 | short ymax; |
||
1982 | } scissor; |
||
1983 | }; |
||
1984 | |||
1985 | /* Documented in the subsystem/shared-functions/sampler chapter... |
||
1986 | */ |
||
1987 | struct gen4_surface_state |
||
1988 | { |
||
1989 | struct { |
||
1990 | unsigned int cube_pos_z:1; |
||
1991 | unsigned int cube_neg_z:1; |
||
1992 | unsigned int cube_pos_y:1; |
||
1993 | unsigned int cube_neg_y:1; |
||
1994 | unsigned int cube_pos_x:1; |
||
1995 | unsigned int cube_neg_x:1; |
||
1996 | unsigned int pad:3; |
||
1997 | unsigned int render_cache_read_mode:1; |
||
1998 | unsigned int mipmap_layout_mode:1; |
||
1999 | unsigned int vert_line_stride_ofs:1; |
||
2000 | unsigned int vert_line_stride:1; |
||
2001 | unsigned int color_blend:1; |
||
2002 | unsigned int writedisable_blue:1; |
||
2003 | unsigned int writedisable_green:1; |
||
2004 | unsigned int writedisable_red:1; |
||
2005 | unsigned int writedisable_alpha:1; |
||
2006 | unsigned int surface_format:9; |
||
2007 | unsigned int data_return_format:1; |
||
2008 | unsigned int pad0:1; |
||
2009 | unsigned int surface_type:3; |
||
2010 | } ss0; |
||
2011 | |||
2012 | struct { |
||
2013 | unsigned int base_addr; |
||
2014 | } ss1; |
||
2015 | |||
2016 | struct { |
||
2017 | unsigned int render_target_rotation:2; |
||
2018 | unsigned int mip_count:4; |
||
2019 | unsigned int width:13; |
||
2020 | unsigned int height:13; |
||
2021 | } ss2; |
||
2022 | |||
2023 | struct { |
||
2024 | unsigned int tile_walk:1; |
||
2025 | unsigned int tiled_surface:1; |
||
2026 | unsigned int pad:1; |
||
2027 | unsigned int pitch:18; |
||
2028 | unsigned int depth:11; |
||
2029 | } ss3; |
||
2030 | |||
2031 | struct { |
||
2032 | unsigned int pad:19; |
||
2033 | unsigned int min_array_elt:9; |
||
2034 | unsigned int min_lod:4; |
||
2035 | } ss4; |
||
2036 | |||
2037 | struct { |
||
2038 | unsigned int pad:20; |
||
2039 | unsigned int y_offset:4; |
||
2040 | unsigned int pad2:1; |
||
2041 | unsigned int x_offset:7; |
||
2042 | } ss5; |
||
2043 | }; |
||
2044 | |||
2045 | /* Surface state DW0 */ |
||
2046 | #define GEN4_SURFACE_RC_READ_WRITE (1 << 8) |
||
2047 | #define GEN4_SURFACE_MIPLAYOUT_SHIFT 10 |
||
2048 | #define GEN4_SURFACE_MIPMAPLAYOUT_BELOW 0 |
||
2049 | #define GEN4_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
||
2050 | #define GEN4_SURFACE_CUBEFACE_ENABLES 0x3f |
||
2051 | #define GEN4_SURFACE_BLEND_ENABLED (1 << 13) |
||
2052 | #define GEN4_SURFACE_WRITEDISABLE_B_SHIFT 14 |
||
2053 | #define GEN4_SURFACE_WRITEDISABLE_G_SHIFT 15 |
||
2054 | #define GEN4_SURFACE_WRITEDISABLE_R_SHIFT 16 |
||
2055 | #define GEN4_SURFACE_WRITEDISABLE_A_SHIFT 17 |
||
2056 | #define GEN4_SURFACE_FORMAT_SHIFT 18 |
||
2057 | #define GEN4_SURFACE_FORMAT_MASK _MASK(26, 18) |
||
2058 | |||
2059 | #define GEN4_SURFACE_TYPE_SHIFT 29 |
||
2060 | #define GEN4_SURFACE_TYPE_MASK _MASK(31, 29) |
||
2061 | #define GEN4_SURFACE_1D 0 |
||
2062 | #define GEN4_SURFACE_2D 1 |
||
2063 | #define GEN4_SURFACE_3D 2 |
||
2064 | #define GEN4_SURFACE_CUBE 3 |
||
2065 | #define GEN4_SURFACE_BUFFER 4 |
||
2066 | #define GEN4_SURFACE_NULL 7 |
||
2067 | |||
2068 | /* Surface state DW2 */ |
||
2069 | #define GEN4_SURFACE_HEIGHT_SHIFT 19 |
||
2070 | #define GEN4_SURFACE_HEIGHT_MASK _MASK(31, 19) |
||
2071 | #define GEN4_SURFACE_WIDTH_SHIFT 6 |
||
2072 | #define GEN4_SURFACE_WIDTH_MASK _MASK(18, 6) |
||
2073 | #define GEN4_SURFACE_LOD_SHIFT 2 |
||
2074 | #define GEN4_SURFACE_LOD_MASK _MASK(5, 2) |
||
2075 | |||
2076 | /* Surface state DW3 */ |
||
2077 | #define GEN4_SURFACE_DEPTH_SHIFT 21 |
||
2078 | #define GEN4_SURFACE_DEPTH_MASK _MASK(31, 21) |
||
2079 | #define GEN4_SURFACE_PITCH_SHIFT 3 |
||
2080 | #define GEN4_SURFACE_PITCH_MASK _MASK(19, 3) |
||
2081 | #define GEN4_SURFACE_TILED (1 << 1) |
||
2082 | #define GEN4_SURFACE_TILED_Y (1 << 0) |
||
2083 | |||
2084 | /* Surface state DW4 */ |
||
2085 | #define GEN4_SURFACE_MIN_LOD_SHIFT 28 |
||
2086 | #define GEN4_SURFACE_MIN_LOD_MASK _MASK(31, 28) |
||
2087 | |||
2088 | /* Surface state DW5 */ |
||
2089 | #define GEN4_SURFACE_X_OFFSET_SHIFT 25 |
||
2090 | #define GEN4_SURFACE_X_OFFSET_MASK _MASK(31, 25) |
||
2091 | #define GEN4_SURFACE_Y_OFFSET_SHIFT 20 |
||
2092 | #define GEN4_SURFACE_Y_OFFSET_MASK _MASK(23, 20) |
||
2093 | |||
2094 | |||
2095 | struct gen4_vertex_buffer_state |
||
2096 | { |
||
2097 | struct { |
||
2098 | unsigned int pitch:11; |
||
2099 | unsigned int pad:15; |
||
2100 | unsigned int access_type:1; |
||
2101 | unsigned int vb_index:5; |
||
2102 | } vb0; |
||
2103 | |||
2104 | unsigned int start_addr; |
||
2105 | unsigned int max_index; |
||
2106 | #if 1 |
||
2107 | unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */ |
||
2108 | #endif |
||
2109 | }; |
||
2110 | |||
2111 | #define GEN4_VBP_MAX 17 |
||
2112 | |||
2113 | struct gen4_vb_array_state { |
||
2114 | struct header header; |
||
2115 | struct gen4_vertex_buffer_state vb[GEN4_VBP_MAX]; |
||
2116 | }; |
||
2117 | |||
2118 | |||
2119 | struct gen4_vertex_element_state |
||
2120 | { |
||
2121 | struct |
||
2122 | { |
||
2123 | unsigned int src_offset:11; |
||
2124 | unsigned int pad:5; |
||
2125 | unsigned int src_format:9; |
||
2126 | unsigned int pad0:1; |
||
2127 | unsigned int valid:1; |
||
2128 | unsigned int vertex_buffer_index:5; |
||
2129 | } ve0; |
||
2130 | |||
2131 | struct |
||
2132 | { |
||
2133 | unsigned int dst_offset:8; |
||
2134 | unsigned int pad:8; |
||
2135 | unsigned int vfcomponent3:4; |
||
2136 | unsigned int vfcomponent2:4; |
||
2137 | unsigned int vfcomponent1:4; |
||
2138 | unsigned int vfcomponent0:4; |
||
2139 | } ve1; |
||
2140 | }; |
||
2141 | |||
2142 | #define GEN4_VEP_MAX 18 |
||
2143 | |||
2144 | struct gen4_vertex_element_packet { |
||
2145 | struct header header; |
||
2146 | struct gen4_vertex_element_state ve[GEN4_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ |
||
2147 | }; |
||
2148 | |||
2149 | |||
2150 | struct gen4_urb_immediate { |
||
2151 | unsigned int opcode:4; |
||
2152 | unsigned int offset:6; |
||
2153 | unsigned int swizzle_control:2; |
||
2154 | unsigned int pad:1; |
||
2155 | unsigned int allocate:1; |
||
2156 | unsigned int used:1; |
||
2157 | unsigned int complete:1; |
||
2158 | unsigned int response_length:4; |
||
2159 | unsigned int msg_length:4; |
||
2160 | unsigned int msg_target:4; |
||
2161 | unsigned int pad1:3; |
||
2162 | unsigned int end_of_thread:1; |
||
2163 | }; |
||
2164 | |||
2165 | /* Instruction format for the execution units: |
||
2166 | */ |
||
2167 | |||
2168 | struct gen4_instruction |
||
2169 | { |
||
2170 | struct |
||
2171 | { |
||
2172 | unsigned int opcode:7; |
||
2173 | unsigned int pad:1; |
||
2174 | unsigned int access_mode:1; |
||
2175 | unsigned int mask_control:1; |
||
2176 | unsigned int dependency_control:2; |
||
2177 | unsigned int compression_control:2; |
||
2178 | unsigned int thread_control:2; |
||
2179 | unsigned int predicate_control:4; |
||
2180 | unsigned int predicate_inverse:1; |
||
2181 | unsigned int execution_size:3; |
||
2182 | unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */ |
||
2183 | unsigned int pad0:2; |
||
2184 | unsigned int debug_control:1; |
||
2185 | unsigned int saturate:1; |
||
2186 | } header; |
||
2187 | |||
2188 | union { |
||
2189 | struct |
||
2190 | { |
||
2191 | unsigned int dest_reg_file:2; |
||
2192 | unsigned int dest_reg_type:3; |
||
2193 | unsigned int src0_reg_file:2; |
||
2194 | unsigned int src0_reg_type:3; |
||
2195 | unsigned int src1_reg_file:2; |
||
2196 | unsigned int src1_reg_type:3; |
||
2197 | unsigned int pad:1; |
||
2198 | unsigned int dest_subreg_nr:5; |
||
2199 | unsigned int dest_reg_nr:8; |
||
2200 | unsigned int dest_horiz_stride:2; |
||
2201 | unsigned int dest_address_mode:1; |
||
2202 | } da1; |
||
2203 | |||
2204 | struct |
||
2205 | { |
||
2206 | unsigned int dest_reg_file:2; |
||
2207 | unsigned int dest_reg_type:3; |
||
2208 | unsigned int src0_reg_file:2; |
||
2209 | unsigned int src0_reg_type:3; |
||
2210 | unsigned int pad:6; |
||
2211 | int dest_indirect_offset:10; /* offset against the deref'd address reg */ |
||
2212 | unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */ |
||
2213 | unsigned int dest_horiz_stride:2; |
||
2214 | unsigned int dest_address_mode:1; |
||
2215 | } ia1; |
||
2216 | |||
2217 | struct |
||
2218 | { |
||
2219 | unsigned int dest_reg_file:2; |
||
2220 | unsigned int dest_reg_type:3; |
||
2221 | unsigned int src0_reg_file:2; |
||
2222 | unsigned int src0_reg_type:3; |
||
2223 | unsigned int src1_reg_file:2; |
||
2224 | unsigned int src1_reg_type:3; |
||
2225 | unsigned int pad0:1; |
||
2226 | unsigned int dest_writemask:4; |
||
2227 | unsigned int dest_subreg_nr:1; |
||
2228 | unsigned int dest_reg_nr:8; |
||
2229 | unsigned int pad1:2; |
||
2230 | unsigned int dest_address_mode:1; |
||
2231 | } da16; |
||
2232 | |||
2233 | struct |
||
2234 | { |
||
2235 | unsigned int dest_reg_file:2; |
||
2236 | unsigned int dest_reg_type:3; |
||
2237 | unsigned int src0_reg_file:2; |
||
2238 | unsigned int src0_reg_type:3; |
||
2239 | unsigned int pad0:6; |
||
2240 | unsigned int dest_writemask:4; |
||
2241 | int dest_indirect_offset:6; |
||
2242 | unsigned int dest_subreg_nr:3; |
||
2243 | unsigned int pad1:2; |
||
2244 | unsigned int dest_address_mode:1; |
||
2245 | } ia16; |
||
2246 | } bits1; |
||
2247 | |||
2248 | |||
2249 | union { |
||
2250 | struct |
||
2251 | { |
||
2252 | unsigned int src0_subreg_nr:5; |
||
2253 | unsigned int src0_reg_nr:8; |
||
2254 | unsigned int src0_abs:1; |
||
2255 | unsigned int src0_negate:1; |
||
2256 | unsigned int src0_address_mode:1; |
||
2257 | unsigned int src0_horiz_stride:2; |
||
2258 | unsigned int src0_width:3; |
||
2259 | unsigned int src0_vert_stride:4; |
||
2260 | unsigned int flag_reg_nr:1; |
||
2261 | unsigned int pad:6; |
||
2262 | } da1; |
||
2263 | |||
2264 | struct |
||
2265 | { |
||
2266 | int src0_indirect_offset:10; |
||
2267 | unsigned int src0_subreg_nr:3; |
||
2268 | unsigned int src0_abs:1; |
||
2269 | unsigned int src0_negate:1; |
||
2270 | unsigned int src0_address_mode:1; |
||
2271 | unsigned int src0_horiz_stride:2; |
||
2272 | unsigned int src0_width:3; |
||
2273 | unsigned int src0_vert_stride:4; |
||
2274 | unsigned int flag_reg_nr:1; |
||
2275 | unsigned int pad:6; |
||
2276 | } ia1; |
||
2277 | |||
2278 | struct |
||
2279 | { |
||
2280 | unsigned int src0_swz_x:2; |
||
2281 | unsigned int src0_swz_y:2; |
||
2282 | unsigned int src0_subreg_nr:1; |
||
2283 | unsigned int src0_reg_nr:8; |
||
2284 | unsigned int src0_abs:1; |
||
2285 | unsigned int src0_negate:1; |
||
2286 | unsigned int src0_address_mode:1; |
||
2287 | unsigned int src0_swz_z:2; |
||
2288 | unsigned int src0_swz_w:2; |
||
2289 | unsigned int pad0:1; |
||
2290 | unsigned int src0_vert_stride:4; |
||
2291 | unsigned int flag_reg_nr:1; |
||
2292 | unsigned int pad1:6; |
||
2293 | } da16; |
||
2294 | |||
2295 | struct |
||
2296 | { |
||
2297 | unsigned int src0_swz_x:2; |
||
2298 | unsigned int src0_swz_y:2; |
||
2299 | int src0_indirect_offset:6; |
||
2300 | unsigned int src0_subreg_nr:3; |
||
2301 | unsigned int src0_abs:1; |
||
2302 | unsigned int src0_negate:1; |
||
2303 | unsigned int src0_address_mode:1; |
||
2304 | unsigned int src0_swz_z:2; |
||
2305 | unsigned int src0_swz_w:2; |
||
2306 | unsigned int pad0:1; |
||
2307 | unsigned int src0_vert_stride:4; |
||
2308 | unsigned int flag_reg_nr:1; |
||
2309 | unsigned int pad1:6; |
||
2310 | } ia16; |
||
2311 | |||
2312 | } bits2; |
||
2313 | |||
2314 | union |
||
2315 | { |
||
2316 | struct |
||
2317 | { |
||
2318 | unsigned int src1_subreg_nr:5; |
||
2319 | unsigned int src1_reg_nr:8; |
||
2320 | unsigned int src1_abs:1; |
||
2321 | unsigned int src1_negate:1; |
||
2322 | unsigned int pad:1; |
||
2323 | unsigned int src1_horiz_stride:2; |
||
2324 | unsigned int src1_width:3; |
||
2325 | unsigned int src1_vert_stride:4; |
||
2326 | unsigned int pad0:7; |
||
2327 | } da1; |
||
2328 | |||
2329 | struct |
||
2330 | { |
||
2331 | unsigned int src1_swz_x:2; |
||
2332 | unsigned int src1_swz_y:2; |
||
2333 | unsigned int src1_subreg_nr:1; |
||
2334 | unsigned int src1_reg_nr:8; |
||
2335 | unsigned int src1_abs:1; |
||
2336 | unsigned int src1_negate:1; |
||
2337 | unsigned int pad0:1; |
||
2338 | unsigned int src1_swz_z:2; |
||
2339 | unsigned int src1_swz_w:2; |
||
2340 | unsigned int pad1:1; |
||
2341 | unsigned int src1_vert_stride:4; |
||
2342 | unsigned int pad2:7; |
||
2343 | } da16; |
||
2344 | |||
2345 | struct |
||
2346 | { |
||
2347 | int src1_indirect_offset:10; |
||
2348 | unsigned int src1_subreg_nr:3; |
||
2349 | unsigned int src1_abs:1; |
||
2350 | unsigned int src1_negate:1; |
||
2351 | unsigned int pad0:1; |
||
2352 | unsigned int src1_horiz_stride:2; |
||
2353 | unsigned int src1_width:3; |
||
2354 | unsigned int src1_vert_stride:4; |
||
2355 | unsigned int flag_reg_nr:1; |
||
2356 | unsigned int pad1:6; |
||
2357 | } ia1; |
||
2358 | |||
2359 | struct |
||
2360 | { |
||
2361 | unsigned int src1_swz_x:2; |
||
2362 | unsigned int src1_swz_y:2; |
||
2363 | int src1_indirect_offset:6; |
||
2364 | unsigned int src1_subreg_nr:3; |
||
2365 | unsigned int src1_abs:1; |
||
2366 | unsigned int src1_negate:1; |
||
2367 | unsigned int pad0:1; |
||
2368 | unsigned int src1_swz_z:2; |
||
2369 | unsigned int src1_swz_w:2; |
||
2370 | unsigned int pad1:1; |
||
2371 | unsigned int src1_vert_stride:4; |
||
2372 | unsigned int flag_reg_nr:1; |
||
2373 | unsigned int pad2:6; |
||
2374 | } ia16; |
||
2375 | |||
2376 | |||
2377 | struct |
||
2378 | { |
||
2379 | int jump_count:16; /* note: signed */ |
||
2380 | unsigned int pop_count:4; |
||
2381 | unsigned int pad0:12; |
||
2382 | } if_else; |
||
2383 | |||
2384 | struct { |
||
2385 | unsigned int function:4; |
||
2386 | unsigned int int_type:1; |
||
2387 | unsigned int precision:1; |
||
2388 | unsigned int saturate:1; |
||
2389 | unsigned int data_type:1; |
||
2390 | unsigned int pad0:8; |
||
2391 | unsigned int response_length:4; |
||
2392 | unsigned int msg_length:4; |
||
2393 | unsigned int msg_target:4; |
||
2394 | unsigned int pad1:3; |
||
2395 | unsigned int end_of_thread:1; |
||
2396 | } math; |
||
2397 | |||
2398 | struct { |
||
2399 | unsigned int binding_table_index:8; |
||
2400 | unsigned int sampler:4; |
||
2401 | unsigned int return_format:2; |
||
2402 | unsigned int msg_type:2; |
||
2403 | unsigned int response_length:4; |
||
2404 | unsigned int msg_length:4; |
||
2405 | unsigned int msg_target:4; |
||
2406 | unsigned int pad1:3; |
||
2407 | unsigned int end_of_thread:1; |
||
2408 | } sampler; |
||
2409 | |||
2410 | struct gen4_urb_immediate urb; |
||
2411 | |||
2412 | struct { |
||
2413 | unsigned int binding_table_index:8; |
||
2414 | unsigned int msg_control:4; |
||
2415 | unsigned int msg_type:2; |
||
2416 | unsigned int target_cache:2; |
||
2417 | unsigned int response_length:4; |
||
2418 | unsigned int msg_length:4; |
||
2419 | unsigned int msg_target:4; |
||
2420 | unsigned int pad1:3; |
||
2421 | unsigned int end_of_thread:1; |
||
2422 | } dp_read; |
||
2423 | |||
2424 | struct { |
||
2425 | unsigned int binding_table_index:8; |
||
2426 | unsigned int msg_control:3; |
||
2427 | unsigned int pixel_scoreboard_clear:1; |
||
2428 | unsigned int msg_type:3; |
||
2429 | unsigned int send_commit_msg:1; |
||
2430 | unsigned int response_length:4; |
||
2431 | unsigned int msg_length:4; |
||
2432 | unsigned int msg_target:4; |
||
2433 | unsigned int pad1:3; |
||
2434 | unsigned int end_of_thread:1; |
||
2435 | } dp_write; |
||
2436 | |||
2437 | struct { |
||
2438 | unsigned int pad:16; |
||
2439 | unsigned int response_length:4; |
||
2440 | unsigned int msg_length:4; |
||
2441 | unsigned int msg_target:4; |
||
2442 | unsigned int pad1:3; |
||
2443 | unsigned int end_of_thread:1; |
||
2444 | } generic; |
||
2445 | |||
2446 | unsigned int ud; |
||
2447 | } bits3; |
||
2448 | }; |
||
2449 | |||
2450 | /* media pipeline */ |
||
2451 | |||
2452 | struct gen4_vfe_state { |
||
2453 | struct { |
||
2454 | unsigned int per_thread_scratch_space:4; |
||
2455 | unsigned int pad3:3; |
||
2456 | unsigned int extend_vfe_state_present:1; |
||
2457 | unsigned int pad2:2; |
||
2458 | unsigned int scratch_base:22; |
||
2459 | } vfe0; |
||
2460 | |||
2461 | struct { |
||
2462 | unsigned int debug_counter_control:2; |
||
2463 | unsigned int children_present:1; |
||
2464 | unsigned int vfe_mode:4; |
||
2465 | unsigned int pad2:2; |
||
2466 | unsigned int num_urb_entries:7; |
||
2467 | unsigned int urb_entry_alloc_size:9; |
||
2468 | unsigned int max_threads:7; |
||
2469 | } vfe1; |
||
2470 | |||
2471 | struct { |
||
2472 | unsigned int pad4:4; |
||
2473 | unsigned int interface_descriptor_base:28; |
||
2474 | } vfe2; |
||
2475 | }; |
||
2476 | |||
2477 | struct gen4_vld_state { |
||
2478 | struct { |
||
2479 | unsigned int pad6:6; |
||
2480 | unsigned int scan_order:1; |
||
2481 | unsigned int intra_vlc_format:1; |
||
2482 | unsigned int quantizer_scale_type:1; |
||
2483 | unsigned int concealment_motion_vector:1; |
||
2484 | unsigned int frame_predict_frame_dct:1; |
||
2485 | unsigned int top_field_first:1; |
||
2486 | unsigned int picture_structure:2; |
||
2487 | unsigned int intra_dc_precision:2; |
||
2488 | unsigned int f_code_0_0:4; |
||
2489 | unsigned int f_code_0_1:4; |
||
2490 | unsigned int f_code_1_0:4; |
||
2491 | unsigned int f_code_1_1:4; |
||
2492 | } vld0; |
||
2493 | |||
2494 | struct { |
||
2495 | unsigned int pad2:9; |
||
2496 | unsigned int picture_coding_type:2; |
||
2497 | unsigned int pad:21; |
||
2498 | } vld1; |
||
2499 | |||
2500 | struct { |
||
2501 | unsigned int index_0:4; |
||
2502 | unsigned int index_1:4; |
||
2503 | unsigned int index_2:4; |
||
2504 | unsigned int index_3:4; |
||
2505 | unsigned int index_4:4; |
||
2506 | unsigned int index_5:4; |
||
2507 | unsigned int index_6:4; |
||
2508 | unsigned int index_7:4; |
||
2509 | } desc_remap_table0; |
||
2510 | |||
2511 | struct { |
||
2512 | unsigned int index_8:4; |
||
2513 | unsigned int index_9:4; |
||
2514 | unsigned int index_10:4; |
||
2515 | unsigned int index_11:4; |
||
2516 | unsigned int index_12:4; |
||
2517 | unsigned int index_13:4; |
||
2518 | unsigned int index_14:4; |
||
2519 | unsigned int index_15:4; |
||
2520 | } desc_remap_table1; |
||
2521 | }; |
||
2522 | |||
2523 | struct gen4_interface_descriptor { |
||
2524 | struct { |
||
2525 | unsigned int grf_reg_blocks:4; |
||
2526 | unsigned int pad:2; |
||
2527 | unsigned int kernel_start_pointer:26; |
||
2528 | } desc0; |
||
2529 | |||
2530 | struct { |
||
2531 | unsigned int pad:7; |
||
2532 | unsigned int software_exception:1; |
||
2533 | unsigned int pad2:3; |
||
2534 | unsigned int maskstack_exception:1; |
||
2535 | unsigned int pad3:1; |
||
2536 | unsigned int illegal_opcode_exception:1; |
||
2537 | unsigned int pad4:2; |
||
2538 | unsigned int floating_point_mode:1; |
||
2539 | unsigned int thread_priority:1; |
||
2540 | unsigned int single_program_flow:1; |
||
2541 | unsigned int pad5:1; |
||
2542 | unsigned int const_urb_entry_read_offset:6; |
||
2543 | unsigned int const_urb_entry_read_len:6; |
||
2544 | } desc1; |
||
2545 | |||
2546 | struct { |
||
2547 | unsigned int pad:2; |
||
2548 | unsigned int sampler_count:3; |
||
2549 | unsigned int sampler_state_pointer:27; |
||
2550 | } desc2; |
||
2551 | |||
2552 | struct { |
||
2553 | unsigned int binding_table_entry_count:5; |
||
2554 | unsigned int binding_table_pointer:27; |
||
2555 | } desc3; |
||
2556 | }; |
||
2557 | |||
2558 | struct gen6_blend_state |
||
2559 | { |
||
2560 | struct { |
||
2561 | unsigned int dest_blend_factor:5; |
||
2562 | unsigned int source_blend_factor:5; |
||
2563 | unsigned int pad3:1; |
||
2564 | unsigned int blend_func:3; |
||
2565 | unsigned int pad2:1; |
||
2566 | unsigned int ia_dest_blend_factor:5; |
||
2567 | unsigned int ia_source_blend_factor:5; |
||
2568 | unsigned int pad1:1; |
||
2569 | unsigned int ia_blend_func:3; |
||
2570 | unsigned int pad0:1; |
||
2571 | unsigned int ia_blend_enable:1; |
||
2572 | unsigned int blend_enable:1; |
||
2573 | } blend0; |
||
2574 | |||
2575 | struct { |
||
2576 | unsigned int post_blend_clamp_enable:1; |
||
2577 | unsigned int pre_blend_clamp_enable:1; |
||
2578 | unsigned int clamp_range:2; |
||
2579 | unsigned int pad0:4; |
||
2580 | unsigned int x_dither_offset:2; |
||
2581 | unsigned int y_dither_offset:2; |
||
2582 | unsigned int dither_enable:1; |
||
2583 | unsigned int alpha_test_func:3; |
||
2584 | unsigned int alpha_test_enable:1; |
||
2585 | unsigned int pad1:1; |
||
2586 | unsigned int logic_op_func:4; |
||
2587 | unsigned int logic_op_enable:1; |
||
2588 | unsigned int pad2:1; |
||
2589 | unsigned int write_disable_b:1; |
||
2590 | unsigned int write_disable_g:1; |
||
2591 | unsigned int write_disable_r:1; |
||
2592 | unsigned int write_disable_a:1; |
||
2593 | unsigned int pad3:1; |
||
2594 | unsigned int alpha_to_coverage_dither:1; |
||
2595 | unsigned int alpha_to_one:1; |
||
2596 | unsigned int alpha_to_coverage:1; |
||
2597 | } blend1; |
||
2598 | }; |
||
2599 | |||
2600 | struct gen6_color_calc_state |
||
2601 | { |
||
2602 | struct { |
||
2603 | unsigned int alpha_test_format:1; |
||
2604 | unsigned int pad0:14; |
||
2605 | unsigned int round_disable:1; |
||
2606 | unsigned int bf_stencil_ref:8; |
||
2607 | unsigned int stencil_ref:8; |
||
2608 | } cc0; |
||
2609 | |||
2610 | union { |
||
2611 | float alpha_ref_f; |
||
2612 | struct { |
||
2613 | unsigned int ui:8; |
||
2614 | unsigned int pad0:24; |
||
2615 | } alpha_ref_fi; |
||
2616 | } cc1; |
||
2617 | |||
2618 | float constant_r; |
||
2619 | float constant_g; |
||
2620 | float constant_b; |
||
2621 | float constant_a; |
||
2622 | }; |
||
2623 | |||
2624 | struct gen6_depth_stencil_state |
||
2625 | { |
||
2626 | struct { |
||
2627 | unsigned int pad0:3; |
||
2628 | unsigned int bf_stencil_pass_depth_pass_op:3; |
||
2629 | unsigned int bf_stencil_pass_depth_fail_op:3; |
||
2630 | unsigned int bf_stencil_fail_op:3; |
||
2631 | unsigned int bf_stencil_func:3; |
||
2632 | unsigned int bf_stencil_enable:1; |
||
2633 | unsigned int pad1:2; |
||
2634 | unsigned int stencil_write_enable:1; |
||
2635 | unsigned int stencil_pass_depth_pass_op:3; |
||
2636 | unsigned int stencil_pass_depth_fail_op:3; |
||
2637 | unsigned int stencil_fail_op:3; |
||
2638 | unsigned int stencil_func:3; |
||
2639 | unsigned int stencil_enable:1; |
||
2640 | } ds0; |
||
2641 | |||
2642 | struct { |
||
2643 | unsigned int bf_stencil_write_mask:8; |
||
2644 | unsigned int bf_stencil_test_mask:8; |
||
2645 | unsigned int stencil_write_mask:8; |
||
2646 | unsigned int stencil_test_mask:8; |
||
2647 | } ds1; |
||
2648 | |||
2649 | struct { |
||
2650 | unsigned int pad0:26; |
||
2651 | unsigned int depth_write_enable:1; |
||
2652 | unsigned int depth_test_func:3; |
||
2653 | unsigned int pad1:1; |
||
2654 | unsigned int depth_test_enable:1; |
||
2655 | } ds2; |
||
2656 | }; |
||
2657 | |||
2658 | typedef enum { |
||
2659 | SAMPLER_FILTER_NEAREST = 0, |
||
2660 | SAMPLER_FILTER_BILINEAR, |
||
2661 | FILTER_COUNT |
||
2662 | } sampler_filter_t; |
||
2663 | |||
2664 | typedef enum { |
||
2665 | SAMPLER_EXTEND_NONE = 0, |
||
2666 | SAMPLER_EXTEND_REPEAT, |
||
2667 | SAMPLER_EXTEND_PAD, |
||
2668 | SAMPLER_EXTEND_REFLECT, |
||
2669 | EXTEND_COUNT |
||
2670 | } sampler_extend_t; |
||
2671 | |||
2672 | typedef enum { |
||
2673 | WM_KERNEL = 0, |
||
2674 | WM_KERNEL_P, |
||
2675 | |||
2676 | WM_KERNEL_MASK, |
||
2677 | WM_KERNEL_MASK_P, |
||
2678 | |||
2679 | WM_KERNEL_MASKCA, |
||
2680 | WM_KERNEL_MASKCA_P, |
||
2681 | |||
2682 | WM_KERNEL_MASKSA, |
||
2683 | WM_KERNEL_MASKSA_P, |
||
2684 | |||
2685 | WM_KERNEL_OPACITY, |
||
2686 | WM_KERNEL_OPACITY_P, |
||
2687 | |||
2688 | WM_KERNEL_VIDEO_PLANAR, |
||
2689 | WM_KERNEL_VIDEO_PACKED, |
||
2690 | KERNEL_COUNT |
||
2691 | } wm_kernel_t; |
||
2692 | |||
2693 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |