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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | |
| 2111 | serge | 2 | #define PCI_MAP_ROM_REG 0x30 |
| 3 | |||
| 1029 | serge | 4 | |
| 2111 | serge | 5 | #define PCI_MAP_IO 0x00000001 |
| 6 | |||
| 7 | |||
| 8 | #define PCI_MAP_IO_TYPE 0x00000003 |
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| 9 | |||
| 10 | |||
| 11 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
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| 12 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
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| 13 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
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| 14 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
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| 15 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
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| 16 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
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| 17 | |||
| 18 | |||
| 19 | |||
| 20 | |||
| 1029 | serge | 21 | bool destructive, bool *min) |
| 1600 | serge | 22 | { |
| 1029 | serge | 23 | int offset; |
| 24 | u32_t addr1; |
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| 25 | u32_t addr2; |
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| 26 | u32_t mask1; |
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| 27 | u32_t mask2; |
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| 28 | int bits = 0; |
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| 29 | |||
| 30 | |||
| 31 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
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| 32 | * the 6 base address registers, and 6 is the ROM base address register. |
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| 33 | */ |
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| 34 | if (index < 0 || index > 6) |
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| 35 | return 0; |
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| 36 | |||
| 37 | |||
| 38 | *min = destructive; |
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| 39 | |||
| 40 | |||
| 41 | if (index == 6) |
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| 42 | offset = PCI_MAP_ROM_REG; |
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| 43 | else |
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| 44 | offset = PCI_MAP_REG_START + (index << 2); |
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| 45 | |||
| 46 | |||
| 47 | /* |
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| 48 | * Check if this is the second part of a 64 bit address. |
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| 49 | * XXX need to check how endianness affects 64 bit addresses. |
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| 50 | */ |
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| 51 | if (index > 0 && index < 6) { |
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| 52 | addr2 = PciRead32(bus, devfn, offset - 4); |
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| 53 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
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| 54 | return 0; |
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| 55 | } |
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| 56 | |||
| 57 | |||
| 58 | PciWrite32(bus, devfn, offset, 0xffffffff); |
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| 59 | mask1 = PciRead32(bus, devfn, offset); |
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| 60 | PciWrite32(bus, devfn, offset, addr1); |
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| 61 | } else { |
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| 62 | mask1 = addr1; |
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| 63 | } |
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| 64 | |||
| 65 | |||
| 66 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
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| 67 | { |
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| 68 | if (PCIGETMEMORY(mask1) == 0) |
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| 69 | { |
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| 70 | addr2 = PciRead32(bus, devfn, offset + 4); |
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| 71 | if (destructive) |
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| 72 | { |
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| 73 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
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| 74 | mask2 = PciRead32(bus, devfn, offset + 4); |
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| 75 | PciWrite32(bus, devfn, offset + 4, addr2); |
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| 76 | } |
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| 77 | else |
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| 78 | { |
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| 79 | mask2 = addr2; |
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| 80 | } |
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| 81 | if (mask2 == 0) |
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| 82 | return 0; |
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| 83 | bits = 32; |
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| 84 | while ((mask2 & 1) == 0) |
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| 85 | { |
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| 86 | bits++; |
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| 87 | mask2 >>= 1; |
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| 88 | } |
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| 89 | if (bits > 32) |
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| 90 | return bits; |
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| 91 | } |
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| 92 | } |
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| 93 | if (index < 6) |
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| 94 | if (PCI_MAP_IS_MEM(mask1)) |
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| 95 | mask1 = PCIGETMEMORY(mask1); |
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| 96 | else |
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| 97 | mask1 = PCIGETIO(mask1); |
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| 98 | else |
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| 99 | mask1 = PCIGETROM(mask1); |
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| 100 | if (mask1 == 0) |
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| 101 | return 0; |
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| 102 | bits = 0; |
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| 103 | while ((mask1 & 1) == 0) { |
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| 104 | bits++; |
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| 105 | mask1 >>= 1; |
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| 106 | } |
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| 107 | /* I/O maps can be no larger than 8 bits */ |
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| 108 | |||
| 109 | |||
| 110 | bits = 8; |
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| 111 | /* ROM maps can be no larger than 24 bits */ |
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| 112 | if (index == 6 && bits > 24) |
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| 113 | bits = 24; |
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| 114 | return bits; |
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| 115 | } |
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| 116 |