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#define UHCI_USBLEGSUP_DEFAULT  0x2000  /* only PIRQ enable set */

#define UHCI_USBLEGSUP_RWC      0x8f00  /* the R/WC bits */

#define UHCI_USBLEGSUP_RO       0x5040  /* R/O and reserved bits */

#define UHCI_USBINTR                 4  /* interrupt register */

#define UHCI_USBCMD_RUN         0x0001  /* RUN/STOP bit */

#define UHCI_USBCMD_HCRESET     0x0002  /* Host Controller reset */

#define UHCI_USBCMD_EGSM        0x0008  /* Global Suspend Mode */

#define UHCI_USBCMD_CONFIGURE   0x0040  /* Config Flag */

#define UHCI_USBINTR_RESUME     0x0002  /* Resume interrupt enable */

#define  USBCMD_RS              0x0001  /* Run/Stop */

#define  USBCMD_HCRESET         0x0002  /* Host reset */

#define  USBCMD_GRESET          0x0004  /* Global reset */

#define  USBCMD_EGSM            0x0008  /* Global Suspend Mode */

#define  USBCMD_FGR             0x0010  /* Force Global Resume */

#define  USBCMD_SWDBG           0x0020  /* SW Debug mode */

#define  USBCMD_CF              0x0040  /* Config Flag (sw only) */

#define  USBCMD_MAXP            0x0080  /* Max Packet (0 = 32, 1 = 64) */

#define   USBSTS_USBINT         0x0001  /* Interrupt due to IOC */

#define   USBSTS_ERROR          0x0002  /* Interrupt due to error */

#define   USBSTS_RD             0x0004  /* Resume Detect */

#define   USBSTS_HSE            0x0008  /* Host System Error: PCI problems */

#define   USBSTS_HCPE           0x0010  /* Host Controller Process Error:

                                         * the schedule is buggy */

#define   USBSTS_HCH            0x0020  /* HC Halted */

#define  USBFLBASEADD                8

#define  USBSOF                     12

#define  USBSOF_DEFAULT             64  /* Frame length is exactly 1 ms */

#define  USBPORTSC2                 18

 * Make sure the controller is completely inactive, unable to

 * generate interrupts or do DMA.

 */

void uhci_reset_hc(hc_t *hc)

{

	/* Turn off PIRQ enable and SMI enable.  (This also turns off the

	 * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.

	 */

    pciWriteWord(hc->PciTag, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);

	 * new notification of any already connected

	 * ports due to the virtual disconnect that it

	 * implies.

	 */

    out16(hc->iobase + UHCI_USBCMD, UHCI_USBCMD_HCRESET);

    __asm__ __volatile__ ("":::"memory");

        dbgprintf("HCRESET not completed yet!\n");

	 * make sure the controller is stopped.

	 */

    out16(hc->iobase + UHCI_USBINTR, 0);

    out16(hc->iobase + UHCI_USBCMD, 0);

};

{

    u16_t legsup;

	unsigned int cmd, intr;

	 * When restarting a suspended controller, we expect all the

	 * settings to be the same as we left them:

	 *

	 *	PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;

	 *	Controller is stopped and configured with EGSM set;

	 *	No interrupts enabled except possibly Resume Detect.

	 *

	 * If any of these conditions are violated we do a complete reset.

	 */

    legsup = pciReadWord(hc->PciTag, UHCI_USBLEGSUP);

	if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {

        dbgprintf("%s: legsup = 0x%04x\n",__FUNCTION__, legsup);

		goto reset_needed;

	}

    if ( (cmd & UHCI_USBCMD_RUN) ||

        !(cmd & UHCI_USBCMD_CONFIGURE) ||

        !(cmd & UHCI_USBCMD_EGSM))

    {

        dbgprintf("%s: cmd = 0x%04x\n", __FUNCTION__, cmd);

		goto reset_needed;

	}

    if (intr & (~UHCI_USBINTR_RESUME))

    {

        dbgprintf("%s: intr = 0x%04x\n", __FUNCTION__, intr);

		goto reset_needed;

	}

	return 0;

    dbgprintf("Performing full reset\n");

    uhci_reset_hc(hc);

	return 1;

}

{

    hc_t   *hc;

    {

        hc_t       *htmp;

        request_t  *rq;

        u16_t  status;

        if (!(status & ~USBSTS_HCH))            /* shared interrupt, not mine */

            continue;

        out16(htmp->iobase + USBSTS, status);     /* Clear it */

        {

            request_t *rtmp;

            td_t      *td;

            rq = (request_t*)rq->list.next;

                continue;

        };

    }

};

{

    int    port;

    u32_t  ifl;

    u16_t  dev_status;

    td_t   *td;

    int i;

    {

        if(hc->ioBase[i]){

           hc->iobase = hc->ioBase[i];

       //    dbgprintf("Io base_%d 0x%x\n", i,hc->ioBase[i]);

           break;

        };

    };

	 * they may have more but gives no way to determine how many there

	 * are.  However according to the UHCI spec, Bit 7 of the port

	 * status and control register is always set to 1.  So we try to

	 * use this to our advantage.  Another common failure mode when

	 * a nonexistent register is addressed is to return all ones, so

	 * we test for that also.

	 */

    for (port = 0; port < 2; port++)

    {

        u32_t status;

        dbgprintf("port%d status %x\n", port, status);

        if (!(status & 0x0080) || status == 0xffff)

			break;

	}

    dbgprintf("detected %d ports\n\n", port);

	 * isn't already safely quiescent.

	 */

    uhci_check_and_reset_hc(hc);

    hc->frame_dma    = GetPgAddr(hc->frame_base);

    hc->frame_number = 0;

    {

    qh_t *qh = alloc_qh();

    qh->qelem = 1;

    }

    for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i)

        hc->qh[i]->qlink = hc->qh[SKEL_ASYNC]->dma | 2;

    td = alloc_td();

    td->status =  (1<<24) | (1<<23) ;

    td->token  = TOKEN( 0x7FF, DATA0, 0, 0, 0xE1);

    td->buffer = 0;

    td->bk     = NULL;

*/

    {

        int qnum;

            qnum = 9;

    }

    out8(hc->iobase + USBSOF, USBSOF_DEFAULT);

    out32(hc->iobase + USBFLBASEADD, hc->frame_dma);

    out16(hc->iobase + USBFRNUM, 0);

                               USBCMD_MAXP);

        out16(hc->iobase + USBPORTSC1 + (port * 2), 0x200);

    delay(100/10);

    {

        time_t timeout;

        dbgprintf("port%d status %x\n", port, status);

        while(timeout--)

        {

            delay(10/10);

            status = in16(hc->iobase + USBPORTSC1 + (port * 2));

            if(status & 1)

            {

                udev_t *dev = kmalloc(sizeof(udev_t),0);

                status = in16(hc->iobase + USBPORTSC1 + (port * 2));

                dbgprintf("port%d status %x\n", port, status);

                dev->port     = port;

                dev->ep0_size = 8;

                dev->status   = status;

                if(status & 4)

                    dbgprintf(" enabled");

                else

                    dbgprintf(" disabled");

                if(status & 0x100){

                    dev->speed = 0x4000000;

                    dbgprintf(" low speed\n");

                } else {

                    dev->speed = 0;

                    dbgprintf(" full speed\n");

                };

                    list_add_tail(&dev->list, &newdev_list);

                    hc->port_map |= 1<

                }

                else {

                    free(dev);

                    out16(hc->iobase + USBPORTSC1 + (port * 2), 0);

                }

                break;

            };

        };

    };

    return true;

};

      req_descr[4]  = {0x0680,0x0100,0x0000,8};

IN(69) OUT(E1) SETUP(2D)

SETUP(0) IN(1)

SETUP(0) OUT(1) OUT(0) OUT(1)...IN(1)

SETUP(0) IN(1) IN(0) IN(1)...OUT(0)

*/

{

    static  udev_id   = 0;

    static  udev_addr = 0;

    static  u16_t __attribute__((aligned(16)))

            req_addr[4] = {0x0500,0x0001,0x0000,0x0000};

            req_descr[4]  = {0x0680,0x0100,0x0000,8};

    td_t  *td0, *td1, *td2;

    u32_t   dev_status;

    count_t timeout;

    int address;

        return false;

    dev->id   = (++udev_id << 8) | address;

    data[1] = 0;

        return false;

    dev->ep0_size = descr->bMaxPacketSize0;

}

                          void *data, size_t req_size)

{

    td_t  *td, *td_prev;

    addr_t data_dma;

    size_t  size = req_size;

    rq->size = req_size;

    rq->dev  = dev;

        data_dma = DMA(data);

    {

        if ( size < packet_size)

        {

            packet_size = size;

        };

        td->link = 1;

            rq->td_head = td;

            td_prev->link   = td->dma | 4;

        td->status = TD_CTRL_ACTIVE | dev->speed;

        td->token  = TOKEN(packet_size,enp->toggle,enp->address,

                           dev->addr,dir);

        td->buffer = data_dma;

        td->bk     = td_prev;

        size-= packet_size;

        enp->toggle ^= DATA1;

    };

    rq->td_tail = td;

        printf("%s: epic fail\n", __FUNCTION__);

    rq->event.data[0] = (addr_t)rq;

}

                  void *data, size_t req_size)

{

    size_t  packet_size = dev->ep0_size;

    size_t  size = req_size;

    u32_t   toggle = DATA1;

    qh_t   *qh;

    addr_t  data_dma = 0;

    bool    retval;

    rq->size = req_size;

    rq->dev  = dev;

    td0->token  = TOKEN( 8, DATA0, 0, dev->addr, 0x2D);

    td0->buffer = DMA(req);

    td0->bk     = NULL;

        data_dma = DMA(data);

    {

        if ( size < packet_size)

        {

            packet_size = size;

        };

        td_prev->link   = td->dma | 4;

        td->status = TD_CTRL_ACTIVE | dev->speed;

        td->token  = TOKEN(packet_size, toggle, 0,dev->addr, pid);

        td->buffer = data_dma;

        td->bk     = td_prev;

        size-= packet_size;

        toggle ^= DATA1;

    }

    td_prev->link   = td->dma | 4;

    td->status = TD_CTRL_ACTIVE | TD_CTRL_IOC | dev->speed ;

    td->token  = (0x7FF<<21)|DATA1|(dev->addr<<8)|pid;

    td->buffer = 0;

    td->bk     = td_prev;

    rq->td_tail = td;

        printf("%s: epic fail\n", __FUNCTION__);

    rq->event.data[0] = (addr_t)rq;

    dbgprintf("td  status 0x%0x\n", td->status);

        (td_prev->status & TD_ANY_ERROR) ||

        (td->status & TD_ANY_ERROR))

    {

        u32_t dev_status = in16(dev->host->iobase + USBSTS);

                   in16(dev->host->iobase + USBFRNUM),

                   in16(dev->host->iobase + USBCMD),

                    dev_status);

        dbgprintf("td0 status %x\n",td0->status);

        dbgprintf("td_prev status %x\n",td_prev->status);

        dbgprintf("td status %x\n",td->status);

        dbgprintf("qh %x \n", qh->qelem);

    } else retval = true;

    {

        td_prev = td->bk;

        free_td(td);

        td = td_prev;

    }while( td != NULL);

    delete event;

*/

    kfree(rq);

};

{

    static  u16_t __attribute__((aligned(16)))

            req_descr[4]  = {0x0680,0x0100,0x0000,18};

            req_conf[4]  = {0x0680,0x0200,0x0000,9};

    conf_descr_t      *conf;

               dev->id, dev->host->pciId, dev->port);

    {

        dbgprintf("%s epic fail\n",__FUNCTION__);

        return;

    };

              "bLength             %d\n"

              "bDescriptorType     %d\n"

              "bcdUSB              %x\n"

              "bDeviceClass        %x\n"

              "bDeviceSubClass     %x\n"

              "bDeviceProtocol     %x\n"

              "bMaxPacketSize0     %d\n"

              "idVendor            %x\n"

              "idProduct           %x\n"

              "bcdDevice           %x\n"

              "iManufacturer       %x\n"

              "iProduct            %x\n"

              "iSerialNumber       %x\n"

              "bNumConfigurations  %d\n\n",

              descr.bLength, descr.bDescriptorType,

              descr.bcdUSB,  descr.bDeviceClass,

              descr.bDeviceSubClass, descr.bDeviceProtocol,

              descr.bMaxPacketSize0, descr.idVendor,

              descr.idProduct, descr.bcdDevice,

              descr.iManufacturer, descr.iProduct,

              descr.iSerialNumber, descr.bNumConfigurations);

    if( !ctrl_request(dev, req_conf, DIN, &data, 8))

        return;

    conf = malloc(conf_size);

        return;

    dptr+= conf->bLength;

              "bLength             %d\n"

              "bDescriptorType     %d\n"

              "wTotalLength        %d\n"

              "bNumInterfaces      %d\n"

              "bConfigurationValue %x\n"

              "iConfiguration      %d\n"

              "bmAttributes        %x\n"

              "bMaxPower           %dmA\n\n",

              conf->bLength,

              conf->bDescriptorType,

              conf->wTotalLength,

              conf->bNumInterfaces,

              conf->bConfigurationValue,

              conf->iConfiguration,

              conf->bmAttributes,

              conf->bMaxPower*2);

        {

            case USB_CLASS_AUDIO:

                dbgprintf( "audio device\n");

                break;

            case USB_CLASS_HID:

                dev->conf = conf;

                list_del(&dev->list);

                return init_hid(dev);

                dbgprintf("printer\n");

                break;

            case USB_CLASS_MASS_STORAGE:

                dbgprintf("mass storage device\n");

                break;

            case USB_CLASS_HUB:

                dbgprintf("hub device\n");

                break;

            default:

                dbgprintf("unknown device\n");

        };

};

>