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Rev | Author | Line No. | Line |
---|---|---|---|
1029 | serge | 1 | |
2 | #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ |
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1605 | serge | 3 | #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
4 | #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ |
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5 | |||
6 | |||
7 | |||
1029 | serge | 8 | #define UHCI_USBINTR 4 /* interrupt register */ |
9 | #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ |
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10 | #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ |
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11 | #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ |
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12 | #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ |
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13 | #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ |
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14 | |||
15 | |||
16 | |||
17 | #define USBCMD_RS 0x0001 /* Run/Stop */ |
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18 | #define USBCMD_HCRESET 0x0002 /* Host reset */ |
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19 | #define USBCMD_GRESET 0x0004 /* Global reset */ |
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20 | #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ |
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21 | #define USBCMD_FGR 0x0010 /* Force Global Resume */ |
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22 | #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ |
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23 | #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ |
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24 | #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ |
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25 | |||
26 | |||
27 | #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ |
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28 | #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ |
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29 | #define USBSTS_RD 0x0004 /* Resume Detect */ |
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30 | #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ |
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31 | #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: |
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32 | * the schedule is buggy */ |
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33 | #define USBSTS_HCH 0x0020 /* HC Halted */ |
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34 | |||
35 | |||
36 | |||
37 | #define USBFLBASEADD 8 |
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38 | #define USBSOF 12 |
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39 | #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
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40 | |||
41 | |||
42 | #define USBPORTSC2 18 |
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43 | |||
44 | |||
45 | |||
46 | |||
47 | |||
48 | * Make sure the controller is completely inactive, unable to |
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49 | * generate interrupts or do DMA. |
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50 | */ |
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51 | void uhci_reset_hc(hc_t *hc) |
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52 | { |
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53 | /* Turn off PIRQ enable and SMI enable. (This also turns off the |
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54 | * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. |
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55 | */ |
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56 | pciWriteWord(hc->PciTag, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); |
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57 | |||
58 | |||
59 | * new notification of any already connected |
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60 | * ports due to the virtual disconnect that it |
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61 | * implies. |
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62 | */ |
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63 | out16(hc->iobase + UHCI_USBCMD, UHCI_USBCMD_HCRESET); |
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64 | __asm__ __volatile__ ("":::"memory"); |
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65 | |||
66 | |||
67 | |||
68 | |||
69 | dbgprintf("HCRESET not completed yet!\n"); |
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70 | |||
71 | |||
72 | * make sure the controller is stopped. |
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73 | */ |
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74 | out16(hc->iobase + UHCI_USBINTR, 0); |
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75 | out16(hc->iobase + UHCI_USBCMD, 0); |
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76 | }; |
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77 | |||
78 | |||
79 | { |
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80 | u16_t legsup; |
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81 | unsigned int cmd, intr; |
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82 | |||
83 | |||
84 | * When restarting a suspended controller, we expect all the |
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85 | * settings to be the same as we left them: |
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86 | * |
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87 | * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; |
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88 | * Controller is stopped and configured with EGSM set; |
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89 | * No interrupts enabled except possibly Resume Detect. |
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90 | * |
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91 | * If any of these conditions are violated we do a complete reset. |
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92 | */ |
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93 | legsup = pciReadWord(hc->PciTag, UHCI_USBLEGSUP); |
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94 | if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { |
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95 | dbgprintf("%s: legsup = 0x%04x\n",__FUNCTION__, legsup); |
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96 | goto reset_needed; |
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97 | } |
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98 | |||
99 | |||
100 | if ( (cmd & UHCI_USBCMD_RUN) || |
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101 | !(cmd & UHCI_USBCMD_CONFIGURE) || |
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102 | !(cmd & UHCI_USBCMD_EGSM)) |
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103 | { |
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104 | dbgprintf("%s: cmd = 0x%04x\n", __FUNCTION__, cmd); |
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105 | goto reset_needed; |
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106 | } |
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107 | |||
108 | |||
109 | if (intr & (~UHCI_USBINTR_RESUME)) |
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110 | { |
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111 | dbgprintf("%s: intr = 0x%04x\n", __FUNCTION__, intr); |
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112 | goto reset_needed; |
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113 | } |
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114 | return 0; |
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115 | |||
116 | |||
117 | dbgprintf("Performing full reset\n"); |
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118 | uhci_reset_hc(hc); |
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119 | return 1; |
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120 | } |
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121 | |||
122 | |||
1605 | serge | 123 | { |
124 | hc_t *hc; |
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125 | |||
1029 | serge | 126 | |
1613 | serge | 127 | |
1605 | serge | 128 | |
129 | |||
130 | |||
131 | { |
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132 | hc_t *htmp; |
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1613 | serge | 133 | request_t *rq; |
134 | u16_t status; |
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1605 | serge | 135 | |
136 | |||
1613 | serge | 137 | |
138 | |||
1605 | serge | 139 | |
140 | |||
1613 | serge | 141 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
1605 | serge | 142 | continue; |
143 | out16(htmp->iobase + USBSTS, status); /* Clear it */ |
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1613 | serge | 144 | |
145 | |||
146 | |||
147 | |||
148 | { |
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149 | request_t *rtmp; |
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150 | td_t *td; |
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151 | |||
152 | |||
153 | rq = (request_t*)rq->list.next; |
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154 | |||
155 | |||
156 | |||
157 | |||
158 | continue; |
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159 | |||
160 | |||
161 | |||
162 | |||
163 | }; |
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164 | } |
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1605 | serge | 165 | }; |
166 | |||
167 | |||
168 | |||
169 | |||
1600 | serge | 170 | { |
1029 | serge | 171 | int port; |
1600 | serge | 172 | u32_t ifl; |
173 | u16_t dev_status; |
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174 | td_t *td; |
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1605 | serge | 175 | int i; |
1029 | serge | 176 | |
177 | |||
178 | |||
179 | |||
180 | { |
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181 | if(hc->ioBase[i]){ |
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182 | hc->iobase = hc->ioBase[i]; |
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183 | // dbgprintf("Io base_%d 0x%x\n", i,hc->ioBase[i]); |
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184 | break; |
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185 | }; |
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186 | }; |
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187 | |||
188 | |||
189 | * they may have more but gives no way to determine how many there |
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190 | * are. However according to the UHCI spec, Bit 7 of the port |
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191 | * status and control register is always set to 1. So we try to |
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192 | * use this to our advantage. Another common failure mode when |
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193 | * a nonexistent register is addressed is to return all ones, so |
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194 | * we test for that also. |
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195 | */ |
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196 | for (port = 0; port < 2; port++) |
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197 | { |
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198 | u32_t status; |
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199 | |||
200 | |||
201 | dbgprintf("port%d status %x\n", port, status); |
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202 | if (!(status & 0x0080) || status == 0xffff) |
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203 | break; |
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204 | } |
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205 | dbgprintf("detected %d ports\n\n", port); |
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206 | |||
207 | |||
208 | |||
209 | |||
210 | * isn't already safely quiescent. |
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211 | */ |
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212 | uhci_check_and_reset_hc(hc); |
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213 | |||
214 | |||
215 | hc->frame_dma = GetPgAddr(hc->frame_base); |
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216 | hc->frame_number = 0; |
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217 | |||
218 | |||
1616 | serge | 219 | sizeof(td_t), 16, 0); |
220 | if (!hc->td_pool) |
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221 | { |
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222 | dbgprintf("unable to create td dma_pool\n"); |
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223 | goto err_create_td_pool; |
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224 | } |
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225 | |||
1605 | serge | 226 | |
227 | { |
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228 | qh_t *qh = alloc_qh(); |
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1029 | serge | 229 | |
230 | |||
231 | qh->qelem = 1; |
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232 | |||
233 | |||
1605 | serge | 234 | } |
235 | for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) |
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236 | hc->qh[i]->qlink = hc->qh[SKEL_ASYNC]->dma | 2; |
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237 | |||
1029 | serge | 238 | |
1605 | serge | 239 | { |
240 | int qnum; |
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241 | |||
1029 | serge | 242 | |
1605 | serge | 243 | |
244 | |||
245 | qnum = 9; |
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246 | |||
247 | |||
248 | } |
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249 | |||
250 | |||
251 | |||
252 | |||
1029 | serge | 253 | out8(hc->iobase + USBSOF, USBSOF_DEFAULT); |
254 | |||
255 | |||
256 | out32(hc->iobase + USBFLBASEADD, hc->frame_dma); |
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257 | |||
258 | |||
259 | out16(hc->iobase + USBFRNUM, 0); |
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260 | |||
261 | |||
262 | |||
1605 | serge | 263 | |
264 | |||
265 | |||
266 | |||
267 | |||
268 | |||
269 | |||
1029 | serge | 270 | USBCMD_MAXP); |
271 | |||
272 | |||
273 | out16(hc->iobase + USBPORTSC1 + (port * 2), 0x200); |
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274 | |||
275 | |||
276 | { |
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277 | time_t timeout; |
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278 | |||
279 | |||
1875 | serge | 280 | |
281 | |||
1029 | serge | 282 | dbgprintf("port%d status %x\n", port, status); |
283 | |||
284 | |||
285 | |||
286 | |||
287 | while(timeout--) |
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288 | { |
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289 | delay(10/10); |
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290 | status = in16(hc->iobase + USBPORTSC1 + (port * 2)); |
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291 | if(status & 1) |
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292 | { |
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293 | udev_t *dev = kmalloc(sizeof(udev_t),0); |
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1600 | serge | 294 | |
1029 | serge | 295 | |
296 | |||
297 | |||
298 | |||
299 | |||
300 | status = in16(hc->iobase + USBPORTSC1 + (port * 2)); |
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301 | dbgprintf("port%d status %x\n", port, status); |
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302 | |||
303 | |||
1600 | serge | 304 | |
305 | |||
1029 | serge | 306 | dev->port = port; |
307 | dev->ep0_size = 8; |
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308 | dev->status = status; |
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309 | |||
310 | |||
311 | if(status & 4) |
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312 | dbgprintf(" enabled"); |
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313 | else |
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314 | dbgprintf(" disabled"); |
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315 | if(status & 0x100){ |
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316 | dev->speed = 0x4000000; |
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317 | dbgprintf(" low speed\n"); |
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318 | } else { |
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319 | dev->speed = 0; |
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320 | dbgprintf(" full speed\n"); |
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321 | }; |
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322 | |||
323 | |||
324 | list_add_tail(&dev->list, &newdev_list); |
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1600 | serge | 325 | hc->port_map |= 1< |
1029 | serge | 326 | } |
327 | else { |
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328 | free(dev); |
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329 | out16(hc->iobase + USBPORTSC1 + (port * 2), 0); |
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330 | } |
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331 | break; |
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332 | }; |
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333 | }; |
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334 | }; |
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335 | return true; |
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1600 | serge | 336 | |
1616 | serge | 337 | |
338 | |||
339 | |||
340 | |||
341 | |||
342 | }; |
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1029 | serge | 343 | |
344 | |||
345 | req_descr[4] = {0x0680,0x0100,0x0000,8}; |
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346 | |||
347 | |||
348 | IN(69) OUT(E1) SETUP(2D) |
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349 | SETUP(0) IN(1) |
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350 | SETUP(0) OUT(1) OUT(0) OUT(1)...IN(1) |
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351 | SETUP(0) IN(1) IN(0) IN(1)...OUT(0) |
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352 | */ |
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353 | |||
354 | |||
355 | |||
1600 | serge | 356 | { |
1029 | serge | 357 | static udev_id = 0; |
358 | static udev_addr = 0; |
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359 | static u16_t __attribute__((aligned(16))) |
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360 | req_addr[4] = {0x0500,0x0001,0x0000,0x0000}; |
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361 | |||
362 | |||
363 | req_descr[4] = {0x0680,0x0100,0x0000,8}; |
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364 | |||
365 | |||
366 | |||
367 | |||
368 | td_t *td0, *td1, *td2; |
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369 | u32_t dev_status; |
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370 | count_t timeout; |
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371 | int address; |
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372 | |||
373 | |||
374 | |||
375 | |||
376 | |||
377 | |||
378 | return false; |
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1600 | serge | 379 | |
1029 | serge | 380 | |
381 | dev->id = (++udev_id << 8) | address; |
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382 | |||
383 | |||
384 | |||
385 | |||
386 | data[1] = 0; |
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387 | |||
388 | |||
389 | return false; |
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1600 | serge | 390 | |
1029 | serge | 391 | |
392 | dev->ep0_size = descr->bMaxPacketSize0; |
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393 | |||
394 | |||
1600 | serge | 395 | } |
1029 | serge | 396 | |
397 | |||
1875 | serge | 398 | |
399 | |||
400 | |||
401 | |||
402 | size_t data_size) |
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403 | { |
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1029 | serge | 404 | size_t packet_size = dev->ep0_size; |
1875 | serge | 405 | int dsize = data_size; |
406 | size_t buf_size; |
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407 | |||
408 | |||
409 | addr_t td_dma; |
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1616 | serge | 410 | addr_t data_dma; |
1875 | serge | 411 | |
1029 | serge | 412 | |
1875 | serge | 413 | |
1029 | serge | 414 | |
1875 | serge | 415 | int td_count = 0; |
416 | |||
417 | |||
418 | { |
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419 | td_count++; |
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420 | dsize-= packet_size; |
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421 | }; |
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422 | |||
423 | |||
424 | td_count*sizeof(td_t); |
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425 | |||
426 | |||
427 | memset(rq, 0, buf_size); |
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428 | |||
429 | |||
430 | td_dma = data_dma + ALIGN16(data_size); |
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431 | |||
432 | |||
1600 | serge | 433 | |
1029 | serge | 434 | |
1875 | serge | 435 | td = MakePtr(td_t*, rq->data, ALIGN16(data_size)); |
436 | rq->td_head = td; |
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437 | rq->size = data_size; |
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438 | rq->dev = dev; |
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1600 | serge | 439 | |
1029 | serge | 440 | |
441 | |||
442 | |||
1875 | serge | 443 | |
444 | |||
445 | { |
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1029 | serge | 446 | if ( dsize < packet_size) |
1875 | serge | 447 | { |
1600 | serge | 448 | packet_size = dsize; |
1875 | serge | 449 | }; |
1600 | serge | 450 | |
451 | |||
1616 | serge | 452 | |
453 | |||
1600 | serge | 454 | |
1029 | serge | 455 | |
456 | td_prev->link = td->dma | 4; |
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457 | td->status = TD_CTRL_ACTIVE | dev->speed; |
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1605 | serge | 458 | td->token = TOKEN(packet_size,enp->toggle,enp->address, |
1600 | serge | 459 | dev->addr,dir); |
1029 | serge | 460 | td->buffer = data_dma; |
461 | td->bk = td_prev; |
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462 | |||
463 | |||
464 | |||
465 | |||
1875 | serge | 466 | td_dma+= sizeof(td_t); |
467 | data_dma+= packet_size; |
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1600 | serge | 468 | |
1875 | serge | 469 | |
470 | enp->toggle ^= DATA1; |
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1029 | serge | 471 | }; |
1605 | serge | 472 | |
473 | |||
1875 | serge | 474 | rq->td_tail = td_prev; |
475 | |||
1613 | serge | 476 | |
477 | |||
478 | |||
479 | printf("%s: epic fail\n", __FUNCTION__); |
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480 | |||
481 | |||
482 | rq->event.data[0] = (addr_t)rq; |
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483 | |||
484 | |||
1029 | serge | 485 | } |
486 | |||
487 | |||
1600 | serge | 488 | void *data, size_t req_size) |
1029 | serge | 489 | { |
490 | size_t packet_size = dev->ep0_size; |
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491 | size_t size = req_size; |
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492 | u32_t toggle = DATA1; |
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493 | |||
494 | |||
495 | qh_t *qh; |
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496 | addr_t data_dma = 0; |
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497 | hc_t *hc = dev->host; |
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1616 | serge | 498 | |
499 | |||
500 | |||
501 | |||
1600 | serge | 502 | |
1029 | serge | 503 | |
1613 | serge | 504 | |
505 | |||
506 | |||
507 | |||
508 | |||
509 | rq->size = req_size; |
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510 | rq->dev = dev; |
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511 | |||
512 | |||
1616 | serge | 513 | td0->dma = td_dma; |
514 | |||
1029 | serge | 515 | |
1875 | serge | 516 | |
1616 | serge | 517 | |
1029 | serge | 518 | td0->token = TOKEN( 8, DATA0, 0, dev->addr, 0x2D); |
519 | td0->buffer = DMA(req); |
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520 | td0->bk = NULL; |
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521 | |||
522 | |||
523 | data_dma = DMA(data); |
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524 | |||
525 | |||
526 | |||
527 | |||
1600 | serge | 528 | { |
1029 | serge | 529 | if ( size < packet_size) |
1600 | serge | 530 | { |
531 | packet_size = size; |
||
532 | }; |
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533 | |||
534 | |||
1616 | serge | 535 | td->dma = td_dma; |
536 | |||
537 | |||
1875 | serge | 538 | |
1616 | serge | 539 | |
1029 | serge | 540 | td->status = TD_CTRL_ACTIVE | dev->speed; |
1605 | serge | 541 | td->token = TOKEN(packet_size, toggle, 0,dev->addr, pid); |
1029 | serge | 542 | td->buffer = data_dma; |
543 | td->bk = td_prev; |
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544 | |||
545 | |||
546 | |||
547 | |||
548 | size-= packet_size; |
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549 | toggle ^= DATA1; |
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550 | } |
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551 | |||
552 | |||
1616 | serge | 553 | td->dma = td_dma; |
554 | |||
555 | |||
1875 | serge | 556 | |
1616 | serge | 557 | |
1029 | serge | 558 | |
559 | |||
560 | |||
561 | |||
562 | td->status = TD_CTRL_ACTIVE | TD_CTRL_IOC | dev->speed ; |
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1605 | serge | 563 | td->token = (0x7FF<<21)|DATA1|(dev->addr<<8)|pid; |
1029 | serge | 564 | td->buffer = 0; |
565 | td->bk = td_prev; |
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566 | |||
567 | |||
1613 | serge | 568 | rq->td_tail = td; |
569 | |||
570 | |||
571 | |||
572 | |||
573 | printf("%s: epic fail\n", __FUNCTION__); |
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574 | |||
575 | |||
576 | rq->event.data[0] = (addr_t)rq; |
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577 | |||
578 | |||
579 | |||
580 | |||
1875 | serge | 581 | |
1613 | serge | 582 | |
1605 | serge | 583 | |
1029 | serge | 584 | |
585 | |||
586 | |||
1605 | serge | 587 | |
588 | |||
1613 | serge | 589 | |
1029 | serge | 590 | |
1613 | serge | 591 | |
592 | |||
593 | dbgprintf("td status 0x%0x\n", td->status); |
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594 | |||
595 | |||
1029 | serge | 596 | (td_prev->status & TD_ANY_ERROR) || |
597 | (td->status & TD_ANY_ERROR)) |
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598 | { |
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599 | u32_t dev_status = in16(dev->host->iobase + USBSTS); |
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600 | |||
601 | |||
602 | in16(dev->host->iobase + USBFRNUM), |
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603 | in16(dev->host->iobase + USBCMD), |
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604 | dev_status); |
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605 | dbgprintf("td0 status %x\n",td0->status); |
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606 | dbgprintf("td_prev status %x\n",td_prev->status); |
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607 | dbgprintf("td status %x\n",td->status); |
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608 | dbgprintf("qh %x \n", qh->qelem); |
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609 | |||
610 | |||
1600 | serge | 611 | } else retval = true; |
612 | |||
1029 | serge | 613 | |
1613 | serge | 614 | |
615 | |||
616 | |||
617 | |||
1029 | serge | 618 | { |
619 | td_prev = td->bk; |
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620 | dma_pool_free(hc->td_pool, td, td->dma); |
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1616 | serge | 621 | td = td_prev; |
1029 | serge | 622 | }while( td != NULL); |
623 | |||
624 | |||
1613 | serge | 625 | delete event; |
626 | */ |
||
627 | kfree(rq); |
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628 | |||
629 | |||
1029 | serge | 630 | }; |
631 | |||
632 | |||
633 | |||
1600 | serge | 634 | { |
1029 | serge | 635 | static u16_t __attribute__((aligned(16))) |
636 | req_descr[4] = {0x0680,0x0100,0x0000,18}; |
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637 | |||
638 | |||
639 | req_conf[4] = {0x0680,0x0200,0x0000,9}; |
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640 | |||
641 | |||
642 | |||
643 | |||
644 | |||
645 | |||
646 | |||
647 | |||
648 | conf_descr_t *conf; |
||
649 | |||
650 | |||
651 | dev->id, dev->host->pciId, dev->port); |
||
652 | |||
653 | |||
654 | { |
||
1613 | serge | 655 | dbgprintf("%s epic fail\n",__FUNCTION__); |
656 | return; |
||
1029 | serge | 657 | }; |
1613 | serge | 658 | |
1029 | serge | 659 | |
660 | |||
661 | |||
662 | "bLength %d\n" |
||
663 | "bDescriptorType %d\n" |
||
664 | "bcdUSB %x\n" |
||
665 | "bDeviceClass %x\n" |
||
666 | "bDeviceSubClass %x\n" |
||
667 | "bDeviceProtocol %x\n" |
||
668 | "bMaxPacketSize0 %d\n" |
||
669 | "idVendor %x\n" |
||
670 | "idProduct %x\n" |
||
671 | "bcdDevice %x\n" |
||
672 | "iManufacturer %x\n" |
||
673 | "iProduct %x\n" |
||
674 | "iSerialNumber %x\n" |
||
675 | "bNumConfigurations %d\n\n", |
||
676 | descr.bLength, descr.bDescriptorType, |
||
677 | descr.bcdUSB, descr.bDeviceClass, |
||
678 | descr.bDeviceSubClass, descr.bDeviceProtocol, |
||
679 | descr.bMaxPacketSize0, descr.idVendor, |
||
680 | descr.idProduct, descr.bcdDevice, |
||
681 | descr.iManufacturer, descr.iProduct, |
||
682 | descr.iSerialNumber, descr.bNumConfigurations); |
||
683 | |||
684 | |||
685 | if( !ctrl_request(dev, req_conf, DIN, &data, 8)) |
||
686 | return; |
||
687 | |||
688 | |||
689 | |||
690 | |||
691 | |||
692 | |||
693 | conf = malloc(conf_size); |
||
694 | |||
695 | |||
696 | return; |
||
697 | |||
698 | |||
699 | dptr+= conf->bLength; |
||
700 | |||
701 | |||
702 | "bLength %d\n" |
||
703 | "bDescriptorType %d\n" |
||
704 | "wTotalLength %d\n" |
||
705 | "bNumInterfaces %d\n" |
||
706 | "bConfigurationValue %x\n" |
||
707 | "iConfiguration %d\n" |
||
708 | "bmAttributes %x\n" |
||
709 | "bMaxPower %dmA\n\n", |
||
710 | conf->bLength, |
||
711 | conf->bDescriptorType, |
||
712 | conf->wTotalLength, |
||
713 | conf->bNumInterfaces, |
||
714 | conf->bConfigurationValue, |
||
715 | conf->iConfiguration, |
||
716 | conf->bmAttributes, |
||
717 | conf->bMaxPower*2); |
||
718 | |||
719 | |||
720 | |||
721 | |||
722 | { |
||
723 | case USB_CLASS_AUDIO: |
||
724 | dbgprintf( "audio device\n"); |
||
725 | break; |
||
726 | case USB_CLASS_HID: |
||
727 | dev->conf = conf; |
||
728 | list_del(&dev->list); |
||
1600 | serge | 729 | return init_hid(dev); |
1029 | serge | 730 | |
731 | |||
732 | dbgprintf("printer\n"); |
||
733 | break; |
||
734 | case USB_CLASS_MASS_STORAGE: |
||
735 | dbgprintf("mass storage device\n"); |
||
736 | break; |
||
737 | case USB_CLASS_HUB: |
||
738 | dbgprintf("hub device\n"); |
||
739 | break; |
||
740 | default: |
||
741 | dbgprintf("unknown device\n"); |
||
742 | }; |
||
743 | };8)|pid; |
||
744 | ><8)|pid; |