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4522 hidnplayr 1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                                                                 ;;
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;; Copyright (C) KolibriOS team 2004-2018. All rights reserved.    ;;
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;; Distributed under terms of the GNU General Public License       ;;
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;;                                                                 ;;
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;;          GNU GENERAL PUBLIC LICENSE                             ;;
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;;             Version 2, June 1991                                ;;
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;;                                                                 ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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struct  PCI_header
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5066 hidnplayr 13
        vendor_id       dw ?    ; 0x00
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        device_id       dw ?    ; 0x02
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        command         dw ?    ; 0x04
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        status          dw ?    ; 0x06
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        revision_id     db ?    ; 0x08
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        prog_if         db ?    ; 0x09
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        subclass        db ?    ; 0x0A
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        class_code      db ?    ; 0x0B
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        cache_line_size db ?    ; 0x0C
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        latency_timer   db ?    ; 0x0D
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        header_type     db ?    ; 0x0E
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        bist            db ?    ; 0x0F
4522 hidnplayr 25
 
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ends
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struct  PCI_header00    PCI_header
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5066 hidnplayr 30
        base_addr_0     dd ?    ; 0x10
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        base_addr_1     dd ?    ; 0x14
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        base_addr_2     dd ?    ; 0x18
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        base_addr_3     dd ?    ; 0x1C
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        base_addr_4     dd ?    ; 0x20
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        base_addr_5     dd ?    ; 0x24
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        cardbus_cis_ptr dd ?    ; 0x28
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        subsys_vendor   dw ?    ; 0x2C
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        subsys_id       dw ?    ; 0x2E
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        exp_rom_addr    dd ?    ; 0x30
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        cap_ptr         db ?    ; 0x34
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                        rb 7    ; reserved
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        interrupt_line  db ?    ; 0x3C
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        interrupt_pin   db ?    ; 0x3D
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        min_grant       db ?    ; 0x3E
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        max_latency     db ?    ; 0x3F
4522 hidnplayr 46
 
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ends
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5066 hidnplayr 49
struct  PCI_header01    PCI_header
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51
        base_addr_0     dd ?    ; 0x10
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        base_addr_1     dd ?    ; 0x14
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        prim_bus_nr     db ?    ; 0x18
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        sec_bus_nr      db ?    ; 0x19
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        sub_bus_nr      db ?    ; 0x1A
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        sec_lat_tmr     db ?    ; 0x1B
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        io_base         db ?    ; 0x1C
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        io_limit        db ?    ; 0x1D
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        sec_status      dw ?    ; 0x1E
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        mem_base        dw ?    ; 0x20
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        mem_limit       dw ?    ; 0x22
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        pref_mem_base   dw ?    ; 0x24
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        pref_mem_limit  dw ?    ; 0x26
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        pref_base_up    dd ?    ; 0x28
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        pref_limit_up   dd ?    ; 0x2C
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        io_base_up      dw ?    ; 0x30
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        io_limit_up     dw ?    ; 0x32
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        cap_ptr         db ?    ; 0x34
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                        rb 3    ; reserved
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        exp_rom_addr    dd ?    ; 0x38
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        interrupt_line  db ?    ; 0x3C
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        interrupt_pin   db ?    ; 0x3E
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        bridge_ctrl     dw ?    ; 0x3F
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75
ends
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77
struct  PCI_header02    PCI_header
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79
        base_addr       dd ?    ; 0x10
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        cap_list_offs   db ?    ; 0x14
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                        rb 1    ; reserved
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        sec_stat        dw ?    ; 0x16
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        pci_bus_nr      db ?    ; 0x18
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        cardbus_bus_nr  db ?    ; 0x19
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        sub_bus_nr      db ?    ; 0x1A
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        cardbus_lat_tmr db ?    ; 0x1B
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        mbar_0          dd ?    ; 0x1C
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        mlimit_0        dd ?    ; 0x20
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        mbar_1          dd ?    ; 0x24
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        mlimit_1        dd ?    ; 0x28
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        iobar_0         dd ?    ; 0x2C
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        iolimit_0       dd ?    ; 0x30
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        iobar_1         dd ?    ; 0x34
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        iolimit_1       dd ?    ; 0x38
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        interrupt_line  db ?    ; 0x3C
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        interrupt_pin   db ?    ; 0x3D
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        bridge_ctrl     dw ?    ; 0x3E
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        subs_did        dw ?    ; 0x40
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        subs_vid        dw ?    ; 0x42
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        legacy_bar      dd ?    ; 0x44
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102
ends
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4522 hidnplayr 104
; Base address bits
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        PCI_BASE_ADDRESS_SPACE_IO               = 0x01
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        PCI_BASE_ADDRESS_IO_MASK                = 0xFFFFFFFC
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        PCI_BASE_ADDRESS_MEM_MASK               = 0xFFFFFFF0
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        PCI_BASE_ADDRESS_MEM_TYPE_MASK          = 0x00000006
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        PCI_BASE_ADDRESS_MEM_TYPE_32            = 0x0
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        PCI_BASE_ADDRESS_MEM_TYPE_RESERVED      = 0x02
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        PCI_BASE_ADDRESS_MEM_TYPE_64            = 0x4
4522 hidnplayr 112
 
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4522 hidnplayr 114
; command bits
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        PCI_CMD_PIO                     = 0x01          ; bit0: io space control
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        PCI_CMD_MMIO                    = 0x02          ; bit1: memory space control
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        PCI_CMD_MASTER                  = 0x04          ; bit2: device acts as a PCI master
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        PCI_CMD_INTX_DISABLE            = 0x400         ; INTx emulation disable
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; status bits
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        PCI_STATUS_CAPA                 = 0x10          ; bit4: new capabilities available
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4522 hidnplayr 124
if used PCI_find_io
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proc PCI_find_io stdcall bus, dev
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127
        push    esi
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        xor     eax, eax
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        mov     esi, PCI_header00.base_addr_0
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  .check:
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        invoke  PciRead32, [bus], [dev], esi
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        test    eax, PCI_BASE_ADDRESS_IO_MASK
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        jz      .inc
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        test    eax, PCI_BASE_ADDRESS_SPACE_IO
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        jz      .inc
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        and     eax, PCI_BASE_ADDRESS_IO_MASK
137
        pop     esi
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        ret
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  .inc:
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        add     esi, 4
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        cmp     esi, PCI_header00.base_addr_5
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        jbe     .check
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        pop     esi
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        xor     eax, eax
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        ret
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148
endp
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end if
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7250 hidnplayr 152
if used PCI_find_mmio
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proc PCI_find_mmio stdcall bus, dev
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7250 hidnplayr 155
        push    esi ebx
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        mov     esi, PCI_header00.base_addr_0
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  .check:
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        invoke  PciRead32, [bus], [dev], esi
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        DEBUGF  1, "BAR: 0x%x\n", eax
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        mov     ebx, eax
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        test    eax, PCI_BASE_ADDRESS_SPACE_IO  ; MMIO address?
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        jnz     .next
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        and     ebx, PCI_BASE_ADDRESS_MEM_TYPE_MASK
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        cmp     bl, PCI_BASE_ADDRESS_MEM_TYPE_64
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        je      .is64
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        cmp     bl, PCI_BASE_ADDRESS_MEM_TYPE_32
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        jne     .next
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        ; Ok, we have a 32-bit BAR.
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        and     eax, PCI_BASE_ADDRESS_MEM_MASK
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        pop     ebx esi
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        DEBUGF  1, "32-bit MMIO address found: 0x%x\n", eax
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        ret
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7250 hidnplayr 174
  .is64:
175
        ; Ok, we have a 64-bit BAR, check if the upper 32-bits are 0, then we can use it..
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        push    eax
4522 hidnplayr 177
        add     esi, 4
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        cmp     esi, PCI_header00.base_addr_5
7250 hidnplayr 179
        ja      .fail
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        invoke  PciRead32, [bus], [dev], esi
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        test    eax, eax
182
        pop     eax
183
        jnz     .next
184
        and     eax, PCI_BASE_ADDRESS_MEM_MASK
185
        pop     ebx esi
186
        DEBUGF  1, "64-bit MMIO address found: 0x00000000%x\n", eax
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        ret
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189
  .next:
190
        add     esi, 4
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        cmp     esi, PCI_header00.base_addr_5
4522 hidnplayr 192
        jbe     .check
7250 hidnplayr 193
  .fail:
4522 hidnplayr 194
        xor     eax, eax
7250 hidnplayr 195
        pop     ebx esi
196
        DEBUGF  1, "No usable MMIO addresses found!\n"
4522 hidnplayr 197
        ret
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199
endp
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end if