Rev 1029 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | /* |
| 2 | * Copyright 2007, 2008 Luc Verhaegen |
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| 3 | * Copyright 2007, 2008 Matthias Hopf |
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| 4 | * Copyright 2007, 2008 Egbert Eich |
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| 5 | * Copyright 2007, 2008 Advanced Micro Devices, Inc. |
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| 6 | * |
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| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | * copy of this software and associated documentation files (the "Software"), |
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| 9 | * to deal in the Software without restriction, including without limitation |
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| 10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | * Software is furnished to do so, subject to the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice shall be included in |
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| 15 | * all copies or substantial portions of the Software. |
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| 16 | * |
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| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 20 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 23 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 24 | */ |
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| 25 | |||
| 26 | #ifdef HAVE_CONFIG_H |
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| 27 | #include "config.h" |
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| 28 | #endif |
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| 29 | |||
| 30 | #include "xf86.h" |
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| 31 | |||
| 32 | /* for usleep */ |
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| 33 | #if HAVE_XF86_ANSIC_H |
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| 34 | # include "xf86_ansic.h" |
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| 35 | #else |
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| 36 | # include |
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| 37 | #endif |
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| 38 | |||
| 39 | #include "rhd.h" |
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| 40 | #include "rhd_crtc.h" |
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| 41 | #include "rhd_connector.h" |
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| 42 | #include "rhd_output.h" |
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| 43 | #include "rhd_regs.h" |
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| 44 | #ifdef ATOM_BIOS |
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| 45 | #include "rhd_atombios.h" |
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| 46 | #endif |
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| 47 | |||
| 48 | struct DDIAPrivate |
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| 49 | { |
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| 50 | Bool RunDualLink; |
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| 51 | CARD32 PcieCfgReg7; |
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| 52 | CARD32 CapabilityFlag; |
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| 53 | |||
| 54 | Bool Stored; |
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| 55 | |||
| 56 | CARD32 DdiaPathControl; |
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| 57 | CARD32 DdiaCntl; |
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| 58 | CARD32 DdiaDcbalancerControl; |
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| 59 | CARD32 DdiaPcieLinkControl2; |
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| 60 | CARD32 DdiaBitDepthControl; |
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| 61 | }; |
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| 62 | |||
| 63 | /* |
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| 64 | * |
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| 65 | */ |
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| 66 | static ModeStatus |
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| 67 | DDIAModeValid(struct rhdOutput *Output, DisplayModePtr Mode) |
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| 68 | { |
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| 69 | RHDFUNC(Output); |
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| 70 | |||
| 71 | if (Mode->Flags & V_INTERLACE) |
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| 72 | return MODE_NO_INTERLACE; |
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| 73 | |||
| 74 | if (Mode->Clock < 25000) |
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| 75 | return MODE_CLOCK_LOW; |
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| 76 | |||
| 77 | if (Output->Connector->Type == RHD_CONNECTOR_DVI_SINGLE) { |
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| 78 | if (Mode->Clock > 165000) |
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| 79 | return MODE_CLOCK_HIGH; |
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| 80 | } else if (Output->Connector->Type == RHD_CONNECTOR_DVI) { |
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| 81 | if (Mode->Clock > 330000) /* could go higher still */ |
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| 82 | return MODE_CLOCK_HIGH; |
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| 83 | } |
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| 84 | |||
| 85 | return MODE_OK; |
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| 86 | } |
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| 87 | |||
| 88 | /* |
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| 89 | * |
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| 90 | */ |
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| 91 | static void |
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| 92 | DDIAMode(struct rhdOutput *Output, DisplayModePtr Mode) |
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| 93 | { |
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| 94 | struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private; |
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| 95 | CARD32 mux0, mux1, mux2, mux3; |
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| 96 | Bool LaneReversal; |
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| 97 | RHDPtr rhdPtr = RHDPTRI(Output); |
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| 98 | |||
| 99 | RHDFUNC(Output); |
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| 100 | |||
| 101 | if (Mode->SynthClock >= 165000) |
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| 102 | Private->RunDualLink = TRUE; |
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| 103 | else |
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| 104 | Private->RunDualLink = FALSE; |
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| 105 | |||
| 106 | /* reset on - will be enabled at POWER_ON */ |
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| 107 | RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, RS69_DDIA_PIXVLD_RESET, RS69_DDIA_PIXVLD_RESET); |
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| 108 | /* RGB 4:4:4 */ |
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| 109 | RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_PIXEL_ENCODING); |
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| 110 | /* TMDS_AC */ |
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| 111 | RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, |
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| 112 | 2 << RS69_DDIA_PATH_SELECT_SHIFT, |
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| 113 | 0x3 << RS69_DDIA_PATH_SELECT_SHIFT); |
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| 114 | /* dual link */ |
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| 115 | RHDRegMask(Output, RS69_DDIA_CNTL, Private->RunDualLink ? |
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| 116 | RS69_DDIA_DUAL_LINK_ENABLE : 0, RS69_DDIA_DUAL_LINK_ENABLE); |
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| 117 | RHDRegMask(Output, RS69_DDIA_DCBALANCER_CONTROL, |
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| 118 | RS69_DDIA_DCBALANCER_EN, |
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| 119 | RS69_DDIA_SYNC_DCBAL_EN_MASK | RS69_DDIA_DCBALANCER_EN); |
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| 120 | |||
| 121 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x80); |
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| 122 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x100); |
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| 123 | |||
| 124 | mux0 = Private->PcieCfgReg7 & 0x3; |
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| 125 | mux1 = (Private->PcieCfgReg7 >> 2) & 0x3; |
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| 126 | mux2 = (Private->PcieCfgReg7 >> 4) & 0x3; |
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| 127 | mux3 = (Private->PcieCfgReg7 >> 6) & 0x3; |
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| 128 | |||
| 129 | RHDRegMask(Output, RS69_DDIA_PCIE_LINK_CONTROL2, |
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| 130 | (mux0 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL0) |
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| 131 | | (mux1 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL1) |
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| 132 | | (mux2 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL2) |
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| 133 | | (mux3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL3), |
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| 134 | (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL0) |
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| 135 | | (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL1) |
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| 136 | | (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL2) |
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| 137 | | (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL3) |
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| 138 | ); |
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| 139 | LaneReversal = Private->PcieCfgReg7 & (0x1 << 10); |
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| 140 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x3); |
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| 141 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x2, 0x2); |
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| 142 | |||
| 143 | RHDRegMask(Output, RS69_DDIA_PCIE_LINK_CONTROL3, |
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| 144 | LaneReversal ? RS69_DDIA_PCIE_MIRROR_EN : 0, |
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| 145 | RS69_DDIA_PCIE_MIRROR_EN); |
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| 146 | |||
| 147 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x70, 0x70); |
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| 148 | |||
| 149 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0, 0x10); |
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| 150 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0, 0x60); |
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| 151 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0, 0x4000000); |
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| 152 | |||
| 153 | switch (rhdPtr->PciDeviceID) { |
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| 154 | case 0x791E: |
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| 155 | if (Mode->SynthClock <= 25000) { |
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| 156 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x2780, 0x3f80); |
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| 157 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000); |
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| 158 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x039f0000, 0x03000000 | 0x039f0000); |
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| 159 | } else if (Mode->SynthClock <= 60000) { |
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| 160 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x2780, 0x3f80); |
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| 161 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000); |
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| 162 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x024f0000, 0x03000000 | 0x024f0000); |
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| 163 | } else { |
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| 164 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0980, 0x3f80); |
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| 165 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000); |
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| 166 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01270000, 0x03000000 | 0x01270000); |
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| 167 | } |
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| 168 | break; |
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| 169 | case 0x791F: |
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| 170 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0980, 0x3f80); |
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| 171 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x4000, 0xc000); |
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| 172 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x00ac0000, 0x03000000 | 0x00ac0000); |
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| 173 | if (Private->CapabilityFlag & 0x10) { |
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| 174 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000); |
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| 175 | if (Mode->SynthClock <= 6500) |
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| 176 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01ac0000, 0x03ff0000); |
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| 177 | else |
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| 178 | RHDRegMaskD(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01110000, 0x03ff0000); |
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| 179 | } |
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| 180 | break; |
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| 181 | } |
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| 182 | usleep (1); |
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| 183 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x04000000, 0x04000000); |
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| 184 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x60, 0x60); |
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| 185 | usleep(30); |
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| 186 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01, 0x01); |
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| 187 | usleep(1); |
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| 188 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x02, 0x02); |
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| 189 | usleep(1); |
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| 190 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x04, 0x04); |
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| 191 | usleep(1); |
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| 192 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x08, 0x08); |
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| 193 | usleep(1); |
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| 194 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x10, 0x10); |
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| 195 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xf); |
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| 196 | |||
| 197 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0180, 0x0180); |
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| 198 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x600, 0x600); |
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| 199 | usleep(5); |
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| 200 | RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x600); |
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| 201 | |||
| 202 | /* hw reset will be turned off at POWER_ON */ |
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| 203 | |||
| 204 | /* select crtc source, sync_a, no stereosync */ |
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| 205 | RHDRegMask(Output, RS69_DDIA_SOURCE_SELECT, Output->Crtc->Id, |
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| 206 | RS69_DDIA_SOURCE_SELECT_BIT |
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| 207 | | RS69_DDIA_SYNC_SELECT |
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| 208 | | RS69_DDIA_STEREOSYNC_SELECT); |
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| 209 | } |
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| 210 | |||
| 211 | /* |
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| 212 | * |
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| 213 | */ |
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| 214 | static void |
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| 215 | DDIAPower(struct rhdOutput *Output, int Power) |
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| 216 | { |
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| 217 | RHDDebug(Output->scrnIndex, "%s(%s,%s)\n",__func__,Output->Name, |
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| 218 | rhdPowerString[Power]); |
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| 219 | |||
| 220 | switch (Power) { |
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| 221 | case RHD_POWER_ON: |
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| 222 | RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, RS69_DDIA_PIXVLD_RESET, |
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| 223 | RS69_DDIA_PIXVLD_RESET); |
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| 224 | RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, 0); |
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| 225 | RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL, |
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| 226 | RS69_DDIA_TEMPORAL_DITHER_RESET, RS69_DDIA_TEMPORAL_DITHER_RESET); |
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| 227 | RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL, |
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| 228 | 0, RS69_DDIA_TEMPORAL_DITHER_RESET); |
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| 229 | RHDRegMask(Output, RS69_DDIA_CNTL, RS69_DDIA_ENABLE, RS69_DDIA_ENABLE); |
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| 230 | RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, 0, RS69_DDIA_PIXVLD_RESET); |
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| 231 | return; |
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| 232 | case RHD_POWER_RESET: |
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| 233 | RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_ENABLE); |
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| 234 | return; |
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| 235 | case RHD_POWER_SHUTDOWN: |
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| 236 | RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL, |
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| 237 | RS69_DDIA_TEMPORAL_DITHER_RESET, RS69_DDIA_TEMPORAL_DITHER_RESET); |
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| 238 | RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL, |
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| 239 | 0, RS69_DDIA_TEMPORAL_DITHER_RESET); |
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| 240 | RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL, |
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| 241 | 0, |
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| 242 | RS69_DDIA_TRUNCATE_EN |
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| 243 | | RS69_DDIA_TRUNCATE_DEPTH |
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| 244 | | RS69_DDIA_SPATIAL_DITHER_EN |
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| 245 | | RS69_DDIA_SPATIAL_DITHER_DEPTH); |
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| 246 | RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL, |
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| 247 | 0, |
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| 248 | RS69_DDIA_TEMPORAL_DITHER_EN |
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| 249 | | RS69_DDIA_TEMPORAL_DITHER_EN |
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| 250 | | RS69_DDIA_TEMPORAL_DITHER_DEPTH |
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| 251 | | RS69_DDIA_TEMPORAL_LEVEL); |
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| 252 | RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_ENABLE); |
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| 253 | return; |
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| 254 | default: |
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| 255 | return; |
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| 256 | } |
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| 257 | } |
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| 258 | |||
| 259 | /* |
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| 260 | * |
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| 261 | */ |
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| 262 | static void |
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| 263 | DDIASave(struct rhdOutput *Output) |
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| 264 | { |
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| 265 | struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private; |
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| 266 | |||
| 267 | RHDFUNC(Output); |
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| 268 | |||
| 269 | Private->DdiaPathControl = RHDRegRead(Output, RS69_DDIA_PATH_CONTROL); |
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| 270 | Private->DdiaCntl = RHDRegRead(Output, RS69_DDIA_CNTL); |
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| 271 | Private->DdiaDcbalancerControl = RHDRegRead(Output, RS69_DDIA_DCBALANCER_CONTROL); |
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| 272 | Private->DdiaPcieLinkControl2 = RHDRegRead(Output, RS69_DDIA_PCIE_LINK_CONTROL2); |
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| 273 | Private->DdiaBitDepthControl = RHDRegRead(Output, RS69_DDIA_BIT_DEPTH_CONTROL); |
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| 274 | |||
| 275 | Private->Stored = TRUE; |
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| 276 | } |
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| 277 | |||
| 278 | /* |
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| 279 | * |
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| 280 | */ |
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| 281 | static void |
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| 282 | DDIARestore(struct rhdOutput *Output) |
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| 283 | { |
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| 284 | struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private; |
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| 285 | RHDFUNC(Output); |
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| 286 | |||
| 287 | if (!Private->Stored) |
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| 288 | return; |
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| 289 | |||
| 290 | /* disalbe */ |
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| 291 | RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_ENABLE); |
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| 292 | /* reset on */ |
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| 293 | RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, RS69_DDIA_PIXVLD_RESET, RS69_DDIA_PIXVLD_RESET); |
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| 294 | RHDRegWrite(Output, RS69_DDIA_PATH_CONTROL, Private->DdiaPathControl | RS69_DDIA_PIXVLD_RESET); |
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| 295 | |||
| 296 | RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, Private->DdiaBitDepthControl); |
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| 297 | /* temporal dither reset on */ |
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| 298 | RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, Private->DdiaBitDepthControl |
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| 299 | | RS69_DDIA_TEMPORAL_DITHER_RESET); |
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| 300 | /* temporal dither reset off */ |
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| 301 | RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, Private->DdiaBitDepthControl); |
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| 302 | |||
| 303 | RHDRegWrite(Output, RS69_DDIA_DCBALANCER_CONTROL, Private->DdiaDcbalancerControl); |
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| 304 | RHDRegWrite(Output, RS69_DDIA_PCIE_LINK_CONTROL2, Private->DdiaPcieLinkControl2); |
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| 305 | /* enable if enabled at startup */ |
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| 306 | RHDRegWrite(Output, RS69_DDIA_CNTL, Private->DdiaCntl); |
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| 307 | /* reset off */ |
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| 308 | RHDRegWrite(Output, RS69_DDIA_PATH_CONTROL, Private->DdiaPathControl); |
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| 309 | } |
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| 310 | |||
| 311 | /* |
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| 312 | * |
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| 313 | */ |
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| 314 | static void |
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| 315 | DDIADestroy(struct rhdOutput *Output) |
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| 316 | { |
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| 317 | struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private; |
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| 318 | |||
| 319 | RHDFUNC(Output); |
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| 320 | |||
| 321 | xfree(Private); |
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| 322 | Output->Private = NULL; |
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| 323 | } |
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| 324 | |||
| 325 | /* |
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| 326 | * |
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| 327 | */ |
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| 328 | struct rhdOutput * |
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| 329 | RHDDDIAInit(RHDPtr rhdPtr) |
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| 330 | { |
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| 331 | #ifdef ATOM_BIOS |
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| 332 | struct rhdOutput *Output; |
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| 333 | struct DDIAPrivate *Private; |
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| 334 | AtomBiosArgRec data; |
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| 335 | |||
| 336 | RHDFUNC(rhdPtr); |
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| 337 | |||
| 338 | /* |
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| 339 | * This needs to be handled separately |
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| 340 | * for now we only deal with it here. |
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| 341 | */ |
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| 342 | if (rhdPtr->ChipSet < RHD_RS600 || rhdPtr->ChipSet >= RHD_RS740) |
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| 343 | return FALSE; |
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| 344 | |||
| 345 | Output = xnfcalloc(sizeof(struct rhdOutput), 1); |
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| 346 | |||
| 347 | Output->Name = "DDIA"; |
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| 348 | |||
| 349 | Output->scrnIndex = rhdPtr->scrnIndex; |
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| 350 | Output->Id = RHD_OUTPUT_DVO; |
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| 351 | |||
| 352 | Output->Sense = NULL; |
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| 353 | Output->ModeValid = DDIAModeValid; |
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| 354 | Output->Mode = DDIAMode; |
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| 355 | Output->Power = DDIAPower; |
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| 356 | Output->Save = DDIASave; |
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| 357 | Output->Restore = DDIARestore; |
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| 358 | Output->Destroy = DDIADestroy; |
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| 359 | |||
| 360 | Private = xnfcalloc(1, sizeof(struct DDIAPrivate)); |
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| 361 | Output->Private = Private; |
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| 362 | Private->Stored = FALSE; |
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| 363 | |||
| 364 | if (RHDAtomBiosFunc(rhdPtr, rhdPtr->atomBIOS, |
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| 365 | ATOM_GET_PCIENB_CFG_REG7, &data) == ATOM_SUCCESS) { |
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| 366 | Private->PcieCfgReg7 = data.val; |
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| 367 | } else { |
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| 368 | xf86DrvMsg(Output->scrnIndex, X_ERROR, "Retrieval of PCIE MUX values failed. " |
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| 369 | "no DDIA block support available\n"); |
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| 370 | goto error; |
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| 371 | } |
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| 372 | if (RHDAtomBiosFunc(rhdPtr, rhdPtr->atomBIOS, |
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| 373 | ATOM_GET_CAPABILITY_FLAG, &data) == ATOM_SUCCESS) { |
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| 374 | Private->CapabilityFlag = data.val; |
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| 375 | } else { |
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| 376 | xf86DrvMsg(Output->scrnIndex, X_ERROR, "Retrieval of Capability flag failed. " |
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| 377 | "no DDIA block support available\n"); |
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| 378 | goto error; |
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| 379 | } |
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| 380 | |||
| 381 | return Output; |
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| 382 | error: |
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| 383 | xfree(Private); |
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| 384 | return NULL; |
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| 385 | |||
| 386 | #else |
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| 387 | return NULL; |
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| 388 | #endif |
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| 389 | } |