Rev 1029 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | |
| 2 | #include "pci.h" |
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| 3 | |||
| 4 | |||
| 5 | |||
| 6 | pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min) |
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| 7 | { |
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| 8 | int offset; |
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| 9 | CARD32 addr1; |
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| 10 | CARD32 addr2; |
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| 11 | CARD32 mask1; |
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| 12 | CARD32 mask2; |
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| 13 | int bits = 0; |
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| 14 | |||
| 15 | |||
| 16 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
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| 17 | * the 6 base address registers, and 6 is the ROM base address register. |
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| 18 | */ |
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| 19 | if (index < 0 || index > 6) |
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| 20 | return 0; |
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| 21 | |||
| 22 | |||
| 23 | *min = destructive; |
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| 24 | |||
| 25 | |||
| 26 | if (index == 6) |
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| 27 | offset = PCI_MAP_ROM_REG; |
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| 28 | else |
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| 29 | offset = PCI_MAP_REG_START + (index << 2); |
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| 30 | |||
| 31 | |||
| 32 | /* |
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| 33 | * Check if this is the second part of a 64 bit address. |
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| 34 | * XXX need to check how endianness affects 64 bit addresses. |
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| 35 | */ |
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| 36 | if (index > 0 && index < 6) { |
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| 37 | addr2 = PciRead32(bus, devfn, offset - 4); |
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| 38 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
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| 39 | return 0; |
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| 40 | } |
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| 41 | |||
| 42 | |||
| 43 | PciWrite32(bus, devfn, offset, 0xffffffff); |
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| 44 | mask1 = PciRead32(bus, devfn, offset); |
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| 45 | PciWrite32(bus, devfn, offset, addr1); |
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| 46 | } else { |
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| 47 | mask1 = addr1; |
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| 48 | } |
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| 49 | |||
| 50 | |||
| 51 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
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| 52 | { |
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| 53 | if (PCIGETMEMORY(mask1) == 0) |
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| 54 | { |
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| 55 | addr2 = PciRead32(bus, devfn, offset + 4); |
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| 56 | if (destructive) |
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| 57 | { |
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| 58 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
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| 59 | mask2 = PciRead32(bus, devfn, offset + 4); |
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| 60 | PciWrite32(bus, devfn, offset + 4, addr2); |
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| 61 | } |
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| 62 | else |
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| 63 | { |
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| 64 | mask2 = addr2; |
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| 65 | } |
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| 66 | if (mask2 == 0) |
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| 67 | return 0; |
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| 68 | bits = 32; |
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| 69 | while ((mask2 & 1) == 0) |
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| 70 | { |
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| 71 | bits++; |
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| 72 | mask2 >>= 1; |
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| 73 | } |
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| 74 | if (bits > 32) |
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| 75 | return bits; |
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| 76 | } |
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| 77 | } |
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| 78 | if (index < 6) |
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| 79 | if (PCI_MAP_IS_MEM(mask1)) |
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| 80 | mask1 = PCIGETMEMORY(mask1); |
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| 81 | else |
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| 82 | mask1 = PCIGETIO(mask1); |
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| 83 | else |
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| 84 | mask1 = PCIGETROM(mask1); |
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| 85 | if (mask1 == 0) |
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| 86 | return 0; |
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| 87 | bits = 0; |
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| 88 | while ((mask1 & 1) == 0) { |
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| 89 | bits++; |
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| 90 | mask1 >>= 1; |
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| 91 | } |
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| 92 | /* I/O maps can be no larger than 8 bits */ |
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| 93 | |||
| 94 | |||
| 95 | bits = 8; |
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| 96 | /* ROM maps can be no larger than 24 bits */ |
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| 97 | if (index == 6 && bits > 24) |
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| 98 | bits = 24; |
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| 99 | return bits; |
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| 100 | } |
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| 101 | |||
| 102 | |||
| 103 | int chipRev; |
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| 104 | int subsysVendor; |
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| 105 | int subsysCard; |
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| 106 | int bus; |
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| 107 | int devfn; |
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| 108 | // int func; |
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| 109 | int class; |
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| 110 | int subclass; |
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| 111 | int interface; |
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| 112 | memType memBase[6]; |
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| 113 | memType ioBase[6]; |
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| 114 | int size[6]; |
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| 115 | unsigned char type[6]; |
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| 116 | memType biosBase; |
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| 117 | int biosSize; |
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| 118 | */ |
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| 119 | |||
| 120 | |||
| 121 | { |
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| 122 | CARD32 reg0,reg2C; |
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| 123 | int i; |
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| 124 | |||
| 125 | |||
| 126 | reg2C = PciRead32(pci->bus,pci->devfn, 0x2C); |
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| 127 | |||
| 128 | |||
| 129 | pci->devtype = reg0 >> 16; |
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| 130 | |||
| 131 | |||
| 132 | pci->subsysCard = reg2C >> 16; |
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| 133 | |||
| 134 | |||
| 135 | { |
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| 136 | CARD32 base; |
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| 137 | |||
| 138 | |||
| 139 | if(base) |
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| 140 | { |
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| 141 | if (base & PCI_MAP_IO) |
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| 142 | { |
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| 143 | pci->ioBase[i] = (memType)PCIGETIO(base); |
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| 144 | pci->type[i] = base & PCI_MAP_IO_ATTR_MASK; |
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| 145 | } |
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| 146 | else |
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| 147 | { |
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| 148 | pci->type[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
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| 149 | pci->memBase[i] = (memType)PCIGETMEMORY(base); |
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| 150 | } |
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| 151 | } |
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| 152 | |||
| 153 | |||
| 154 | pciGetBaseSize(pci->bus,pci->devfn, i, TRUE, &pci->validSize); |
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| 155 | } |
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| 156 | |||
| 157 | |||
| 158 |