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1317 serge 1
if 0
2
 
3
 Copyright 2008  Serge
4
 
5
 The below code is a rework from code in
6
 xf86-video-radeonhd/src/r5xx_accel.c, xf86-video-radeonhd/src/r5xx_xaa.c
7
 
8
 git://anongit.freedesktop.org/git/nouveau/xf86-video-radeonhd
9
 git://anongit.freedesktop.org/git/xorg/driver/xf86-video-ati
10
 
11
 
12
 Copyright 2008  Luc Verhaegen 
13
 Copyright 2008  Matthias Hopf 
14
 Copyright 2008  Egbert Eich   
15
 Copyright 2008  Advanced Micro Devices, Inc.
16
 
17
 Permission is hereby granted, free of charge, to any person obtaining a
18
 copy of this software and associated documentation files (the "Software"),
19
 to deal in the Software without restriction, including without limitation
20
 the rights to use, copy, modify, merge, publish, distribute, sublicense,
21
 and/or sell copies of the Software, and to permit persons to whom the
22
 Software is furnished to do so, subject to the following conditions:
23
 
24
 The above copyright notice and this permission notice shall be included in
25
 all copies or substantial portions of the Software.
26
 
27
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28
 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29
 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
30
 THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
31
 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32
 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33
 OTHER DEALINGS IN THE SOFTWARE.
34
 
35
 The below code is a rework from code in xf86-video-ati/src/radeon_accel.c
36
 The original license is included below, it has the messed up disclaimer and
37
 an all rights reserved statement.
38
 
39
 
40
 Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
41
                VA Linux Systems Inc., Fremont, California.
42
 
43
 All Rights Reserved.
44
 
45
 Permission is hereby granted, free of charge, to any person obtaining
46
 a copy of this software and associated documentation files (the
47
 "Software"), to deal in the Software without restriction, including
48
 without limitation on the rights to use, copy, modify, merge,
49
 publish, distribute, sublicense, and/or sell copies of the Software,
50
 and to permit persons to whom the Software is furnished to do so,
51
 subject to the following conditions:
52
 
53
 The above copyright notice and this permission notice (including the
54
 next paragraph) shall be included in all copies or substantial
55
 portions of the Software.
56
 
57
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
58
 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
59
 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
60
 NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
61
 THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
62
 WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
63
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
64
 DEALINGS IN THE SOFTWARE.
65
 
66
 Authors:
67
   Kevin E. Martin 
68
   Rickard E. Faith 
69
   Alan Hourihane 
70
 
71
end if
72
 
73
RADEON_CP_ME_RAM_ADDR            equ 0x07d4
74
RADEON_CP_ME_RAM_RADDR           equ 0x07d8
75
RADEON_CP_ME_RAM_DATAH           equ 0x07dc
76
RADEON_CP_ME_RAM_DATAL           equ 0x07e0
77
 
78
RADEON_CP_RB_BASE                equ 0x0700
79
RADEON_CP_RB_CNTL                equ 0x0704
80
  RADEON_RB_NO_UPDATE            equ (1 shl 27)
81
RADEON_CP_RB_RPTR_ADDR           equ 0x070c
82
RADEON_CP_RB_RPTR                equ 0x0710
83
RADEON_CP_RB_WPTR                equ 0x0714
84
 
85
RADEON_CP_CSQ_CNTL               equ 0x0740
86
  RADEON_CSQ_CNT_PRIMARY_MASK    equ (0xff shl 0)
87
  RADEON_CSQ_PRIDIS_INDDIS       equ (0    shl 28)
88
  RADEON_CSQ_PRIPIO_INDDIS       equ (1    shl 28)
89
  RADEON_CSQ_PRIBM_INDDIS        equ (2    shl 28)
90
  RADEON_CSQ_PRIPIO_INDBM        equ (3    shl 28)
91
  RADEON_CSQ_PRIBM_INDBM         equ (4    shl 28)
92
  RADEON_CSQ_PRIPIO_INDPIO       equ (15   shl 28)
93
 
94
RADEON_CP_RB_WPTR_DELAY          equ 0x0718
95
 
96
RADEON_SCRATCH_UMSK              equ 0x0770
97
RADEON_SCRATCH_ADDR              equ 0x0774
98
 
99
RADEON_ISYNC_CNTL                equ 0x1724
100
  RADEON_ISYNC_ANY2D_IDLE3D      equ (1 shl 0)
101
  RADEON_ISYNC_ANY3D_IDLE2D      equ (1 shl 1)
102
  RADEON_ISYNC_TRIG2D_IDLE3D     equ (1 shl 2)
103
  RADEON_ISYNC_TRIG3D_IDLE2D     equ (1 shl 3)
104
  RADEON_ISYNC_WAIT_IDLEGUI      equ (1 shl 4)
105
  RADEON_ISYNC_CPSCRATCH_IDLEGUI equ (1 shl 5)
106
 
107
RADEON_AIC_CNTL                  equ 0x01d0
108
  RADEON_PCIGART_TRANSLATE_EN    equ (1 shl 0)
109
RADEON_AIC_STAT                  equ 0x01d4
110
RADEON_AIC_PT_BASE               equ 0x01d8
111
RADEON_AIC_LO_ADDR               equ 0x01dc
112
RADEON_AIC_HI_ADDR               equ 0x01e0
113
RADEON_AIC_TLB_ADDR              equ 0x01e4
114
RADEON_AIC_TLB_DATA              equ 0x01e8
115
 
116
RADEON_WAIT_UNTIL                equ 0x1720
117
  RADEON_WAIT_CRTC_PFLIP         equ (1 shl 0)
118
  RADEON_WAIT_2D_IDLE            equ (1 shl 14)
119
  RADEON_WAIT_3D_IDLE            equ (1 shl 15)
120
  RADEON_WAIT_2D_IDLECLEAN       equ (1 shl 16)
121
  RADEON_WAIT_3D_IDLECLEAN       equ (1 shl 17)
122
  RADEON_WAIT_HOST_IDLECLEAN     equ (1 shl 18)
123
 
124
D1GRPH_PITCH                     equ 0x6120
125
D1GRPH_X_END                     equ 0x6134
126
D1GRPH_Y_END                     equ 0x6138
127
 
128
 
129
R5XX_DATATYPE_ARGB8888           equ  6
130
 
131
R5XX_RB3D_CNTL                   equ  0x1c3c
132
 
133
R5XX_RBBM_STATUS                 equ  0x0e40
134
  R5XX_RBBM_FIFOCNT_MASK         equ  0x007f
135
  R5XX_RBBM_ACTIVE               equ  (1 shl 31)
136
 
137
R5XX_RBBM_SOFT_RESET             equ  0x00f0
138
  R5XX_SOFT_RESET_CP             equ  (1 shl 0)
139
  R5XX_SOFT_RESET_HI             equ  (1 shl 1)
140
  R5XX_SOFT_RESET_SE             equ  (1 shl 2)
141
  R5XX_SOFT_RESET_RE             equ  (1 shl 3)
142
  R5XX_SOFT_RESET_PP             equ  (1 shl 4)
143
  R5XX_SOFT_RESET_E2             equ  (1 shl 5)
144
  R5XX_SOFT_RESET_RB             equ  (1 shl 6)
145
  R5XX_SOFT_RESET_HDP            equ  (1 shl 7)
146
 
147
R5XX_SRC_PITCH_OFFSET            equ  0x1428
148
R5XX_DST_PITCH_OFFSET            equ  0x142c
149
 
150
R5XX_DP_DATATYPE                 equ  0x16c4
151
  R5XX_HOST_BIG_ENDIAN_EN        equ  (1 shl 29)
152
 
153
R5XX_DP_CNTL                     equ  0x16c0
154
  R5XX_DST_X_LEFT_TO_RIGHT       equ (1 shl  0)
155
  R5XX_DST_Y_TOP_TO_BOTTOM       equ (1 shl  1)
156
  R5XX_DP_DST_TILE_LINEAR        equ (0 shl  3)
157
  R5XX_DP_DST_TILE_MACRO         equ (1 shl  3)
158
  R5XX_DP_DST_TILE_MICRO         equ (2 shl  3)
159
  R5XX_DP_DST_TILE_BOTH          equ (3 shl  3)
160
 
161
RADEON_RB3D_ZCACHE_CTLSTAT       equ 0x3254
162
  RADEON_RB3D_ZC_FLUSH           equ (1 shl 0)
163
  RADEON_RB3D_ZC_FREE            equ (1 shl 2)
164
  RADEON_RB3D_ZC_FLUSH_ALL       equ 0x5
165
  RADEON_RB3D_ZC_BUSY            equ (1 shl 31)
166
 
167
R5XX_RB3D_DSTCACHE_CTLSTAT       equ  0x325C
168
  R5XX_RB3D_DC_FLUSH             equ  (3 shl 0)
169
  R5XX_RB3D_DC_FREE              equ  (3 shl 2)
170
  R5XX_RB3D_DC_FLUSH_ALL         equ  0xf
171
  R5XX_RB3D_DC_BUSY              equ  (1 shl 31)
172
 
173
R5XX_SURFACE_CNTL                equ  0x0b00
174
  R5XX_SURF_TRANSLATION_DIS      equ  (1 shl 8)
175
  R5XX_NONSURF_AP0_SWP_16BPP     equ  (1 shl 20)
176
  R5XX_NONSURF_AP0_SWP_32BPP     equ  (1 shl 21)
177
  R5XX_NONSURF_AP1_SWP_16BPP     equ  (1 shl 22)
178
  R5XX_NONSURF_AP1_SWP_32BPP     equ  (1 shl 23)
179
 
180
R5XX_DEFAULT_SC_BOTTOM_RIGHT     equ  0x16e8
181
  R5XX_DEFAULT_SC_RIGHT_MAX      equ  (0x1fff shl  0)
182
  R5XX_DEFAULT_SC_BOTTOM_MAX     equ  (0x1fff shl 16)
183
 
184
R5XX_SC_TOP_LEFT                 equ  0x16ec
185
  R5XX_SC_BOTTOM_RIGHT           equ  0x16f0
186
  R5XX_SC_SIGN_MASK_LO           equ  0x8000
187
  R5XX_SC_SIGN_MASK_HI           equ  0x80000000
188
 
189
R5XX_DP_GUI_MASTER_CNTL          equ  0x146c
190
R5XX_GMC_SRC_PITCH_OFFSET_CNTL   equ  (1 shl 0)
191
R5XX_GMC_DST_PITCH_OFFSET_CNTL   equ  (1 shl 1)
192
R5XX_GMC_SRC_CLIPPING            equ  (1 shl 2)
193
R5XX_GMC_DST_CLIPPING            equ  (1    shl 3)
194
R5XX_GMC_BRUSH_DATATYPE_MASK     equ  (0x0f shl 4)
195
R5XX_GMC_BRUSH_8X8_MONO_FG_BG    equ  (0    shl 4)
196
R5XX_GMC_BRUSH_8X8_MONO_FG_LA    equ  (1    shl 4)
197
R5XX_GMC_BRUSH_1X8_MONO_FG_BG    equ  (4    shl 4)
198
R5XX_GMC_BRUSH_1X8_MONO_FG_LA    equ  (5    shl 4)
199
R5XX_GMC_BRUSH_32x1_MONO_FG_BG   equ  (6    shl 4)
200
R5XX_GMC_BRUSH_32x1_MONO_FG_LA   equ  (7    shl 4)
201
R5XX_GMC_BRUSH_32x32_MONO_FG_BG  equ  (8    shl 4)
202
R5XX_GMC_BRUSH_32x32_MONO_FG_LA  equ  (9    shl 4)
203
R5XX_GMC_BRUSH_8x8_COLOR         equ  (10   shl 4)
204
R5XX_GMC_BRUSH_1X8_COLOR         equ  (12   shl 4)
205
R5XX_GMC_BRUSH_SOLID_COLOR       equ  (13   shl 4)
206
R5XX_GMC_BRUSH_NONE              equ  (15   shl 4)
207
R5XX_GMC_DST_8BPP_CI             equ  (2    shl 8)
208
R5XX_GMC_DST_15BPP               equ  (3    shl 8)
209
R5XX_GMC_DST_16BPP               equ  (4    shl 8)
210
R5XX_GMC_DST_24BPP               equ  (5    shl 8)
211
R5XX_GMC_DST_32BPP               equ  (6    shl 8)
212
R5XX_GMC_DST_8BPP_RGB            equ  (7    shl 8)
213
R5XX_GMC_DST_Y8                  equ  (8    shl 8)
214
R5XX_GMC_DST_RGB8                equ  (9    shl 8)
215
R5XX_GMC_DST_VYUY                equ  (11   shl 8)
216
R5XX_GMC_DST_YVYU                equ  (12   shl 8)
217
R5XX_GMC_DST_AYUV444             equ  (14   shl 8)
218
R5XX_GMC_DST_ARGB4444            equ  (15   shl 8)
219
R5XX_GMC_DST_DATATYPE_MASK       equ  (0x0f shl 8)
220
R5XX_GMC_DST_DATATYPE_SHIFT      equ  8
221
R5XX_GMC_SRC_DATATYPE_MASK       equ  (3    shl 12)
222
R5XX_GMC_SRC_DATATYPE_MONO_FG_BG equ  (0    shl 12)
223
R5XX_GMC_SRC_DATATYPE_MONO_FG_LA equ  (1    shl 12)
224
R5XX_GMC_SRC_DATATYPE_COLOR      equ  (3    shl 12)
225
R5XX_GMC_BYTE_PIX_ORDER          equ  (1    shl 14)
226
R5XX_GMC_BYTE_MSB_TO_LSB         equ  (0    shl 14)
227
R5XX_GMC_BYTE_LSB_TO_MSB         equ  (1    shl 14)
228
R5XX_GMC_CONVERSION_TEMP         equ  (1    shl 15)
229
R5XX_GMC_CONVERSION_TEMP_6500    equ  (0    shl 15)
230
R5XX_GMC_CONVERSION_TEMP_9300    equ  (1    shl 15)
231
R5XX_GMC_ROP3_MASK               equ  (0xff shl 16)
232
R5XX_DP_SRC_SOURCE_MASK          equ  (7    shl 24)
233
R5XX_DP_SRC_SOURCE_MEMORY        equ  (2    shl 24)
234
R5XX_DP_SRC_SOURCE_HOST_DATA     equ  (3    shl 24)
235
R5XX_GMC_3D_FCN_EN               equ  (1    shl 27)
236
R5XX_GMC_CLR_CMP_CNTL_DIS        equ  (1    shl 28)
237
R5XX_GMC_AUX_CLIP_DIS            equ  (1    shl 29)
238
R5XX_GMC_WR_MSK_DIS              equ  (1    shl 30)
239
R5XX_GMC_LD_BRUSH_Y_X            equ  (1    shl 31)
240
R5XX_ROP3_ZERO                   equ  0x00000000
241
R5XX_ROP3_DSa                    equ  0x00880000
242
R5XX_ROP3_SDna                   equ  0x00440000
243
R5XX_ROP3_S                      equ  0x00cc0000
244
R5XX_ROP3_DSna                   equ  0x00220000
245
R5XX_ROP3_D                      equ  0x00aa0000
246
R5XX_ROP3_DSx                    equ  0x00660000
247
R5XX_ROP3_DSo                    equ  0x00ee0000
248
R5XX_ROP3_DSon                   equ  0x00110000
249
R5XX_ROP3_DSxn                   equ  0x00990000
250
R5XX_ROP3_Dn                     equ  0x00550000
251
R5XX_ROP3_SDno                   equ  0x00dd0000
252
R5XX_ROP3_Sn                     equ  0x00330000
253
R5XX_ROP3_DSno                   equ  0x00bb0000
254
R5XX_ROP3_DSan                   equ  0x00770000
255
R5XX_ROP3_ONE                    equ  0x00ff0000
256
R5XX_ROP3_DPa                    equ  0x00a00000
257
R5XX_ROP3_PDna                   equ  0x00500000
258
R5XX_ROP3_P                      equ  0x00f00000
259
R5XX_ROP3_DPna                   equ  0x000a0000
260
R5XX_ROP3_D                      equ  0x00aa0000
261
R5XX_ROP3_DPx                    equ  0x005a0000
262
R5XX_ROP3_DPo                    equ  0x00fa0000
263
R5XX_ROP3_DPon                   equ  0x00050000
264
R5XX_ROP3_PDxn                   equ  0x00a50000
265
R5XX_ROP3_PDno                   equ  0x00f50000
266
R5XX_ROP3_Pn                     equ  0x000f0000
267
R5XX_ROP3_DPno                   equ  0x00af0000
268
R5XX_ROP3_DPan                   equ  0x005f0000
269
 
270
R5XX_HOST_PATH_CNTL              equ  0x0130
271
R5XX_HDP_SOFT_RESET              equ  (1 shl 26)
272
R5XX_HDP_APER_CNTL               equ  (1 shl 23)
273
 
274
R5XX_RB3D_DSTCACHE_MODE             equ  0x3258
275
R5XX_RB3D_DC_CACHE_ENABLE           equ      (0)
276
R5XX_RB3D_DC_2D_CACHE_DISABLE       equ      (1)
277
R5XX_RB3D_DC_3D_CACHE_DISABLE       equ      (2)
278
R5XX_RB3D_DC_CACHE_DISABLE          equ      (3)
279
R5XX_RB3D_DC_2D_CACHE_LINESIZE_128  equ  (1 shl  2)
280
R5XX_RB3D_DC_3D_CACHE_LINESIZE_128  equ  (2 shl  2)
281
R5XX_RB3D_DC_2D_CACHE_AUTOFLUSH     equ  (1 shl  8)
282
R5XX_RB3D_DC_3D_CACHE_AUTOFLUSH     equ  (2 shl  8)
283
R200_RB3D_DC_2D_CACHE_AUTOFREE      equ  (1 shl 10)
284
R200_RB3D_DC_3D_CACHE_AUTOFREE      equ  (2 shl 10)
285
R5XX_RB3D_DC_FORCE_RMW              equ  (1 shl 16)
286
R5XX_RB3D_DC_DISABLE_RI_FILL        equ  (1 shl 24)
287
R5XX_RB3D_DC_DISABLE_RI_READ        equ  (1 shl 25)
288
 
289
R5XX_BRUSH_Y_X                      equ  0x1474
290
R5XX_DP_BRUSH_BKGD_CLR              equ  0x1478
291
R5XX_DP_BRUSH_FRGD_CLR              equ  0x147c
292
R5XX_BRUSH_DATA0                    equ  0x1480
293
R5XX_BRUSH_DATA1                    equ  0x1484
294
 
295
R5XX_SRC_Y_X                        equ  0x1434
296
 
297
R5XX_DST_Y_X                        equ  0x1438
298
R5XX_DST_HEIGHT_WIDTH               equ  0x143c
299
R5XX_DST_WIDTH_HEIGHT               equ  0x1598
300
 
301
R5XX_DST_LINE_START                 equ  0x1600
302
R5XX_DST_LINE_END                   equ  0x1604
303
R5XX_DST_LINE_PATCOUNT              equ  0x1608
304
  R5XX_BRES_CNTL_SHIFT              equ  8
305
 
306
 
307
R5XX_DP_SRC_BKGD_CLR                equ  0x15dc
308
R5XX_DP_SRC_FRGD_CLR                equ  0x15d8
309
 
310
R5XX_DP_WRITE_MASK                  equ  0x16cc
311
 
312
 
313
RADEON_CP_PACKET0                   equ 0x00000000
314
 
315
struc RHD
316
{
317
  .control           rd 1
318
  .control_saved     rd 1
319
  .datatype          rd 1
320
  .surface_cntl      rd 1
321
  .dst_pitch_offset  rd 1
322
  .ring_base         rd 1
323
  .ring_rp           rd 1
324
  .ring_wp           rd 1
325
};
326
 
327
R5XX_LOOP_COUNT equ 2000000
328
 
329
 
330
 
331
align 4
332
R5xxFIFOWaitLocal:
333
 
334
           mov ecx, R5XX_LOOP_COUNT
335
@@:
336
           rdr ebx, R5XX_RBBM_STATUS
337
           and ebx, R5XX_RBBM_FIFOCNT_MASK
338
 
339
           cmp eax, ebx
340
           jbe .done
341
           loop @B
342
 
343
           mov esi, msgR5xxFIFOWaitLocaltimeout
344
           call SysMsgBoardStr
345
           xor eax, eax
346
           ret
347
.done:
348
           mov eax, 1
349
           ret
350
 
351
align 4
352
R5xxFIFOWait:
353
           call R5xxFIFOWaitLocal
354
           test eax, eax
355
           jz .reset
356
 
357
           ret
358
.reset:
359
           call R5xx2DReset
360
           call R5xx2DSetup
361
 
362
           ret
363
 
364
 
365
; Wait for the graphics engine to be completely idle: the FIFO has
366
; drained, the Pixel Cache is flushed, and the engine is idle.  This is
367
; a standard "sync" function that will make the hardware "quiescent".
368
 
369
align 4
370
R5xx2DIdleLocal:
371
 
372
           mov ecx, R5XX_LOOP_COUNT
373
@@:
374
           rdr eax, R5XX_RBBM_STATUS
375
           and eax, R5XX_RBBM_FIFOCNT_MASK
376
           cmp eax, 0x40
377
           je @F
378
           loop @B
379
 
380
           mov esi, msgR5xx2DIdleLocaltimeout
381
           call SysMsgBoardStr
382
           xor eax, eax
383
           ret
384
@@:
385
           mov ecx, R5XX_LOOP_COUNT
386
@@:
387
           rdr eax, R5XX_RBBM_STATUS
388
           test eax, R5XX_RBBM_ACTIVE
389
           jz .done
390
           loop @B
391
 
392
           mov esi, msgR5xx2DIdleLocaltimeout
393
           call SysMsgBoardStr
394
           xor eax, eax
395
           ret
396
.done:
397
           call R5xx2DFlush
398
           ret
399
 
400
align 4
401
R5xx2DFlush:
402
           rmask R5XX_RB3D_DSTCACHE_CTLSTAT, R5XX_RB3D_DC_FLUSH_ALL, R5XX_RB3D_DC_FLUSH_ALL
403
 
404
           mov ecx, R5XX_LOOP_COUNT
405
@@:
406
           rdr eax, R5XX_RB3D_DSTCACHE_CTLSTAT
407
           test eax, R5XX_RB3D_DC_BUSY
408
           jz .done
409
           loop @B
410
.fail:
411
           mov esi, msgR5xx2DFlushtimeout
412
           call SysMsgBoardStr
413
           xor eax, eax
414
           ret
415
.done:
416
           mov eax, 1
417
           ret
418
 
419
align 4
420
proc R5xx2DReset
421
           locals
422
             save    rd 1
423
             tmp     rd 1
424
           endl
425
 
426
 ; The following RBBM_SOFT_RESET sequence can help un-wedge
427
 ; an R300 after the command processor got stuck.
428
 
429
           rdr eax, R5XX_RBBM_SOFT_RESET
430
           mov [save], eax
431
 
432
           or eax, R5XX_SOFT_RESET_CP or \
433
                   R5XX_SOFT_RESET_HI or R5XX_SOFT_RESET_SE or \
434
                   R5XX_SOFT_RESET_RE or R5XX_SOFT_RESET_PP or \
435
                   R5XX_SOFT_RESET_E2 or R5XX_SOFT_RESET_RB
436
           mov [tmp], eax
437
 
438
           wrr R5XX_RBBM_SOFT_RESET, eax
439
 
440
           rdr ebx, R5XX_RBBM_SOFT_RESET
441
           and eax, not (R5XX_SOFT_RESET_CP or R5XX_SOFT_RESET_HI or \
442
                         R5XX_SOFT_RESET_SE or R5XX_SOFT_RESET_RE or \
443
                         R5XX_SOFT_RESET_PP or R5XX_SOFT_RESET_E2 or \
444
                         R5XX_SOFT_RESET_RB)
445
           wrr R5XX_RBBM_SOFT_RESET, eax
446
           rdr ebx, R5XX_RBBM_SOFT_RESET
447
           mov eax, [save]
448
           wrr R5XX_RBBM_SOFT_RESET, eax
449
           rdr ebx, R5XX_RBBM_SOFT_RESET
450
           call R5xx2DFlush
451
 
452
; Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
453
; unexpected behaviour on some machines.  Here we use
454
; R5XX_HOST_PATH_CNTL to reset it.
455
 
456
           rdr edx, R5XX_HOST_PATH_CNTL
457
 
458
           rdr ebx, R5XX_RBBM_SOFT_RESET
459
 
460
           or ebx, R5XX_SOFT_RESET_CP or R5XX_SOFT_RESET_HI or R5XX_SOFT_RESET_E2
461
 
462
           wrr R5XX_RBBM_SOFT_RESET, ebx
463
 
464
           rdr eax, R5XX_RBBM_SOFT_RESET
465
 
466
           wrr R5XX_RBBM_SOFT_RESET, 0
467
 
468
           rdr ebx, R5XX_RB3D_DSTCACHE_MODE
469
 
470
           or ebx, (1 shl 17)
471
           wrr R5XX_RB3D_DSTCACHE_MODE, ebx
472
 
473
           lea eax, [edx+R5XX_HDP_SOFT_RESET]
474
           wrr R5XX_HOST_PATH_CNTL, eax
475
 
476
           rdr ebx, R5XX_HOST_PATH_CNTL
477
 
478
           wrr R5XX_HOST_PATH_CNTL, edx
479
 
480
           ret
481
endp
482
 
483
align 4
484
R5xx2DSetup:
485
 
486
; Setup engine location. This shouldn't be necessary since we
487
; set them appropriately before any accel ops, but let's avoid
488
; random bogus DMA in case we inadvertently trigger the engine
489
; in the wrong place (happened).
490
 
491
           mov eax, 2
492
           call R5xxFIFOWaitLocal
493
 
494
           mov eax, [rhd.dst_pitch_offset]
495
           wrr R5XX_DST_PITCH_OFFSET, eax
496
 
497
           wrr R5XX_SRC_PITCH_OFFSET, eax
498
 
499
           mov eax, 1
500
           call R5xxFIFOWaitLocal
501
 
502
           rmask R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN
503
 
504
           mov eax, [rhd.surface_cntl]
505
           wrr R5XX_SURFACE_CNTL, eax
506
 
507
           mov eax, 1
508
           call R5xxFIFOWaitLocal
509
 
510
           wrr R5XX_DEFAULT_SC_BOTTOM_RIGHT,\
511
               (R5XX_DEFAULT_SC_RIGHT_MAX or R5XX_DEFAULT_SC_BOTTOM_MAX)
512
 
513
           mov eax, 1
514
           call R5xxFIFOWaitLocal
515
 
516
           mov eax, [rhd.control]
517
           or eax, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
518
           wrr R5XX_DP_GUI_MASTER_CNTL, eax
519
 
520
           mov eax, 5
521
           call R5xxFIFOWaitLocal
522
 
523
           wrr R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF
524
 
525
           wrr R5XX_DP_BRUSH_BKGD_CLR, 0x00000000
526
 
527
           wrr R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF
528
           wrr R5XX_DP_SRC_BKGD_CLR, 0x00000000
529
           wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
530
 
531
           call R5xx2DIdleLocal
532
           ret
533
 
534
align 4
535
R5xx2DPreInit:
536
 
537
           mov [rhd.control],\
538
               (R5XX_DATATYPE_ARGB8888 shl R5XX_GMC_DST_DATATYPE_SHIFT) or\
539
                R5XX_GMC_CLR_CMP_CNTL_DIS or R5XX_GMC_DST_PITCH_OFFSET_CNTL
540
 
541
           mov [rhd.datatype], R5XX_DATATYPE_ARGB8888
542
           mov [rhd.surface_cntl],0
543
 
544
           rdr eax, D1GRPH_PITCH
545
           shl eax, 18
546
 
547
           mov ebx, [r500_LFB]
548
           shr ebx, 10
549
           or eax, ebx
550
 
551
           mov [rhd.dst_pitch_offset], eax
552
 
553
           ret
554
 
555
RADEON_BUS_CNTL            equ 0x0030
556
  RADEON_BUS_MASTER_DIS    equ (1 shl 6)
557
 
558
align 4
559
R5xxCpInit:
560
           stdcall CreateRingBuffer, 0x8000, PG_SW+PG_NOCACHE
561
           test eax, eax
562
           jz .fail
563
 
564
           mov [rhd.ring_base], eax
565
           call GetPgAddr
566
 
567
           wrr RADEON_CP_RB_BASE, eax
568
 
569
           wrr RADEON_CP_RB_WPTR_DELAY, 0
570
 
571
           rdr ebx, RADEON_CP_RB_RPTR
572
           wrr RADEON_CP_RB_WPTR, ebx
573
 
574
           mov [rhd.ring_rp], ebx
575
           mov [rhd.ring_wp], ebx
576
 
577
           wrr RADEON_CP_RB_RPTR_ADDR, 0       ;ring buffer read pointer
578
                                               ;no update
579
 
580
           wrr RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE + 12
581
           wrr RADEON_SCRATCH_UMSK, 0          ;no scratch update
582
 
583
           rdr ebx, RADEON_BUS_CNTL
584
           and ebx, not RADEON_BUS_MASTER_DIS
585
 
586
           wrr RADEON_BUS_CNTL, ebx
587
 
588
         ;  wrr RADEON_LAST_FRAME_REG, 0
589
         ;  wrr RADEON_LAST_DISPATCH_REG, 0
590
         ;  wrr RADEON_LAST_CLEAR_REG, 0
591
 
592
           call R5xx2DIdleLocal
593
 
594
           wrr RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D + \
595
                                  RADEON_ISYNC_ANY3D_IDLE2D + \
596
                                  RADEON_ISYNC_WAIT_IDLEGUI + \
597
                                  RADEON_ISYNC_CPSCRATCH_IDLEGUI
598
.fail:
599
           ret
600
 
601
align 4
602
load_microcode:
603
 
604
           pushfd
605
           cli
606
 
607
           call R5xx2DIdleLocal
608
 
609
           wrr RADEON_CP_ME_RAM_ADDR, 0
610
 
611
           lea esi, [R520_cp_microcode]
612
           mov ecx, 256
613
@@:
614
           mov eax, [esi]
615
           mov ebx, [esi+4]
616
           wrr RADEON_CP_ME_RAM_DATAH, ebx
617
           wrr RADEON_CP_ME_RAM_DATAL, eax
618
           add esi, 8
619
           loop @B
620
 
621
           popfd
622
           ret
623
 
624
 
625
align 4
626
R5xx2DInit:
627
 
628
           call R5xx2DPreInit
629
           wrr R5XX_RB3D_CNTL, 0
630
 
631
           call R5xx2DReset
632
           call R5xx2DSetup
633
 
634
           rdr eax, RADEON_AIC_CNTL                     ;disable GART
635
           and eax, not RADEON_PCIGART_TRANSLATE_EN
636
           wrr RADEON_AIC_CNTL, eax
637
 
638
           call load_microcode
639
 
640
           call R5xxCpInit
641
 
642
           rdr eax, D1GRPH_X_END
643
           rdr ebx, D1GRPH_Y_END
644
           dec eax
645
           dec ebx
646
 
647
           mov [__xmin], 0         ;set clip
648
           mov [__ymin], 0
649
           mov [__xmax], eax
650
           mov [__ymax], ebx
651
 
652
           wrr RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM
653
 
654
       ;    BEGIN_RING
655
       ;    RADEON_PURGE_CACHE
656
       ;    RADEON_PURGE_ZCACHE
657
       ;    RADEON_WAIT_UNTIL_IDLE
658
       ;    COMMIT_RING
659
 
660
           ret
661
 
662
proc R5xxSetupForSolidFill stdcall,color:dword, rop:dword, planemask:dword
663
 
664
           mov edx, [rop]
665
           mov edx, [R5xxRops+4+edx*8]
666
           or edx, [rhd.control]
667
           or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
668
 
669
; Save for later clipping
670
           mov [rhd.control_saved], edx
671
 
672
           mov eax, 4
673
           call R5xxFIFOWait
674
 
675
           wrr R5XX_DP_GUI_MASTER_CNTL, edx
676
 
677
           mov eax, [color]
678
           wrr R5XX_DP_BRUSH_FRGD_CLR, eax
679
 
680
           mov ebx, [planemask]
681
           wrr R5XX_DP_WRITE_MASK, ebx
682
 
683
           wrr R5XX_DP_CNTL, (R5XX_DST_X_LEFT_TO_RIGHT or R5XX_DST_Y_TOP_TO_BOTTOM)
684
 
685
           ret
686
 endp
687
 
688
align 4
689
proc R5xxSolidFillRect stdcall, x:dword, y:dword, w:dword, h:dword
690
 
691
           mov eax, 3
692
           call R5xxFIFOWait
693
 
694
           mov eax, [rhd.dst_pitch_offset]
695
           wrr R5XX_DST_PITCH_OFFSET, eax
696
 
697
           mov ebx, [y]
698
           shl ebx, 16
699
           mov bx, word [x]
700
           wrr R5XX_DST_Y_X, ebx
701
 
702
           mov ecx, [w]
703
           shl ecx, 16
704
           mov cx, word [h]
705
           wrr R5XX_DST_WIDTH_HEIGHT, ecx
706
 
707
           ret
708
endp
709
 
710
handle     equ  IOCTL.handle
711
io_code    equ  IOCTL.io_code
712
input      equ  IOCTL.input
713
inp_size   equ  IOCTL.inp_size
714
output     equ  IOCTL.output
715
out_size   equ  IOCTL.out_size
716
 
717
SRV_GETVERSION  equ 0
718
SOLID_FILL      equ 1
719
LINE_2P         equ 2
720
 
721
align 4
722
proc r500_entry stdcall, state:dword
723
 
724
.close:
725
          ; call r500_close
726
 
727
           xor eax, eax
728
           ret
729
endp
730
 
731
CURRENT_TASK	    equ (OS_BASE+0x0003000)
732
TASK_COUNT	    equ (OS_BASE+0x0003004)
733
WIN_STACK 	    equ (OS_BASE+0x000C000)
734
 
735
 
736
align 4
737
proc r500_HDraw stdcall, ioctl:dword
738
 
739
           mov ebx, [ioctl]
740
           mov eax, [ebx+io_code]
741
           cmp eax, LINE_2P
742
           ja .fail
743
 
744
           cmp eax, SRV_GETVERSION
745
           jne @F
746
 
747
           mov eax, [ebx+output]
748
           cmp [ebx+out_size], 4
749
           jne .fail
750
           mov [eax], dword API_VERSION
751
           xor eax, eax
752
           ret
753
@@:
754
           mov edx, [CURRENT_TASK]
755
           movzx edx, word [WIN_STACK+edx*2]
756
           cmp edx, [TASK_COUNT]
757
           jne .skip                                   ;skip if window inactive
758
 
759
           cmp eax, SOLID_FILL
760
           jne @F
761
 
762
           cmp [ebx+inp_size], 5
763
           jne .fail
764
 
765
           mov esi, [ebx+input]
766
           call solid_fill
767
.skip:
768
           xor eax, eax
769
           ret
770
@@:
771
           cmp eax, LINE_2P
772
           jne @F
773
 
774
           cmp [ebx+inp_size], 5
775
           jne .fail
776
 
777
           mov esi, [ebx+input]
778
           call solid_line
779
           xor eax, eax
780
           ret
781
@@:
782
 
783
.fail:
784
           or eax, -1
785
           ret
786
endp
787
 
788
restore   handle
789
restore   io_code
790
restore   input
791
restore   inp_size
792
restore   output
793
restore   out_size
794
 
795
struc FILL
796
{
797
  .color  rd 1
798
  .x      rd 1
799
  .y      rd 1
800
  .w      rd 1
801
  .h      rd 1
802
}
803
 
804
virtual at 0
805
  FILL FILL
806
end virtual
807
 
808
struc LINE2P
809
{
810
  .color  rd 1
811
  .x1      rd 1
812
  .y1      rd 1
813
  .x2      rd 1
814
  .y2      rd 1
815
}
816
 
817
virtual at 0
818
  LINE2P LINE2P
819
end virtual
820
 
821
GXcopy  equ 3
822
 
823
RADEON_CP_PACKET3         equ 0xC0000000
824
 
825
PAINT_MULTI               equ 0xC0009A00
826
 
827
DST_PITCH_OFFSET_CNTL     equ (  1 shl  1)
828
BRUSH_SOLID_COLOR         equ ( 13 shl  4)
829
COLOR_ARGB                equ (  6 shl  8)
830
SRC_DATATYPE_COLOR        equ (  3 shl 12)
831
 
832
;RADEON_ROP3_P             equ
833
 
834
; esi= input params
835
align 4
836
solid_fill:
837
 
838
           mov ebx, [esi+FILL.x]
839
           mov ecx, [esi+FILL.y]
840
           mov eax, [esi+FILL.w]
841
           mov edx, [esi+FILL.h]
842
 
843
           lea eax, [eax+ebx-1]     ;x2
844
           lea edx, [edx+ecx-1]     ;y2
845
 
846
           push edx                 ;y2
847
           push eax                 ;x2
848
 
849
           mov eax, esp             ;&x2
850
           lea ebx, [esp+4]         ;&y2
851
 
852
           lea ecx, [esi+FILL.x]
853
           lea edx, [esi+FILL.y]
854
 
855
           push ebx                 ;&y2
856
           push eax                 ;&x2
857
           push edx                 ;&y1
858
           push ecx                 ;&x1
859
 
860
           call _BlockClip
861
           add esp, 16
862
           test eax, eax
863
           jnz .exit
864
 
865
           ;mov edx, [R5xxRops+4+GXcopy*8]
866
           ;or edx, [rhd.control]
867
           ;or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
868
 
869
           pushfd
870
           cli
871
 
872
 
873
       BEGIN_RING
874
         OUT_PACKET3 PAINT_MULTI, 4
875
         OUT_RING (DST_PITCH_OFFSET_CNTL + \
876
                     BRUSH_SOLID_COLOR     + \
877
                     COLOR_ARGB            + \
878
                     SRC_DATATYPE_COLOR    + \
879
                     (1 shl 28)+(1 shl 30) + \
880
                     R5XX_ROP3_P)
881
 
882
         OUT_RING [rhd.dst_pitch_offset]
883
         OUT_RING [esi+FILL.color]
884
 
885
           mov ebx, [esi+FILL.y]
886
           shl ebx, 16
887
           mov bx, word [esi+FILL.x]
888
         OUT_RING ebx
889
 
890
           mov ecx, [esp+4]             ;x2
891
           sub ecx, [esi+FILL.x]
892
           inc ecx                      ;w
893
 
894
           mov eax, [esp+8]             ;y2
895
           sub eax, [esi+FILL.y]
896
           inc eax                      ;h
897
 
898
           shl ecx, 16
899
           mov cx, ax                   ;w|h
900
 
901
         OUT_RING ecx
902
       COMMIT_RING
903
 
904
if 0
905
;           mov eax, 7
906
;           call R5xxFIFOWait
907
 
908
;           wrr R5XX_DP_GUI_MASTER_CNTL, edx
909
 
910
;           mov eax, [esi+FILL.color]
911
;           wrr R5XX_DP_BRUSH_FRGD_CLR, eax
912
 
913
;           wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
914
 
915
;           wrr R5XX_DP_CNTL, (R5XX_DST_X_LEFT_TO_RIGHT or R5XX_DST_Y_TOP_TO_BOTTOM)
916
 
917
;           mov eax, [rhd.dst_pitch_offset]
918
;           wrr R5XX_DST_PITCH_OFFSET, eax
919
 
920
;           mov ebx, [esi+FILL.y]
921
;           shl ebx, 16
922
;           mov bx, word [esi+FILL.x]
923
;           wrr R5XX_DST_Y_X, ebx
924
 
925
;           mov ecx, [esp+4]             ;x2
926
;           sub ecx, [esi+FILL.x]
927
;           inc ecx                      ;w
928
 
929
;           mov eax, [esp+8]             ;y2
930
;           sub eax, [esi+FILL.y]
931
;           inc eax                      ;h
932
 
933
;           shl ecx, 16
934
;           mov cx, ax                        ;w|h
935
;           wrr R5XX_DST_WIDTH_HEIGHT, ecx
936
end if
937
           popfd
938
.exit:
939
           add esp, 8
940
           ret
941
 
942
align 4
943
solid_line:
944
 
945
           lea eax, [esi+LINE2P.y2]
946
           lea ebx, [esi+LINE2P.x2]
947
           lea ecx, [esi+LINE2P.y1]
948
           lea edx, [esi+LINE2P.x1]
949
 
950
           push eax
951
           push ebx
952
           push ecx
953
           push edx
954
 
955
           call _LineClip
956
           add esp, 16
957
           test eax, eax
958
           jnz .exit
959
 
960
           mov edx, [R5xxRops+4+GXcopy*8]
961
           or edx, [rhd.control]
962
           or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
963
 
964
           pushfd
965
           cli
966
 
967
           mov eax, 7
968
           call R5xxFIFOWait
969
 
970
           wrr R5XX_DST_LINE_PATCOUNT, (0x55 shl R5XX_BRES_CNTL_SHIFT)
971
           wrr R5XX_DP_GUI_MASTER_CNTL, edx
972
 
973
           mov eax, [esi+FILL.color]
974
           wrr R5XX_DP_BRUSH_FRGD_CLR, eax
975
 
976
           wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
977
 
978
           mov eax, [rhd.dst_pitch_offset]
979
           wrr R5XX_DST_PITCH_OFFSET, eax
980
 
981
           mov ebx, [esi+LINE2P.y1]
982
           shl ebx, 16
983
           mov bx, word [esi+LINE2P.x1]
984
           wrr R5XX_DST_LINE_START, ebx
985
 
986
           mov ecx, [esi+LINE2P.y2]
987
           shl ecx, 16
988
           mov cx, word [esi+LINE2P.x2]
989
           wrr R5XX_DST_LINE_END, ecx
990
           popfd
991
.exit:
992
           ret
993
 
994
align 4
995
__L1OutCode:
996
           cmp     eax, [__xmin]
997
           mov     ecx, edx
998
           setl    dl
999
           sal     edx, 3
1000
           cmp     eax, [__xmax]
1001
           jle     L9
1002
           or      edx, 4
1003
L9:
1004
           cmp     ecx, [__ymin]
1005
           jge     L11
1006
           or      edx, 1
1007
L11:
1008
           cmp     ecx, [__ymax]
1009
           jle     L13
1010
           or      edx, 2
1011
L13:
1012
           movzx   eax, dl
1013
           ret
1014
 
1015
align 4
1016
_line_inter:
1017
           push    ebp
1018
           mov     ebp, edx
1019
           push    edi
1020
           push    esi
1021
           push    ebx
1022
           sub     esp, 4
1023
           mov     ebx, [eax]
1024
           mov     [esp], eax
1025
           mov     edx, [esp+24]
1026
           mov     edi, [ebp]
1027
           sub     ecx, ebx
1028
           mov     eax, ecx
1029
           sar     eax, 31
1030
           sub     edx, edi
1031
           mov     esi, eax
1032
           xor     esi, ecx
1033
           sub     esi, eax
1034
           mov     eax, [esp+28]
1035
           lea     ecx, [edx+edx]
1036
           sub     eax, ebx
1037
           cdq
1038
           xor     eax, edx
1039
           sub     eax, edx
1040
           imul    ecx, eax
1041
           test    ecx, ecx
1042
           jle     L17
1043
           add     ecx, esi
1044
           jmp     L19
1045
L17:
1046
           sub     ecx, esi
1047
L19:
1048
           lea     edx, [esi+esi]
1049
           mov     eax, ecx
1050
           mov     ebx, edx
1051
           cdq
1052
           idiv    ebx
1053
           lea     eax, [eax+edi]
1054
           mov     [ebp], eax
1055
           mov     eax, [esp]
1056
           mov     edx, [esp+28]
1057
           mov     [eax], edx
1058
           pop     eax
1059
           pop     ebx
1060
           pop     esi
1061
           pop     edi
1062
           pop     ebp
1063
           ret
1064
 
1065
_LineClip:
1066
           push    ebp
1067
           push    edi
1068
           push    esi
1069
           push    ebx
1070
           mov     eax, [esp+24]
1071
           mov     ecx, [esp+20]
1072
           mov     ebp, [esp+28]
1073
           mov     edi, [esp+32]
1074
           mov     edx, [eax]
1075
           mov     eax, [ecx]
1076
           call    __L1OutCode
1077
           mov     edx, [edi]
1078
           mov     bl, al
1079
           mov     eax, [ebp]
1080
           call    __L1OutCode
1081
L48:
1082
           mov     esi, eax
1083
L47:
1084
           mov     eax, esi
1085
           and     al, bl
1086
           jne     L23
1087
           mov     edx, esi
1088
           cmp     bl, dl
1089
           je      L23
1090
           test    bl, bl
1091
           jne     L26
1092
           movsx   eax, dl
1093
           test    al, 1
1094
           je      L28
1095
           push    [__ymin]
1096
           mov     ecx, [esp+24]
1097
           push    dword [ecx]
1098
           jmp     L51
1099
L28:
1100
           test    al, 2
1101
           je      L31
1102
           push    [__ymax]
1103
           mov     edx, [esp+24]
1104
           push    dword [edx]
1105
L51:
1106
           mov     eax, [esp+32]
1107
           mov     edx, ebp
1108
           mov     ecx, [eax]
1109
           mov     eax, edi
1110
           jmp     L49
1111
L31:
1112
           test    al, 4
1113
           je      L33
1114
           push    [__xmax]
1115
           jmp     L52
1116
L33:
1117
           test    al, 8
1118
           je      L30
1119
           push    [__xmin]
1120
L52:
1121
           mov     edx, [esp+28]
1122
           push    dword [edx]
1123
           mov     edx, edi
1124
           mov     eax, [esp+28]
1125
           mov     ecx, [eax]
1126
           mov     eax, ebp
1127
L49:
1128
           call    _line_inter
1129
           pop     esi
1130
           pop     eax
1131
L30:
1132
           mov     edx, [edi]
1133
           mov     eax, [ebp]
1134
           call    __L1OutCode
1135
           jmp     L48
1136
L26:
1137
           movsx   eax, bl
1138
           test    al, 1
1139
           je      L36
1140
           push    [__ymin]
1141
           jmp     L53
1142
L36:
1143
           test    al, 2
1144
           je      L39
1145
           push    [__ymax]
1146
L53:
1147
           push    dword [ebp]
1148
           mov     ecx, [edi]
1149
           mov     edx, [esp+28]
1150
           mov     eax, [esp+32]
1151
           jmp     L50
1152
L39:
1153
           test    al, 4
1154
           je      L41
1155
           push    [__xmax]
1156
           jmp     L54
1157
L41:
1158
           test    al, 8
1159
           je      L38
1160
           push    [__xmin]
1161
L54:
1162
           push    dword [edi]
1163
           mov     ecx, [ebp]
1164
           mov     edx, [esp+32]
1165
           mov     eax, [esp+28]
1166
L50:
1167
           call    _line_inter
1168
           pop     edx
1169
           pop     ecx
1170
L38:
1171
           mov     ecx, [esp+24]
1172
           mov     edx, [ecx]
1173
           mov     ecx, [esp+20]
1174
           mov     eax, [ecx]
1175
           call    __L1OutCode
1176
           mov     bl, al
1177
           jmp     L47
1178
L23:
1179
           pop     ebx
1180
           movsx   eax, al
1181
           pop     esi
1182
           pop     edi
1183
           pop     ebp
1184
           ret
1185
 
1186
align 4
1187
_block_inter:
1188
           test    cl, 1
1189
           push    ebx
1190
           mov     ebx, eax
1191
           je      L57
1192
           mov     eax, [__ymin]
1193
           jmp     L66
1194
L57:
1195
           test    cl, 2
1196
           je      L60
1197
           mov     eax, [__ymax]
1198
L66:
1199
           mov     [edx], eax
1200
           jmp     L65
1201
L60:
1202
           test    cl, 4
1203
           je      L62
1204
           mov     eax, [__xmax]
1205
           jmp     L67
1206
L62:
1207
           and     cl, 8
1208
           je      L65
1209
           mov     eax, [__xmin]
1210
L67:
1211
           mov     [ebx], eax
1212
L65:
1213
           pop     ebx
1214
           ret
1215
 
1216
align 4
1217
_BlockClip:
1218
           push    ebp
1219
           push    edi
1220
           push    esi
1221
           push    ebx
1222
           mov     eax, [esp+24]
1223
           mov     ecx, [esp+20]
1224
           mov     ebp, [esp+28]
1225
           mov     edi, [esp+32]
1226
           mov     edx, [eax]
1227
           mov     eax, [ecx]
1228
           call    __L1OutCode
1229
           mov     edx, [edi]
1230
           mov     ebx, eax
1231
           mov     eax, [ebp]
1232
           call    __L1OutCode
1233
L80:
1234
           mov     esi, eax
1235
L79:
1236
           test    esi, ebx
1237
           jne     L70
1238
           cmp     ebx, esi
1239
           je      L72
1240
           test    ebx, ebx
1241
           jne     L74
1242
           mov     edx, edi
1243
           mov     eax, ebp
1244
           mov     ecx, esi
1245
           call    _block_inter
1246
           mov     edx, [edi]
1247
           mov     eax, [ebp]
1248
           call    __L1OutCode
1249
           jmp     L80
1250
L74:
1251
           mov     edx, [esp+24]
1252
           mov     ecx, ebx
1253
           mov     eax, [esp+20]
1254
           call    _block_inter
1255
           mov     eax, [esp+24]
1256
           mov     ecx, [esp+20]
1257
           mov     edx, [eax]
1258
           mov     eax, [ecx]
1259
           call    __L1OutCode
1260
           mov     ebx, eax
1261
           jmp     L79
1262
L72:
1263
           mov     esi, ebx
1264
L70:
1265
           mov     eax, esi
1266
           and     eax, ebx
1267
           pop     ebx
1268
           cwde
1269
           pop     esi
1270
           pop     edi
1271
           pop     ebp
1272
           ret