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5270 | serge | 1 | #ifndef _UAPI_ASM_X86_PROCESSOR_FLAGS_H |
2 | #define _UAPI_ASM_X86_PROCESSOR_FLAGS_H |
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3 | /* Various flags defined: can be included from assembler. */ |
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4 | |||
5 | #include |
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6 | |||
7 | /* |
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8 | * EFLAGS bits |
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9 | */ |
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10 | #define X86_EFLAGS_CF_BIT 0 /* Carry Flag */ |
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11 | #define X86_EFLAGS_CF _BITUL(X86_EFLAGS_CF_BIT) |
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12 | #define X86_EFLAGS_FIXED_BIT 1 /* Bit 1 - always on */ |
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13 | #define X86_EFLAGS_FIXED _BITUL(X86_EFLAGS_FIXED_BIT) |
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14 | #define X86_EFLAGS_PF_BIT 2 /* Parity Flag */ |
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15 | #define X86_EFLAGS_PF _BITUL(X86_EFLAGS_PF_BIT) |
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16 | #define X86_EFLAGS_AF_BIT 4 /* Auxiliary carry Flag */ |
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17 | #define X86_EFLAGS_AF _BITUL(X86_EFLAGS_AF_BIT) |
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18 | #define X86_EFLAGS_ZF_BIT 6 /* Zero Flag */ |
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19 | #define X86_EFLAGS_ZF _BITUL(X86_EFLAGS_ZF_BIT) |
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20 | #define X86_EFLAGS_SF_BIT 7 /* Sign Flag */ |
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21 | #define X86_EFLAGS_SF _BITUL(X86_EFLAGS_SF_BIT) |
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22 | #define X86_EFLAGS_TF_BIT 8 /* Trap Flag */ |
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23 | #define X86_EFLAGS_TF _BITUL(X86_EFLAGS_TF_BIT) |
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24 | #define X86_EFLAGS_IF_BIT 9 /* Interrupt Flag */ |
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25 | #define X86_EFLAGS_IF _BITUL(X86_EFLAGS_IF_BIT) |
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26 | #define X86_EFLAGS_DF_BIT 10 /* Direction Flag */ |
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27 | #define X86_EFLAGS_DF _BITUL(X86_EFLAGS_DF_BIT) |
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28 | #define X86_EFLAGS_OF_BIT 11 /* Overflow Flag */ |
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29 | #define X86_EFLAGS_OF _BITUL(X86_EFLAGS_OF_BIT) |
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30 | #define X86_EFLAGS_IOPL_BIT 12 /* I/O Privilege Level (2 bits) */ |
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31 | #define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT) |
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32 | #define X86_EFLAGS_NT_BIT 14 /* Nested Task */ |
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33 | #define X86_EFLAGS_NT _BITUL(X86_EFLAGS_NT_BIT) |
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34 | #define X86_EFLAGS_RF_BIT 16 /* Resume Flag */ |
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35 | #define X86_EFLAGS_RF _BITUL(X86_EFLAGS_RF_BIT) |
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36 | #define X86_EFLAGS_VM_BIT 17 /* Virtual Mode */ |
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37 | #define X86_EFLAGS_VM _BITUL(X86_EFLAGS_VM_BIT) |
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38 | #define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */ |
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39 | #define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT) |
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40 | #define X86_EFLAGS_VIF_BIT 19 /* Virtual Interrupt Flag */ |
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41 | #define X86_EFLAGS_VIF _BITUL(X86_EFLAGS_VIF_BIT) |
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42 | #define X86_EFLAGS_VIP_BIT 20 /* Virtual Interrupt Pending */ |
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43 | #define X86_EFLAGS_VIP _BITUL(X86_EFLAGS_VIP_BIT) |
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44 | #define X86_EFLAGS_ID_BIT 21 /* CPUID detection */ |
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45 | #define X86_EFLAGS_ID _BITUL(X86_EFLAGS_ID_BIT) |
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46 | |||
47 | /* |
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48 | * Basic CPU control in CR0 |
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49 | */ |
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50 | #define X86_CR0_PE_BIT 0 /* Protection Enable */ |
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51 | #define X86_CR0_PE _BITUL(X86_CR0_PE_BIT) |
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52 | #define X86_CR0_MP_BIT 1 /* Monitor Coprocessor */ |
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53 | #define X86_CR0_MP _BITUL(X86_CR0_MP_BIT) |
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54 | #define X86_CR0_EM_BIT 2 /* Emulation */ |
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55 | #define X86_CR0_EM _BITUL(X86_CR0_EM_BIT) |
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56 | #define X86_CR0_TS_BIT 3 /* Task Switched */ |
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57 | #define X86_CR0_TS _BITUL(X86_CR0_TS_BIT) |
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58 | #define X86_CR0_ET_BIT 4 /* Extension Type */ |
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59 | #define X86_CR0_ET _BITUL(X86_CR0_ET_BIT) |
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60 | #define X86_CR0_NE_BIT 5 /* Numeric Error */ |
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61 | #define X86_CR0_NE _BITUL(X86_CR0_NE_BIT) |
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62 | #define X86_CR0_WP_BIT 16 /* Write Protect */ |
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63 | #define X86_CR0_WP _BITUL(X86_CR0_WP_BIT) |
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64 | #define X86_CR0_AM_BIT 18 /* Alignment Mask */ |
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65 | #define X86_CR0_AM _BITUL(X86_CR0_AM_BIT) |
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66 | #define X86_CR0_NW_BIT 29 /* Not Write-through */ |
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67 | #define X86_CR0_NW _BITUL(X86_CR0_NW_BIT) |
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68 | #define X86_CR0_CD_BIT 30 /* Cache Disable */ |
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69 | #define X86_CR0_CD _BITUL(X86_CR0_CD_BIT) |
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70 | #define X86_CR0_PG_BIT 31 /* Paging */ |
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71 | #define X86_CR0_PG _BITUL(X86_CR0_PG_BIT) |
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72 | |||
73 | /* |
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74 | * Paging options in CR3 |
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75 | */ |
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76 | #define X86_CR3_PWT_BIT 3 /* Page Write Through */ |
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77 | #define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT) |
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78 | #define X86_CR3_PCD_BIT 4 /* Page Cache Disable */ |
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79 | #define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT) |
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80 | #define X86_CR3_PCID_MASK _AC(0x00000fff,UL) /* PCID Mask */ |
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81 | |||
82 | /* |
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83 | * Intel CPU features in CR4 |
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84 | */ |
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85 | #define X86_CR4_VME_BIT 0 /* enable vm86 extensions */ |
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86 | #define X86_CR4_VME _BITUL(X86_CR4_VME_BIT) |
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87 | #define X86_CR4_PVI_BIT 1 /* virtual interrupts flag enable */ |
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88 | #define X86_CR4_PVI _BITUL(X86_CR4_PVI_BIT) |
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89 | #define X86_CR4_TSD_BIT 2 /* disable time stamp at ipl 3 */ |
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90 | #define X86_CR4_TSD _BITUL(X86_CR4_TSD_BIT) |
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91 | #define X86_CR4_DE_BIT 3 /* enable debugging extensions */ |
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92 | #define X86_CR4_DE _BITUL(X86_CR4_DE_BIT) |
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93 | #define X86_CR4_PSE_BIT 4 /* enable page size extensions */ |
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94 | #define X86_CR4_PSE _BITUL(X86_CR4_PSE_BIT) |
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95 | #define X86_CR4_PAE_BIT 5 /* enable physical address extensions */ |
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96 | #define X86_CR4_PAE _BITUL(X86_CR4_PAE_BIT) |
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97 | #define X86_CR4_MCE_BIT 6 /* Machine check enable */ |
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98 | #define X86_CR4_MCE _BITUL(X86_CR4_MCE_BIT) |
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99 | #define X86_CR4_PGE_BIT 7 /* enable global pages */ |
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100 | #define X86_CR4_PGE _BITUL(X86_CR4_PGE_BIT) |
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101 | #define X86_CR4_PCE_BIT 8 /* enable performance counters at ipl 3 */ |
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102 | #define X86_CR4_PCE _BITUL(X86_CR4_PCE_BIT) |
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103 | #define X86_CR4_OSFXSR_BIT 9 /* enable fast FPU save and restore */ |
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104 | #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) |
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105 | #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ |
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106 | #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) |
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107 | #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ |
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108 | #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) |
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109 | #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ |
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110 | #define X86_CR4_SMXE _BITUL(X86_CR4_SMXE_BIT) |
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111 | #define X86_CR4_FSGSBASE_BIT 16 /* enable RDWRFSGS support */ |
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112 | #define X86_CR4_FSGSBASE _BITUL(X86_CR4_FSGSBASE_BIT) |
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113 | #define X86_CR4_PCIDE_BIT 17 /* enable PCID support */ |
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114 | #define X86_CR4_PCIDE _BITUL(X86_CR4_PCIDE_BIT) |
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115 | #define X86_CR4_OSXSAVE_BIT 18 /* enable xsave and xrestore */ |
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116 | #define X86_CR4_OSXSAVE _BITUL(X86_CR4_OSXSAVE_BIT) |
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117 | #define X86_CR4_SMEP_BIT 20 /* enable SMEP support */ |
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118 | #define X86_CR4_SMEP _BITUL(X86_CR4_SMEP_BIT) |
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119 | #define X86_CR4_SMAP_BIT 21 /* enable SMAP support */ |
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120 | #define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT) |
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7143 | serge | 121 | #define X86_CR4_PKE_BIT 22 /* enable Protection Keys support */ |
122 | #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) |
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5270 | serge | 123 | |
124 | /* |
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125 | * x86-64 Task Priority Register, CR8 |
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126 | */ |
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127 | #define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */ |
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128 | |||
129 | /* |
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130 | * AMD and Transmeta use MSRs for configuration; see |
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131 | */ |
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132 | |||
133 | /* |
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134 | * NSC/Cyrix CPU configuration register indexes |
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135 | */ |
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136 | #define CX86_PCR0 0x20 |
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137 | #define CX86_GCR 0xb8 |
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138 | #define CX86_CCR0 0xc0 |
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139 | #define CX86_CCR1 0xc1 |
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140 | #define CX86_CCR2 0xc2 |
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141 | #define CX86_CCR3 0xc3 |
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142 | #define CX86_CCR4 0xe8 |
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143 | #define CX86_CCR5 0xe9 |
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144 | #define CX86_CCR6 0xea |
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145 | #define CX86_CCR7 0xeb |
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146 | #define CX86_PCR1 0xf0 |
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147 | #define CX86_DIR0 0xfe |
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148 | #define CX86_DIR1 0xff |
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149 | #define CX86_ARR_BASE 0xc4 |
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150 | #define CX86_RCR_BASE 0xdc |
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151 | |||
152 | |||
153 | #endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */><> |