WebSVN – Kolibri OS – Blame – /drivers/include/linux/uapi/drm/radeon_drm.h

Rev	Author	Line No.	Line
5056	serge	1	/* radeon_drm.h -- Public header for the radeon driver -- linux-c --
		2	*
		3	* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
		4	* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
		5	* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
		6	* All rights reserved.
		7	*
		8	* Permission is hereby granted, free of charge, to any person obtaining a
		9	* copy of this software and associated documentation files (the "Software"),
		10	* to deal in the Software without restriction, including without limitation
		11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		12	* and/or sell copies of the Software, and to permit persons to whom the
		13	* Software is furnished to do so, subject to the following conditions:
		14	*
		15	* The above copyright notice and this permission notice (including the next
		16	* paragraph) shall be included in all copies or substantial portions of the
		17	* Software.
		18	*
		19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		22	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
		23	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		24	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		25	* DEALINGS IN THE SOFTWARE.
		26	*
		27	* Authors:
		28	* Kevin E. Martin
		29	* Gareth Hughes
		30	* Keith Whitwell
		31	*/
		32
		33	#ifndef __RADEON_DRM_H__
		34	#define __RADEON_DRM_H__
		35
		36	#include
		37
		38	/* WARNING: If you change any of these defines, make sure to change the
		39	* defines in the X server file (radeon_sarea.h)
		40	*/
		41	#ifndef __RADEON_SAREA_DEFINES__
		42	#define __RADEON_SAREA_DEFINES__
		43
		44	/* Old style state flags, required for sarea interface (1.1 and 1.2
		45	* clears) and 1.2 drm_vertex2 ioctl.
		46	*/
		47	#define RADEON_UPLOAD_CONTEXT 0x00000001
		48	#define RADEON_UPLOAD_VERTFMT 0x00000002
		49	#define RADEON_UPLOAD_LINE 0x00000004
		50	#define RADEON_UPLOAD_BUMPMAP 0x00000008
		51	#define RADEON_UPLOAD_MASKS 0x00000010
		52	#define RADEON_UPLOAD_VIEWPORT 0x00000020
		53	#define RADEON_UPLOAD_SETUP 0x00000040
		54	#define RADEON_UPLOAD_TCL 0x00000080
		55	#define RADEON_UPLOAD_MISC 0x00000100
		56	#define RADEON_UPLOAD_TEX0 0x00000200
		57	#define RADEON_UPLOAD_TEX1 0x00000400
		58	#define RADEON_UPLOAD_TEX2 0x00000800
		59	#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
		60	#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
		61	#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
		62	#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
		63	#define RADEON_REQUIRE_QUIESCENCE 0x00010000
		64	#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
		65	#define RADEON_UPLOAD_ALL 0x003effff
		66	#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
		67
		68	/* New style per-packet identifiers for use in cmd_buffer ioctl with
		69	* the RADEON_EMIT_PACKET command. Comments relate new packets to old
		70	* state bits and the packet size:
		71	*/
		72	#define RADEON_EMIT_PP_MISC 0 /* context/7 */
		73	#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
		74	#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
		75	#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
		76	#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
		77	#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
		78	#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
		79	#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
		80	#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
		81	#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
		82	#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
		83	#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
		84	#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
		85	#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
		86	#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
		87	#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
		88	#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
		89	#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
		90	#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
		91	#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
		92	#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
		93	#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
		94	#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
		95	#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
		96	#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
		97	#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
		98	#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
		99	#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
		100	#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
		101	#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
		102	#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
		103	#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
		104	#define R200_EMIT_VAP_CTL 32 /* vap/1 */
		105	#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
		106	#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
		107	#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
		108	#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
		109	#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
		110	#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
		111	#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
		112	#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
		113	#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
		114	#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
		115	#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
		116	#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
		117	#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
		118	#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
		119	#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
		120	#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
		121	#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
		122	#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
		123	#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
		124	#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
		125	#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
		126	#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
		127	#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
		128	#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
		129	#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
		130	#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
		131	#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
		132	#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
		133	#define R200_EMIT_PP_CUBIC_FACES_0 61
		134	#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
		135	#define R200_EMIT_PP_CUBIC_FACES_1 63
		136	#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
		137	#define R200_EMIT_PP_CUBIC_FACES_2 65
		138	#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
		139	#define R200_EMIT_PP_CUBIC_FACES_3 67
		140	#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
		141	#define R200_EMIT_PP_CUBIC_FACES_4 69
		142	#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
		143	#define R200_EMIT_PP_CUBIC_FACES_5 71
		144	#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
		145	#define RADEON_EMIT_PP_TEX_SIZE_0 73
		146	#define RADEON_EMIT_PP_TEX_SIZE_1 74
		147	#define RADEON_EMIT_PP_TEX_SIZE_2 75
		148	#define R200_EMIT_RB3D_BLENDCOLOR 76
		149	#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
		150	#define RADEON_EMIT_PP_CUBIC_FACES_0 78
		151	#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
		152	#define RADEON_EMIT_PP_CUBIC_FACES_1 80
		153	#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
		154	#define RADEON_EMIT_PP_CUBIC_FACES_2 82
		155	#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
		156	#define R200_EMIT_PP_TRI_PERF_CNTL 84
		157	#define R200_EMIT_PP_AFS_0 85
		158	#define R200_EMIT_PP_AFS_1 86
		159	#define R200_EMIT_ATF_TFACTOR 87
		160	#define R200_EMIT_PP_TXCTLALL_0 88
		161	#define R200_EMIT_PP_TXCTLALL_1 89
		162	#define R200_EMIT_PP_TXCTLALL_2 90
		163	#define R200_EMIT_PP_TXCTLALL_3 91
		164	#define R200_EMIT_PP_TXCTLALL_4 92
		165	#define R200_EMIT_PP_TXCTLALL_5 93
		166	#define R200_EMIT_VAP_PVS_CNTL 94
		167	#define RADEON_MAX_STATE_PACKETS 95
		168
		169	/* Commands understood by cmd_buffer ioctl. More can be added but
		170	* obviously these can't be removed or changed:
		171	*/
		172	#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
		173	#define RADEON_CMD_SCALARS 2 /* emit scalar data */
		174	#define RADEON_CMD_VECTORS 3 /* emit vector data */
		175	#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
		176	#define RADEON_CMD_PACKET3 5 /* emit hw packet */
		177	#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
		178	#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
		179	#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
		180	* doesn't make the cpu wait, just
		181	* the graphics hardware */
		182	#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
		183
		184	typedef union {
		185	int i;
		186	struct {
		187	unsigned char cmd_type, pad0, pad1, pad2;
		188	} header;
		189	struct {
		190	unsigned char cmd_type, packet_id, pad0, pad1;
		191	} packet;
		192	struct {
		193	unsigned char cmd_type, offset, stride, count;
		194	} scalars;
		195	struct {
		196	unsigned char cmd_type, offset, stride, count;
		197	} vectors;
		198	struct {
		199	unsigned char cmd_type, addr_lo, addr_hi, count;
		200	} veclinear;
		201	struct {
		202	unsigned char cmd_type, buf_idx, pad0, pad1;
		203	} dma;
		204	struct {
		205	unsigned char cmd_type, flags, pad0, pad1;
		206	} wait;
		207	} drm_radeon_cmd_header_t;
		208
		209	#define RADEON_WAIT_2D 0x1
		210	#define RADEON_WAIT_3D 0x2
		211
		212	/* Allowed parameters for R300_CMD_PACKET3
		213	*/
		214	#define R300_CMD_PACKET3_CLEAR 0
		215	#define R300_CMD_PACKET3_RAW 1
		216
		217	/* Commands understood by cmd_buffer ioctl for R300.
		218	* The interface has not been stabilized, so some of these may be removed
		219	* and eventually reordered before stabilization.
		220	*/
		221	#define R300_CMD_PACKET0 1
		222	#define R300_CMD_VPU 2 /* emit vertex program upload */
		223	#define R300_CMD_PACKET3 3 /* emit a packet3 */
		224	#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
		225	#define R300_CMD_CP_DELAY 5
		226	#define R300_CMD_DMA_DISCARD 6
		227	#define R300_CMD_WAIT 7
		228	# define R300_WAIT_2D 0x1
		229	# define R300_WAIT_3D 0x2
		230	/* these two defines are DOING IT WRONG - however
		231	* we have userspace which relies on using these.
		232	* The wait interface is backwards compat new
		233	* code should use the NEW_WAIT defines below
		234	* THESE ARE NOT BIT FIELDS
		235	*/
		236	# define R300_WAIT_2D_CLEAN 0x3
		237	# define R300_WAIT_3D_CLEAN 0x4
		238
		239	# define R300_NEW_WAIT_2D_3D 0x3
		240	# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
		241	# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
		242	# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
		243
		244	#define R300_CMD_SCRATCH 8
		245	#define R300_CMD_R500FP 9
		246
		247	typedef union {
		248	unsigned int u;
		249	struct {
		250	unsigned char cmd_type, pad0, pad1, pad2;
		251	} header;
		252	struct {
		253	unsigned char cmd_type, count, reglo, reghi;
		254	} packet0;
		255	struct {
		256	unsigned char cmd_type, count, adrlo, adrhi;
		257	} vpu;
		258	struct {
		259	unsigned char cmd_type, packet, pad0, pad1;
		260	} packet3;
		261	struct {
		262	unsigned char cmd_type, packet;
		263	unsigned short count; /* amount of packet2 to emit */
		264	} delay;
		265	struct {
		266	unsigned char cmd_type, buf_idx, pad0, pad1;
		267	} dma;
		268	struct {
		269	unsigned char cmd_type, flags, pad0, pad1;
		270	} wait;
		271	struct {
		272	unsigned char cmd_type, reg, n_bufs, flags;
		273	} scratch;
		274	struct {
		275	unsigned char cmd_type, count, adrlo, adrhi_flags;
		276	} r500fp;
		277	} drm_r300_cmd_header_t;
		278
		279	#define RADEON_FRONT 0x1
		280	#define RADEON_BACK 0x2
		281	#define RADEON_DEPTH 0x4
		282	#define RADEON_STENCIL 0x8
		283	#define RADEON_CLEAR_FASTZ 0x80000000
		284	#define RADEON_USE_HIERZ 0x40000000
		285	#define RADEON_USE_COMP_ZBUF 0x20000000
		286
		287	#define R500FP_CONSTANT_TYPE (1 << 1)
		288	#define R500FP_CONSTANT_CLAMP (1 << 2)
		289
		290	/* Primitive types
		291	*/
		292	#define RADEON_POINTS 0x1
		293	#define RADEON_LINES 0x2
		294	#define RADEON_LINE_STRIP 0x3
		295	#define RADEON_TRIANGLES 0x4
		296	#define RADEON_TRIANGLE_FAN 0x5
		297	#define RADEON_TRIANGLE_STRIP 0x6
		298
		299	/* Vertex/indirect buffer size
		300	*/
		301	#define RADEON_BUFFER_SIZE 65536
		302
		303	/* Byte offsets for indirect buffer data
		304	*/
		305	#define RADEON_INDEX_PRIM_OFFSET 20
		306
		307	#define RADEON_SCRATCH_REG_OFFSET 32
		308
		309	#define R600_SCRATCH_REG_OFFSET 256
		310
		311	#define RADEON_NR_SAREA_CLIPRECTS 12
		312
		313	/* There are 2 heaps (local/GART). Each region within a heap is a
		314	* minimum of 64k, and there are at most 64 of them per heap.
		315	*/
		316	#define RADEON_LOCAL_TEX_HEAP 0
		317	#define RADEON_GART_TEX_HEAP 1
		318	#define RADEON_NR_TEX_HEAPS 2
		319	#define RADEON_NR_TEX_REGIONS 64
		320	#define RADEON_LOG_TEX_GRANULARITY 16
		321
		322	#define RADEON_MAX_TEXTURE_LEVELS 12
		323	#define RADEON_MAX_TEXTURE_UNITS 3
		324
		325	#define RADEON_MAX_SURFACES 8
		326
		327	/* Blits have strict offset rules. All blit offset must be aligned on
		328	* a 1K-byte boundary.
		329	*/
		330	#define RADEON_OFFSET_SHIFT 10
		331	#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
		332	#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
		333
		334	#endif /* __RADEON_SAREA_DEFINES__ */
		335
		336	typedef struct {
		337	unsigned int red;
		338	unsigned int green;
		339	unsigned int blue;
		340	unsigned int alpha;
		341	} radeon_color_regs_t;
		342
		343	typedef struct {
		344	/* Context state */
		345	unsigned int pp_misc; /* 0x1c14 */
		346	unsigned int pp_fog_color;
		347	unsigned int re_solid_color;
		348	unsigned int rb3d_blendcntl;
		349	unsigned int rb3d_depthoffset;
		350	unsigned int rb3d_depthpitch;
		351	unsigned int rb3d_zstencilcntl;
		352
		353	unsigned int pp_cntl; /* 0x1c38 */
		354	unsigned int rb3d_cntl;
		355	unsigned int rb3d_coloroffset;
		356	unsigned int re_width_height;
		357	unsigned int rb3d_colorpitch;
		358	unsigned int se_cntl;
		359
		360	/* Vertex format state */
		361	unsigned int se_coord_fmt; /* 0x1c50 */
		362
		363	/* Line state */
		364	unsigned int re_line_pattern; /* 0x1cd0 */
		365	unsigned int re_line_state;
		366
		367	unsigned int se_line_width; /* 0x1db8 */
		368
		369	/* Bumpmap state */
		370	unsigned int pp_lum_matrix; /* 0x1d00 */
		371
		372	unsigned int pp_rot_matrix_0; /* 0x1d58 */
		373	unsigned int pp_rot_matrix_1;
		374
		375	/* Mask state */
		376	unsigned int rb3d_stencilrefmask; /* 0x1d7c */
		377	unsigned int rb3d_ropcntl;
		378	unsigned int rb3d_planemask;
		379
		380	/* Viewport state */
		381	unsigned int se_vport_xscale; /* 0x1d98 */
		382	unsigned int se_vport_xoffset;
		383	unsigned int se_vport_yscale;
		384	unsigned int se_vport_yoffset;
		385	unsigned int se_vport_zscale;
		386	unsigned int se_vport_zoffset;
		387
		388	/* Setup state */
		389	unsigned int se_cntl_status; /* 0x2140 */
		390
		391	/* Misc state */
		392	unsigned int re_top_left; /* 0x26c0 */
		393	unsigned int re_misc;
		394	} drm_radeon_context_regs_t;
		395
		396	typedef struct {
		397	/* Zbias state */
		398	unsigned int se_zbias_factor; /* 0x1dac */
		399	unsigned int se_zbias_constant;
		400	} drm_radeon_context2_regs_t;
		401
		402	/* Setup registers for each texture unit
		403	*/
		404	typedef struct {
		405	unsigned int pp_txfilter;
		406	unsigned int pp_txformat;
		407	unsigned int pp_txoffset;
		408	unsigned int pp_txcblend;
		409	unsigned int pp_txablend;
		410	unsigned int pp_tfactor;
		411	unsigned int pp_border_color;
		412	} drm_radeon_texture_regs_t;
		413
		414	typedef struct {
		415	unsigned int start;
		416	unsigned int finish;
		417	unsigned int prim:8;
		418	unsigned int stateidx:8;
		419	unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
		420	unsigned int vc_format; /* vertex format */
		421	} drm_radeon_prim_t;
		422
		423	typedef struct {
		424	drm_radeon_context_regs_t context;
		425	drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
		426	drm_radeon_context2_regs_t context2;
		427	unsigned int dirty;
		428	} drm_radeon_state_t;
		429
		430	typedef struct {
		431	/* The channel for communication of state information to the
		432	* kernel on firing a vertex buffer with either of the
		433	* obsoleted vertex/index ioctls.
		434	*/
		435	drm_radeon_context_regs_t context_state;
		436	drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
		437	unsigned int dirty;
		438	unsigned int vertsize;
		439	unsigned int vc_format;
		440
		441	/* The current cliprects, or a subset thereof.
		442	*/
		443	struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
		444	unsigned int nbox;
		445
		446	/* Counters for client-side throttling of rendering clients.
		447	*/
		448	unsigned int last_frame;
		449	unsigned int last_dispatch;
		450	unsigned int last_clear;
		451
		452	struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
		453	1];
		454	unsigned int tex_age[RADEON_NR_TEX_HEAPS];
		455	int ctx_owner;
		456	int pfState; /* number of 3d windows (0,1,2ormore) */
		457	int pfCurrentPage; /* which buffer is being displayed? */
		458	int crtc2_base; /* CRTC2 frame offset */
		459	int tiling_enabled; /* set by drm, read by 2d + 3d clients */
		460	} drm_radeon_sarea_t;
		461
		462	/* WARNING: If you change any of these defines, make sure to change the
		463	* defines in the Xserver file (xf86drmRadeon.h)
		464	*
		465	* KW: actually it's illegal to change any of this (backwards compatibility).
		466	*/
		467
		468	/* Radeon specific ioctls
		469	* The device specific ioctl range is 0x40 to 0x79.
		470	*/
		471	#define DRM_RADEON_CP_INIT 0x00
		472	#define DRM_RADEON_CP_START 0x01
		473	#define DRM_RADEON_CP_STOP 0x02
		474	#define DRM_RADEON_CP_RESET 0x03
		475	#define DRM_RADEON_CP_IDLE 0x04
		476	#define DRM_RADEON_RESET 0x05
		477	#define DRM_RADEON_FULLSCREEN 0x06
		478	#define DRM_RADEON_SWAP 0x07
		479	#define DRM_RADEON_CLEAR 0x08
		480	#define DRM_RADEON_VERTEX 0x09
		481	#define DRM_RADEON_INDICES 0x0A
		482	#define DRM_RADEON_NOT_USED
		483	#define DRM_RADEON_STIPPLE 0x0C
		484	#define DRM_RADEON_INDIRECT 0x0D
		485	#define DRM_RADEON_TEXTURE 0x0E
		486	#define DRM_RADEON_VERTEX2 0x0F
		487	#define DRM_RADEON_CMDBUF 0x10
		488	#define DRM_RADEON_GETPARAM 0x11
		489	#define DRM_RADEON_FLIP 0x12
		490	#define DRM_RADEON_ALLOC 0x13
		491	#define DRM_RADEON_FREE 0x14
		492	#define DRM_RADEON_INIT_HEAP 0x15
		493	#define DRM_RADEON_IRQ_EMIT 0x16
		494	#define DRM_RADEON_IRQ_WAIT 0x17
		495	#define DRM_RADEON_CP_RESUME 0x18
		496	#define DRM_RADEON_SETPARAM 0x19
		497	#define DRM_RADEON_SURF_ALLOC 0x1a
		498	#define DRM_RADEON_SURF_FREE 0x1b
		499	/* KMS ioctl */
		500	#define DRM_RADEON_GEM_INFO 0x1c
		501	#define DRM_RADEON_GEM_CREATE 0x1d
		502	#define DRM_RADEON_GEM_MMAP 0x1e
		503	#define DRM_RADEON_GEM_PREAD 0x21
		504	#define DRM_RADEON_GEM_PWRITE 0x22
		505	#define DRM_RADEON_GEM_SET_DOMAIN 0x23
		506	#define DRM_RADEON_GEM_WAIT_IDLE 0x24
		507	#define DRM_RADEON_CS 0x26
		508	#define DRM_RADEON_INFO 0x27
		509	#define DRM_RADEON_GEM_SET_TILING 0x28
		510	#define DRM_RADEON_GEM_GET_TILING 0x29
		511	#define DRM_RADEON_GEM_BUSY 0x2a
		512	#define DRM_RADEON_GEM_VA 0x2b
		513	#define DRM_RADEON_GEM_OP 0x2c
		514
		515	#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
		516	#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
		517	#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
		518	#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
		519	#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
		520	#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
		521	#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
		522	#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
		523	#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
		524	#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
		525	#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
		526	#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
		527	#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
		528	#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
		529	#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
		530	#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
		531	#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
		532	#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
		533	#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
		534	#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
		535	#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
		536	#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
		537	#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
		538	#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
		539	#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
		540	#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
		541	#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
		542	/* KMS */
		543	#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
		544	#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
		545	#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
		546	#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
		547	#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
		548	#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
		549	#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
		550	#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
		551	#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
		552	#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
		553	#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
		554	#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
		555	#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
		556	#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
		557
		558	typedef struct drm_radeon_init {
		559	enum {
		560	RADEON_INIT_CP = 0x01,
		561	RADEON_CLEANUP_CP = 0x02,
		562	RADEON_INIT_R200_CP = 0x03,
		563	RADEON_INIT_R300_CP = 0x04,
		564	RADEON_INIT_R600_CP = 0x05
		565	} func;
		566	unsigned long sarea_priv_offset;
		567	int is_pci;
		568	int cp_mode;
		569	int gart_size;
		570	int ring_size;
		571	int usec_timeout;
		572
		573	unsigned int fb_bpp;
		574	unsigned int front_offset, front_pitch;
		575	unsigned int back_offset, back_pitch;
		576	unsigned int depth_bpp;
		577	unsigned int depth_offset, depth_pitch;
		578
		579	unsigned long fb_offset;
		580	unsigned long mmio_offset;
		581	unsigned long ring_offset;
		582	unsigned long ring_rptr_offset;
		583	unsigned long buffers_offset;
		584	unsigned long gart_textures_offset;
		585	} drm_radeon_init_t;
		586
		587	typedef struct drm_radeon_cp_stop {
		588	int flush;
		589	int idle;
		590	} drm_radeon_cp_stop_t;
		591
		592	typedef struct drm_radeon_fullscreen {
		593	enum {
		594	RADEON_INIT_FULLSCREEN = 0x01,
		595	RADEON_CLEANUP_FULLSCREEN = 0x02
		596	} func;
		597	} drm_radeon_fullscreen_t;
		598
		599	#define CLEAR_X1 0
		600	#define CLEAR_Y1 1
		601	#define CLEAR_X2 2
		602	#define CLEAR_Y2 3
		603	#define CLEAR_DEPTH 4
		604
		605	typedef union drm_radeon_clear_rect {
		606	float f[5];
		607	unsigned int ui[5];
		608	} drm_radeon_clear_rect_t;
		609
		610	typedef struct drm_radeon_clear {
		611	unsigned int flags;
		612	unsigned int clear_color;
		613	unsigned int clear_depth;
		614	unsigned int color_mask;
		615	unsigned int depth_mask; /* misnamed field: should be stencil */
		616	drm_radeon_clear_rect_t __user *depth_boxes;
		617	} drm_radeon_clear_t;
		618
		619	typedef struct drm_radeon_vertex {
		620	int prim;
		621	int idx; /* Index of vertex buffer */
		622	int count; /* Number of vertices in buffer */
		623	int discard; /* Client finished with buffer? */
		624	} drm_radeon_vertex_t;
		625
		626	typedef struct drm_radeon_indices {
		627	int prim;
		628	int idx;
		629	int start;
		630	int end;
		631	int discard; /* Client finished with buffer? */
		632	} drm_radeon_indices_t;
		633
		634	/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
		635	* - allows multiple primitives and state changes in a single ioctl
		636	* - supports driver change to emit native primitives
		637	*/
		638	typedef struct drm_radeon_vertex2 {
		639	int idx; /* Index of vertex buffer */
		640	int discard; /* Client finished with buffer? */
		641	int nr_states;
		642	drm_radeon_state_t __user *state;
		643	int nr_prims;
		644	drm_radeon_prim_t __user *prim;
		645	} drm_radeon_vertex2_t;
		646
		647	/* v1.3 - obsoletes drm_radeon_vertex2
		648	* - allows arbitrarily large cliprect list
		649	* - allows updating of tcl packet, vector and scalar state
		650	* - allows memory-efficient description of state updates
		651	* - allows state to be emitted without a primitive
		652	* (for clears, ctx switches)
		653	* - allows more than one dma buffer to be referenced per ioctl
		654	* - supports tcl driver
		655	* - may be extended in future versions with new cmd types, packets
		656	*/
		657	typedef struct drm_radeon_cmd_buffer {
		658	int bufsz;
		659	char __user *buf;
		660	int nbox;
		661	struct drm_clip_rect __user *boxes;
		662	} drm_radeon_cmd_buffer_t;
		663
		664	typedef struct drm_radeon_tex_image {
		665	unsigned int x, y; /* Blit coordinates */
		666	unsigned int width, height;
		667	const void __user *data;
		668	} drm_radeon_tex_image_t;
		669
		670	typedef struct drm_radeon_texture {
		671	unsigned int offset;
		672	int pitch;
		673	int format;
		674	int width; /* Texture image coordinates */
		675	int height;
		676	drm_radeon_tex_image_t __user *image;
		677	} drm_radeon_texture_t;
		678
		679	typedef struct drm_radeon_stipple {
		680	unsigned int __user *mask;
		681	} drm_radeon_stipple_t;
		682
		683	typedef struct drm_radeon_indirect {
		684	int idx;
		685	int start;
		686	int end;
		687	int discard;
		688	} drm_radeon_indirect_t;
		689
		690	/* enum for card type parameters */
		691	#define RADEON_CARD_PCI 0
		692	#define RADEON_CARD_AGP 1
		693	#define RADEON_CARD_PCIE 2
		694
		695	/* 1.3: An ioctl to get parameters that aren't available to the 3d
		696	* client any other way.
		697	*/
		698	#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
		699	#define RADEON_PARAM_LAST_FRAME 2
		700	#define RADEON_PARAM_LAST_DISPATCH 3
		701	#define RADEON_PARAM_LAST_CLEAR 4
		702	/* Added with DRM version 1.6. */
		703	#define RADEON_PARAM_IRQ_NR 5
		704	#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
		705	/* Added with DRM version 1.8. */
		706	#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
		707	#define RADEON_PARAM_STATUS_HANDLE 8
		708	#define RADEON_PARAM_SAREA_HANDLE 9
		709	#define RADEON_PARAM_GART_TEX_HANDLE 10
		710	#define RADEON_PARAM_SCRATCH_OFFSET 11
		711	#define RADEON_PARAM_CARD_TYPE 12
		712	#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
		713	#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
		714	#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
		715	#define RADEON_PARAM_DEVICE_ID 16
		716	#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
		717
		718	typedef struct drm_radeon_getparam {
		719	int param;
		720	void __user *value;
		721	} drm_radeon_getparam_t;
		722
		723	/* 1.6: Set up a memory manager for regions of shared memory:
		724	*/
		725	#define RADEON_MEM_REGION_GART 1
		726	#define RADEON_MEM_REGION_FB 2
		727
		728	typedef struct drm_radeon_mem_alloc {
		729	int region;
		730	int alignment;
		731	int size;
		732	int __user region_offset; / offset from start of fb or GART */
		733	} drm_radeon_mem_alloc_t;
		734
		735	typedef struct drm_radeon_mem_free {
		736	int region;
		737	int region_offset;
		738	} drm_radeon_mem_free_t;
		739
		740	typedef struct drm_radeon_mem_init_heap {
		741	int region;
		742	int size;
		743	int start;
		744	} drm_radeon_mem_init_heap_t;
		745
		746	/* 1.6: Userspace can request & wait on irq's:
		747	*/
		748	typedef struct drm_radeon_irq_emit {
		749	int __user *irq_seq;
		750	} drm_radeon_irq_emit_t;
		751
		752	typedef struct drm_radeon_irq_wait {
		753	int irq_seq;
		754	} drm_radeon_irq_wait_t;
		755
		756	/* 1.10: Clients tell the DRM where they think the framebuffer is located in
		757	* the card's address space, via a new generic ioctl to set parameters
		758	*/
		759
		760	typedef struct drm_radeon_setparam {
		761	unsigned int param;
		762	__s64 value;
		763	} drm_radeon_setparam_t;
		764
		765	#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
		766	#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
		767	#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
		768	#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
		769	#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
		770	#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
		771	/* 1.14: Clients can allocate/free a surface
		772	*/
		773	typedef struct drm_radeon_surface_alloc {
		774	unsigned int address;
		775	unsigned int size;
		776	unsigned int flags;
		777	} drm_radeon_surface_alloc_t;
		778
		779	typedef struct drm_radeon_surface_free {
		780	unsigned int address;
		781	} drm_radeon_surface_free_t;
		782
		783	#define DRM_RADEON_VBLANK_CRTC1 1
		784	#define DRM_RADEON_VBLANK_CRTC2 2
		785
		786	/*
		787	* Kernel modesetting world below.
		788	*/
		789	#define RADEON_GEM_DOMAIN_CPU 0x1
		790	#define RADEON_GEM_DOMAIN_GTT 0x2
		791	#define RADEON_GEM_DOMAIN_VRAM 0x4
		792
		793	struct drm_radeon_gem_info {
		794	uint64_t gart_size;
		795	uint64_t vram_size;
		796	uint64_t vram_visible;
		797	};
		798
		799	#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
		800	#define RADEON_GEM_GTT_UC (1 << 1)
		801	#define RADEON_GEM_GTT_WC (1 << 2)
		802
		803	struct drm_radeon_gem_create {
		804	uint64_t size;
		805	uint64_t alignment;
		806	uint32_t handle;
		807	uint32_t initial_domain;
		808	uint32_t flags;
		809	};
		810
		811	#define RADEON_TILING_MACRO 0x1
		812	#define RADEON_TILING_MICRO 0x2
		813	#define RADEON_TILING_SWAP_16BIT 0x4
		814	#define RADEON_TILING_SWAP_32BIT 0x8
		815	/* this object requires a surface when mapped - i.e. front buffer */
		816	#define RADEON_TILING_SURFACE 0x10
		817	#define RADEON_TILING_MICRO_SQUARE 0x20
		818	#define RADEON_TILING_EG_BANKW_SHIFT 8
		819	#define RADEON_TILING_EG_BANKW_MASK 0xf
		820	#define RADEON_TILING_EG_BANKH_SHIFT 12
		821	#define RADEON_TILING_EG_BANKH_MASK 0xf
		822	#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
		823	#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
		824	#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
		825	#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
		826	#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
		827	#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
		828
		829	struct drm_radeon_gem_set_tiling {
		830	uint32_t handle;
		831	uint32_t tiling_flags;
		832	uint32_t pitch;
		833	};
		834
		835	struct drm_radeon_gem_get_tiling {
		836	uint32_t handle;
		837	uint32_t tiling_flags;
		838	uint32_t pitch;
		839	};
		840
		841	struct drm_radeon_gem_mmap {
		842	uint32_t handle;
		843	uint32_t pad;
		844	uint64_t offset;
		845	uint64_t size;
		846	uint64_t addr_ptr;
		847	};
		848
		849	struct drm_radeon_gem_set_domain {
		850	uint32_t handle;
		851	uint32_t read_domains;
		852	uint32_t write_domain;
		853	};
		854
		855	struct drm_radeon_gem_wait_idle {
		856	uint32_t handle;
		857	uint32_t pad;
		858	};
		859
		860	struct drm_radeon_gem_busy {
		861	uint32_t handle;
		862	uint32_t domain;
		863	};
		864
		865	struct drm_radeon_gem_pread {
		866	/** Handle for the object being read. */
		867	uint32_t handle;
		868	uint32_t pad;
		869	/** Offset into the object to read from */
		870	uint64_t offset;
		871	/** Length of data to read */
		872	uint64_t size;
		873	/** Pointer to write the data into. */
		874	/* void , but pointers are not 32/64 compatible /
		875	uint64_t data_ptr;
		876	};
		877
		878	struct drm_radeon_gem_pwrite {
		879	/** Handle for the object being written to. */
		880	uint32_t handle;
		881	uint32_t pad;
		882	/** Offset into the object to write to */
		883	uint64_t offset;
		884	/** Length of data to write */
		885	uint64_t size;
		886	/** Pointer to read the data from. */
		887	/* void , but pointers are not 32/64 compatible /
		888	uint64_t data_ptr;
		889	};
		890
		891	/* Sets or returns a value associated with a buffer. */
		892	struct drm_radeon_gem_op {
		893	uint32_t handle; /* buffer */
		894	uint32_t op; /* RADEON_GEM_OP_* */
		895	uint64_t value; /* input or return value */
		896	};
		897
		898	#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
		899	#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
		900
		901	#define RADEON_VA_MAP 1
		902	#define RADEON_VA_UNMAP 2
		903
		904	#define RADEON_VA_RESULT_OK 0
		905	#define RADEON_VA_RESULT_ERROR 1
		906	#define RADEON_VA_RESULT_VA_EXIST 2
		907
		908	#define RADEON_VM_PAGE_VALID (1 << 0)
		909	#define RADEON_VM_PAGE_READABLE (1 << 1)
		910	#define RADEON_VM_PAGE_WRITEABLE (1 << 2)
		911	#define RADEON_VM_PAGE_SYSTEM (1 << 3)
		912	#define RADEON_VM_PAGE_SNOOPED (1 << 4)
		913
		914	struct drm_radeon_gem_va {
		915	uint32_t handle;
		916	uint32_t operation;
		917	uint32_t vm_id;
		918	uint32_t flags;
		919	uint64_t offset;
		920	};
		921
		922	#define RADEON_CHUNK_ID_RELOCS 0x01
		923	#define RADEON_CHUNK_ID_IB 0x02
		924	#define RADEON_CHUNK_ID_FLAGS 0x03
		925	#define RADEON_CHUNK_ID_CONST_IB 0x04
		926
		927	/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
		928	#define RADEON_CS_KEEP_TILING_FLAGS 0x01
		929	#define RADEON_CS_USE_VM 0x02
		930	#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */
		931	/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
		932	#define RADEON_CS_RING_GFX 0
		933	#define RADEON_CS_RING_COMPUTE 1
		934	#define RADEON_CS_RING_DMA 2
		935	#define RADEON_CS_RING_UVD 3
		936	#define RADEON_CS_RING_VCE 4
		937	/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
		938	/* 0 = normal, + = higher priority, - = lower priority */
		939
		940	struct drm_radeon_cs_chunk {
		941	uint32_t chunk_id;
		942	uint32_t length_dw;
		943	uint64_t chunk_data;
		944	};
		945
		946	/* drm_radeon_cs_reloc.flags */
5178	serge	947	#define RADEON_RELOC_PRIO_MASK (0xf << 0)
5056	serge	948
		949	struct drm_radeon_cs_reloc {
		950	uint32_t handle;
		951	uint32_t read_domains;
		952	uint32_t write_domain;
		953	uint32_t flags;
		954	};
		955
		956	struct drm_radeon_cs {
		957	uint32_t num_chunks;
		958	uint32_t cs_id;
		959	/* this points to uint64_t * which point to cs chunks */
		960	uint64_t chunks;
		961	/* updates to the limits after this CS ioctl */
		962	uint64_t gart_limit;
		963	uint64_t vram_limit;
		964	};
		965
		966	#define RADEON_INFO_DEVICE_ID 0x00
		967	#define RADEON_INFO_NUM_GB_PIPES 0x01
		968	#define RADEON_INFO_NUM_Z_PIPES 0x02
		969	#define RADEON_INFO_ACCEL_WORKING 0x03
		970	#define RADEON_INFO_CRTC_FROM_ID 0x04
		971	#define RADEON_INFO_ACCEL_WORKING2 0x05
		972	#define RADEON_INFO_TILING_CONFIG 0x06
		973	#define RADEON_INFO_WANT_HYPERZ 0x07
		974	#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */
		975	#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
		976	#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
		977	#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
		978	#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
		979	#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */
		980	/* virtual address start, va < start are reserved by the kernel */
		981	#define RADEON_INFO_VA_START 0x0e
		982	/* maximum size of ib using the virtual memory cs */
		983	#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
		984	/* max pipes - needed for compute shaders */
		985	#define RADEON_INFO_MAX_PIPES 0x10
		986	/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
		987	#define RADEON_INFO_TIMESTAMP 0x11
		988	/* max shader engines (SE) - needed for geometry shaders, etc. */
		989	#define RADEON_INFO_MAX_SE 0x12
		990	/* max SH per SE */
		991	#define RADEON_INFO_MAX_SH_PER_SE 0x13
		992	/* fast fb access is enabled */
		993	#define RADEON_INFO_FASTFB_WORKING 0x14
		994	/* query if a RADEON_CS_RING_* submission is supported */
		995	#define RADEON_INFO_RING_WORKING 0x15
		996	/* SI tile mode array */
		997	#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
		998	/* query if CP DMA is supported on the compute ring */
		999	#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
		1000	/* CIK macrotile mode array */
		1001	#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
		1002	/* query the number of render backends */
		1003	#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
		1004	/* max engine clock - needed for OpenCL */
		1005	#define RADEON_INFO_MAX_SCLK 0x1a
		1006	/* version of VCE firmware */
		1007	#define RADEON_INFO_VCE_FW_VERSION 0x1b
		1008	/* version of VCE feedback */
		1009	#define RADEON_INFO_VCE_FB_VERSION 0x1c
		1010	#define RADEON_INFO_NUM_BYTES_MOVED 0x1d
		1011	#define RADEON_INFO_VRAM_USAGE 0x1e
		1012	#define RADEON_INFO_GTT_USAGE 0x1f
		1013	#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
		1014
		1015	struct drm_radeon_info {
		1016	uint32_t request;
		1017	uint32_t pad;
		1018	uint64_t value;
		1019	};
		1020
		1021	/* Those correspond to the tile index to use, this is to explicitly state
		1022	* the API that is implicitly defined by the tile mode array.
		1023	*/
		1024	#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
		1025	#define SI_TILE_MODE_COLOR_1D 13
		1026	#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
		1027	#define SI_TILE_MODE_COLOR_2D_8BPP 14
		1028	#define SI_TILE_MODE_COLOR_2D_16BPP 15
		1029	#define SI_TILE_MODE_COLOR_2D_32BPP 16
		1030	#define SI_TILE_MODE_COLOR_2D_64BPP 17
		1031	#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
		1032	#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
		1033	#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
		1034	#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
		1035	#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
		1036	#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
		1037	#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
		1038
		1039	#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
		1040
		1041	#endif

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(root)/drivers/include/linux/uapi/drm/radeon_drm.h – Rev 5178