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Rev | Author | Line No. | Line |
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1628 | serge | 1 | /* |
2 | * pci_regs.h |
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3 | * |
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4 | * PCI standard defines |
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5 | * Copyright 1994, Drew Eckhardt |
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6 | * Copyright 1997--1999 Martin Mares |
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7 | * |
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8 | * For more information, please consult the following manuals (look at |
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9 | * http://www.pcisig.com/ for how to get them): |
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10 | * |
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11 | * PCI BIOS Specification |
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12 | * PCI Local Bus Specification |
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13 | * PCI to PCI Bridge Specification |
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14 | * PCI System Design Guide |
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15 | * |
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16 | * For hypertransport information, please consult the following manuals |
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17 | * from http://www.hypertransport.org |
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18 | * |
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19 | * The Hypertransport I/O Link Specification |
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20 | */ |
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21 | |||
22 | #ifndef LINUX_PCI_REGS_H |
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23 | #define LINUX_PCI_REGS_H |
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24 | |||
25 | /* |
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26 | * Under PCI, each device has 256 bytes of configuration address space, |
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27 | * of which the first 64 bytes are standardized as follows: |
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28 | */ |
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29 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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30 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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31 | #define PCI_COMMAND 0x04 /* 16 bits */ |
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32 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
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33 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
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34 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ |
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35 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ |
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36 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
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37 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
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38 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
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39 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
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40 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
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41 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
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42 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
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43 | |||
44 | #define PCI_STATUS 0x06 /* 16 bits */ |
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45 | #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ |
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46 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
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47 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
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48 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
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49 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
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50 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
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51 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
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52 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
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53 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
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54 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
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55 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
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56 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
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57 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
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58 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
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59 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
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60 | |||
61 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
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62 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
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63 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
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64 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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65 | |||
66 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
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67 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
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68 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
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69 | #define PCI_HEADER_TYPE_NORMAL 0 |
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70 | #define PCI_HEADER_TYPE_BRIDGE 1 |
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71 | #define PCI_HEADER_TYPE_CARDBUS 2 |
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72 | |||
73 | #define PCI_BIST 0x0f /* 8 bits */ |
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74 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
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75 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
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76 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
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77 | |||
78 | /* |
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79 | * Base addresses specify locations in memory or I/O space. |
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80 | * Decoded size can be determined by writing a value of |
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81 | * 0xffffffff to the register, and reading it back. Only |
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82 | * 1 bits are decoded. |
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83 | */ |
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84 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
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85 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
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86 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
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87 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
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88 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
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89 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
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90 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
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91 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
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92 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
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93 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
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94 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
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95 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
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96 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
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97 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
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98 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) |
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99 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) |
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100 | /* bit 1 is reserved if address_space = 1 */ |
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101 | |||
102 | /* Header type 0 (normal devices) */ |
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103 | #define PCI_CARDBUS_CIS 0x28 |
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104 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
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105 | #define PCI_SUBSYSTEM_ID 0x2e |
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106 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
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107 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
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108 | #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
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109 | |||
110 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
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111 | |||
112 | /* 0x35-0x3b are reserved */ |
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113 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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114 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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115 | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
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116 | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
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117 | |||
118 | /* Header type 1 (PCI-to-PCI bridges) */ |
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119 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
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120 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
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121 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
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122 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ |
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123 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
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124 | #define PCI_IO_LIMIT 0x1d |
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125 | #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ |
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126 | #define PCI_IO_RANGE_TYPE_16 0x00 |
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127 | #define PCI_IO_RANGE_TYPE_32 0x01 |
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128 | #define PCI_IO_RANGE_MASK (~0x0fUL) |
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129 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
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130 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
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131 | #define PCI_MEMORY_LIMIT 0x22 |
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132 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL |
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133 | #define PCI_MEMORY_RANGE_MASK (~0x0fUL) |
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134 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ |
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135 | #define PCI_PREF_MEMORY_LIMIT 0x26 |
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136 | #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL |
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137 | #define PCI_PREF_RANGE_TYPE_32 0x00 |
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138 | #define PCI_PREF_RANGE_TYPE_64 0x01 |
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139 | #define PCI_PREF_RANGE_MASK (~0x0fUL) |
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140 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
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141 | #define PCI_PREF_LIMIT_UPPER32 0x2c |
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142 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
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143 | #define PCI_IO_LIMIT_UPPER16 0x32 |
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144 | /* 0x34 same as for htype 0 */ |
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145 | /* 0x35-0x3b is reserved */ |
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146 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
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147 | /* 0x3c-0x3d are same as for htype 0 */ |
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148 | #define PCI_BRIDGE_CONTROL 0x3e |
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149 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
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150 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
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151 | #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ |
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152 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
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153 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
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154 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
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155 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
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156 | |||
157 | /* Header type 2 (CardBus bridges) */ |
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158 | #define PCI_CB_CAPABILITY_LIST 0x14 |
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159 | /* 0x15 reserved */ |
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160 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ |
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161 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ |
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162 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ |
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163 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ |
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164 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ |
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165 | #define PCI_CB_MEMORY_BASE_0 0x1c |
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166 | #define PCI_CB_MEMORY_LIMIT_0 0x20 |
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167 | #define PCI_CB_MEMORY_BASE_1 0x24 |
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168 | #define PCI_CB_MEMORY_LIMIT_1 0x28 |
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169 | #define PCI_CB_IO_BASE_0 0x2c |
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170 | #define PCI_CB_IO_BASE_0_HI 0x2e |
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171 | #define PCI_CB_IO_LIMIT_0 0x30 |
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172 | #define PCI_CB_IO_LIMIT_0_HI 0x32 |
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173 | #define PCI_CB_IO_BASE_1 0x34 |
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174 | #define PCI_CB_IO_BASE_1_HI 0x36 |
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175 | #define PCI_CB_IO_LIMIT_1 0x38 |
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176 | #define PCI_CB_IO_LIMIT_1_HI 0x3a |
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177 | #define PCI_CB_IO_RANGE_MASK (~0x03UL) |
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178 | /* 0x3c-0x3d are same as for htype 0 */ |
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179 | #define PCI_CB_BRIDGE_CONTROL 0x3e |
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180 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ |
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181 | #define PCI_CB_BRIDGE_CTL_SERR 0x02 |
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182 | #define PCI_CB_BRIDGE_CTL_ISA 0x04 |
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183 | #define PCI_CB_BRIDGE_CTL_VGA 0x08 |
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184 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 |
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185 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ |
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186 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ |
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187 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ |
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188 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 |
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189 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 |
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190 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
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191 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
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192 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ |
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193 | /* 0x48-0x7f reserved */ |
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194 | |||
195 | /* Capability lists */ |
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196 | |||
197 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
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198 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
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199 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
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200 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
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201 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
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202 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
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203 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
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204 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
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205 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
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206 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ |
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207 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
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208 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
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209 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
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210 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
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211 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ |
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212 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
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213 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
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214 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
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215 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
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216 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
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217 | #define PCI_CAP_SIZEOF 4 |
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218 | |||
219 | /* Power Management Registers */ |
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220 | |||
221 | #define PCI_PM_PMC 2 /* PM Capabilities Register */ |
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222 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
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223 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
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224 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ |
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225 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
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226 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ |
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227 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
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228 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
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229 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
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230 | #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ |
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231 | #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ |
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232 | #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ |
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233 | #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ |
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234 | #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ |
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235 | #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ |
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236 | #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ |
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237 | #define PCI_PM_CTRL 4 /* PM control and status register */ |
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238 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
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239 | #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ |
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240 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
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241 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ |
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242 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |
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243 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ |
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244 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ |
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245 | #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ |
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246 | #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ |
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247 | #define PCI_PM_DATA_REGISTER 7 /* (??) */ |
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248 | #define PCI_PM_SIZEOF 8 |
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249 | |||
250 | /* AGP registers */ |
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251 | |||
252 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
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253 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
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254 | #define PCI_AGP_STATUS 4 /* Status register */ |
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255 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
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256 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
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257 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
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258 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
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259 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
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260 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
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261 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
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262 | #define PCI_AGP_COMMAND 8 /* Control register */ |
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263 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
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264 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
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265 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
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266 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
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267 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
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268 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
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269 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
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270 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
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271 | #define PCI_AGP_SIZEOF 12 |
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272 | |||
273 | /* Vital Product Data */ |
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274 | |||
275 | #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ |
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276 | #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ |
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277 | #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ |
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278 | #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ |
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279 | |||
280 | /* Slot Identification */ |
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281 | |||
282 | #define PCI_SID_ESR 2 /* Expansion Slot Register */ |
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283 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ |
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284 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ |
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285 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ |
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286 | |||
287 | /* Message Signalled Interrupts registers */ |
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288 | |||
289 | #define PCI_MSI_FLAGS 2 /* Various flags */ |
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290 | #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ |
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291 | #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ |
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292 | #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ |
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293 | #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ |
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294 | #define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */ |
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295 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
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296 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ |
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297 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
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298 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
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299 | #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
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300 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
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301 | #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
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302 | |||
303 | /* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ |
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304 | #define PCI_MSIX_FLAGS 2 |
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305 | #define PCI_MSIX_FLAGS_QSIZE 0x7FF |
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306 | #define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
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307 | #define PCI_MSIX_FLAGS_MASKALL (1 << 14) |
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308 | #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
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309 | |||
310 | /* CompactPCI Hotswap Register */ |
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311 | |||
312 | #define PCI_CHSWP_CSR 2 /* Control and Status Register */ |
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313 | #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ |
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314 | #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ |
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315 | #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ |
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316 | #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ |
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317 | #define PCI_CHSWP_PI 0x30 /* Programming Interface */ |
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318 | #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ |
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319 | #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ |
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320 | |||
321 | /* PCI Advanced Feature registers */ |
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322 | |||
323 | #define PCI_AF_LENGTH 2 |
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324 | #define PCI_AF_CAP 3 |
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325 | #define PCI_AF_CAP_TP 0x01 |
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326 | #define PCI_AF_CAP_FLR 0x02 |
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327 | #define PCI_AF_CTRL 4 |
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328 | #define PCI_AF_CTRL_FLR 0x01 |
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329 | #define PCI_AF_STATUS 5 |
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330 | #define PCI_AF_STATUS_TP 0x01 |
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331 | |||
332 | /* PCI-X registers */ |
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333 | |||
334 | #define PCI_X_CMD 2 /* Modes & Features */ |
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335 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
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336 | #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ |
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337 | #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ |
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338 | #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ |
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339 | #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ |
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340 | #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ |
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341 | #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ |
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342 | /* Max # of outstanding split transactions */ |
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343 | #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ |
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344 | #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ |
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345 | #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ |
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346 | #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ |
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347 | #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ |
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348 | #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ |
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349 | #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ |
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350 | #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ |
||
351 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
||
352 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
||
353 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ |
||
354 | #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ |
||
355 | #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ |
||
356 | #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ |
||
357 | #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ |
||
358 | #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ |
||
359 | #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ |
||
360 | #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ |
||
361 | #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ |
||
362 | #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ |
||
363 | #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ |
||
364 | #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
||
365 | #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
||
366 | #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
||
367 | |||
368 | /* PCI Bridge Subsystem ID registers */ |
||
369 | |||
370 | #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ |
||
371 | #define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */ |
||
372 | |||
373 | /* PCI Express capability registers */ |
||
374 | |||
375 | #define PCI_EXP_FLAGS 2 /* Capabilities register */ |
||
376 | #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ |
||
377 | #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ |
||
378 | #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ |
||
379 | #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ |
||
380 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ |
||
381 | #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ |
||
382 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ |
||
383 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ |
||
384 | #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ |
||
385 | #define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */ |
||
386 | #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
||
387 | #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ |
||
388 | #define PCI_EXP_DEVCAP 4 /* Device capabilities */ |
||
389 | #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ |
||
390 | #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ |
||
391 | #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ |
||
392 | #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
||
393 | #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
||
394 | #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
||
395 | #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
||
396 | #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
||
397 | #define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ |
||
398 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
||
399 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
||
400 | #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ |
||
401 | #define PCI_EXP_DEVCTL 8 /* Device Control */ |
||
402 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ |
||
403 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
||
404 | #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
||
405 | #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
||
406 | #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ |
||
407 | #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ |
||
408 | #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ |
||
409 | #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ |
||
410 | #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ |
||
411 | #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ |
||
412 | #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ |
||
413 | #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ |
||
414 | #define PCI_EXP_DEVSTA 10 /* Device Status */ |
||
415 | #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ |
||
416 | #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ |
||
417 | #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ |
||
418 | #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ |
||
419 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
||
420 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
||
421 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
||
422 | #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ |
||
423 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ |
||
424 | #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ |
||
425 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ |
||
426 | #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ |
||
427 | #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ |
||
428 | #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */ |
||
429 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
||
430 | #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ |
||
431 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |
||
432 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
||
433 | #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ |
||
434 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
||
435 | #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ |
||
436 | #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ |
||
437 | #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ |
||
438 | #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ |
||
439 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ |
||
440 | #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ |
||
441 | #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ |
||
442 | #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ |
||
443 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
||
444 | #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
||
445 | #define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ |
||
446 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ |
||
447 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ |
||
448 | #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ |
||
449 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
||
450 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
||
451 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
||
452 | #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ |
||
453 | #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ |
||
454 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
||
455 | #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
||
456 | #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ |
||
457 | #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ |
||
458 | #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ |
||
459 | #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ |
||
460 | #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ |
||
461 | #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ |
||
462 | #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ |
||
463 | #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ |
||
464 | #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ |
||
465 | #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ |
||
466 | #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ |
||
467 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
||
468 | #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ |
||
469 | #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ |
||
470 | #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ |
||
471 | #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ |
||
472 | #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ |
||
473 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ |
||
474 | #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ |
||
475 | #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ |
||
476 | #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ |
||
477 | #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ |
||
478 | #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ |
||
479 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |
||
480 | #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ |
||
481 | #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ |
||
482 | #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ |
||
483 | #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ |
||
484 | #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ |
||
485 | #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ |
||
486 | #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ |
||
487 | #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ |
||
488 | #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ |
||
489 | #define PCI_EXP_RTCTL 28 /* Root Control */ |
||
490 | #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ |
||
491 | #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ |
||
492 | #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
||
493 | #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
||
494 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
||
495 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
||
496 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
||
497 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
||
498 | #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
||
499 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
||
500 | #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ |
||
501 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
||
502 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
||
503 | |||
504 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
||
505 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |
||
506 | #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) |
||
507 | #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) |
||
508 | |||
509 | #define PCI_EXT_CAP_ID_ERR 1 |
||
510 | #define PCI_EXT_CAP_ID_VC 2 |
||
511 | #define PCI_EXT_CAP_ID_DSN 3 |
||
512 | #define PCI_EXT_CAP_ID_PWR 4 |
||
513 | #define PCI_EXT_CAP_ID_VNDR 11 |
||
514 | #define PCI_EXT_CAP_ID_ACS 13 |
||
515 | #define PCI_EXT_CAP_ID_ARI 14 |
||
516 | #define PCI_EXT_CAP_ID_ATS 15 |
||
517 | #define PCI_EXT_CAP_ID_SRIOV 16 |
||
518 | |||
519 | /* Advanced Error Reporting */ |
||
520 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
||
521 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
||
522 | #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
||
523 | #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
||
524 | #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ |
||
525 | #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ |
||
526 | #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ |
||
527 | #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ |
||
528 | #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ |
||
529 | #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ |
||
530 | #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ |
||
531 | #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ |
||
532 | #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
||
533 | /* Same bits as above */ |
||
534 | #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ |
||
535 | /* Same bits as above */ |
||
536 | #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ |
||
537 | #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ |
||
538 | #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ |
||
539 | #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
||
540 | #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ |
||
541 | #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ |
||
542 | #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
||
543 | /* Same bits as above */ |
||
544 | #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ |
||
545 | #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ |
||
546 | #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ |
||
547 | #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ |
||
548 | #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ |
||
549 | #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ |
||
550 | #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ |
||
551 | #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ |
||
552 | /* Correctable Err Reporting Enable */ |
||
553 | #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 |
||
554 | /* Non-fatal Err Reporting Enable */ |
||
555 | #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 |
||
556 | /* Fatal Err Reporting Enable */ |
||
557 | #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 |
||
558 | #define PCI_ERR_ROOT_STATUS 48 |
||
559 | #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ |
||
560 | /* Multi ERR_COR Received */ |
||
561 | #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 |
||
562 | /* ERR_FATAL/NONFATAL Recevied */ |
||
563 | #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 |
||
564 | /* Multi ERR_FATAL/NONFATAL Recevied */ |
||
565 | #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 |
||
566 | #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ |
||
567 | #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ |
||
568 | #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ |
||
569 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
||
570 | |||
571 | /* Virtual Channel */ |
||
572 | #define PCI_VC_PORT_REG1 4 |
||
573 | #define PCI_VC_PORT_REG2 8 |
||
574 | #define PCI_VC_PORT_CTRL 12 |
||
575 | #define PCI_VC_PORT_STATUS 14 |
||
576 | #define PCI_VC_RES_CAP 16 |
||
577 | #define PCI_VC_RES_CTRL 20 |
||
578 | #define PCI_VC_RES_STATUS 26 |
||
579 | |||
580 | /* Power Budgeting */ |
||
581 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
||
582 | #define PCI_PWR_DATA 8 /* Data Register */ |
||
583 | #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ |
||
584 | #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ |
||
585 | #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ |
||
586 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
||
587 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
||
588 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
||
589 | #define PCI_PWR_CAP 12 /* Capability */ |
||
590 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
||
591 | |||
592 | /* |
||
593 | * Hypertransport sub capability types |
||
594 | * |
||
595 | * Unfortunately there are both 3 bit and 5 bit capability types defined |
||
596 | * in the HT spec, catering for that is a little messy. You probably don't |
||
597 | * want to use these directly, just use pci_find_ht_capability() and it |
||
598 | * will do the right thing for you. |
||
599 | */ |
||
600 | #define HT_3BIT_CAP_MASK 0xE0 |
||
601 | #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ |
||
602 | #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ |
||
603 | |||
604 | #define HT_5BIT_CAP_MASK 0xF8 |
||
605 | #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ |
||
606 | #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ |
||
607 | #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ |
||
608 | #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ |
||
609 | #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ |
||
610 | #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ |
||
611 | #define HT_MSI_FLAGS 0x02 /* Offset to flags */ |
||
612 | #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ |
||
613 | #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ |
||
614 | #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ |
||
615 | #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ |
||
616 | #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ |
||
617 | #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ |
||
618 | #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ |
||
619 | #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ |
||
620 | #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ |
||
621 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ |
||
622 | #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ |
||
623 | |||
624 | /* Alternative Routing-ID Interpretation */ |
||
625 | #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ |
||
626 | #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ |
||
627 | #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ |
||
628 | #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ |
||
629 | #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ |
||
630 | #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ |
||
631 | #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ |
||
632 | #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ |
||
633 | |||
634 | /* Address Translation Service */ |
||
635 | #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ |
||
636 | #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ |
||
637 | #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ |
||
638 | #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ |
||
639 | #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ |
||
640 | #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ |
||
641 | #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ |
||
642 | |||
643 | /* Single Root I/O Virtualization */ |
||
644 | #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ |
||
645 | #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ |
||
646 | #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ |
||
647 | #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ |
||
648 | #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ |
||
649 | #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ |
||
650 | #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ |
||
651 | #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ |
||
652 | #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ |
||
653 | #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ |
||
654 | #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ |
||
655 | #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ |
||
656 | #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ |
||
657 | #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ |
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658 | #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ |
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659 | #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ |
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660 | #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ |
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661 | #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ |
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662 | #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ |
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663 | #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ |
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664 | #define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ |
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665 | #define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ |
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666 | #define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ |
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667 | #define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ |
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668 | #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ |
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669 | #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ |
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670 | #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ |
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671 | #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
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672 | #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
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673 | |||
674 | /* Access Control Service */ |
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675 | #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
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676 | #define PCI_ACS_SV 0x01 /* Source Validation */ |
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677 | #define PCI_ACS_TB 0x02 /* Translation Blocking */ |
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678 | #define PCI_ACS_RR 0x04 /* P2P Request Redirect */ |
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679 | #define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ |
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680 | #define PCI_ACS_UF 0x10 /* Upstream Forwarding */ |
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681 | #define PCI_ACS_EC 0x20 /* P2P Egress Control */ |
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682 | #define PCI_ACS_DT 0x40 /* Direct Translated P2P */ |
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683 | #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
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684 | #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ |
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685 | |||
686 | #endif /* LINUX_PCI_REGS_H */><>><>><> |