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/*

 *	pci.h

 *

 *	PCI defines and function prototypes

 *	Copyright 1994, Drew Eckhardt

 *	Copyright 1997--1999 Martin Mares 

 *

 *	For more information, please consult the following manuals (look at

 *	http://www.pcisig.com/ for how to get them):

 *

 *	PCI BIOS Specification

 *	PCI Local Bus Specification

 *	PCI to PCI Bridge Specification

 *	PCI System Design Guide

 */

#ifndef LINUX_PCI_H

#define LINUX_PCI_H

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

/*

 * The PCI interface treats multi-function devices as independent

 * devices.  The slot/function address of each device is encoded

 * in a single byte as follows:

 *

 *	7:3 = slot

 *	2:0 = function

 *

 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.

 * In the interest of not exposing interfaces to user-space unnecessarily,

 * the following kernel-only defines are being added here.

 */

#define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))

/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */

#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)

/* pci_slot represents a physical slot */

struct pci_slot {

	struct pci_bus *bus;		/* The bus this slot is on */

	struct list_head list;		/* node in list of slots on this bus */

	struct hotplug_slot *hotplug;	/* Hotplug info (migrate over time) */

	unsigned char number;		/* PCI_SLOT(pci_dev->devfn) */

	struct kobject kobj;

};

static inline const char *pci_slot_name(const struct pci_slot *slot)

{

	return kobject_name(&slot->kobj);

}

/* File state for mmap()s on /proc/bus/pci/X/Y */

enum pci_mmap_state {

	pci_mmap_io,

	pci_mmap_mem

};

/* This defines the direction arg to the DMA mapping routines. */

#define PCI_DMA_BIDIRECTIONAL	0

#define PCI_DMA_TODEVICE	1

#define PCI_DMA_FROMDEVICE	2

#define PCI_DMA_NONE		3

/*

 *  For PCI devices, the region numbers are assigned this way:

 */

enum {

	/* #0-5: standard PCI resources */

	PCI_STD_RESOURCES,

	PCI_STD_RESOURCE_END = 5,

	/* #6: expansion ROM resource */

	PCI_ROM_RESOURCE,

	/* device specific resources */

#ifdef CONFIG_PCI_IOV

	PCI_IOV_RESOURCES,

	PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,

#endif

	/* resources assigned to buses behind the bridge */

#define PCI_BRIDGE_RESOURCE_NUM 4

	PCI_BRIDGE_RESOURCES,

	PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +

				  PCI_BRIDGE_RESOURCE_NUM - 1,

	/* total resources associated with a PCI device */

	PCI_NUM_RESOURCES,

	/* preserve this for compatibility */

	DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,

};

typedef int __bitwise pci_power_t;

#define PCI_D0		((pci_power_t __force) 0)

#define PCI_D1		((pci_power_t __force) 1)

#define PCI_D2		((pci_power_t __force) 2)

#define PCI_D3hot	((pci_power_t __force) 3)

#define PCI_D3cold	((pci_power_t __force) 4)

#define PCI_UNKNOWN	((pci_power_t __force) 5)

#define PCI_POWER_ERROR	((pci_power_t __force) -1)

/* Remember to update this when the list above changes! */

extern const char *pci_power_names[];

static inline const char *pci_power_name(pci_power_t state)

{

	return pci_power_names[1 + (int) state];

}

#define PCI_PM_D2_DELAY		200

#define PCI_PM_D3_WAIT		10

#define PCI_PM_D3COLD_WAIT	100

#define PCI_PM_BUS_WAIT		50

/** The pci_channel state describes connectivity between the CPU and

 *  the pci device.  If some PCI bus between here and the pci device

 *  has crashed or locked up, this info is reflected here.

 */

typedef unsigned int __bitwise pci_channel_state_t;

enum pci_channel_state {

	/* I/O channel is in normal state */

	pci_channel_io_normal = (__force pci_channel_state_t) 1,

	/* I/O to channel is blocked */

	pci_channel_io_frozen = (__force pci_channel_state_t) 2,

	/* PCI card is dead */

	pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,

};

typedef unsigned int __bitwise pcie_reset_state_t;

enum pcie_reset_state {

	/* Reset is NOT asserted (Use to deassert reset) */

	pcie_deassert_reset = (__force pcie_reset_state_t) 1,

	/* Use #PERST to reset PCIe device */

	pcie_warm_reset = (__force pcie_reset_state_t) 2,

	/* Use PCIe Hot Reset to reset device */

	pcie_hot_reset = (__force pcie_reset_state_t) 3

};

typedef unsigned short __bitwise pci_dev_flags_t;

enum pci_dev_flags {

	/* INTX_DISABLE in PCI_COMMAND register disables MSI

	 * generation too.

	 */

	PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),

	/* Device configuration is irrevocably lost if disabled into D3 */

	PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),

	/* Provide indication device is assigned by a Virtual Machine Manager */

	PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),

	/* Flag for quirk use to store if quirk-specific ACS is enabled */

	PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),

	/* Flag to indicate the device uses dma_alias_devfn */

	PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),

	/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */

	PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),

	/* Do not use bus resets for device */

	PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),

	/* Do not use PM reset even if device advertises NoSoftRst- */

	PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),

	/* Get VPD from function 0 VPD */

	PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),

};

enum pci_irq_reroute_variant {

	INTEL_IRQ_REROUTE_VARIANT = 1,

	MAX_IRQ_REROUTE_VARIANTS = 3

};

typedef unsigned short __bitwise pci_bus_flags_t;

enum pci_bus_flags {

	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,

	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,

};

/* These values come from the PCI Express Spec */

enum pcie_link_width {

	PCIE_LNK_WIDTH_RESRV	= 0x00,

	PCIE_LNK_X1		= 0x01,

	PCIE_LNK_X2		= 0x02,

	PCIE_LNK_X4		= 0x04,

	PCIE_LNK_X8		= 0x08,

	PCIE_LNK_X12		= 0x0C,

	PCIE_LNK_X16		= 0x10,

	PCIE_LNK_X32		= 0x20,

	PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,

};

/* Based on the PCI Hotplug Spec, but some values are made up by us */

enum pci_bus_speed {

	PCI_SPEED_33MHz			= 0x00,

	PCI_SPEED_66MHz			= 0x01,

	PCI_SPEED_66MHz_PCIX		= 0x02,

	PCI_SPEED_100MHz_PCIX		= 0x03,

	PCI_SPEED_133MHz_PCIX		= 0x04,

	PCI_SPEED_66MHz_PCIX_ECC	= 0x05,

	PCI_SPEED_100MHz_PCIX_ECC	= 0x06,

	PCI_SPEED_133MHz_PCIX_ECC	= 0x07,

	PCI_SPEED_66MHz_PCIX_266	= 0x09,

	PCI_SPEED_100MHz_PCIX_266	= 0x0a,

	PCI_SPEED_133MHz_PCIX_266	= 0x0b,

	AGP_UNKNOWN			= 0x0c,

	AGP_1X				= 0x0d,

	AGP_2X				= 0x0e,

	AGP_4X				= 0x0f,

	AGP_8X				= 0x10,

	PCI_SPEED_66MHz_PCIX_533	= 0x11,

	PCI_SPEED_100MHz_PCIX_533	= 0x12,

	PCI_SPEED_133MHz_PCIX_533	= 0x13,

	PCIE_SPEED_2_5GT		= 0x14,

	PCIE_SPEED_5_0GT		= 0x15,

	PCIE_SPEED_8_0GT		= 0x16,

	PCI_SPEED_UNKNOWN		= 0xff,

};

struct pci_cap_saved_data {

	u16 cap_nr;

	bool cap_extended;

	unsigned int size;

	u32 data[0];

};

struct pci_cap_saved_state {

	struct hlist_node next;

	struct pci_cap_saved_data cap;

};

struct pcie_link_state;

struct pci_vpd;

struct pci_sriov;

struct pci_ats;

/*

 * The pci_dev structure is used to describe PCI devices.

 */

struct pci_dev {

	struct list_head bus_list;	/* node in per-bus list */

	struct pci_bus	*bus;		/* bus this device is on */

	struct pci_bus	*subordinate;	/* bus this device bridges to */

	void		*sysdata;	/* hook for sys-specific extension */

//    struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */

	struct pci_slot	*slot;		/* Physical slot this device is in */

	u32           busnr;

	unsigned int	devfn;		/* encoded device & function index */

	unsigned short	vendor;

	unsigned short	device;

	unsigned short	subsystem_vendor;

	unsigned short	subsystem_device;

	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */

	u8		revision;	/* PCI revision, low byte of class word */

	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */

	u8		pcie_cap;	/* PCIe capability offset */

	u8		msi_cap;	/* MSI capability offset */

	u8		msix_cap;	/* MSI-X capability offset */

	u8		pcie_mpss:3;	/* PCIe Max Payload Size Supported */

	u8		rom_base_reg;	/* which config register controls the ROM */

	u8		pin;		/* which interrupt pin this device uses */

	u16		pcie_flags_reg;	/* cached PCIe Capabilities Register */

	u8		dma_alias_devfn;/* devfn of DMA alias, if any */

	u64		dma_mask;	/* Mask of the bits of bus address this

					   device implements.  Normally this is

					   0xffffffff.  You only need to change

					   this if your device has broken DMA

					   or supports 64-bit transfers.  */

	pci_power_t     current_state;  /* Current operating state. In ACPI-speak,

					   this is D0-D3, D0 being fully functional,

					   and D3 being off. */

	u8		pm_cap;		/* PM capability offset */

	unsigned int	pme_support:5;	/* Bitmask of states from which PME#

					   can be generated */

	unsigned int	pme_interrupt:1;

	unsigned int	pme_poll:1;	/* Poll device's PME status bit */

	unsigned int	d1_support:1;	/* Low power state D1 is supported */

	unsigned int	d2_support:1;	/* Low power state D2 is supported */

	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */

	unsigned int	no_d3cold:1;	/* D3cold is forbidden */

	unsigned int	d3cold_allowed:1;	/* D3cold is allowed by user */

	unsigned int	mmio_always_on:1;	/* disallow turning off io/mem

						   decoding during bar sizing */

	unsigned int	wakeup_prepared:1;

	unsigned int	runtime_d3cold:1;	/* whether go through runtime

						   D3cold, not set for devices

						   powered on/off by the

						   corresponding bridge */

	unsigned int	ignore_hotplug:1;	/* Ignore hotplug events */

	unsigned int	d3_delay;	/* D3->D0 transition time in ms */

	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */

#ifdef CONFIG_PCIEASPM

	struct pcie_link_state	*link_state;	/* ASPM link state */

#endif

	pci_channel_state_t error_state;	/* current connectivity state */

	struct	device	dev;		/* Generic device interface */

	int		cfg_size;	/* Size of configuration space */

	/*

	 * Instead of touching interrupt line and base address registers

	 * directly, use the values stored here. They might be different!

	 */

	unsigned int	irq;

	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */

	bool match_driver;		/* Skip attaching driver */

	/* These fields are used by common fixups */

	unsigned int	transparent:1;	/* Subtractive decode PCI bridge */

	unsigned int	multifunction:1;/* Part of multi-function device */

	/* keep track of device state */

	unsigned int	is_added:1;

	unsigned int	is_busmaster:1; /* device is busmaster */

	unsigned int	no_msi:1;	/* device may not use msi */

	unsigned int	no_64bit_msi:1; /* device may only use 32-bit MSIs */

	unsigned int	block_cfg_access:1;	/* config space access is blocked */

	unsigned int	broken_parity_status:1;	/* Device generates false positive parity */

	unsigned int	irq_reroute_variant:2;	/* device needs IRQ rerouting variant */

	unsigned int	msi_enabled:1;

	unsigned int	msix_enabled:1;

	unsigned int	ari_enabled:1;	/* ARI forwarding */

	unsigned int	ats_enabled:1;	/* Address Translation Service */

	unsigned int	is_managed:1;

	unsigned int    needs_freset:1; /* Dev requires fundamental reset */

	unsigned int	state_saved:1;

	unsigned int	is_physfn:1;

	unsigned int	is_virtfn:1;

	unsigned int	reset_fn:1;

	unsigned int    is_hotplug_bridge:1;

	unsigned int    __aer_firmware_first_valid:1;

	unsigned int	__aer_firmware_first:1;

	unsigned int	broken_intx_masking:1;

	unsigned int	io_window_1k:1;	/* Intel P2P bridge 1K I/O windows */

	unsigned int	irq_managed:1;

	unsigned int	has_secondary_link:1;

	unsigned int	non_compliant_bars:1;	/* broken BARs; ignore them */

	pci_dev_flags_t dev_flags;

	atomic_t	enable_cnt;	/* pci_enable_device has been called */

	u32		saved_config_space[16]; /* config space saved at suspend time */

	struct hlist_head saved_cap_space;

	struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */

	int rom_attr_enabled;		/* has display of the rom attribute been enabled? */

#ifdef CONFIG_PCI_MSI

	const struct attribute_group **msi_irq_groups;

#endif

#ifdef CONFIG_PCI_ATS

	union {

		struct pci_sriov *sriov;	/* SR-IOV capability related */

		struct pci_dev *physfn;	/* the PF this VF is associated with */

	};

	u16		ats_cap;	/* ATS Capability offset */

	u8		ats_stu;	/* ATS Smallest Translation Unit */

	atomic_t	ats_ref_cnt;	/* number of VFs with ATS enabled */

#endif

	phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */

	size_t romlen; /* Length of ROM if it's not from the BAR */

	char *driver_override; /* Driver name to force a match */

};

static inline struct pci_dev *pci_physfn(struct pci_dev *dev)

{

#ifdef CONFIG_PCI_IOV

	if (dev->is_virtfn)

		dev = dev->physfn;

#endif

	return dev;

}

struct pci_dev *pci_alloc_dev(struct pci_bus *bus);

#define	to_pci_dev(n) container_of(n, struct pci_dev, dev)

#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)

static inline int pci_channel_offline(struct pci_dev *pdev)

{

	return (pdev->error_state != pci_channel_io_normal);

}

struct pci_host_bridge {

	struct device dev;

	struct pci_bus *bus;		/* root bus */

	struct list_head windows;	/* resource_entry */

	void (*release_fn)(struct pci_host_bridge *);

	void *release_data;

	unsigned int ignore_reset_delay:1;	/* for entire hierarchy */

	/* Resource alignment requirements */

	resource_size_t (*align_resource)(struct pci_dev *dev,

			const struct resource *res,

			resource_size_t start,

			resource_size_t size,

			resource_size_t align);

};

#define	to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)

struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);

void pci_set_host_bridge_release(struct pci_host_bridge *bridge,

		     void (*release_fn)(struct pci_host_bridge *),

		     void *release_data);

int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);

/*

 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond

 * to P2P or CardBus bridge windows) go in a table.  Additional ones (for

 * buses below host bridges or subtractive decode bridges) go in the list.

 * Use pci_bus_for_each_resource() to iterate through all the resources.

 */

/*

 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly

 * and there's no way to program the bridge with the details of the window.

 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-

 * decode bit set, because they are explicit and can be programmed with _SRS.

 */

#define PCI_SUBTRACTIVE_DECODE	0x1

struct pci_bus_resource {

	struct list_head list;

	struct resource *res;

	unsigned int flags;

};

#define PCI_REGION_FLAG_MASK	0x0fU	/* These bits of resource flags tell us the PCI region flags */

struct pci_bus {

	struct list_head node;		/* node in list of buses */

	struct pci_bus	*parent;	/* parent bus this bridge is on */

	struct list_head children;	/* list of child buses */

	struct list_head devices;	/* list of devices on this bus */

	struct pci_dev	*self;		/* bridge device as seen by parent */

	struct list_head slots;		/* list of slots on this bus;

					   protected by pci_slot_mutex */

	struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];

	struct list_head resources;	/* address space routed to this bus */

	struct resource busn_res;	/* bus numbers routed to this bus */

	struct pci_ops	*ops;		/* configuration access functions */

	struct msi_controller *msi;	/* MSI controller */

	void		*sysdata;	/* hook for sys-specific extension */

	struct proc_dir_entry *procdir;	/* directory entry in /proc/bus/pci */

	unsigned char	number;		/* bus number */

	unsigned char	primary;	/* number of primary bridge */

	unsigned char	max_bus_speed;	/* enum pci_bus_speed */

	unsigned char	cur_bus_speed;	/* enum pci_bus_speed */

#ifdef CONFIG_PCI_DOMAINS_GENERIC

	int		domain_nr;

#endif

	char		name[48];

	unsigned short  bridge_ctl;	/* manage NO_ISA/FBB/et al behaviors */

	pci_bus_flags_t bus_flags;	/* inherited by child buses */

	struct device		*bridge;

	struct device		dev;

	struct bin_attribute	*legacy_io; /* legacy I/O for this bus */

	struct bin_attribute	*legacy_mem; /* legacy mem */

	unsigned int		is_added:1;

};

#define to_pci_bus(n)	container_of(n, struct pci_bus, dev)

/*

 * Returns true if the PCI bus is root (behind host-PCI bridge),

 * false otherwise

 *

 * Some code assumes that "bus->self == NULL" means that bus is a root bus.

 * This is incorrect because "virtual" buses added for SR-IOV (via

 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.

 */

static inline bool pci_is_root_bus(struct pci_bus *pbus)

{

	return !(pbus->parent);

}

/**

 * pci_is_bridge - check if the PCI device is a bridge

 * @dev: PCI device

 *

 * Return true if the PCI device is bridge whether it has subordinate

 * or not.

 */

static inline bool pci_is_bridge(struct pci_dev *dev)

{

	return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||

		dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;

}

static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)

{

	dev = pci_physfn(dev);

	if (pci_is_root_bus(dev->bus))

		return NULL;

	return dev->bus->self;

}

struct device *pci_get_host_bridge_device(struct pci_dev *dev);

void pci_put_host_bridge_device(struct device *dev);

#ifdef CONFIG_PCI_MSI

static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)

{

	return pci_dev->msi_enabled || pci_dev->msix_enabled;

}

#else

static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }

#endif

/*

 * Error values that may be returned by PCI functions.

 */

#define PCIBIOS_SUCCESSFUL		0x00

#define PCIBIOS_FUNC_NOT_SUPPORTED	0x81

#define PCIBIOS_BAD_VENDOR_ID		0x83

#define PCIBIOS_DEVICE_NOT_FOUND	0x86

#define PCIBIOS_BAD_REGISTER_NUMBER	0x87

#define PCIBIOS_SET_FAILED		0x88

#define PCIBIOS_BUFFER_TOO_SMALL	0x89

/*

 * Translate above to generic errno for passing back through non-PCI code.

 */

static inline int pcibios_err_to_errno(int err)

{

	if (err <= PCIBIOS_SUCCESSFUL)

		return err; /* Assume already errno */

	switch (err) {

	case PCIBIOS_FUNC_NOT_SUPPORTED:

		return -ENOENT;

	case PCIBIOS_BAD_VENDOR_ID:

		return -ENOTTY;

	case PCIBIOS_DEVICE_NOT_FOUND:

		return -ENODEV;

	case PCIBIOS_BAD_REGISTER_NUMBER:

		return -EFAULT;

	case PCIBIOS_SET_FAILED:

		return -EIO;

	case PCIBIOS_BUFFER_TOO_SMALL:

		return -ENOSPC;

	}

	return -ERANGE;

}

/* Low-level architecture-dependent routines */

struct pci_ops {

	void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);

	int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);

	int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);

};

/*

 * ACPI needs to be able to access PCI config space before we've done a

 * PCI bus scan and created pci_bus structures.

 */

int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,

		 int reg, int len, u32 *val);

int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,

		  int reg, int len, u32 val);

#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT

typedef u64 pci_bus_addr_t;

#else

typedef u32 pci_bus_addr_t;

#endif

struct pci_bus_region {

	pci_bus_addr_t start;

	pci_bus_addr_t end;

};

struct pci_dynids {

	spinlock_t lock;            /* protects list, index */

	struct list_head list;      /* for IDs added at runtime */

};

/*

 * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides

 * a set of callbacks in struct pci_error_handlers, that device driver

 * will be notified of PCI bus errors, and will be driven to recovery

 * when an error occurs.

 */

typedef unsigned int __bitwise pci_ers_result_t;

enum pci_ers_result {

	/* no result/none/not supported in device driver */

	PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,

	/* Device driver can recover without slot reset */

	PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,

	/* Device driver wants slot to be reset. */

	PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,

	/* Device has completely failed, is unrecoverable */

	PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,

	/* Device driver is fully recovered and operational */

	PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,

	/* No AER capabilities registered for the driver */

	PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,

};

/* PCI bus error event callbacks */

struct pci_error_handlers {

	/* PCI bus error detected on this device */

	pci_ers_result_t (*error_detected)(struct pci_dev *dev,

					   enum pci_channel_state error);

	/* MMIO has been re-enabled, but not DMA */

	pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);

	/* PCI Express link has been reset */

	pci_ers_result_t (*link_reset)(struct pci_dev *dev);

	/* PCI slot has been reset */

	pci_ers_result_t (*slot_reset)(struct pci_dev *dev);

	/* PCI function reset prepare or completed */

	void (*reset_notify)(struct pci_dev *dev, bool prepare);

	/* Device driver may resume normal operations */

	void (*resume)(struct pci_dev *dev);

};

struct module;

struct pci_driver {

	struct list_head node;

	const char *name;

	const struct pci_device_id *id_table;	/* must be non-NULL for probe to be called */

	int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);	/* New device inserted */

	void (*remove) (struct pci_dev *dev);	/* Device removed (NULL if not a hot-plug capable driver) */

	int  (*suspend) (struct pci_dev *dev, pm_message_t state);	/* Device suspended */

	int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);

	int  (*resume_early) (struct pci_dev *dev);

	int  (*resume) (struct pci_dev *dev);	                /* Device woken up */

	void (*shutdown) (struct pci_dev *dev);

	int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */

	const struct pci_error_handlers *err_handler;

	struct device_driver	driver;

	struct pci_dynids dynids;

};

#define	to_pci_driver(drv) container_of(drv, struct pci_driver, driver)

/**

 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table

 * @_table: device table name

 *

 * This macro is deprecated and should not be used in new code.

 */

#define DEFINE_PCI_DEVICE_TABLE(_table) \

	const struct pci_device_id _table[]

/**

 * PCI_DEVICE - macro used to describe a specific pci device

 * @vend: the 16 bit PCI Vendor ID

 * @dev: the 16 bit PCI Device ID

 *

 * This macro is used to create a struct pci_device_id that matches a

 * specific device.  The subvendor and subdevice fields will be set to

 * PCI_ANY_ID.

 */

#define PCI_DEVICE(vend,dev) \

	.vendor = (vend), .device = (dev), \

	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

/**

 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem

 * @vend: the 16 bit PCI Vendor ID

 * @dev: the 16 bit PCI Device ID

 * @subvend: the 16 bit PCI Subvendor ID

 * @subdev: the 16 bit PCI Subdevice ID

 *

 * This macro is used to create a struct pci_device_id that matches a

 * specific device with subsystem information.

 */

#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \

	.vendor = (vend), .device = (dev), \

	.subvendor = (subvend), .subdevice = (subdev)

/**

 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class

 * @dev_class: the class, subclass, prog-if triple for this device

 * @dev_class_mask: the class mask for this device

 *

 * This macro is used to create a struct pci_device_id that matches a

 * specific PCI class.  The vendor, device, subvendor, and subdevice

 * fields will be set to PCI_ANY_ID.

 */

#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \

	.class = (dev_class), .class_mask = (dev_class_mask), \

	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \

	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

/**

 * PCI_VDEVICE - macro used to describe a specific pci device in short form

 * @vend: the vendor name

 * @dev: the 16 bit PCI Device ID

 *

 * This macro is used to create a struct pci_device_id that matches a

 * specific PCI device.  The subvendor, and subdevice fields will be set

 * to PCI_ANY_ID. The macro allows the next field to follow as the device

 * private data.

 */

#define PCI_VDEVICE(vend, dev) \

	.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \

	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0

enum {

	PCI_REASSIGN_ALL_RSRC	= 0x00000001,	/* ignore firmware setup */

	PCI_REASSIGN_ALL_BUS	= 0x00000002,	/* reassign all bus numbers */

	PCI_PROBE_ONLY		= 0x00000004,	/* use existing setup */

	PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,	/* don't do ISA alignment */

	PCI_ENABLE_PROC_DOMAINS	= 0x00000010,	/* enable domains in /proc */

	PCI_COMPAT_DOMAIN_0	= 0x00000020,	/* ... except domain 0 */

	PCI_SCAN_ALL_PCIE_DEVS	= 0x00000040,	/* scan all, not just dev 0 */

};

/* these external functions are only available when PCI support is enabled */

#ifdef CONFIG_PCI

extern unsigned int pci_flags;

static inline void pci_set_flags(int flags) { pci_flags = flags; }

static inline void pci_add_flags(int flags) { pci_flags |= flags; }

static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }

static inline int pci_has_flag(int flag) { return pci_flags & flag; }

void pcie_bus_configure_settings(struct pci_bus *bus);

enum pcie_bus_config_types {

	PCIE_BUS_TUNE_OFF,	/* don't touch MPS at all */

	PCIE_BUS_DEFAULT,	/* ensure MPS matches upstream bridge */

	PCIE_BUS_SAFE,		/* use largest MPS boot-time devices support */

	PCIE_BUS_PERFORMANCE,	/* use MPS and MRRS for best performance */

	PCIE_BUS_PEER2PEER,	/* set MPS = 128 for all devices */

};

extern enum pcie_bus_config_types pcie_bus_config;

extern struct bus_type pci_bus_type;

/* Do NOT directly access these two variables, unless you are arch-specific PCI

 * code, or PCI core code. */

extern struct list_head pci_root_buses;	/* list of all known PCI buses */

/* Some device drivers need know if PCI is initiated */

int no_pci_devices(void);

void pcibios_resource_survey_bus(struct pci_bus *bus);

void pcibios_bus_add_device(struct pci_dev *pdev);

void pcibios_add_bus(struct pci_bus *bus);

void pcibios_remove_bus(struct pci_bus *bus);

void pcibios_fixup_bus(struct pci_bus *);

int __must_check pcibios_enable_device(struct pci_dev *, int mask);

/* Architecture-specific versions may override this (weak) */

char *pcibios_setup(char *str);

/* Used only when drivers/pci/setup.c is used */

resource_size_t pcibios_align_resource(void *, const struct resource *,

				resource_size_t,

				resource_size_t);

void pcibios_update_irq(struct pci_dev *, int irq);

/* Weak but can be overriden by arch */

void pci_fixup_cardbus(struct pci_bus *);

/* Generic PCI functions used internally */

void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,

			     struct resource *res);

void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,

			     struct pci_bus_region *region);

void pcibios_scan_specific_bus(int busn);

struct pci_bus *pci_find_bus(int domain, int busnr);

void pci_bus_add_devices(const struct pci_bus *bus);

struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);

struct pci_bus *pci_create_root_bus(struct device *parent, int bus,

				    struct pci_ops *ops, void *sysdata,

				    struct list_head *resources);

int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);

int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);

void pci_bus_release_busn_res(struct pci_bus *b);

struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,

				      struct pci_ops *ops, void *sysdata,

				      struct list_head *resources,

				      struct msi_controller *msi);

struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,

					     struct pci_ops *ops, void *sysdata,

					     struct list_head *resources);

struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,

				int busnr);

void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);

struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,

				 const char *name,

				 struct hotplug_slot *hotplug);

void pci_destroy_slot(struct pci_slot *slot);

#ifdef CONFIG_SYSFS

void pci_dev_assign_slot(struct pci_dev *dev);

#else

static inline void pci_dev_assign_slot(struct pci_dev *dev) { }

#endif

int pci_scan_slot(struct pci_bus *bus, int devfn);

struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);

void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);

unsigned int pci_scan_child_bus(struct pci_bus *bus);

void pci_bus_add_device(struct pci_dev *dev);

void pci_read_bridge_bases(struct pci_bus *child);

struct resource *pci_find_parent_resource(const struct pci_dev *dev,

					  struct resource *res);

struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);

u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);

int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);

u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);

struct pci_dev *pci_dev_get(struct pci_dev *dev);

void pci_dev_put(struct pci_dev *dev);

void pci_remove_bus(struct pci_bus *b);

void pci_stop_and_remove_bus_device(struct pci_dev *dev);

void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);

void pci_stop_root_bus(struct pci_bus *bus);

void pci_remove_root_bus(struct pci_bus *bus);

void pci_setup_cardbus(struct pci_bus *bus);

void pci_sort_breadthfirst(void);

#define dev_is_pci(d) ((d)->bus == &pci_bus_type)

#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))

#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))

/* Generic PCI functions exported to card drivers */

enum pci_lost_interrupt_reason {

	PCI_LOST_IRQ_NO_INFORMATION = 0,

	PCI_LOST_IRQ_DISABLE_MSI,

	PCI_LOST_IRQ_DISABLE_MSIX,

	PCI_LOST_IRQ_DISABLE_ACPI,

};

enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);

int pci_find_capability(struct pci_dev *dev, int cap);

int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);

int pci_find_ext_capability(struct pci_dev *dev, int cap);

int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);

int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);

int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);

struct pci_bus *pci_find_next_bus(const struct pci_bus *from);

struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,

				struct pci_dev *from);

struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,

				unsigned int ss_vendor, unsigned int ss_device,

				struct pci_dev *from);

struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);

struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,

					    unsigned int devfn);

static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,

						   unsigned int devfn)

{

	return pci_get_domain_bus_and_slot(0, bus, devfn);

}

struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);

int pci_dev_present(const struct pci_device_id *ids);

int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,

			     int where, u8 *val);

int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,

			     int where, u16 *val);

int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,

			      int where, u32 *val);

int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,

			      int where, u8 val);

int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,

			      int where, u16 val);

int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,

			       int where, u32 val);

int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,

			    int where, int size, u32 *val);

int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,

			    int where, int size, u32 val);

int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,

			      int where, int size, u32 *val);

int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,

			       int where, int size, u32 val);

struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);

static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)

{

	*val = PciRead8(dev->busnr, dev->devfn, where);

	return 1;

}

static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)

{

	*val = PciRead16(dev->busnr, dev->devfn, where);

	return 1;

}

static inline int pci_read_config_dword(const struct pci_dev *dev, int where,

					u32 *val)

{

	*val = PciRead32(dev->busnr, dev->devfn, where);

	return 1;

}

static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)

{

	PciWrite8(dev->busnr, dev->devfn, where, val);

	return 1;

}

static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)

{

	PciWrite16(dev->busnr, dev->devfn, where, val);

	return 1;

}

static inline int pci_write_config_dword(const struct pci_dev *dev, int where,

					 u32 val)

{

	PciWrite32(dev->busnr, dev->devfn, where, val);

	return 1;

}

int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);

int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);

int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);

int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);

int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,

				       u16 clear, u16 set);

int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,

					u32 clear, u32 set);

static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,

					   u16 set)

{

	return pcie_capability_clear_and_set_word(dev, pos, 0, set);

}

static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,

					    u32 set)

{

	return pcie_capability_clear_and_set_dword(dev, pos, 0, set);

}

static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,

					     u16 clear)

{

	return pcie_capability_clear_and_set_word(dev, pos, clear, 0);

}

static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,

					      u32 clear)

{

	return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);

}

/* user-space driven config access */

int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);

int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);

int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);

int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);

int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);

int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);

int __must_check pci_enable_device(struct pci_dev *dev);

int __must_check pci_enable_device_io(struct pci_dev *dev);

int __must_check pci_enable_device_mem(struct pci_dev *dev);

int __must_check pci_reenable_device(struct pci_dev *);

int __must_check pcim_enable_device(struct pci_dev *pdev);

void pcim_pin_device(struct pci_dev *pdev);

static inline int pci_is_enabled(struct pci_dev *pdev)

{

	return (atomic_read(&pdev->enable_cnt) > 0);

}

static inline int pci_is_managed(struct pci_dev *pdev)

{

	return pdev->is_managed;

}

void pci_disable_device(struct pci_dev *dev);

extern unsigned int pcibios_max_latency;

void pci_set_master(struct pci_dev *dev);

void pci_clear_master(struct pci_dev *dev);

int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);

int pci_set_cacheline_size(struct pci_dev *dev);

#define HAVE_PCI_SET_MWI

int __must_check pci_set_mwi(struct pci_dev *dev);

int pci_try_set_mwi(struct pci_dev *dev);

void pci_clear_mwi(struct pci_dev *dev);

void pci_intx(struct pci_dev *dev, int enable);

bool pci_intx_mask_supported(struct pci_dev *dev);

bool pci_check_and_mask_intx(struct pci_dev *dev);

bool pci_check_and_unmask_intx(struct pci_dev *dev);

int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);

int pci_wait_for_pending_transaction(struct pci_dev *dev);

int pcix_get_max_mmrbc(struct pci_dev *dev);

int pcix_get_mmrbc(struct pci_dev *dev);

int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);

int pcie_get_readrq(struct pci_dev *dev);

int pcie_set_readrq(struct pci_dev *dev, int rq);

int pcie_get_mps(struct pci_dev *dev);

int pcie_set_mps(struct pci_dev *dev, int mps);

int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,

			  enum pcie_link_width *width);

int __pci_reset_function(struct pci_dev *dev);

int __pci_reset_function_locked(struct pci_dev *dev);

int pci_reset_function(struct pci_dev *dev);

int pci_try_reset_function(struct pci_dev *dev);

int pci_probe_reset_slot(struct pci_slot *slot);

int pci_reset_slot(struct pci_slot *slot);

int pci_try_reset_slot(struct pci_slot *slot);

int pci_probe_reset_bus(struct pci_bus *bus);

int pci_reset_bus(struct pci_bus *bus);

int pci_try_reset_bus(struct pci_bus *bus);

void pci_reset_secondary_bus(struct pci_dev *dev);

void pcibios_reset_secondary_bus(struct pci_dev *dev);

void pci_reset_bridge_secondary_bus(struct pci_dev *dev);

void pci_update_resource(struct pci_dev *dev, int resno);

int __must_check pci_assign_resource(struct pci_dev *dev, int i);

int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);

int pci_select_bars(struct pci_dev *dev, unsigned long flags);

bool pci_device_is_present(struct pci_dev *pdev);

void pci_ignore_hotplug(struct pci_dev *dev);

/* ROM control related routines */

int pci_enable_rom(struct pci_dev *pdev);

void pci_disable_rom(struct pci_dev *pdev);

void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);

void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);

size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);

void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);

/* Power management related routines */

int pci_save_state(struct pci_dev *dev);

void pci_restore_state(struct pci_dev *dev);

struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);

int pci_load_saved_state(struct pci_dev *dev,

			 struct pci_saved_state *state);

int pci_load_and_free_saved_state(struct pci_dev *dev,

				  struct pci_saved_state **state);

struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);

struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,

						   u16 cap);

int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);

int pci_add_ext_cap_save_buffer(struct pci_dev *dev,

				u16 cap, unsigned int size);

int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);

int pci_set_power_state(struct pci_dev *dev, pci_power_t state);

pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);

bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);

void pci_pme_active(struct pci_dev *dev, bool enable);

int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,

		      bool runtime, bool enable);

int pci_wake_from_d3(struct pci_dev *dev, bool enable);

int pci_prepare_to_sleep(struct pci_dev *dev);

int pci_back_from_sleep(struct pci_dev *dev);

bool pci_dev_run_wake(struct pci_dev *dev);

bool pci_check_pme_status(struct pci_dev *dev);

void pci_pme_wakeup_bus(struct pci_bus *bus);

static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,

				  bool enable)

{

	return __pci_enable_wake(dev, state, false, enable);

}