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/*

 *	pci.h

 *

 *	PCI defines and function prototypes

 *	Copyright 1994, Drew Eckhardt

 *	Copyright 1997--1999 Martin Mares 

 *

 *	For more information, please consult the following manuals (look at

 *	http://www.pcisig.com/ for how to get them):

 *

 *	PCI BIOS Specification

 *	PCI Local Bus Specification

 *	PCI to PCI Bridge Specification

 *	PCI System Design Guide

 */

#ifndef LINUX_PCI_H

#define LINUX_PCI_H

#include 

#include 

#include 

#include 

#include 

#include 	/* The pci register defines */

#include 

#define PCI_CFG_SPACE_SIZE      256

#define PCI_CFG_SPACE_EXP_SIZE  4096

#define PCI_ANY_ID (~0)

#define PCI_CLASS_NOT_DEFINED           0x0000

#define PCI_CLASS_NOT_DEFINED_VGA       0x0001

#define PCI_BASE_CLASS_STORAGE          0x01

#define PCI_CLASS_STORAGE_SCSI          0x0100

#define PCI_CLASS_STORAGE_IDE           0x0101

#define PCI_CLASS_STORAGE_FLOPPY        0x0102

#define PCI_CLASS_STORAGE_IPI           0x0103

#define PCI_CLASS_STORAGE_RAID          0x0104

#define PCI_CLASS_STORAGE_SATA          0x0106

#define PCI_CLASS_STORAGE_SATA_AHCI     0x010601

#define PCI_CLASS_STORAGE_SAS           0x0107

#define PCI_CLASS_STORAGE_OTHER         0x0180

#define PCI_BASE_CLASS_NETWORK          0x02

#define PCI_CLASS_NETWORK_ETHERNET      0x0200

#define PCI_CLASS_NETWORK_TOKEN_RING    0x0201

#define PCI_CLASS_NETWORK_FDDI          0x0202

#define PCI_CLASS_NETWORK_ATM           0x0203

#define PCI_CLASS_NETWORK_OTHER         0x0280

#define PCI_BASE_CLASS_DISPLAY          0x03

#define PCI_CLASS_DISPLAY_VGA           0x0300

#define PCI_CLASS_DISPLAY_XGA           0x0301

#define PCI_CLASS_DISPLAY_3D            0x0302

#define PCI_CLASS_DISPLAY_OTHER         0x0380

#define PCI_BASE_CLASS_MULTIMEDIA       0x04

#define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400

#define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401

#define PCI_CLASS_MULTIMEDIA_PHONE      0x0402

#define PCI_CLASS_MULTIMEDIA_OTHER      0x0480

#define PCI_BASE_CLASS_MEMORY           0x05

#define PCI_CLASS_MEMORY_RAM            0x0500

#define PCI_CLASS_MEMORY_FLASH          0x0501

#define PCI_CLASS_MEMORY_OTHER          0x0580

#define PCI_BASE_CLASS_BRIDGE           0x06

#define PCI_CLASS_BRIDGE_HOST           0x0600

#define PCI_CLASS_BRIDGE_ISA            0x0601

#define PCI_CLASS_BRIDGE_EISA           0x0602

#define PCI_CLASS_BRIDGE_MC             0x0603

#define PCI_CLASS_BRIDGE_PCI            0x0604

#define PCI_CLASS_BRIDGE_PCMCIA         0x0605

#define PCI_CLASS_BRIDGE_NUBUS          0x0606

#define PCI_CLASS_BRIDGE_CARDBUS        0x0607

#define PCI_CLASS_BRIDGE_RACEWAY        0x0608

#define PCI_CLASS_BRIDGE_OTHER          0x0680

#define PCI_BASE_CLASS_COMMUNICATION    0x07

#define PCI_CLASS_COMMUNICATION_SERIAL  0x0700

#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701

#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702

#define PCI_CLASS_COMMUNICATION_MODEM   0x0703

#define PCI_CLASS_COMMUNICATION_OTHER   0x0780

#define PCI_BASE_CLASS_SYSTEM           0x08

#define PCI_CLASS_SYSTEM_PIC            0x0800

#define PCI_CLASS_SYSTEM_PIC_IOAPIC     0x080010

#define PCI_CLASS_SYSTEM_PIC_IOXAPIC    0x080020

#define PCI_CLASS_SYSTEM_DMA            0x0801

#define PCI_CLASS_SYSTEM_TIMER          0x0802

#define PCI_CLASS_SYSTEM_RTC            0x0803

#define PCI_CLASS_SYSTEM_PCI_HOTPLUG    0x0804

#define PCI_CLASS_SYSTEM_SDHCI          0x0805

#define PCI_CLASS_SYSTEM_OTHER          0x0880

#define PCI_BASE_CLASS_INPUT            0x09

#define PCI_CLASS_INPUT_KEYBOARD        0x0900

#define PCI_CLASS_INPUT_PEN             0x0901

#define PCI_CLASS_INPUT_MOUSE           0x0902

#define PCI_CLASS_INPUT_SCANNER         0x0903

#define PCI_CLASS_INPUT_GAMEPORT        0x0904

#define PCI_CLASS_INPUT_OTHER           0x0980

#define PCI_BASE_CLASS_DOCKING          0x0a

#define PCI_CLASS_DOCKING_GENERIC       0x0a00

#define PCI_CLASS_DOCKING_OTHER         0x0a80

#define PCI_BASE_CLASS_PROCESSOR        0x0b

#define PCI_CLASS_PROCESSOR_386         0x0b00

#define PCI_CLASS_PROCESSOR_486         0x0b01

#define PCI_CLASS_PROCESSOR_PENTIUM     0x0b02

#define PCI_CLASS_PROCESSOR_ALPHA       0x0b10

#define PCI_CLASS_PROCESSOR_POWERPC     0x0b20

#define PCI_CLASS_PROCESSOR_MIPS        0x0b30

#define PCI_CLASS_PROCESSOR_CO          0x0b40

#define PCI_BASE_CLASS_SERIAL           0x0c

#define PCI_CLASS_SERIAL_FIREWIRE       0x0c00

#define PCI_CLASS_SERIAL_FIREWIRE_OHCI  0x0c0010

#define PCI_CLASS_SERIAL_ACCESS         0x0c01

#define PCI_CLASS_SERIAL_SSA            0x0c02

#define PCI_CLASS_SERIAL_USB            0x0c03

#define PCI_CLASS_SERIAL_USB_UHCI       0x0c0300

#define PCI_CLASS_SERIAL_USB_OHCI       0x0c0310

#define PCI_CLASS_SERIAL_USB_EHCI       0x0c0320

#define PCI_CLASS_SERIAL_FIBER          0x0c04

#define PCI_CLASS_SERIAL_SMBUS          0x0c05

#define PCI_BASE_CLASS_WIRELESS                 0x0d

#define PCI_CLASS_WIRELESS_RF_CONTROLLER        0x0d10

#define PCI_CLASS_WIRELESS_WHCI                 0x0d1010

#define PCI_BASE_CLASS_INTELLIGENT      0x0e

#define PCI_CLASS_INTELLIGENT_I2O       0x0e00

#define PCI_BASE_CLASS_SATELLITE        0x0f

#define PCI_CLASS_SATELLITE_TV          0x0f00

#define PCI_CLASS_SATELLITE_AUDIO       0x0f01

#define PCI_CLASS_SATELLITE_VOICE       0x0f03

#define PCI_CLASS_SATELLITE_DATA        0x0f04

#define PCI_BASE_CLASS_CRYPT            0x10

#define PCI_CLASS_CRYPT_NETWORK         0x1000

#define PCI_CLASS_CRYPT_ENTERTAINMENT   0x1001

#define PCI_CLASS_CRYPT_OTHER           0x1080

#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11

#define PCI_CLASS_SP_DPIO               0x1100

#define PCI_CLASS_SP_OTHER              0x1180

#define PCI_CLASS_OTHERS                0xff

#define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)

#define PCI_MAP_IS_MEM(b)   (!PCI_MAP_IS_IO(b))

#define PCI_MAP_IS64BITMEM(b)   \

    (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)

#define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)

#define PCIGETMEMORY64HIGH(b)   (*((CARD32*)&b + 1))

#define PCIGETMEMORY64(b)   \

    (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))

#define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc

#define PCIGETIO(b)     ((b) & PCI_MAP_IO_ADDRESS_MASK)

#define PCI_MAP_ROM_DECODE_ENABLE     0x00000001

#define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800

#define PCIGETROM(b)        ((b) & PCI_MAP_ROM_ADDRESS_MASK)

#ifndef PCI_DOM_MASK

# define PCI_DOM_MASK 0x0ffu

#endif

#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)

#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \

                  (((d) & 0x00001fu) << 11) | \

                  (((f) & 0x000007u) << 8))

#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))

#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)

#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)

#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)

/*

 * The PCI interface treats multi-function devices as independent

 * devices.  The slot/function address of each device is encoded

 * in a single byte as follows:

 *

 *	7:3 = slot

 *	2:0 = function

 */

#define PCI_DEVFN(slot, func)  ((((slot) & 0x1f) << 3) | ((func) & 0x07))

#define PCI_SLOT(devfn)        (((devfn) >> 3) & 0x1f)

#define PCI_FUNC(devfn)        ((devfn) & 0x07)

typedef unsigned int PCITAG;

extern inline PCITAG

pciTag(int busnum, int devnum, int funcnum)

{

    return(PCI_MAKE_TAG(busnum,devnum,funcnum));

}

/* pci_slot represents a physical slot */

struct pci_slot {

	struct pci_bus *bus;		/* The bus this slot is on */

	struct list_head list;		/* node in list of slots on this bus */

	struct hotplug_slot *hotplug;	/* Hotplug info (migrate over time) */

	unsigned char number;		/* PCI_SLOT(pci_dev->devfn) */

};

/* File state for mmap()s on /proc/bus/pci/X/Y */

enum pci_mmap_state {

	pci_mmap_io,

	pci_mmap_mem

};

/* This defines the direction arg to the DMA mapping routines. */

#define PCI_DMA_BIDIRECTIONAL	0

#define PCI_DMA_TODEVICE	1

#define PCI_DMA_FROMDEVICE	2

#define PCI_DMA_NONE		3

/*

 *  For PCI devices, the region numbers are assigned this way:

 */

enum {