Rev 5056 | Rev 6082 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1964 | serge | 1 | /* |
2 | * pci.h |
||
3 | * |
||
4 | * PCI defines and function prototypes |
||
5 | * Copyright 1994, Drew Eckhardt |
||
6 | * Copyright 1997--1999 Martin Mares |
||
7 | * |
||
8 | * For more information, please consult the following manuals (look at |
||
9 | * http://www.pcisig.com/ for how to get them): |
||
10 | * |
||
11 | * PCI BIOS Specification |
||
12 | * PCI Local Bus Specification |
||
13 | * PCI to PCI Bridge Specification |
||
14 | * PCI System Design Guide |
||
15 | */ |
||
1970 | serge | 16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H |
||
18 | |||
3031 | serge | 19 | #include |
5270 | serge | 20 | #include |
21 | #include |
||
22 | #include |
||
23 | #include |
||
24 | |||
2161 | serge | 25 | #include |
5270 | serge | 26 | #include |
1408 | serge | 27 | |
1628 | serge | 28 | |
2161 | serge | 29 | #define PCI_CFG_SPACE_SIZE 256 |
30 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
||
1970 | serge | 31 | |
2161 | serge | 32 | |
1408 | serge | 33 | #define PCI_ANY_ID (~0) |
34 | |||
35 | |||
36 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
||
37 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
||
38 | |||
39 | #define PCI_BASE_CLASS_STORAGE 0x01 |
||
40 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
||
41 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
||
42 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
||
43 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
||
44 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
||
45 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
||
46 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
||
47 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
||
48 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
||
49 | |||
50 | #define PCI_BASE_CLASS_NETWORK 0x02 |
||
51 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
||
52 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
||
53 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
||
54 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
||
55 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
||
56 | |||
57 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
||
58 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
||
59 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
||
60 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
||
61 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
||
62 | |||
63 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
||
64 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
||
65 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
||
66 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
||
67 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
||
68 | |||
69 | #define PCI_BASE_CLASS_MEMORY 0x05 |
||
70 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
||
71 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
||
72 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
||
73 | |||
74 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
||
75 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
||
76 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
||
77 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
||
78 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
||
79 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
||
80 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
||
81 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
||
82 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
||
83 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
||
84 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
||
85 | |||
86 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
||
87 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
||
88 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
||
89 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
||
90 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
||
91 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
||
92 | |||
93 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
||
94 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
||
95 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
||
96 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
||
97 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
||
98 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
||
99 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
||
100 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
||
101 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
||
102 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
||
103 | |||
104 | #define PCI_BASE_CLASS_INPUT 0x09 |
||
105 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
||
106 | #define PCI_CLASS_INPUT_PEN 0x0901 |
||
107 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
||
108 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
||
109 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
||
110 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
||
111 | |||
112 | #define PCI_BASE_CLASS_DOCKING 0x0a |
||
113 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
||
114 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
||
115 | |||
116 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
||
117 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
||
118 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
||
119 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
||
120 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
||
121 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
||
122 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
||
123 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
||
124 | |||
125 | #define PCI_BASE_CLASS_SERIAL 0x0c |
||
126 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
||
127 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
||
128 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
||
129 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
||
130 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
||
131 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
||
132 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
||
133 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
||
134 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
||
135 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
||
136 | |||
137 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
||
138 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
||
139 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
||
140 | |||
141 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
||
142 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
||
143 | |||
144 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
||
145 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
||
146 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
||
147 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
||
148 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
||
149 | |||
150 | #define PCI_BASE_CLASS_CRYPT 0x10 |
||
151 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
||
152 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
||
153 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
||
154 | |||
155 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
||
156 | #define PCI_CLASS_SP_DPIO 0x1100 |
||
157 | #define PCI_CLASS_SP_OTHER 0x1180 |
||
158 | |||
159 | #define PCI_CLASS_OTHERS 0xff |
||
160 | |||
161 | |||
162 | |||
1964 | serge | 163 | |
164 | |||
1408 | serge | 165 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
166 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
||
167 | |||
168 | #define PCI_MAP_IS64BITMEM(b) \ |
||
169 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
||
170 | |||
171 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
||
172 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
||
173 | #define PCIGETMEMORY64(b) \ |
||
174 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
||
175 | |||
176 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
||
177 | |||
178 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
||
179 | |||
180 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
||
181 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
||
182 | |||
183 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
||
184 | |||
185 | |||
186 | #ifndef PCI_DOM_MASK |
||
187 | # define PCI_DOM_MASK 0x0ffu |
||
188 | #endif |
||
189 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
||
190 | |||
191 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
||
192 | (((d) & 0x00001fu) << 11) | \ |
||
193 | (((f) & 0x000007u) << 8)) |
||
194 | |||
195 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
||
196 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
||
197 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
||
198 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
||
199 | |||
2161 | serge | 200 | /* |
201 | * The PCI interface treats multi-function devices as independent |
||
202 | * devices. The slot/function address of each device is encoded |
||
203 | * in a single byte as follows: |
||
204 | * |
||
205 | * 7:3 = slot |
||
206 | * 2:0 = function |
||
207 | */ |
||
1408 | serge | 208 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
209 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
||
210 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
||
211 | |||
212 | |||
213 | |||
214 | typedef unsigned int PCITAG; |
||
215 | |||
216 | extern inline PCITAG |
||
217 | pciTag(int busnum, int devnum, int funcnum) |
||
218 | { |
||
219 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
||
220 | } |
||
221 | |||
2161 | serge | 222 | /* pci_slot represents a physical slot */ |
223 | struct pci_slot { |
||
224 | struct pci_bus *bus; /* The bus this slot is on */ |
||
225 | struct list_head list; /* node in list of slots on this bus */ |
||
226 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
||
227 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
||
228 | }; |
||
1627 | serge | 229 | |
2161 | serge | 230 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
231 | enum pci_mmap_state { |
||
232 | pci_mmap_io, |
||
233 | pci_mmap_mem |
||
1964 | serge | 234 | }; |
235 | |||
2161 | serge | 236 | /* This defines the direction arg to the DMA mapping routines. */ |
237 | #define PCI_DMA_BIDIRECTIONAL 0 |
||
238 | #define PCI_DMA_TODEVICE 1 |
||
239 | #define PCI_DMA_FROMDEVICE 2 |
||
240 | #define PCI_DMA_NONE 3 |
||
241 | |||
1408 | serge | 242 | /* |
2161 | serge | 243 | * For PCI devices, the region numbers are assigned this way: |
1627 | serge | 244 | */ |
2161 | serge | 245 | enum { |
246 | /* #0-5: standard PCI resources */ |
||
247 | PCI_STD_RESOURCES, |
||
248 | PCI_STD_RESOURCE_END = 5, |
||
1627 | serge | 249 | |
2161 | serge | 250 | /* #6: expansion ROM resource */ |
251 | PCI_ROM_RESOURCE, |
||
1627 | serge | 252 | |
2161 | serge | 253 | /* device specific resources */ |
254 | #ifdef CONFIG_PCI_IOV |
||
255 | PCI_IOV_RESOURCES, |
||
256 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
||
257 | #endif |
||
1627 | serge | 258 | |
2161 | serge | 259 | /* resources assigned to buses behind the bridge */ |
260 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
||
1627 | serge | 261 | |
2161 | serge | 262 | PCI_BRIDGE_RESOURCES, |
263 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
||
264 | PCI_BRIDGE_RESOURCE_NUM - 1, |
||
1627 | serge | 265 | |
2161 | serge | 266 | /* total resources associated with a PCI device */ |
267 | PCI_NUM_RESOURCES, |
||
1627 | serge | 268 | |
2161 | serge | 269 | /* preserve this for compatibility */ |
3747 | Serge | 270 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
2161 | serge | 271 | }; |
1627 | serge | 272 | |
2161 | serge | 273 | typedef int __bitwise pci_power_t; |
1627 | serge | 274 | |
2161 | serge | 275 | #define PCI_D0 ((pci_power_t __force) 0) |
276 | #define PCI_D1 ((pci_power_t __force) 1) |
||
277 | #define PCI_D2 ((pci_power_t __force) 2) |
||
278 | #define PCI_D3hot ((pci_power_t __force) 3) |
||
279 | #define PCI_D3cold ((pci_power_t __force) 4) |
||
280 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
||
281 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
||
3031 | serge | 282 | |
283 | /* Remember to update this when the list above changes! */ |
||
284 | extern const char *pci_power_names[]; |
||
285 | |||
286 | static inline const char *pci_power_name(pci_power_t state) |
||
287 | { |
||
288 | return pci_power_names[1 + (int) state]; |
||
289 | } |
||
290 | |||
291 | #define PCI_PM_D2_DELAY 200 |
||
292 | #define PCI_PM_D3_WAIT 10 |
||
293 | #define PCI_PM_D3COLD_WAIT 100 |
||
294 | #define PCI_PM_BUS_WAIT 50 |
||
295 | |||
2161 | serge | 296 | /** The pci_channel state describes connectivity between the CPU and |
297 | * the pci device. If some PCI bus between here and the pci device |
||
298 | * has crashed or locked up, this info is reflected here. |
||
299 | */ |
||
300 | typedef unsigned int __bitwise pci_channel_state_t; |
||
1964 | serge | 301 | |
2161 | serge | 302 | enum pci_channel_state { |
303 | /* I/O channel is in normal state */ |
||
304 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
||
1964 | serge | 305 | |
2161 | serge | 306 | /* I/O to channel is blocked */ |
307 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
||
1964 | serge | 308 | |
2161 | serge | 309 | /* PCI card is dead */ |
310 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
||
311 | }; |
||
312 | typedef unsigned short __bitwise pci_bus_flags_t; |
||
313 | enum pci_bus_flags { |
||
314 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
||
315 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
||
316 | }; |
||
1964 | serge | 317 | |
5270 | serge | 318 | /* These values come from the PCI Express Spec */ |
319 | enum pcie_link_width { |
||
320 | PCIE_LNK_WIDTH_RESRV = 0x00, |
||
321 | PCIE_LNK_X1 = 0x01, |
||
322 | PCIE_LNK_X2 = 0x02, |
||
323 | PCIE_LNK_X4 = 0x04, |
||
324 | PCIE_LNK_X8 = 0x08, |
||
325 | PCIE_LNK_X12 = 0x0C, |
||
326 | PCIE_LNK_X16 = 0x10, |
||
327 | PCIE_LNK_X32 = 0x20, |
||
328 | PCIE_LNK_WIDTH_UNKNOWN = 0xFF, |
||
329 | }; |
||
330 | |||
2161 | serge | 331 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
332 | enum pci_bus_speed { |
||
333 | PCI_SPEED_33MHz = 0x00, |
||
334 | PCI_SPEED_66MHz = 0x01, |
||
335 | PCI_SPEED_66MHz_PCIX = 0x02, |
||
336 | PCI_SPEED_100MHz_PCIX = 0x03, |
||
337 | PCI_SPEED_133MHz_PCIX = 0x04, |
||
338 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
||
339 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
||
340 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
||
341 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
||
342 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
||
343 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
||
344 | AGP_UNKNOWN = 0x0c, |
||
345 | AGP_1X = 0x0d, |
||
346 | AGP_2X = 0x0e, |
||
347 | AGP_4X = 0x0f, |
||
348 | AGP_8X = 0x10, |
||
349 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
||
350 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
||
351 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
||
352 | PCIE_SPEED_2_5GT = 0x14, |
||
353 | PCIE_SPEED_5_0GT = 0x15, |
||
354 | PCIE_SPEED_8_0GT = 0x16, |
||
355 | PCI_SPEED_UNKNOWN = 0xff, |
||
356 | }; |
||
1408 | serge | 357 | |
5270 | serge | 358 | struct pci_cap_saved_data { |
359 | u16 cap_nr; |
||
360 | bool cap_extended; |
||
361 | unsigned int size; |
||
362 | u32 data[0]; |
||
363 | }; |
||
364 | |||
365 | struct pci_cap_saved_state { |
||
366 | struct hlist_node next; |
||
367 | struct pci_cap_saved_data cap; |
||
368 | }; |
||
369 | |||
370 | struct pcie_link_state; |
||
371 | struct pci_vpd; |
||
372 | struct pci_sriov; |
||
373 | struct pci_ats; |
||
374 | |||
1408 | serge | 375 | /* |
376 | * The pci_dev structure is used to describe PCI devices. |
||
377 | */ |
||
378 | struct pci_dev { |
||
2161 | serge | 379 | struct list_head bus_list; /* node in per-bus list */ |
380 | struct pci_bus *bus; /* bus this device is on */ |
||
381 | struct pci_bus *subordinate; /* bus this device bridges to */ |
||
1408 | serge | 382 | |
2161 | serge | 383 | void *sysdata; /* hook for sys-specific extension */ |
1408 | serge | 384 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
2161 | serge | 385 | struct pci_slot *slot; /* Physical slot this device is in */ |
5270 | serge | 386 | u32 busnr; |
2161 | serge | 387 | unsigned int devfn; /* encoded device & function index */ |
388 | unsigned short vendor; |
||
389 | unsigned short device; |
||
390 | unsigned short subsystem_vendor; |
||
391 | unsigned short subsystem_device; |
||
392 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
||
393 | u8 revision; /* PCI revision, low byte of class word */ |
||
394 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
||
395 | u8 pcie_cap; /* PCI-E capability offset */ |
||
3031 | serge | 396 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
2161 | serge | 397 | u8 rom_base_reg; /* which config register controls the ROM */ |
398 | u8 pin; /* which interrupt pin this device uses */ |
||
3031 | serge | 399 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
1408 | serge | 400 | |
401 | // struct pci_driver *driver; /* which driver has allocated this device */ |
||
5270 | serge | 402 | u64 dma_mask; /* Mask of the bits of bus address this |
1408 | serge | 403 | device implements. Normally this is |
404 | 0xffffffff. You only need to change |
||
405 | this if your device has broken DMA |
||
406 | or supports 64-bit transfers. */ |
||
407 | |||
408 | // struct device_dma_parameters dma_parms; |
||
409 | |||
2161 | serge | 410 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
411 | this is D0-D3, D0 being fully functional, |
||
412 | and D3 being off. */ |
||
3747 | Serge | 413 | u8 pm_cap; /* PM capability offset */ |
1408 | serge | 414 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
415 | can be generated */ |
||
2161 | serge | 416 | unsigned int pme_interrupt:1; |
3031 | serge | 417 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
1408 | serge | 418 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
419 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
||
3031 | serge | 420 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
421 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
||
422 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
||
2161 | serge | 423 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
424 | decoding during bar sizing */ |
||
425 | unsigned int wakeup_prepared:1; |
||
3031 | serge | 426 | unsigned int runtime_d3cold:1; /* whether go through runtime |
427 | D3cold, not set for devices |
||
428 | powered on/off by the |
||
429 | corresponding bridge */ |
||
2161 | serge | 430 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
3031 | serge | 431 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1408 | serge | 432 | |
3031 | serge | 433 | #ifdef CONFIG_PCIEASPM |
434 | struct pcie_link_state *link_state; /* ASPM link state. */ |
||
435 | #endif |
||
2161 | serge | 436 | |
437 | pci_channel_state_t error_state; /* current connectivity state */ |
||
1430 | serge | 438 | struct device dev; /* Generic device interface */ |
3747 | Serge | 439 | |
2161 | serge | 440 | int cfg_size; /* Size of configuration space */ |
1408 | serge | 441 | |
442 | /* |
||
443 | * Instead of touching interrupt line and base address registers |
||
444 | * directly, use the values stored here. They might be different! |
||
445 | */ |
||
446 | unsigned int irq; |
||
447 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
||
448 | |||
449 | /* These fields are used by common fixups */ |
||
450 | unsigned int transparent:1; /* Transparent PCI bridge */ |
||
451 | unsigned int multifunction:1;/* Part of multi-function device */ |
||
452 | /* keep track of device state */ |
||
453 | unsigned int is_added:1; |
||
454 | unsigned int is_busmaster:1; /* device is busmaster */ |
||
455 | unsigned int no_msi:1; /* device may not use msi */ |
||
3031 | serge | 456 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
1408 | serge | 457 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
458 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
||
459 | unsigned int msi_enabled:1; |
||
460 | unsigned int msix_enabled:1; |
||
2161 | serge | 461 | unsigned int ari_enabled:1; /* ARI forwarding */ |
1408 | serge | 462 | unsigned int is_managed:1; |
2161 | serge | 463 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
464 | Use pci_is_pcie() instead */ |
||
465 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
||
1408 | serge | 466 | unsigned int state_saved:1; |
467 | unsigned int is_physfn:1; |
||
468 | unsigned int is_virtfn:1; |
||
2161 | serge | 469 | unsigned int reset_fn:1; |
470 | unsigned int is_hotplug_bridge:1; |
||
3031 | serge | 471 | unsigned int __aer_firmware_first_valid:1; |
472 | unsigned int __aer_firmware_first:1; |
||
473 | unsigned int broken_intx_masking:1; |
||
474 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
||
475 | // pci_dev_flags_t dev_flags; |
||
476 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
||
1408 | serge | 477 | |
3031 | serge | 478 | |
479 | |||
1408 | serge | 480 | }; |
481 | |||
482 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
||
483 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
||
484 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
||
485 | #define pci_resource_len(dev,bar) \ |
||
486 | ((pci_resource_start((dev), (bar)) == 0 && \ |
||
487 | pci_resource_end((dev), (bar)) == \ |
||
488 | pci_resource_start((dev), (bar))) ? 0 : \ |
||
489 | \ |
||
490 | (pci_resource_end((dev), (bar)) - \ |
||
491 | pci_resource_start((dev), (bar)) + 1)) |
||
492 | |||
5056 | serge | 493 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
1408 | serge | 494 | |
2161 | serge | 495 | struct pci_bus { |
496 | struct list_head node; /* node in list of buses */ |
||
497 | struct pci_bus *parent; /* parent bus this bridge is on */ |
||
498 | struct list_head children; /* list of child buses */ |
||
499 | struct list_head devices; /* list of devices on this bus */ |
||
500 | struct pci_dev *self; /* bridge device as seen by parent */ |
||
501 | struct list_head slots; /* list of slots on this bus */ |
||
502 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
||
503 | struct list_head resources; /* address space routed to this bus */ |
||
3031 | serge | 504 | struct resource busn_res; /* bus numbers routed to this bus */ |
1964 | serge | 505 | |
2161 | serge | 506 | struct pci_ops *ops; /* configuration access functions */ |
507 | void *sysdata; /* hook for sys-specific extension */ |
||
508 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
||
1964 | serge | 509 | |
2161 | serge | 510 | unsigned char number; /* bus number */ |
511 | unsigned char primary; /* number of primary bridge */ |
||
512 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
||
513 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
||
514 | |||
515 | char name[48]; |
||
516 | |||
517 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
||
5056 | serge | 518 | pci_bus_flags_t bus_flags; /* inherited by child buses */ |
2161 | serge | 519 | struct device *bridge; |
520 | struct device dev; |
||
521 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
||
522 | struct bin_attribute *legacy_mem; /* legacy mem */ |
||
523 | unsigned int is_added:1; |
||
524 | }; |
||
525 | |||
526 | |||
527 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
||
528 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
||
529 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
||
530 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
||
531 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
||
532 | |||
533 | |||
534 | /* Low-level architecture-dependent routines */ |
||
535 | |||
536 | struct pci_sysdata { |
||
537 | int domain; /* PCI domain */ |
||
538 | int node; /* NUMA node */ |
||
539 | }; |
||
540 | |||
541 | |||
542 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
||
543 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
||
544 | |||
545 | /* |
||
5056 | serge | 546 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
2161 | serge | 547 | * false otherwise |
5056 | serge | 548 | * |
549 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. |
||
550 | * This is incorrect because "virtual" buses added for SR-IOV (via |
||
551 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. |
||
2161 | serge | 552 | */ |
553 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
||
554 | { |
||
555 | return !(pbus->parent); |
||
556 | } |
||
557 | |||
558 | struct pci_bus * |
||
559 | pci_find_next_bus(const struct pci_bus *from); |
||
560 | |||
561 | |||
562 | /* |
||
563 | * Error values that may be returned by PCI functions. |
||
564 | */ |
||
565 | #define PCIBIOS_SUCCESSFUL 0x00 |
||
566 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
||
567 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
||
568 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
||
569 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
||
570 | #define PCIBIOS_SET_FAILED 0x88 |
||
571 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
||
572 | |||
5056 | serge | 573 | /* |
574 | * Translate above to generic errno for passing back through non-PCI code. |
||
575 | */ |
||
576 | static inline int pcibios_err_to_errno(int err) |
||
577 | { |
||
578 | if (err <= PCIBIOS_SUCCESSFUL) |
||
579 | return err; /* Assume already errno */ |
||
580 | |||
581 | switch (err) { |
||
582 | case PCIBIOS_FUNC_NOT_SUPPORTED: |
||
583 | return -ENOENT; |
||
584 | case PCIBIOS_BAD_VENDOR_ID: |
||
5270 | serge | 585 | return -ENOTTY; |
5056 | serge | 586 | case PCIBIOS_DEVICE_NOT_FOUND: |
587 | return -ENODEV; |
||
588 | case PCIBIOS_BAD_REGISTER_NUMBER: |
||
589 | return -EFAULT; |
||
590 | case PCIBIOS_SET_FAILED: |
||
591 | return -EIO; |
||
592 | case PCIBIOS_BUFFER_TOO_SMALL: |
||
593 | return -ENOSPC; |
||
594 | } |
||
595 | |||
5270 | serge | 596 | return -ERANGE; |
5056 | serge | 597 | } |
598 | |||
2161 | serge | 599 | /* Low-level architecture-dependent routines */ |
600 | |||
601 | struct pci_ops { |
||
602 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
||
603 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
||
604 | }; |
||
605 | |||
5270 | serge | 606 | /* |
607 | * ACPI needs to be able to access PCI config space before we've done a |
||
608 | * PCI bus scan and created pci_bus structures. |
||
609 | */ |
||
610 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
||
611 | int reg, int len, u32 *val); |
||
612 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, |
||
613 | int reg, int len, u32 val); |
||
2161 | serge | 614 | |
5270 | serge | 615 | struct pci_bus_region { |
616 | dma_addr_t start; |
||
617 | dma_addr_t end; |
||
618 | }; |
||
619 | |||
2161 | serge | 620 | enum pci_bar_type { |
621 | pci_bar_unknown, /* Standard PCI BAR probe */ |
||
622 | pci_bar_io, /* An io port BAR */ |
||
623 | pci_bar_mem32, /* A 32-bit memory BAR */ |
||
624 | pci_bar_mem64, /* A 64-bit memory BAR */ |
||
625 | }; |
||
626 | |||
627 | /* |
||
628 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
||
629 | * a PCI domain is defined to be a set of PCI busses which share |
||
630 | * configuration space. |
||
631 | */ |
||
632 | #ifdef CONFIG_PCI_DOMAINS |
||
633 | extern int pci_domains_supported; |
||
634 | #else |
||
635 | enum { pci_domains_supported = 0 }; |
||
636 | static inline int pci_domain_nr(struct pci_bus *bus) |
||
637 | { |
||
638 | return 0; |
||
639 | } |
||
640 | |||
641 | static inline int pci_proc_domain(struct pci_bus *bus) |
||
642 | { |
||
643 | return 0; |
||
644 | } |
||
645 | #endif /* CONFIG_PCI_DOMAINS */ |
||
646 | |||
647 | /** |
||
648 | * pci_pcie_cap - get the saved PCIe capability offset |
||
649 | * @dev: PCI device |
||
650 | * |
||
651 | * PCIe capability offset is calculated at PCI device initialization |
||
652 | * time and saved in the data structure. This function returns saved |
||
653 | * PCIe capability offset. Using this instead of pci_find_capability() |
||
654 | * reduces unnecessary search in the PCI configuration space. If you |
||
655 | * need to calculate PCIe capability offset from raw device for some |
||
656 | * reasons, please use pci_find_capability() instead. |
||
657 | */ |
||
658 | static inline int pci_pcie_cap(struct pci_dev *dev) |
||
659 | { |
||
660 | return dev->pcie_cap; |
||
661 | } |
||
662 | |||
663 | /** |
||
664 | * pci_is_pcie - check if the PCI device is PCI Express capable |
||
665 | * @dev: PCI device |
||
666 | * |
||
5056 | serge | 667 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
2161 | serge | 668 | */ |
669 | static inline bool pci_is_pcie(struct pci_dev *dev) |
||
670 | { |
||
671 | return !!pci_pcie_cap(dev); |
||
672 | } |
||
673 | |||
3031 | serge | 674 | /** |
675 | * pci_pcie_type - get the PCIe device/port type |
||
676 | * @dev: PCI device |
||
677 | */ |
||
678 | static inline int pci_pcie_type(const struct pci_dev *dev) |
||
679 | { |
||
680 | return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
||
681 | } |
||
682 | |||
683 | |||
2161 | serge | 684 | static inline int pci_iov_init(struct pci_dev *dev) |
685 | { |
||
686 | return -ENODEV; |
||
687 | } |
||
688 | static inline void pci_iov_release(struct pci_dev *dev) |
||
689 | |||
690 | {} |
||
691 | |||
692 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
||
693 | enum pci_bar_type *type) |
||
694 | { |
||
695 | return 0; |
||
696 | } |
||
697 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
||
698 | { |
||
699 | } |
||
700 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
||
701 | { |
||
702 | return 0; |
||
703 | } |
||
704 | |||
705 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
||
706 | { |
||
707 | return -ENODEV; |
||
708 | } |
||
709 | static inline void pci_disable_ats(struct pci_dev *dev) |
||
710 | { |
||
711 | } |
||
712 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
||
713 | { |
||
714 | return -ENODEV; |
||
715 | } |
||
716 | static inline int pci_ats_enabled(struct pci_dev *dev) |
||
717 | { |
||
718 | return 0; |
||
719 | } |
||
720 | |||
721 | int pci_setup_device(struct pci_dev *dev); |
||
722 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
||
723 | struct resource *res, unsigned int reg); |
||
724 | int pci_resource_bar(struct pci_dev *dev, int resno, |
||
725 | enum pci_bar_type *type); |
||
726 | int pci_bus_add_child(struct pci_bus *bus); |
||
727 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
||
728 | |||
729 | |||
1408 | serge | 730 | typedef struct |
731 | { |
||
732 | struct list_head link; |
||
733 | struct pci_dev pci_dev; |
||
734 | }pci_dev_t; |
||
735 | |||
736 | int enum_pci_devices(void); |
||
737 | |||
2967 | Serge | 738 | const struct pci_device_id* |
739 | find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
||
1408 | serge | 740 | |
741 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
||
742 | |||
3391 | Serge | 743 | #define pci_set_dma_mask(a, b) 0 |
744 | #define pci_set_consistent_dma_mask(a, b) |
||
1408 | serge | 745 | |
2967 | Serge | 746 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
747 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
||
1408 | serge | 748 | |
2967 | Serge | 749 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); |
750 | |||
1964 | serge | 751 | #define pci_name(x) "radeon" |
1631 | serge | 752 | |
5056 | serge | 753 | static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
754 | { |
||
755 | return pdev->resource[bar].start; |
||
756 | } |
||
757 | |||
1408 | serge | 758 | #endif //__PCI__H__(n))-1)) |
759 | |||
760 |