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5270 | serge | 1 | #ifndef __LINUX_CACHE_H |
2 | #define __LINUX_CACHE_H |
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3 | |||
4 | #include |
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5 | #include |
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6 | |||
7 | #ifndef L1_CACHE_ALIGN |
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8 | #define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES) |
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9 | #endif |
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10 | |||
11 | #ifndef SMP_CACHE_BYTES |
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12 | #define SMP_CACHE_BYTES L1_CACHE_BYTES |
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13 | #endif |
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14 | |||
7143 | serge | 15 | /* |
16 | * __read_mostly is used to keep rarely changing variables out of frequently |
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17 | * updated cachelines. If an architecture doesn't support it, ignore the |
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18 | * hint. |
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19 | */ |
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5270 | serge | 20 | #ifndef __read_mostly |
21 | #define __read_mostly |
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22 | #endif |
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23 | |||
7143 | serge | 24 | /* |
25 | * __ro_after_init is used to mark things that are read-only after init (i.e. |
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26 | * after mark_rodata_ro() has been called). These are effectively read-only, |
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27 | * but may get written to during init, so can't live in .rodata (via "const"). |
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28 | */ |
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29 | #ifndef __ro_after_init |
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30 | #define __ro_after_init __attribute__((__section__(".data..ro_after_init"))) |
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31 | #endif |
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32 | |||
5270 | serge | 33 | #ifndef ____cacheline_aligned |
34 | #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) |
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35 | #endif |
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36 | |||
37 | #ifndef ____cacheline_aligned_in_smp |
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38 | #ifdef CONFIG_SMP |
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39 | #define ____cacheline_aligned_in_smp ____cacheline_aligned |
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40 | #else |
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41 | #define ____cacheline_aligned_in_smp |
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42 | #endif /* CONFIG_SMP */ |
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43 | #endif |
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44 | |||
45 | #ifndef __cacheline_aligned |
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46 | #define __cacheline_aligned \ |
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47 | __attribute__((__aligned__(SMP_CACHE_BYTES), \ |
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48 | __section__(".data..cacheline_aligned"))) |
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49 | #endif /* __cacheline_aligned */ |
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50 | |||
51 | #ifndef __cacheline_aligned_in_smp |
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52 | #ifdef CONFIG_SMP |
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53 | #define __cacheline_aligned_in_smp __cacheline_aligned |
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54 | #else |
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55 | #define __cacheline_aligned_in_smp |
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56 | #endif /* CONFIG_SMP */ |
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57 | #endif |
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58 | |||
59 | /* |
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60 | * The maximum alignment needed for some critical structures |
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61 | * These could be inter-node cacheline sizes/L3 cacheline |
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62 | * size etc. Define this in asm/cache.h for your arch |
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63 | */ |
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64 | #ifndef INTERNODE_CACHE_SHIFT |
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65 | #define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT |
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66 | #endif |
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67 | |||
68 | #if !defined(____cacheline_internodealigned_in_smp) |
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69 | #if defined(CONFIG_SMP) |
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70 | #define ____cacheline_internodealigned_in_smp \ |
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71 | __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT)))) |
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72 | #else |
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73 | #define ____cacheline_internodealigned_in_smp |
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74 | #endif |
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75 | #endif |
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76 | |||
77 | #ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE |
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78 | #define cache_line_size() L1_CACHE_BYTES |
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79 | #endif |
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80 | |||
81 | #endif /* __LINUX_CACHE_H */><> |