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3262 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | /* |
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28 | * Authors: Thomas Hellstrom |
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29 | */ |
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30 | |||
31 | #ifndef _TTM_PLACEMENT_H_ |
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32 | #define _TTM_PLACEMENT_H_ |
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33 | /* |
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34 | * Memory regions for data placement. |
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35 | */ |
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36 | |||
37 | #define TTM_PL_SYSTEM 0 |
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38 | #define TTM_PL_TT 1 |
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39 | #define TTM_PL_VRAM 2 |
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40 | #define TTM_PL_PRIV0 3 |
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41 | #define TTM_PL_PRIV1 4 |
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42 | #define TTM_PL_PRIV2 5 |
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43 | #define TTM_PL_PRIV3 6 |
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44 | #define TTM_PL_PRIV4 7 |
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45 | #define TTM_PL_PRIV5 8 |
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46 | #define TTM_PL_SWAPPED 15 |
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47 | |||
48 | #define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM) |
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49 | #define TTM_PL_FLAG_TT (1 << TTM_PL_TT) |
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50 | #define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM) |
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51 | #define TTM_PL_FLAG_PRIV0 (1 << TTM_PL_PRIV0) |
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52 | #define TTM_PL_FLAG_PRIV1 (1 << TTM_PL_PRIV1) |
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53 | #define TTM_PL_FLAG_PRIV2 (1 << TTM_PL_PRIV2) |
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54 | #define TTM_PL_FLAG_PRIV3 (1 << TTM_PL_PRIV3) |
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55 | #define TTM_PL_FLAG_PRIV4 (1 << TTM_PL_PRIV4) |
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56 | #define TTM_PL_FLAG_PRIV5 (1 << TTM_PL_PRIV5) |
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57 | #define TTM_PL_FLAG_SWAPPED (1 << TTM_PL_SWAPPED) |
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58 | #define TTM_PL_MASK_MEM 0x0000FFFF |
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59 | |||
60 | /* |
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61 | * Other flags that affects data placement. |
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62 | * TTM_PL_FLAG_CACHED indicates cache-coherent mappings |
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63 | * if available. |
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64 | * TTM_PL_FLAG_SHARED means that another application may |
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65 | * reference the buffer. |
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66 | * TTM_PL_FLAG_NO_EVICT means that the buffer may never |
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67 | * be evicted to make room for other buffers. |
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68 | */ |
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69 | |||
70 | #define TTM_PL_FLAG_CACHED (1 << 16) |
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71 | #define TTM_PL_FLAG_UNCACHED (1 << 17) |
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72 | #define TTM_PL_FLAG_WC (1 << 18) |
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73 | #define TTM_PL_FLAG_SHARED (1 << 20) |
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74 | #define TTM_PL_FLAG_NO_EVICT (1 << 21) |
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75 | |||
76 | #define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \ |
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77 | TTM_PL_FLAG_UNCACHED | \ |
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78 | TTM_PL_FLAG_WC) |
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79 | |||
80 | #define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING) |
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81 | |||
82 | /* |
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83 | * Access flags to be used for CPU- and GPU- mappings. |
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84 | * The idea is that the TTM synchronization mechanism will |
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85 | * allow concurrent READ access and exclusive write access. |
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86 | * Currently GPU- and CPU accesses are exclusive. |
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87 | */ |
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88 | |||
89 | #define TTM_ACCESS_READ (1 << 0) |
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90 | #define TTM_ACCESS_WRITE (1 << 1) |
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91 | |||
92 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |