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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1408 | serge | 1 | /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- |
| 2 | * |
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| 3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
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| 4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
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| 5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. |
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| 6 | * All rights reserved. |
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| 7 | * |
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| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 9 | * copy of this software and associated documentation files (the "Software"), |
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| 10 | * to deal in the Software without restriction, including without limitation |
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| 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 12 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 13 | * Software is furnished to do so, subject to the following conditions: |
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| 14 | * |
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| 15 | * The above copyright notice and this permission notice (including the next |
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| 16 | * paragraph) shall be included in all copies or substantial portions of the |
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| 17 | * Software. |
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| 18 | * |
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| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 25 | * DEALINGS IN THE SOFTWARE. |
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| 26 | * |
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| 27 | * Authors: |
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| 28 | * Kevin E. Martin |
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| 29 | * Gareth Hughes |
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| 30 | * Keith Whitwell |
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| 31 | */ |
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| 32 | |||
| 33 | #ifndef __RADEON_DRM_H__ |
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| 34 | #define __RADEON_DRM_H__ |
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| 35 | |||
| 36 | #include "drm.h" |
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| 37 | |||
| 38 | /* WARNING: If you change any of these defines, make sure to change the |
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| 39 | * defines in the X server file (radeon_sarea.h) |
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| 40 | */ |
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| 41 | #ifndef __RADEON_SAREA_DEFINES__ |
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| 42 | #define __RADEON_SAREA_DEFINES__ |
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| 43 | |||
| 44 | /* Old style state flags, required for sarea interface (1.1 and 1.2 |
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| 45 | * clears) and 1.2 drm_vertex2 ioctl. |
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| 46 | */ |
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| 47 | #define RADEON_UPLOAD_CONTEXT 0x00000001 |
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| 48 | #define RADEON_UPLOAD_VERTFMT 0x00000002 |
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| 49 | #define RADEON_UPLOAD_LINE 0x00000004 |
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| 50 | #define RADEON_UPLOAD_BUMPMAP 0x00000008 |
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| 51 | #define RADEON_UPLOAD_MASKS 0x00000010 |
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| 52 | #define RADEON_UPLOAD_VIEWPORT 0x00000020 |
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| 53 | #define RADEON_UPLOAD_SETUP 0x00000040 |
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| 54 | #define RADEON_UPLOAD_TCL 0x00000080 |
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| 55 | #define RADEON_UPLOAD_MISC 0x00000100 |
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| 56 | #define RADEON_UPLOAD_TEX0 0x00000200 |
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| 57 | #define RADEON_UPLOAD_TEX1 0x00000400 |
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| 58 | #define RADEON_UPLOAD_TEX2 0x00000800 |
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| 59 | #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 |
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| 60 | #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 |
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| 61 | #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 |
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| 62 | #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ |
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| 63 | #define RADEON_REQUIRE_QUIESCENCE 0x00010000 |
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| 64 | #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ |
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| 65 | #define RADEON_UPLOAD_ALL 0x003effff |
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| 66 | #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff |
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| 67 | |||
| 68 | /* New style per-packet identifiers for use in cmd_buffer ioctl with |
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| 69 | * the RADEON_EMIT_PACKET command. Comments relate new packets to old |
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| 70 | * state bits and the packet size: |
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| 71 | */ |
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| 72 | #define RADEON_EMIT_PP_MISC 0 /* context/7 */ |
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| 73 | #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ |
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| 74 | #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ |
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| 75 | #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ |
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| 76 | #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ |
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| 77 | #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ |
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| 78 | #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ |
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| 79 | #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ |
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| 80 | #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ |
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| 81 | #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ |
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| 82 | #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ |
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| 83 | #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ |
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| 84 | #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ |
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| 85 | #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ |
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| 86 | #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ |
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| 87 | #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ |
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| 88 | #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ |
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| 89 | #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ |
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| 90 | #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ |
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| 91 | #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ |
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| 92 | #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ |
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| 93 | #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ |
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| 94 | #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ |
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| 95 | #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ |
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| 96 | #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ |
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| 97 | #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ |
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| 98 | #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ |
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| 99 | #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ |
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| 100 | #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ |
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| 101 | #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ |
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| 102 | #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ |
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| 103 | #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ |
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| 104 | #define R200_EMIT_VAP_CTL 32 /* vap/1 */ |
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| 105 | #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ |
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| 106 | #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ |
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| 107 | #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ |
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| 108 | #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ |
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| 109 | #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ |
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| 110 | #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ |
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| 111 | #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ |
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| 112 | #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ |
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| 113 | #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ |
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| 114 | #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ |
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| 115 | #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ |
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| 116 | #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ |
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| 117 | #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ |
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| 118 | #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ |
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| 119 | #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ |
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| 120 | #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ |
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| 121 | #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ |
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| 122 | #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ |
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| 123 | #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ |
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| 124 | #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ |
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| 125 | #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ |
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| 126 | #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ |
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| 127 | #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ |
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| 128 | #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ |
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| 129 | #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ |
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| 130 | #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ |
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| 131 | #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ |
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| 132 | #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ |
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| 133 | #define R200_EMIT_PP_CUBIC_FACES_0 61 |
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| 134 | #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 |
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| 135 | #define R200_EMIT_PP_CUBIC_FACES_1 63 |
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| 136 | #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 |
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| 137 | #define R200_EMIT_PP_CUBIC_FACES_2 65 |
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| 138 | #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 |
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| 139 | #define R200_EMIT_PP_CUBIC_FACES_3 67 |
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| 140 | #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 |
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| 141 | #define R200_EMIT_PP_CUBIC_FACES_4 69 |
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| 142 | #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 |
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| 143 | #define R200_EMIT_PP_CUBIC_FACES_5 71 |
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| 144 | #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 |
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| 145 | #define RADEON_EMIT_PP_TEX_SIZE_0 73 |
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| 146 | #define RADEON_EMIT_PP_TEX_SIZE_1 74 |
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| 147 | #define RADEON_EMIT_PP_TEX_SIZE_2 75 |
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| 148 | #define R200_EMIT_RB3D_BLENDCOLOR 76 |
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| 149 | #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 |
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| 150 | #define RADEON_EMIT_PP_CUBIC_FACES_0 78 |
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| 151 | #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 |
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| 152 | #define RADEON_EMIT_PP_CUBIC_FACES_1 80 |
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| 153 | #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 |
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| 154 | #define RADEON_EMIT_PP_CUBIC_FACES_2 82 |
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| 155 | #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 |
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| 156 | #define R200_EMIT_PP_TRI_PERF_CNTL 84 |
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| 157 | #define R200_EMIT_PP_AFS_0 85 |
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| 158 | #define R200_EMIT_PP_AFS_1 86 |
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| 159 | #define R200_EMIT_ATF_TFACTOR 87 |
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| 160 | #define R200_EMIT_PP_TXCTLALL_0 88 |
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| 161 | #define R200_EMIT_PP_TXCTLALL_1 89 |
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| 162 | #define R200_EMIT_PP_TXCTLALL_2 90 |
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| 163 | #define R200_EMIT_PP_TXCTLALL_3 91 |
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| 164 | #define R200_EMIT_PP_TXCTLALL_4 92 |
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| 165 | #define R200_EMIT_PP_TXCTLALL_5 93 |
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| 166 | #define R200_EMIT_VAP_PVS_CNTL 94 |
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| 167 | #define RADEON_MAX_STATE_PACKETS 95 |
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| 168 | |||
| 169 | /* Commands understood by cmd_buffer ioctl. More can be added but |
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| 170 | * obviously these can't be removed or changed: |
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| 171 | */ |
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| 172 | #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ |
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| 173 | #define RADEON_CMD_SCALARS 2 /* emit scalar data */ |
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| 174 | #define RADEON_CMD_VECTORS 3 /* emit vector data */ |
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| 175 | #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ |
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| 176 | #define RADEON_CMD_PACKET3 5 /* emit hw packet */ |
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| 177 | #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ |
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| 178 | #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ |
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| 179 | #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: |
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| 180 | * doesn't make the cpu wait, just |
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| 181 | * the graphics hardware */ |
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| 182 | #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ |
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| 183 | |||
| 184 | typedef union { |
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| 185 | int i; |
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| 186 | struct { |
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| 187 | unsigned char cmd_type, pad0, pad1, pad2; |
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| 188 | } header; |
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| 189 | struct { |
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| 190 | unsigned char cmd_type, packet_id, pad0, pad1; |
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| 191 | } packet; |
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| 192 | struct { |
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| 193 | unsigned char cmd_type, offset, stride, count; |
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| 194 | } scalars; |
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| 195 | struct { |
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| 196 | unsigned char cmd_type, offset, stride, count; |
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| 197 | } vectors; |
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| 198 | struct { |
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| 199 | unsigned char cmd_type, addr_lo, addr_hi, count; |
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| 200 | } veclinear; |
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| 201 | struct { |
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| 202 | unsigned char cmd_type, buf_idx, pad0, pad1; |
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| 203 | } dma; |
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| 204 | struct { |
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| 205 | unsigned char cmd_type, flags, pad0, pad1; |
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| 206 | } wait; |
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| 207 | } drm_radeon_cmd_header_t; |
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| 208 | |||
| 209 | #define RADEON_WAIT_2D 0x1 |
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| 210 | #define RADEON_WAIT_3D 0x2 |
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| 211 | |||
| 212 | /* Allowed parameters for R300_CMD_PACKET3 |
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| 213 | */ |
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| 214 | #define R300_CMD_PACKET3_CLEAR 0 |
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| 215 | #define R300_CMD_PACKET3_RAW 1 |
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| 216 | |||
| 217 | /* Commands understood by cmd_buffer ioctl for R300. |
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| 218 | * The interface has not been stabilized, so some of these may be removed |
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| 219 | * and eventually reordered before stabilization. |
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| 220 | */ |
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| 221 | #define R300_CMD_PACKET0 1 |
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| 222 | #define R300_CMD_VPU 2 /* emit vertex program upload */ |
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| 223 | #define R300_CMD_PACKET3 3 /* emit a packet3 */ |
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| 224 | #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ |
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| 225 | #define R300_CMD_CP_DELAY 5 |
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| 226 | #define R300_CMD_DMA_DISCARD 6 |
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| 227 | #define R300_CMD_WAIT 7 |
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| 228 | # define R300_WAIT_2D 0x1 |
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| 229 | # define R300_WAIT_3D 0x2 |
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| 230 | /* these two defines are DOING IT WRONG - however |
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| 231 | * we have userspace which relies on using these. |
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| 232 | * The wait interface is backwards compat new |
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| 233 | * code should use the NEW_WAIT defines below |
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| 234 | * THESE ARE NOT BIT FIELDS |
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| 235 | */ |
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| 236 | # define R300_WAIT_2D_CLEAN 0x3 |
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| 237 | # define R300_WAIT_3D_CLEAN 0x4 |
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| 238 | |||
| 239 | # define R300_NEW_WAIT_2D_3D 0x3 |
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| 240 | # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 |
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| 241 | # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 |
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| 242 | # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 |
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| 243 | |||
| 244 | #define R300_CMD_SCRATCH 8 |
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| 245 | #define R300_CMD_R500FP 9 |
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| 246 | |||
| 247 | typedef union { |
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| 248 | unsigned int u; |
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| 249 | struct { |
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| 250 | unsigned char cmd_type, pad0, pad1, pad2; |
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| 251 | } header; |
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| 252 | struct { |
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| 253 | unsigned char cmd_type, count, reglo, reghi; |
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| 254 | } packet0; |
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| 255 | struct { |
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| 256 | unsigned char cmd_type, count, adrlo, adrhi; |
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| 257 | } vpu; |
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| 258 | struct { |
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| 259 | unsigned char cmd_type, packet, pad0, pad1; |
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| 260 | } packet3; |
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| 261 | struct { |
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| 262 | unsigned char cmd_type, packet; |
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| 263 | unsigned short count; /* amount of packet2 to emit */ |
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| 264 | } delay; |
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| 265 | struct { |
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| 266 | unsigned char cmd_type, buf_idx, pad0, pad1; |
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| 267 | } dma; |
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| 268 | struct { |
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| 269 | unsigned char cmd_type, flags, pad0, pad1; |
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| 270 | } wait; |
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| 271 | struct { |
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| 272 | unsigned char cmd_type, reg, n_bufs, flags; |
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| 273 | } scratch; |
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| 274 | struct { |
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| 275 | unsigned char cmd_type, count, adrlo, adrhi_flags; |
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| 276 | } r500fp; |
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| 277 | } drm_r300_cmd_header_t; |
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| 278 | |||
| 279 | #define RADEON_FRONT 0x1 |
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| 280 | #define RADEON_BACK 0x2 |
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| 281 | #define RADEON_DEPTH 0x4 |
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| 282 | #define RADEON_STENCIL 0x8 |
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| 283 | #define RADEON_CLEAR_FASTZ 0x80000000 |
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| 284 | #define RADEON_USE_HIERZ 0x40000000 |
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| 285 | #define RADEON_USE_COMP_ZBUF 0x20000000 |
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| 286 | |||
| 287 | #define R500FP_CONSTANT_TYPE (1 << 1) |
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| 288 | #define R500FP_CONSTANT_CLAMP (1 << 2) |
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| 289 | |||
| 290 | /* Primitive types |
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| 291 | */ |
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| 292 | #define RADEON_POINTS 0x1 |
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| 293 | #define RADEON_LINES 0x2 |
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| 294 | #define RADEON_LINE_STRIP 0x3 |
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| 295 | #define RADEON_TRIANGLES 0x4 |
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| 296 | #define RADEON_TRIANGLE_FAN 0x5 |
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| 297 | #define RADEON_TRIANGLE_STRIP 0x6 |
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| 298 | |||
| 299 | /* Vertex/indirect buffer size |
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| 300 | */ |
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| 301 | #define RADEON_BUFFER_SIZE 65536 |
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| 302 | |||
| 303 | /* Byte offsets for indirect buffer data |
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| 304 | */ |
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| 305 | #define RADEON_INDEX_PRIM_OFFSET 20 |
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| 306 | |||
| 307 | #define RADEON_SCRATCH_REG_OFFSET 32 |
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| 308 | |||
| 309 | #define R600_SCRATCH_REG_OFFSET 256 |
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| 310 | |||
| 311 | #define RADEON_NR_SAREA_CLIPRECTS 12 |
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| 312 | |||
| 313 | /* There are 2 heaps (local/GART). Each region within a heap is a |
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| 314 | * minimum of 64k, and there are at most 64 of them per heap. |
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| 315 | */ |
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| 316 | #define RADEON_LOCAL_TEX_HEAP 0 |
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| 317 | #define RADEON_GART_TEX_HEAP 1 |
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| 318 | #define RADEON_NR_TEX_HEAPS 2 |
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| 319 | #define RADEON_NR_TEX_REGIONS 64 |
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| 320 | #define RADEON_LOG_TEX_GRANULARITY 16 |
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| 321 | |||
| 322 | #define RADEON_MAX_TEXTURE_LEVELS 12 |
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| 323 | #define RADEON_MAX_TEXTURE_UNITS 3 |
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| 324 | |||
| 325 | #define RADEON_MAX_SURFACES 8 |
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| 326 | |||
| 327 | /* Blits have strict offset rules. All blit offset must be aligned on |
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| 328 | * a 1K-byte boundary. |
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| 329 | */ |
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| 330 | #define RADEON_OFFSET_SHIFT 10 |
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| 331 | #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) |
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| 332 | #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) |
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| 333 | |||
| 334 | #endif /* __RADEON_SAREA_DEFINES__ */ |
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| 335 | |||
| 336 | typedef struct { |
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| 337 | unsigned int red; |
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| 338 | unsigned int green; |
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| 339 | unsigned int blue; |
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| 340 | unsigned int alpha; |
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| 341 | } radeon_color_regs_t; |
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| 342 | |||
| 343 | typedef struct { |
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| 344 | /* Context state */ |
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| 345 | unsigned int pp_misc; /* 0x1c14 */ |
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| 346 | unsigned int pp_fog_color; |
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| 347 | unsigned int re_solid_color; |
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| 348 | unsigned int rb3d_blendcntl; |
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| 349 | unsigned int rb3d_depthoffset; |
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| 350 | unsigned int rb3d_depthpitch; |
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| 351 | unsigned int rb3d_zstencilcntl; |
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| 352 | |||
| 353 | unsigned int pp_cntl; /* 0x1c38 */ |
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| 354 | unsigned int rb3d_cntl; |
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| 355 | unsigned int rb3d_coloroffset; |
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| 356 | unsigned int re_width_height; |
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| 357 | unsigned int rb3d_colorpitch; |
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| 358 | unsigned int se_cntl; |
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| 359 | |||
| 360 | /* Vertex format state */ |
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| 361 | unsigned int se_coord_fmt; /* 0x1c50 */ |
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| 362 | |||
| 363 | /* Line state */ |
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| 364 | unsigned int re_line_pattern; /* 0x1cd0 */ |
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| 365 | unsigned int re_line_state; |
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| 366 | |||
| 367 | unsigned int se_line_width; /* 0x1db8 */ |
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| 368 | |||
| 369 | /* Bumpmap state */ |
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| 370 | unsigned int pp_lum_matrix; /* 0x1d00 */ |
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| 371 | |||
| 372 | unsigned int pp_rot_matrix_0; /* 0x1d58 */ |
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| 373 | unsigned int pp_rot_matrix_1; |
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| 374 | |||
| 375 | /* Mask state */ |
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| 376 | unsigned int rb3d_stencilrefmask; /* 0x1d7c */ |
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| 377 | unsigned int rb3d_ropcntl; |
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| 378 | unsigned int rb3d_planemask; |
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| 379 | |||
| 380 | /* Viewport state */ |
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| 381 | unsigned int se_vport_xscale; /* 0x1d98 */ |
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| 382 | unsigned int se_vport_xoffset; |
||
| 383 | unsigned int se_vport_yscale; |
||
| 384 | unsigned int se_vport_yoffset; |
||
| 385 | unsigned int se_vport_zscale; |
||
| 386 | unsigned int se_vport_zoffset; |
||
| 387 | |||
| 388 | /* Setup state */ |
||
| 389 | unsigned int se_cntl_status; /* 0x2140 */ |
||
| 390 | |||
| 391 | /* Misc state */ |
||
| 392 | unsigned int re_top_left; /* 0x26c0 */ |
||
| 393 | unsigned int re_misc; |
||
| 394 | } drm_radeon_context_regs_t; |
||
| 395 | |||
| 396 | typedef struct { |
||
| 397 | /* Zbias state */ |
||
| 398 | unsigned int se_zbias_factor; /* 0x1dac */ |
||
| 399 | unsigned int se_zbias_constant; |
||
| 400 | } drm_radeon_context2_regs_t; |
||
| 401 | |||
| 402 | /* Setup registers for each texture unit |
||
| 403 | */ |
||
| 404 | typedef struct { |
||
| 405 | unsigned int pp_txfilter; |
||
| 406 | unsigned int pp_txformat; |
||
| 407 | unsigned int pp_txoffset; |
||
| 408 | unsigned int pp_txcblend; |
||
| 409 | unsigned int pp_txablend; |
||
| 410 | unsigned int pp_tfactor; |
||
| 411 | unsigned int pp_border_color; |
||
| 412 | } drm_radeon_texture_regs_t; |
||
| 413 | |||
| 414 | typedef struct { |
||
| 415 | unsigned int start; |
||
| 416 | unsigned int finish; |
||
| 417 | unsigned int prim:8; |
||
| 418 | unsigned int stateidx:8; |
||
| 419 | unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ |
||
| 420 | unsigned int vc_format; /* vertex format */ |
||
| 421 | } drm_radeon_prim_t; |
||
| 422 | |||
| 423 | typedef struct { |
||
| 424 | drm_radeon_context_regs_t context; |
||
| 425 | drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; |
||
| 426 | drm_radeon_context2_regs_t context2; |
||
| 427 | unsigned int dirty; |
||
| 428 | } drm_radeon_state_t; |
||
| 429 | |||
| 430 | typedef struct { |
||
| 431 | /* The channel for communication of state information to the |
||
| 432 | * kernel on firing a vertex buffer with either of the |
||
| 433 | * obsoleted vertex/index ioctls. |
||
| 434 | */ |
||
| 435 | drm_radeon_context_regs_t context_state; |
||
| 436 | drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; |
||
| 437 | unsigned int dirty; |
||
| 438 | unsigned int vertsize; |
||
| 439 | unsigned int vc_format; |
||
| 440 | |||
| 441 | /* The current cliprects, or a subset thereof. |
||
| 442 | */ |
||
| 443 | // struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; |
||
| 444 | unsigned int nbox; |
||
| 445 | |||
| 446 | /* Counters for client-side throttling of rendering clients. |
||
| 447 | */ |
||
| 448 | unsigned int last_frame; |
||
| 449 | unsigned int last_dispatch; |
||
| 450 | unsigned int last_clear; |
||
| 451 | |||
| 452 | // struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + |
||
| 453 | // 1]; |
||
| 454 | unsigned int tex_age[RADEON_NR_TEX_HEAPS]; |
||
| 455 | int ctx_owner; |
||
| 456 | int pfState; /* number of 3d windows (0,1,2ormore) */ |
||
| 457 | int pfCurrentPage; /* which buffer is being displayed? */ |
||
| 458 | int crtc2_base; /* CRTC2 frame offset */ |
||
| 459 | int tiling_enabled; /* set by drm, read by 2d + 3d clients */ |
||
| 460 | } drm_radeon_sarea_t; |
||
| 461 | |||
| 462 | /* WARNING: If you change any of these defines, make sure to change the |
||
| 463 | * defines in the Xserver file (xf86drmRadeon.h) |
||
| 464 | * |
||
| 465 | * KW: actually it's illegal to change any of this (backwards compatibility). |
||
| 466 | */ |
||
| 467 | |||
| 468 | /* Radeon specific ioctls |
||
| 469 | * The device specific ioctl range is 0x40 to 0x79. |
||
| 470 | */ |
||
| 471 | #define DRM_RADEON_CP_INIT 0x00 |
||
| 472 | #define DRM_RADEON_CP_START 0x01 |
||
| 473 | #define DRM_RADEON_CP_STOP 0x02 |
||
| 474 | #define DRM_RADEON_CP_RESET 0x03 |
||
| 475 | #define DRM_RADEON_CP_IDLE 0x04 |
||
| 476 | #define DRM_RADEON_RESET 0x05 |
||
| 477 | #define DRM_RADEON_FULLSCREEN 0x06 |
||
| 478 | #define DRM_RADEON_SWAP 0x07 |
||
| 479 | #define DRM_RADEON_CLEAR 0x08 |
||
| 480 | #define DRM_RADEON_VERTEX 0x09 |
||
| 481 | #define DRM_RADEON_INDICES 0x0A |
||
| 482 | #define DRM_RADEON_NOT_USED |
||
| 483 | #define DRM_RADEON_STIPPLE 0x0C |
||
| 484 | #define DRM_RADEON_INDIRECT 0x0D |
||
| 485 | #define DRM_RADEON_TEXTURE 0x0E |
||
| 486 | #define DRM_RADEON_VERTEX2 0x0F |
||
| 487 | #define DRM_RADEON_CMDBUF 0x10 |
||
| 488 | #define DRM_RADEON_GETPARAM 0x11 |
||
| 489 | #define DRM_RADEON_FLIP 0x12 |
||
| 490 | #define DRM_RADEON_ALLOC 0x13 |
||
| 491 | #define DRM_RADEON_FREE 0x14 |
||
| 492 | #define DRM_RADEON_INIT_HEAP 0x15 |
||
| 493 | #define DRM_RADEON_IRQ_EMIT 0x16 |
||
| 494 | #define DRM_RADEON_IRQ_WAIT 0x17 |
||
| 495 | #define DRM_RADEON_CP_RESUME 0x18 |
||
| 496 | #define DRM_RADEON_SETPARAM 0x19 |
||
| 497 | #define DRM_RADEON_SURF_ALLOC 0x1a |
||
| 498 | #define DRM_RADEON_SURF_FREE 0x1b |
||
| 499 | /* KMS ioctl */ |
||
| 500 | #define DRM_RADEON_GEM_INFO 0x1c |
||
| 501 | #define DRM_RADEON_GEM_CREATE 0x1d |
||
| 502 | #define DRM_RADEON_GEM_MMAP 0x1e |
||
| 503 | #define DRM_RADEON_GEM_PREAD 0x21 |
||
| 504 | #define DRM_RADEON_GEM_PWRITE 0x22 |
||
| 505 | #define DRM_RADEON_GEM_SET_DOMAIN 0x23 |
||
| 506 | #define DRM_RADEON_GEM_WAIT_IDLE 0x24 |
||
| 507 | #define DRM_RADEON_CS 0x26 |
||
| 508 | #define DRM_RADEON_INFO 0x27 |
||
| 509 | #define DRM_RADEON_GEM_SET_TILING 0x28 |
||
| 510 | #define DRM_RADEON_GEM_GET_TILING 0x29 |
||
| 511 | #define DRM_RADEON_GEM_BUSY 0x2a |
||
| 512 | |||
| 513 | #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) |
||
| 514 | #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) |
||
| 515 | #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) |
||
| 516 | #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) |
||
| 517 | #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) |
||
| 518 | #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) |
||
| 519 | #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) |
||
| 520 | #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) |
||
| 521 | #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) |
||
| 522 | #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) |
||
| 523 | #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) |
||
| 524 | #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) |
||
| 525 | #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) |
||
| 526 | #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) |
||
| 527 | #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) |
||
| 528 | #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) |
||
| 529 | #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) |
||
| 530 | #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) |
||
| 531 | #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) |
||
| 532 | #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) |
||
| 533 | #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) |
||
| 534 | #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) |
||
| 535 | #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) |
||
| 536 | #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) |
||
| 537 | #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) |
||
| 538 | #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) |
||
| 539 | #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) |
||
| 540 | /* KMS */ |
||
| 541 | #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) |
||
| 542 | #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) |
||
| 543 | #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) |
||
| 544 | #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) |
||
| 545 | #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) |
||
| 546 | #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) |
||
| 547 | #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) |
||
| 548 | #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) |
||
| 549 | #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) |
||
| 1964 | serge | 550 | #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) |
| 551 | #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) |
||
| 1408 | serge | 552 | #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) |
| 2967 | Serge | 553 | #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) |
| 1408 | serge | 554 | |
| 555 | typedef struct drm_radeon_init { |
||
| 556 | enum { |
||
| 557 | RADEON_INIT_CP = 0x01, |
||
| 558 | RADEON_CLEANUP_CP = 0x02, |
||
| 559 | RADEON_INIT_R200_CP = 0x03, |
||
| 560 | RADEON_INIT_R300_CP = 0x04, |
||
| 561 | RADEON_INIT_R600_CP = 0x05 |
||
| 562 | } func; |
||
| 563 | unsigned long sarea_priv_offset; |
||
| 564 | int is_pci; |
||
| 565 | int cp_mode; |
||
| 566 | int gart_size; |
||
| 567 | int ring_size; |
||
| 568 | int usec_timeout; |
||
| 569 | |||
| 570 | unsigned int fb_bpp; |
||
| 571 | unsigned int front_offset, front_pitch; |
||
| 572 | unsigned int back_offset, back_pitch; |
||
| 573 | unsigned int depth_bpp; |
||
| 574 | unsigned int depth_offset, depth_pitch; |
||
| 575 | |||
| 576 | unsigned long fb_offset; |
||
| 577 | unsigned long mmio_offset; |
||
| 578 | unsigned long ring_offset; |
||
| 579 | unsigned long ring_rptr_offset; |
||
| 580 | unsigned long buffers_offset; |
||
| 581 | unsigned long gart_textures_offset; |
||
| 582 | } drm_radeon_init_t; |
||
| 583 | |||
| 584 | typedef struct drm_radeon_cp_stop { |
||
| 585 | int flush; |
||
| 586 | int idle; |
||
| 587 | } drm_radeon_cp_stop_t; |
||
| 588 | |||
| 589 | typedef struct drm_radeon_fullscreen { |
||
| 590 | enum { |
||
| 591 | RADEON_INIT_FULLSCREEN = 0x01, |
||
| 592 | RADEON_CLEANUP_FULLSCREEN = 0x02 |
||
| 593 | } func; |
||
| 594 | } drm_radeon_fullscreen_t; |
||
| 595 | |||
| 596 | #define CLEAR_X1 0 |
||
| 597 | #define CLEAR_Y1 1 |
||
| 598 | #define CLEAR_X2 2 |
||
| 599 | #define CLEAR_Y2 3 |
||
| 600 | #define CLEAR_DEPTH 4 |
||
| 601 | |||
| 602 | typedef union drm_radeon_clear_rect { |
||
| 603 | float f[5]; |
||
| 604 | unsigned int ui[5]; |
||
| 605 | } drm_radeon_clear_rect_t; |
||
| 606 | |||
| 607 | typedef struct drm_radeon_clear { |
||
| 608 | unsigned int flags; |
||
| 609 | unsigned int clear_color; |
||
| 610 | unsigned int clear_depth; |
||
| 611 | unsigned int color_mask; |
||
| 612 | unsigned int depth_mask; /* misnamed field: should be stencil */ |
||
| 613 | // drm_radeon_clear_rect_t __user *depth_boxes; |
||
| 614 | } drm_radeon_clear_t; |
||
| 615 | |||
| 616 | typedef struct drm_radeon_vertex { |
||
| 617 | int prim; |
||
| 618 | int idx; /* Index of vertex buffer */ |
||
| 619 | int count; /* Number of vertices in buffer */ |
||
| 620 | int discard; /* Client finished with buffer? */ |
||
| 621 | } drm_radeon_vertex_t; |
||
| 622 | |||
| 623 | typedef struct drm_radeon_indices { |
||
| 624 | int prim; |
||
| 625 | int idx; |
||
| 626 | int start; |
||
| 627 | int end; |
||
| 628 | int discard; /* Client finished with buffer? */ |
||
| 629 | } drm_radeon_indices_t; |
||
| 630 | |||
| 631 | /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices |
||
| 632 | * - allows multiple primitives and state changes in a single ioctl |
||
| 633 | * - supports driver change to emit native primitives |
||
| 634 | */ |
||
| 635 | typedef struct drm_radeon_vertex2 { |
||
| 636 | int idx; /* Index of vertex buffer */ |
||
| 637 | int discard; /* Client finished with buffer? */ |
||
| 638 | int nr_states; |
||
| 639 | // drm_radeon_state_t __user *state; |
||
| 640 | int nr_prims; |
||
| 641 | // drm_radeon_prim_t __user *prim; |
||
| 642 | } drm_radeon_vertex2_t; |
||
| 643 | |||
| 644 | /* v1.3 - obsoletes drm_radeon_vertex2 |
||
| 1964 | serge | 645 | * - allows arbitrarily large cliprect list |
| 1408 | serge | 646 | * - allows updating of tcl packet, vector and scalar state |
| 647 | * - allows memory-efficient description of state updates |
||
| 648 | * - allows state to be emitted without a primitive |
||
| 649 | * (for clears, ctx switches) |
||
| 650 | * - allows more than one dma buffer to be referenced per ioctl |
||
| 651 | * - supports tcl driver |
||
| 652 | * - may be extended in future versions with new cmd types, packets |
||
| 653 | */ |
||
| 654 | typedef struct drm_radeon_cmd_buffer { |
||
| 655 | int bufsz; |
||
| 656 | char __user *buf; |
||
| 657 | int nbox; |
||
| 658 | struct drm_clip_rect __user *boxes; |
||
| 659 | } drm_radeon_cmd_buffer_t; |
||
| 660 | |||
| 661 | typedef struct drm_radeon_tex_image { |
||
| 662 | unsigned int x, y; /* Blit coordinates */ |
||
| 663 | unsigned int width, height; |
||
| 664 | const void __user *data; |
||
| 665 | } drm_radeon_tex_image_t; |
||
| 666 | |||
| 667 | typedef struct drm_radeon_texture { |
||
| 668 | unsigned int offset; |
||
| 669 | int pitch; |
||
| 670 | int format; |
||
| 671 | int width; /* Texture image coordinates */ |
||
| 672 | int height; |
||
| 673 | drm_radeon_tex_image_t __user *image; |
||
| 674 | } drm_radeon_texture_t; |
||
| 675 | |||
| 676 | typedef struct drm_radeon_stipple { |
||
| 677 | unsigned int __user *mask; |
||
| 678 | } drm_radeon_stipple_t; |
||
| 679 | |||
| 680 | typedef struct drm_radeon_indirect { |
||
| 681 | int idx; |
||
| 682 | int start; |
||
| 683 | int end; |
||
| 684 | int discard; |
||
| 685 | } drm_radeon_indirect_t; |
||
| 686 | |||
| 687 | /* enum for card type parameters */ |
||
| 688 | #define RADEON_CARD_PCI 0 |
||
| 689 | #define RADEON_CARD_AGP 1 |
||
| 690 | #define RADEON_CARD_PCIE 2 |
||
| 691 | |||
| 692 | /* 1.3: An ioctl to get parameters that aren't available to the 3d |
||
| 693 | * client any other way. |
||
| 694 | */ |
||
| 695 | #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ |
||
| 696 | #define RADEON_PARAM_LAST_FRAME 2 |
||
| 697 | #define RADEON_PARAM_LAST_DISPATCH 3 |
||
| 698 | #define RADEON_PARAM_LAST_CLEAR 4 |
||
| 699 | /* Added with DRM version 1.6. */ |
||
| 700 | #define RADEON_PARAM_IRQ_NR 5 |
||
| 701 | #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ |
||
| 702 | /* Added with DRM version 1.8. */ |
||
| 703 | #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ |
||
| 704 | #define RADEON_PARAM_STATUS_HANDLE 8 |
||
| 705 | #define RADEON_PARAM_SAREA_HANDLE 9 |
||
| 706 | #define RADEON_PARAM_GART_TEX_HANDLE 10 |
||
| 707 | #define RADEON_PARAM_SCRATCH_OFFSET 11 |
||
| 708 | #define RADEON_PARAM_CARD_TYPE 12 |
||
| 709 | #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ |
||
| 710 | #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ |
||
| 711 | #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ |
||
| 712 | #define RADEON_PARAM_DEVICE_ID 16 |
||
| 713 | #define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ |
||
| 714 | |||
| 715 | typedef struct drm_radeon_getparam { |
||
| 716 | int param; |
||
| 717 | void __user *value; |
||
| 718 | } drm_radeon_getparam_t; |
||
| 719 | |||
| 720 | /* 1.6: Set up a memory manager for regions of shared memory: |
||
| 721 | */ |
||
| 722 | #define RADEON_MEM_REGION_GART 1 |
||
| 723 | #define RADEON_MEM_REGION_FB 2 |
||
| 724 | |||
| 725 | typedef struct drm_radeon_mem_alloc { |
||
| 726 | int region; |
||
| 727 | int alignment; |
||
| 728 | int size; |
||
| 729 | int __user *region_offset; /* offset from start of fb or GART */ |
||
| 730 | } drm_radeon_mem_alloc_t; |
||
| 731 | |||
| 732 | typedef struct drm_radeon_mem_free { |
||
| 733 | int region; |
||
| 734 | int region_offset; |
||
| 735 | } drm_radeon_mem_free_t; |
||
| 736 | |||
| 737 | typedef struct drm_radeon_mem_init_heap { |
||
| 738 | int region; |
||
| 739 | int size; |
||
| 740 | int start; |
||
| 741 | } drm_radeon_mem_init_heap_t; |
||
| 742 | |||
| 743 | /* 1.6: Userspace can request & wait on irq's: |
||
| 744 | */ |
||
| 745 | typedef struct drm_radeon_irq_emit { |
||
| 746 | int __user *irq_seq; |
||
| 747 | } drm_radeon_irq_emit_t; |
||
| 748 | |||
| 749 | typedef struct drm_radeon_irq_wait { |
||
| 750 | int irq_seq; |
||
| 751 | } drm_radeon_irq_wait_t; |
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| 752 | |||
| 753 | /* 1.10: Clients tell the DRM where they think the framebuffer is located in |
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| 754 | * the card's address space, via a new generic ioctl to set parameters |
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| 755 | */ |
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| 756 | |||
| 757 | typedef struct drm_radeon_setparam { |
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| 758 | unsigned int param; |
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| 759 | __s64 value; |
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| 760 | } drm_radeon_setparam_t; |
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| 761 | |||
| 762 | #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ |
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| 763 | #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ |
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| 764 | #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ |
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| 765 | #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ |
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| 766 | #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ |
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| 767 | #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ |
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| 768 | /* 1.14: Clients can allocate/free a surface |
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| 769 | */ |
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| 770 | typedef struct drm_radeon_surface_alloc { |
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| 771 | unsigned int address; |
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| 772 | unsigned int size; |
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| 773 | unsigned int flags; |
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| 774 | } drm_radeon_surface_alloc_t; |
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| 775 | |||
| 776 | typedef struct drm_radeon_surface_free { |
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| 777 | unsigned int address; |
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| 778 | } drm_radeon_surface_free_t; |
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| 779 | |||
| 780 | #define DRM_RADEON_VBLANK_CRTC1 1 |
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| 781 | #define DRM_RADEON_VBLANK_CRTC2 2 |
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| 782 | |||
| 783 | /* |
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| 784 | * Kernel modesetting world below. |
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| 785 | */ |
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| 786 | #define RADEON_GEM_DOMAIN_CPU 0x1 |
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| 787 | #define RADEON_GEM_DOMAIN_GTT 0x2 |
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| 788 | #define RADEON_GEM_DOMAIN_VRAM 0x4 |
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| 789 | |||
| 790 | struct drm_radeon_gem_info { |
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| 791 | uint64_t gart_size; |
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| 792 | uint64_t vram_size; |
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| 793 | uint64_t vram_visible; |
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| 794 | }; |
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| 795 | |||
| 796 | #define RADEON_GEM_NO_BACKING_STORE 1 |
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| 797 | |||
| 798 | struct drm_radeon_gem_create { |
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| 799 | uint64_t size; |
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| 800 | uint64_t alignment; |
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| 801 | uint32_t handle; |
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| 802 | uint32_t initial_domain; |
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| 803 | uint32_t flags; |
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| 804 | }; |
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| 805 | |||
| 806 | #define RADEON_TILING_MACRO 0x1 |
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| 807 | #define RADEON_TILING_MICRO 0x2 |
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| 808 | #define RADEON_TILING_SWAP_16BIT 0x4 |
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| 809 | #define RADEON_TILING_SWAP_32BIT 0x8 |
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| 810 | #define RADEON_TILING_SURFACE 0x10 /* this object requires a surface |
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| 811 | * when mapped - i.e. front buffer */ |
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| 1430 | serge | 812 | #define RADEON_TILING_MICRO_SQUARE 0x20 |
| 1408 | serge | 813 | |
| 814 | struct drm_radeon_gem_set_tiling { |
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| 815 | uint32_t handle; |
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| 816 | uint32_t tiling_flags; |
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| 817 | uint32_t pitch; |
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| 818 | }; |
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| 819 | |||
| 820 | struct drm_radeon_gem_get_tiling { |
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| 821 | uint32_t handle; |
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| 822 | uint32_t tiling_flags; |
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| 823 | uint32_t pitch; |
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| 824 | }; |
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| 825 | |||
| 826 | struct drm_radeon_gem_mmap { |
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| 827 | uint32_t handle; |
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| 828 | uint32_t pad; |
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| 829 | uint64_t offset; |
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| 830 | uint64_t size; |
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| 831 | uint64_t addr_ptr; |
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| 832 | }; |
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| 833 | |||
| 834 | struct drm_radeon_gem_set_domain { |
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| 835 | uint32_t handle; |
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| 836 | uint32_t read_domains; |
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| 837 | uint32_t write_domain; |
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| 838 | }; |
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| 839 | |||
| 840 | struct drm_radeon_gem_wait_idle { |
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| 841 | uint32_t handle; |
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| 842 | uint32_t pad; |
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| 843 | }; |
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| 844 | |||
| 845 | struct drm_radeon_gem_busy { |
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| 846 | uint32_t handle; |
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| 847 | uint32_t domain; |
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| 848 | }; |
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| 849 | |||
| 850 | struct drm_radeon_gem_pread { |
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| 851 | /** Handle for the object being read. */ |
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| 852 | uint32_t handle; |
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| 853 | uint32_t pad; |
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| 854 | /** Offset into the object to read from */ |
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| 855 | uint64_t offset; |
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| 856 | /** Length of data to read */ |
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| 857 | uint64_t size; |
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| 858 | /** Pointer to write the data into. */ |
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| 859 | /* void *, but pointers are not 32/64 compatible */ |
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| 860 | uint64_t data_ptr; |
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| 861 | }; |
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| 862 | |||
| 863 | struct drm_radeon_gem_pwrite { |
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| 864 | /** Handle for the object being written to. */ |
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| 865 | uint32_t handle; |
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| 866 | uint32_t pad; |
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| 867 | /** Offset into the object to write to */ |
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| 868 | uint64_t offset; |
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| 869 | /** Length of data to write */ |
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| 870 | uint64_t size; |
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| 871 | /** Pointer to read the data from. */ |
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| 872 | /* void *, but pointers are not 32/64 compatible */ |
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| 873 | uint64_t data_ptr; |
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| 874 | }; |
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| 875 | |||
| 2967 | Serge | 876 | #define RADEON_VA_MAP 1 |
| 877 | #define RADEON_VA_UNMAP 2 |
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| 878 | |||
| 879 | #define RADEON_VA_RESULT_OK 0 |
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| 880 | #define RADEON_VA_RESULT_ERROR 1 |
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| 881 | #define RADEON_VA_RESULT_VA_EXIST 2 |
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| 882 | |||
| 883 | #define RADEON_VM_PAGE_VALID (1 << 0) |
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| 884 | #define RADEON_VM_PAGE_READABLE (1 << 1) |
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| 885 | #define RADEON_VM_PAGE_WRITEABLE (1 << 2) |
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| 886 | #define RADEON_VM_PAGE_SYSTEM (1 << 3) |
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| 887 | #define RADEON_VM_PAGE_SNOOPED (1 << 4) |
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| 888 | |||
| 889 | struct drm_radeon_gem_va { |
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| 890 | uint32_t handle; |
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| 891 | uint32_t operation; |
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| 892 | uint32_t vm_id; |
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| 893 | uint32_t flags; |
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| 894 | uint64_t offset; |
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| 895 | }; |
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| 896 | |||
| 1408 | serge | 897 | #define RADEON_CHUNK_ID_RELOCS 0x01 |
| 898 | #define RADEON_CHUNK_ID_IB 0x02 |
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| 2967 | Serge | 899 | #define RADEON_CHUNK_ID_FLAGS 0x03 |
| 1408 | serge | 900 | |
| 2967 | Serge | 901 | /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ |
| 902 | #define RADEON_CS_KEEP_TILING_FLAGS 0x01 |
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| 903 | #define RADEON_CS_USE_VM 0x02 |
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| 904 | /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ |
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| 905 | #define RADEON_CS_RING_GFX 0 |
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| 906 | #define RADEON_CS_RING_COMPUTE 1 |
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| 907 | /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ |
||
| 908 | /* 0 = normal, + = higher priority, - = lower priority */ |
||
| 909 | |||
| 1408 | serge | 910 | struct drm_radeon_cs_chunk { |
| 911 | uint32_t chunk_id; |
||
| 912 | uint32_t length_dw; |
||
| 913 | uint64_t chunk_data; |
||
| 914 | }; |
||
| 915 | |||
| 2967 | Serge | 916 | /* drm_radeon_cs_reloc.flags */ |
| 917 | #define RADEON_RELOC_DONT_SYNC 0x01 |
||
| 918 | |||
| 1408 | serge | 919 | struct drm_radeon_cs_reloc { |
| 920 | uint32_t handle; |
||
| 921 | uint32_t read_domains; |
||
| 922 | uint32_t write_domain; |
||
| 923 | uint32_t flags; |
||
| 924 | }; |
||
| 925 | |||
| 926 | struct drm_radeon_cs { |
||
| 927 | uint32_t num_chunks; |
||
| 928 | uint32_t cs_id; |
||
| 929 | /* this points to uint64_t * which point to cs chunks */ |
||
| 930 | uint64_t chunks; |
||
| 931 | /* updates to the limits after this CS ioctl */ |
||
| 932 | uint64_t gart_limit; |
||
| 933 | uint64_t vram_limit; |
||
| 934 | }; |
||
| 935 | |||
| 936 | #define RADEON_INFO_DEVICE_ID 0x00 |
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| 937 | #define RADEON_INFO_NUM_GB_PIPES 0x01 |
||
| 938 | #define RADEON_INFO_NUM_Z_PIPES 0x02 |
||
| 939 | #define RADEON_INFO_ACCEL_WORKING 0x03 |
||
| 1964 | serge | 940 | #define RADEON_INFO_CRTC_FROM_ID 0x04 |
| 941 | #define RADEON_INFO_ACCEL_WORKING2 0x05 |
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| 942 | #define RADEON_INFO_TILING_CONFIG 0x06 |
||
| 943 | #define RADEON_INFO_WANT_HYPERZ 0x07 |
||
| 944 | #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ |
||
| 945 | #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ |
||
| 946 | #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ |
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| 947 | #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ |
||
| 948 | #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ |
||
| 2161 | serge | 949 | #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ |
| 2967 | Serge | 950 | /* virtual address start, va < start are reserved by the kernel */ |
| 951 | #define RADEON_INFO_VA_START 0x0e |
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| 952 | /* maximum size of ib using the virtual memory cs */ |
||
| 953 | #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f |
||
| 1408 | serge | 954 | |
| 955 | struct drm_radeon_info { |
||
| 956 | uint32_t request; |
||
| 957 | uint32_t pad; |
||
| 958 | uint64_t value; |
||
| 959 | }; |
||
| 960 | |||
| 961 | #endif |