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4103 | Serge | 1 | /* |
2 | * Copyright 2013 Intel Corporation |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the |
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14 | * next paragraph) shall be included in all copies or substantial portions |
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15 | * of the Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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23 | * DEALINGS IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef _I915_PCIIDS_H |
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26 | #define _I915_PCIIDS_H |
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27 | |||
28 | /* |
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29 | * A pci_device_id struct { |
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30 | * __u32 vendor, device; |
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31 | * __u32 subvendor, subdevice; |
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32 | * __u32 class, class_mask; |
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33 | * kernel_ulong_t driver_data; |
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34 | * }; |
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35 | * Don't use C99 here because "class" is reserved and we want to |
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36 | * give userspace flexibility. |
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37 | */ |
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38 | #define INTEL_VGA_DEVICE(id, info) { \ |
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39 | 0x8086, id, \ |
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40 | ~0, ~0, \ |
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41 | 0x030000, 0xff0000, \ |
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42 | (unsigned long) info } |
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43 | |||
44 | #define INTEL_QUANTA_VGA_DEVICE(info) { \ |
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45 | 0x8086, 0x16a, \ |
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46 | 0x152d, 0x8990, \ |
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47 | 0x030000, 0xff0000, \ |
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48 | (unsigned long) info } |
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49 | |||
50 | #define INTEL_I830_IDS(info) \ |
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51 | INTEL_VGA_DEVICE(0x3577, info) |
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52 | |||
53 | #define INTEL_I845G_IDS(info) \ |
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54 | INTEL_VGA_DEVICE(0x2562, info) |
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55 | |||
56 | #define INTEL_I85X_IDS(info) \ |
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57 | INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ |
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58 | INTEL_VGA_DEVICE(0x358e, info) |
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59 | |||
60 | #define INTEL_I865G_IDS(info) \ |
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61 | INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ |
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62 | |||
63 | #define INTEL_I915G_IDS(info) \ |
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64 | INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ |
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65 | INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ |
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66 | |||
67 | #define INTEL_I915GM_IDS(info) \ |
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68 | INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ |
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69 | |||
70 | #define INTEL_I945G_IDS(info) \ |
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71 | INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ |
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72 | |||
73 | #define INTEL_I945GM_IDS(info) \ |
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74 | INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ |
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75 | INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ |
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76 | |||
77 | #define INTEL_I965G_IDS(info) \ |
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78 | INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ |
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79 | INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ |
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80 | INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ |
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81 | INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ |
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82 | |||
83 | #define INTEL_G33_IDS(info) \ |
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84 | INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ |
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85 | INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ |
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86 | INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ |
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87 | |||
88 | #define INTEL_I965GM_IDS(info) \ |
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89 | INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ |
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90 | INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ |
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91 | |||
92 | #define INTEL_GM45_IDS(info) \ |
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93 | INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ |
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94 | |||
95 | #define INTEL_G45_IDS(info) \ |
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96 | INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ |
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97 | INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ |
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98 | INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ |
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99 | INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ |
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100 | INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ |
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101 | INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ |
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102 | |||
103 | #define INTEL_PINEVIEW_IDS(info) \ |
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104 | INTEL_VGA_DEVICE(0xa001, info), \ |
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105 | INTEL_VGA_DEVICE(0xa011, info) |
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106 | |||
107 | #define INTEL_IRONLAKE_D_IDS(info) \ |
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108 | INTEL_VGA_DEVICE(0x0042, info) |
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109 | |||
110 | #define INTEL_IRONLAKE_M_IDS(info) \ |
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111 | INTEL_VGA_DEVICE(0x0046, info) |
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112 | |||
113 | #define INTEL_SNB_D_IDS(info) \ |
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114 | INTEL_VGA_DEVICE(0x0102, info), \ |
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115 | INTEL_VGA_DEVICE(0x0112, info), \ |
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116 | INTEL_VGA_DEVICE(0x0122, info), \ |
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117 | INTEL_VGA_DEVICE(0x010A, info) |
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118 | |||
119 | #define INTEL_SNB_M_IDS(info) \ |
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120 | INTEL_VGA_DEVICE(0x0106, info), \ |
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121 | INTEL_VGA_DEVICE(0x0116, info), \ |
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122 | INTEL_VGA_DEVICE(0x0126, info) |
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123 | |||
124 | #define INTEL_IVB_M_IDS(info) \ |
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125 | INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ |
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126 | INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ |
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127 | |||
128 | #define INTEL_IVB_D_IDS(info) \ |
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129 | INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ |
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130 | INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ |
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131 | INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ |
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132 | INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ |
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133 | |||
134 | #define INTEL_IVB_Q_IDS(info) \ |
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135 | INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ |
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136 | |||
137 | #define INTEL_HSW_D_IDS(info) \ |
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138 | INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ |
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139 | INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ |
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140 | INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ |
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141 | INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ |
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142 | INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ |
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143 | INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ |
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144 | INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ |
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145 | INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ |
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146 | INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ |
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147 | INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ |
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148 | INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ |
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149 | INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ |
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150 | INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ |
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151 | INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ |
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152 | INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ |
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153 | INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ |
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154 | INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ |
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155 | INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ |
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156 | INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ |
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157 | INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ |
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158 | INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ |
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159 | INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ |
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160 | INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ |
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161 | INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ |
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162 | INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ |
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163 | INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ |
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164 | INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ |
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165 | INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ |
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166 | INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ |
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167 | INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ |
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168 | INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ |
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169 | INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ |
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170 | INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ |
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171 | INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ |
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172 | INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ |
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173 | INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ |
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174 | INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ |
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175 | INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ |
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176 | INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ |
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177 | INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ |
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178 | INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ |
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179 | INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ |
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180 | INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ |
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181 | INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ |
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182 | INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \ |
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183 | |||
184 | #define INTEL_HSW_M_IDS(info) \ |
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185 | INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ |
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186 | INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ |
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187 | INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ |
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188 | INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ |
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189 | INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ |
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190 | INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ |
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191 | INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ |
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192 | INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ |
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193 | INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ |
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5056 | serge | 194 | INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ |
195 | INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ |
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4103 | Serge | 196 | INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ |
197 | INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ |
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198 | INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ |
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199 | INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ |
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200 | |||
201 | #define INTEL_VLV_M_IDS(info) \ |
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202 | INTEL_VGA_DEVICE(0x0f30, info), \ |
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203 | INTEL_VGA_DEVICE(0x0f31, info), \ |
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204 | INTEL_VGA_DEVICE(0x0f32, info), \ |
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205 | INTEL_VGA_DEVICE(0x0f33, info), \ |
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206 | INTEL_VGA_DEVICE(0x0157, info) |
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207 | |||
208 | #define INTEL_VLV_D_IDS(info) \ |
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209 | INTEL_VGA_DEVICE(0x0155, info) |
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210 | |||
4559 | Serge | 211 | #define _INTEL_BDW_M(gt, id, info) \ |
212 | INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) |
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213 | #define _INTEL_BDW_D(gt, id, info) \ |
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214 | INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) |
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215 | |||
216 | #define _INTEL_BDW_M_IDS(gt, info) \ |
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217 | _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \ |
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218 | _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \ |
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219 | _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \ |
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220 | _INTEL_BDW_M(gt, 0x160E, info) /* ULX */ |
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221 | |||
222 | #define _INTEL_BDW_D_IDS(gt, info) \ |
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223 | _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ |
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224 | _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ |
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225 | |||
5056 | serge | 226 | #define INTEL_BDW_GT12M_IDS(info) \ |
4559 | Serge | 227 | _INTEL_BDW_M_IDS(1, info), \ |
5056 | serge | 228 | _INTEL_BDW_M_IDS(2, info) |
229 | |||
230 | #define INTEL_BDW_GT12D_IDS(info) \ |
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231 | _INTEL_BDW_D_IDS(1, info), \ |
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232 | _INTEL_BDW_D_IDS(2, info) |
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233 | |||
234 | #define INTEL_BDW_GT3M_IDS(info) \ |
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4559 | Serge | 235 | _INTEL_BDW_M_IDS(3, info) |
236 | |||
5056 | serge | 237 | #define INTEL_BDW_GT3D_IDS(info) \ |
4559 | Serge | 238 | _INTEL_BDW_D_IDS(3, info) |
239 | |||
5056 | serge | 240 | #define INTEL_BDW_RSVDM_IDS(info) \ |
241 | _INTEL_BDW_M_IDS(4, info) |
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242 | |||
243 | #define INTEL_BDW_RSVDD_IDS(info) \ |
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244 | _INTEL_BDW_D_IDS(4, info) |
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245 | |||
246 | #define INTEL_BDW_M_IDS(info) \ |
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247 | INTEL_BDW_GT12M_IDS(info), \ |
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248 | INTEL_BDW_GT3M_IDS(info), \ |
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249 | INTEL_BDW_RSVDM_IDS(info) |
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250 | |||
251 | #define INTEL_BDW_D_IDS(info) \ |
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252 | INTEL_BDW_GT12D_IDS(info), \ |
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253 | INTEL_BDW_GT3D_IDS(info), \ |
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254 | INTEL_BDW_RSVDD_IDS(info) |
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255 | |||
256 | #define INTEL_CHV_IDS(info) \ |
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257 | INTEL_VGA_DEVICE(0x22b0, info), \ |
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258 | INTEL_VGA_DEVICE(0x22b1, info), \ |
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259 | INTEL_VGA_DEVICE(0x22b2, info), \ |
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260 | INTEL_VGA_DEVICE(0x22b3, info) |
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261 | |||
4103 | Serge | 262 | #endif /* _I915_PCIIDS_H */><>><> |