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1408 | serge | 1 | /* |
2 | * Copyright © 2008 Keith Packard |
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3 | * |
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4 | * Permission to use, copy, modify, distribute, and sell this software and its |
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5 | * documentation for any purpose is hereby granted without fee, provided that |
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6 | * the above copyright notice appear in all copies and that both that copyright |
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7 | * notice and this permission notice appear in supporting documentation, and |
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8 | * that the name of the copyright holders not be used in advertising or |
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9 | * publicity pertaining to distribution of the software without specific, |
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10 | * written prior permission. The copyright holders make no representations |
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11 | * about the suitability of this software for any purpose. It is provided "as |
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12 | * is" without express or implied warranty. |
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13 | * |
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14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
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15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
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16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
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17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
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18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
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19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
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20 | * OF THIS SOFTWARE. |
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21 | */ |
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22 | |||
23 | #ifndef _DRM_DP_HELPER_H_ |
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24 | #define _DRM_DP_HELPER_H_ |
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25 | |||
1964 | serge | 26 | #include |
27 | #include |
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3192 | Serge | 28 | #include |
1964 | serge | 29 | |
3031 | serge | 30 | /* |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
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32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, |
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33 | * 1.0 devices basically don't exist in the wild. |
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34 | * |
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35 | * Abbreviations, in chronological order: |
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36 | * |
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37 | * eDP: Embedded DisplayPort version 1 |
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38 | * DPI: DisplayPort Interoperability Guideline v1.1a |
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39 | * 1.2: DisplayPort 1.2 |
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40 | * |
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41 | * 1.2 formally includes both eDP and DPI definitions. |
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42 | */ |
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1408 | serge | 43 | |
4559 | Serge | 44 | #define DP_AUX_I2C_WRITE 0x0 |
45 | #define DP_AUX_I2C_READ 0x1 |
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46 | #define DP_AUX_I2C_STATUS 0x2 |
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47 | #define DP_AUX_I2C_MOT 0x4 |
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48 | #define DP_AUX_NATIVE_WRITE 0x8 |
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49 | #define DP_AUX_NATIVE_READ 0x9 |
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1408 | serge | 50 | |
4559 | Serge | 51 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
52 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
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53 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
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54 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
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1408 | serge | 55 | |
4559 | Serge | 56 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
57 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
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58 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
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59 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
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1408 | serge | 60 | |
61 | /* AUX CH addresses */ |
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62 | /* DPCD */ |
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63 | #define DP_DPCD_REV 0x000 |
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64 | |||
65 | #define DP_MAX_LINK_RATE 0x001 |
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66 | |||
67 | #define DP_MAX_LANE_COUNT 0x002 |
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68 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
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3031 | serge | 69 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
1408 | serge | 70 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
71 | |||
72 | #define DP_MAX_DOWNSPREAD 0x003 |
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73 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
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74 | |||
75 | #define DP_NORP 0x004 |
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76 | |||
77 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
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78 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
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79 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
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4559 | Serge | 80 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
81 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
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82 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
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83 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
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1408 | serge | 84 | # define DP_FORMAT_CONVERSION (1 << 3) |
3031 | serge | 85 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
1408 | serge | 86 | |
87 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
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88 | |||
3031 | serge | 89 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
90 | # define DP_PORT_COUNT_MASK 0x0f |
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91 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
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92 | # define DP_OUI_SUPPORT (1 << 7) |
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1964 | serge | 93 | |
3031 | serge | 94 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
95 | # define DP_I2C_SPEED_1K 0x01 |
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96 | # define DP_I2C_SPEED_5K 0x02 |
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97 | # define DP_I2C_SPEED_10K 0x04 |
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98 | # define DP_I2C_SPEED_100K 0x08 |
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99 | # define DP_I2C_SPEED_400K 0x10 |
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100 | # define DP_I2C_SPEED_1M 0x20 |
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101 | |||
102 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
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103 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
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104 | |||
105 | /* Multiple stream transport */ |
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106 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
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107 | # define DP_MST_CAP (1 << 0) |
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108 | |||
109 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
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2967 | Serge | 110 | # define DP_PSR_IS_SUPPORTED 1 |
3031 | serge | 111 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
2967 | Serge | 112 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
113 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
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114 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
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115 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
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116 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
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117 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
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118 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
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119 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
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120 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
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121 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
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122 | |||
3031 | serge | 123 | /* |
124 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts |
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125 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
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126 | * each port's descriptor is one byte wide. If it was set, each port's is |
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127 | * four bytes wide, starting with the one byte from the base info. As of |
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128 | * DP interop v1.1a only VGA defines additional detail. |
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129 | */ |
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130 | |||
131 | /* offset 0 */ |
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132 | #define DP_DOWNSTREAM_PORT_0 0x80 |
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133 | # define DP_DS_PORT_TYPE_MASK (7 << 0) |
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134 | # define DP_DS_PORT_TYPE_DP 0 |
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135 | # define DP_DS_PORT_TYPE_VGA 1 |
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136 | # define DP_DS_PORT_TYPE_DVI 2 |
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137 | # define DP_DS_PORT_TYPE_HDMI 3 |
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138 | # define DP_DS_PORT_TYPE_NON_EDID 4 |
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139 | # define DP_DS_PORT_HPD (1 << 3) |
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140 | /* offset 1 for VGA is maximum megapixels per second / 8 */ |
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141 | /* offset 2 */ |
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142 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
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143 | # define DP_DS_VGA_8BPC 0 |
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144 | # define DP_DS_VGA_10BPC 1 |
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145 | # define DP_DS_VGA_12BPC 2 |
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146 | # define DP_DS_VGA_16BPC 3 |
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147 | |||
1408 | serge | 148 | /* link configuration */ |
149 | #define DP_LINK_BW_SET 0x100 |
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150 | # define DP_LINK_BW_1_62 0x06 |
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151 | # define DP_LINK_BW_2_7 0x0a |
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3031 | serge | 152 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
1408 | serge | 153 | |
154 | #define DP_LANE_COUNT_SET 0x101 |
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155 | # define DP_LANE_COUNT_MASK 0x0f |
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156 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
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157 | |||
158 | #define DP_TRAINING_PATTERN_SET 0x102 |
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159 | # define DP_TRAINING_PATTERN_DISABLE 0 |
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160 | # define DP_TRAINING_PATTERN_1 1 |
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161 | # define DP_TRAINING_PATTERN_2 2 |
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3031 | serge | 162 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
1408 | serge | 163 | # define DP_TRAINING_PATTERN_MASK 0x3 |
164 | |||
165 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
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166 | # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) |
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167 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) |
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168 | # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) |
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169 | # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) |
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170 | |||
171 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
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172 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
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173 | |||
174 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
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175 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
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176 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
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177 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
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178 | |||
179 | #define DP_TRAINING_LANE0_SET 0x103 |
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180 | #define DP_TRAINING_LANE1_SET 0x104 |
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181 | #define DP_TRAINING_LANE2_SET 0x105 |
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182 | #define DP_TRAINING_LANE3_SET 0x106 |
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183 | |||
184 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
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185 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
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186 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
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187 | # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) |
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188 | # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) |
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189 | # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) |
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190 | # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) |
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191 | |||
192 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
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193 | # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) |
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194 | # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) |
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195 | # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) |
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196 | # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) |
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197 | |||
198 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
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199 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
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200 | |||
201 | #define DP_DOWNSPREAD_CTRL 0x107 |
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202 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
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3031 | serge | 203 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
1408 | serge | 204 | |
205 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
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206 | # define DP_SET_ANSI_8B10B (1 << 0) |
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207 | |||
3031 | serge | 208 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
209 | /* bitmask as for DP_I2C_SPEED_CAP */ |
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210 | |||
211 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
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212 | |||
213 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
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214 | # define DP_MST_EN (1 << 0) |
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215 | # define DP_UP_REQ_EN (1 << 1) |
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216 | # define DP_UPSTREAM_IS_SRC (1 << 2) |
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217 | |||
218 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
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2967 | Serge | 219 | # define DP_PSR_ENABLE (1 << 0) |
220 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
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221 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
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222 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
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223 | |||
3031 | serge | 224 | #define DP_SINK_COUNT 0x200 |
225 | /* prior to 1.2 bit 7 was reserved mbz */ |
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226 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
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227 | # define DP_SINK_CP_READY (1 << 6) |
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228 | |||
2967 | Serge | 229 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
230 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
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231 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
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232 | # define DP_CP_IRQ (1 << 2) |
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233 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
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234 | |||
1408 | serge | 235 | #define DP_LANE0_1_STATUS 0x202 |
236 | #define DP_LANE2_3_STATUS 0x203 |
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237 | # define DP_LANE_CR_DONE (1 << 0) |
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238 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
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239 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
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240 | |||
241 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
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242 | DP_LANE_CHANNEL_EQ_DONE | \ |
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243 | DP_LANE_SYMBOL_LOCKED) |
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244 | |||
245 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
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246 | |||
247 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
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248 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
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249 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
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250 | |||
251 | #define DP_SINK_STATUS 0x205 |
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252 | |||
253 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
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254 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
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255 | |||
256 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
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257 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
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258 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
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259 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
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260 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
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261 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
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262 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
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263 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
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264 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
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265 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
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266 | |||
2967 | Serge | 267 | #define DP_TEST_REQUEST 0x218 |
268 | # define DP_TEST_LINK_TRAINING (1 << 0) |
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4559 | Serge | 269 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
2967 | Serge | 270 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
271 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
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4559 | Serge | 272 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
2967 | Serge | 273 | |
274 | #define DP_TEST_LINK_RATE 0x219 |
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275 | # define DP_LINK_RATE_162 (0x6) |
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276 | # define DP_LINK_RATE_27 (0xa) |
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277 | |||
278 | #define DP_TEST_LANE_COUNT 0x220 |
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279 | |||
280 | #define DP_TEST_PATTERN 0x221 |
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281 | |||
282 | #define DP_TEST_RESPONSE 0x260 |
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283 | # define DP_TEST_ACK (1 << 0) |
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284 | # define DP_TEST_NAK (1 << 1) |
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285 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
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286 | |||
3031 | serge | 287 | #define DP_SOURCE_OUI 0x300 |
288 | #define DP_SINK_OUI 0x400 |
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289 | #define DP_BRANCH_OUI 0x500 |
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290 | |||
1408 | serge | 291 | #define DP_SET_POWER 0x600 |
292 | # define DP_SET_POWER_D0 0x1 |
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293 | # define DP_SET_POWER_D3 0x2 |
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294 | |||
3031 | serge | 295 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
2967 | Serge | 296 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
297 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
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298 | |||
3031 | serge | 299 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
2967 | Serge | 300 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
301 | |||
3031 | serge | 302 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
2967 | Serge | 303 | # define DP_PSR_SINK_INACTIVE 0 |
304 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
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305 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
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306 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
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307 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
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308 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
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309 | # define DP_PSR_SINK_STATE_MASK 0x07 |
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310 | |||
1408 | serge | 311 | #define MODE_I2C_START 1 |
312 | #define MODE_I2C_WRITE 2 |
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313 | #define MODE_I2C_READ 4 |
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314 | #define MODE_I2C_STOP 8 |
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315 | |||
3192 | Serge | 316 | /** |
317 | * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp |
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318 | * aux algorithm |
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319 | * @running: set by the algo indicating whether an i2c is ongoing or whether |
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320 | * the i2c bus is quiescent |
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321 | * @address: i2c target address for the currently ongoing transfer |
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322 | * @aux_ch: driver callback to transfer a single byte of the i2c payload |
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323 | */ |
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1408 | serge | 324 | struct i2c_algo_dp_aux_data { |
325 | bool running; |
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326 | u16 address; |
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327 | int (*aux_ch) (struct i2c_adapter *adapter, |
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328 | int mode, uint8_t write_byte, |
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329 | uint8_t *read_byte); |
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330 | }; |
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331 | |||
332 | int |
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333 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
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334 | |||
3192 | Serge | 335 | |
336 | #define DP_LINK_STATUS_SIZE 6 |
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4559 | Serge | 337 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 338 | int lane_count); |
4559 | Serge | 339 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 340 | int lane_count); |
4559 | Serge | 341 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 342 | int lane); |
4559 | Serge | 343 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 344 | int lane); |
345 | |||
346 | #define DP_RECEIVER_CAP_SIZE 0xf |
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4103 | Serge | 347 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
348 | |||
4559 | Serge | 349 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
350 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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3192 | Serge | 351 | |
352 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
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353 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
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354 | |||
4103 | Serge | 355 | struct edp_sdp_header { |
356 | u8 HB0; /* Secondary Data Packet ID */ |
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357 | u8 HB1; /* Secondary Data Packet Type */ |
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358 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ |
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359 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ |
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360 | } __packed; |
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361 | |||
362 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F |
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363 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F |
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364 | |||
365 | struct edp_vsc_psr { |
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366 | struct edp_sdp_header sdp_header; |
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367 | u8 DB0; /* Stereo Interface */ |
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368 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ |
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369 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ |
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370 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ |
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371 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ |
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372 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ |
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373 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ |
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374 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ |
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375 | u8 DB8_31[24]; /* Reserved */ |
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376 | } __packed; |
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377 | |||
378 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
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379 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
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380 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
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381 | |||
3192 | Serge | 382 | static inline int |
4559 | Serge | 383 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3192 | Serge | 384 | { |
385 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
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386 | } |
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387 | |||
388 | static inline u8 |
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4559 | Serge | 389 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3192 | Serge | 390 | { |
391 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
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392 | } |
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393 | |||
4559 | Serge | 394 | static inline bool |
395 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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396 | { |
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397 | return dpcd[DP_DPCD_REV] >= 0x11 && |
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398 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
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399 | } |
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400 | |||
1408 | serge | 401 | #endif /* _DRM_DP_HELPER_H_ */2) |