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1408 | serge | 1 | /* |
2 | * Copyright © 2008 Keith Packard |
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3 | * |
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4 | * Permission to use, copy, modify, distribute, and sell this software and its |
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5 | * documentation for any purpose is hereby granted without fee, provided that |
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6 | * the above copyright notice appear in all copies and that both that copyright |
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7 | * notice and this permission notice appear in supporting documentation, and |
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8 | * that the name of the copyright holders not be used in advertising or |
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9 | * publicity pertaining to distribution of the software without specific, |
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10 | * written prior permission. The copyright holders make no representations |
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11 | * about the suitability of this software for any purpose. It is provided "as |
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12 | * is" without express or implied warranty. |
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13 | * |
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14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
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15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
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16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
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17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
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18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
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19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
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20 | * OF THIS SOFTWARE. |
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21 | */ |
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22 | |||
23 | #ifndef _DRM_DP_HELPER_H_ |
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24 | #define _DRM_DP_HELPER_H_ |
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25 | |||
1964 | serge | 26 | #include |
27 | #include |
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28 | |||
1408 | serge | 29 | /* From the VESA DisplayPort spec */ |
30 | |||
31 | #define AUX_NATIVE_WRITE 0x8 |
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32 | #define AUX_NATIVE_READ 0x9 |
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33 | #define AUX_I2C_WRITE 0x0 |
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34 | #define AUX_I2C_READ 0x1 |
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35 | #define AUX_I2C_STATUS 0x2 |
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36 | #define AUX_I2C_MOT 0x4 |
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37 | |||
38 | #define AUX_NATIVE_REPLY_ACK (0x0 << 4) |
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39 | #define AUX_NATIVE_REPLY_NACK (0x1 << 4) |
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40 | #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) |
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41 | #define AUX_NATIVE_REPLY_MASK (0x3 << 4) |
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42 | |||
43 | #define AUX_I2C_REPLY_ACK (0x0 << 6) |
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44 | #define AUX_I2C_REPLY_NACK (0x1 << 6) |
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45 | #define AUX_I2C_REPLY_DEFER (0x2 << 6) |
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46 | #define AUX_I2C_REPLY_MASK (0x3 << 6) |
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47 | |||
48 | /* AUX CH addresses */ |
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49 | /* DPCD */ |
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50 | #define DP_DPCD_REV 0x000 |
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51 | |||
52 | #define DP_MAX_LINK_RATE 0x001 |
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53 | |||
54 | #define DP_MAX_LANE_COUNT 0x002 |
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55 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
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1964 | serge | 56 | # define DP_TPS3_SUPPORTED (1 << 6) |
1408 | serge | 57 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
58 | |||
59 | #define DP_MAX_DOWNSPREAD 0x003 |
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60 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
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61 | |||
62 | #define DP_NORP 0x004 |
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63 | |||
64 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
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65 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
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66 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
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67 | /* 00b = DisplayPort */ |
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68 | /* 01b = Analog */ |
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69 | /* 10b = TMDS or HDMI */ |
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70 | /* 11b = Other */ |
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71 | # define DP_FORMAT_CONVERSION (1 << 3) |
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72 | |||
73 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
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74 | |||
2967 | Serge | 75 | #define DP_EDP_CONFIGURATION_CAP 0x00d |
1964 | serge | 76 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
77 | |||
2967 | Serge | 78 | #define DP_PSR_SUPPORT 0x070 |
79 | # define DP_PSR_IS_SUPPORTED 1 |
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80 | #define DP_PSR_CAPS 0x071 |
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81 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
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82 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
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83 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
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84 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
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85 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
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86 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
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87 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
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88 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
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89 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
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90 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
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91 | |||
1408 | serge | 92 | /* link configuration */ |
93 | #define DP_LINK_BW_SET 0x100 |
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94 | # define DP_LINK_BW_1_62 0x06 |
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95 | # define DP_LINK_BW_2_7 0x0a |
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1964 | serge | 96 | # define DP_LINK_BW_5_4 0x14 |
1408 | serge | 97 | |
98 | #define DP_LANE_COUNT_SET 0x101 |
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99 | # define DP_LANE_COUNT_MASK 0x0f |
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100 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
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101 | |||
102 | #define DP_TRAINING_PATTERN_SET 0x102 |
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103 | # define DP_TRAINING_PATTERN_DISABLE 0 |
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104 | # define DP_TRAINING_PATTERN_1 1 |
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105 | # define DP_TRAINING_PATTERN_2 2 |
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1964 | serge | 106 | # define DP_TRAINING_PATTERN_3 3 |
1408 | serge | 107 | # define DP_TRAINING_PATTERN_MASK 0x3 |
108 | |||
109 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
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110 | # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) |
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111 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) |
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112 | # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) |
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113 | # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) |
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114 | |||
115 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
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116 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
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117 | |||
118 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
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119 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
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120 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
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121 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
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122 | |||
123 | #define DP_TRAINING_LANE0_SET 0x103 |
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124 | #define DP_TRAINING_LANE1_SET 0x104 |
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125 | #define DP_TRAINING_LANE2_SET 0x105 |
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126 | #define DP_TRAINING_LANE3_SET 0x106 |
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127 | |||
128 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
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129 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
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130 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
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131 | # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) |
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132 | # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) |
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133 | # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) |
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134 | # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) |
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135 | |||
136 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
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137 | # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) |
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138 | # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) |
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139 | # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) |
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140 | # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) |
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141 | |||
142 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
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143 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
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144 | |||
145 | #define DP_DOWNSPREAD_CTRL 0x107 |
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146 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
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147 | |||
148 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
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149 | # define DP_SET_ANSI_8B10B (1 << 0) |
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150 | |||
2967 | Serge | 151 | #define DP_PSR_EN_CFG 0x170 |
152 | # define DP_PSR_ENABLE (1 << 0) |
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153 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
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154 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
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155 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
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156 | |||
157 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
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158 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
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159 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
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160 | # define DP_CP_IRQ (1 << 2) |
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161 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
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162 | |||
163 | #define DP_EDP_CONFIGURATION_SET 0x10a |
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164 | |||
1408 | serge | 165 | #define DP_LANE0_1_STATUS 0x202 |
166 | #define DP_LANE2_3_STATUS 0x203 |
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167 | # define DP_LANE_CR_DONE (1 << 0) |
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168 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
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169 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
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170 | |||
171 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
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172 | DP_LANE_CHANNEL_EQ_DONE | \ |
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173 | DP_LANE_SYMBOL_LOCKED) |
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174 | |||
175 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
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176 | |||
177 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
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178 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
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179 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
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180 | |||
181 | #define DP_SINK_STATUS 0x205 |
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182 | |||
183 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
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184 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
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185 | |||
186 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
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187 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
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188 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
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189 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
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190 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
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191 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
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192 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
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193 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
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194 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
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195 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
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196 | |||
2967 | Serge | 197 | #define DP_TEST_REQUEST 0x218 |
198 | # define DP_TEST_LINK_TRAINING (1 << 0) |
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199 | # define DP_TEST_LINK_PATTERN (1 << 1) |
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200 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
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201 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
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202 | |||
203 | #define DP_TEST_LINK_RATE 0x219 |
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204 | # define DP_LINK_RATE_162 (0x6) |
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205 | # define DP_LINK_RATE_27 (0xa) |
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206 | |||
207 | #define DP_TEST_LANE_COUNT 0x220 |
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208 | |||
209 | #define DP_TEST_PATTERN 0x221 |
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210 | |||
211 | #define DP_TEST_RESPONSE 0x260 |
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212 | # define DP_TEST_ACK (1 << 0) |
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213 | # define DP_TEST_NAK (1 << 1) |
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214 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
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215 | |||
1408 | serge | 216 | #define DP_SET_POWER 0x600 |
217 | # define DP_SET_POWER_D0 0x1 |
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218 | # define DP_SET_POWER_D3 0x2 |
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219 | |||
2967 | Serge | 220 | #define DP_PSR_ERROR_STATUS 0x2006 |
221 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
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222 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
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223 | |||
224 | #define DP_PSR_ESI 0x2007 |
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225 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
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226 | |||
227 | #define DP_PSR_STATUS 0x2008 |
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228 | # define DP_PSR_SINK_INACTIVE 0 |
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229 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
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230 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
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231 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
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232 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
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233 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
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234 | # define DP_PSR_SINK_STATE_MASK 0x07 |
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235 | |||
1408 | serge | 236 | #define MODE_I2C_START 1 |
237 | #define MODE_I2C_WRITE 2 |
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238 | #define MODE_I2C_READ 4 |
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239 | #define MODE_I2C_STOP 8 |
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240 | |||
241 | struct i2c_algo_dp_aux_data { |
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242 | bool running; |
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243 | u16 address; |
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244 | int (*aux_ch) (struct i2c_adapter *adapter, |
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245 | int mode, uint8_t write_byte, |
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246 | uint8_t *read_byte); |
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247 | }; |
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248 | |||
249 | int |
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250 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
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251 | |||
252 | #endif /* _DRM_DP_HELPER_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |