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5270 serge 1 
#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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/* Keep includes the same across arches.  */
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#include
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/*
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 * The cache doesn't need to be flushed when TLB entries change when
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 * the cache is mapped to physical memory, not virtual memory
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 */
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#define flush_cache_all()			do { } while (0)
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#define flush_cache_mm(mm)			do { } while (0)
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#define flush_cache_dup_mm(mm)			do { } while (0)
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#define flush_cache_range(vma, start, end)	do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page)			do { } while (0)
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#define flush_dcache_mmap_lock(mapping)		do { } while (0)
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#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
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#define flush_icache_range(start, end)		do { } while (0)
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#define flush_icache_page(vma,pg)		do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len)	do { } while (0)
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#define flush_cache_vmap(start, end)		do { } while (0)
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#define flush_cache_vunmap(start, end)		do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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	do { \
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		memcpy(dst, src, len); \
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		flush_icache_user_range(vma, page, vaddr, len); \
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	} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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	memcpy(dst, src, len)
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#endif /* __ASM_CACHEFLUSH_H */