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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5270 | serge | 1 | #ifndef _ASM_X86_PERCPU_H |
| 2 | #define _ASM_X86_PERCPU_H |
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| 3 | |||
| 4 | #ifdef CONFIG_X86_64 |
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| 5 | #define __percpu_seg gs |
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| 6 | #define __percpu_mov_op movq |
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| 7 | #else |
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| 8 | #define __percpu_seg fs |
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| 9 | #define __percpu_mov_op movl |
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| 10 | #endif |
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| 11 | |||
| 12 | #ifdef __ASSEMBLY__ |
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| 13 | |||
| 14 | /* |
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| 15 | * PER_CPU finds an address of a per-cpu variable. |
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| 16 | * |
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| 17 | * Args: |
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| 18 | * var - variable name |
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| 19 | * reg - 32bit register |
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| 20 | * |
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| 21 | * The resulting address is stored in the "reg" argument. |
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| 22 | * |
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| 23 | * Example: |
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| 24 | * PER_CPU(cpu_gdt_descr, %ebx) |
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| 25 | */ |
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| 26 | #ifdef CONFIG_SMP |
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| 27 | #define PER_CPU(var, reg) \ |
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| 28 | __percpu_mov_op %__percpu_seg:this_cpu_off, reg; \ |
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| 29 | lea var(reg), reg |
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| 30 | #define PER_CPU_VAR(var) %__percpu_seg:var |
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| 31 | #else /* ! SMP */ |
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| 32 | #define PER_CPU(var, reg) __percpu_mov_op $var, reg |
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| 33 | #define PER_CPU_VAR(var) var |
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| 34 | #endif /* SMP */ |
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| 35 | |||
| 36 | #ifdef CONFIG_X86_64_SMP |
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| 37 | #define INIT_PER_CPU_VAR(var) init_per_cpu__##var |
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| 38 | #else |
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| 39 | #define INIT_PER_CPU_VAR(var) var |
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| 40 | #endif |
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| 41 | |||
| 42 | #else /* ...!ASSEMBLY */ |
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| 43 | |||
| 44 | #include |
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| 45 | #include |
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| 46 | |||
| 47 | #ifdef CONFIG_SMP |
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| 48 | #define __percpu_prefix "%%"__stringify(__percpu_seg)":" |
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| 49 | #define __my_cpu_offset this_cpu_read(this_cpu_off) |
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| 50 | |||
| 51 | /* |
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| 52 | * Compared to the generic __my_cpu_offset version, the following |
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| 53 | * saves one instruction and avoids clobbering a temp register. |
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| 54 | */ |
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| 55 | #define arch_raw_cpu_ptr(ptr) \ |
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| 56 | ({ \ |
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| 57 | unsigned long tcp_ptr__; \ |
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| 58 | asm volatile("add " __percpu_arg(1) ", %0" \ |
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| 59 | : "=r" (tcp_ptr__) \ |
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| 60 | : "m" (this_cpu_off), "0" (ptr)); \ |
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| 61 | (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ |
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| 62 | }) |
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| 63 | #else |
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| 64 | #define __percpu_prefix "" |
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| 65 | #endif |
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| 66 | |||
| 67 | #define __percpu_arg(x) __percpu_prefix "%" #x |
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| 68 | |||
| 69 | /* |
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| 70 | * Initialized pointers to per-cpu variables needed for the boot |
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| 71 | * processor need to use these macros to get the proper address |
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| 72 | * offset from __per_cpu_load on SMP. |
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| 73 | * |
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| 74 | * There also must be an entry in vmlinux_64.lds.S |
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| 75 | */ |
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| 76 | #define DECLARE_INIT_PER_CPU(var) \ |
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| 77 | extern typeof(var) init_per_cpu_var(var) |
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| 78 | |||
| 79 | #ifdef CONFIG_X86_64_SMP |
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| 80 | #define init_per_cpu_var(var) init_per_cpu__##var |
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| 81 | #else |
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| 82 | #define init_per_cpu_var(var) var |
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| 83 | #endif |
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| 84 | |||
| 85 | /* For arch-specific code, we can use direct single-insn ops (they |
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| 86 | * don't give an lvalue though). */ |
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| 87 | extern void __bad_percpu_size(void); |
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| 88 | |||
| 89 | #define percpu_to_op(op, var, val) \ |
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| 90 | do { \ |
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| 91 | typedef typeof(var) pto_T__; \ |
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| 92 | if (0) { \ |
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| 93 | pto_T__ pto_tmp__; \ |
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| 94 | pto_tmp__ = (val); \ |
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| 95 | (void)pto_tmp__; \ |
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| 96 | } \ |
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| 97 | switch (sizeof(var)) { \ |
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| 98 | case 1: \ |
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| 99 | asm(op "b %1,"__percpu_arg(0) \ |
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| 100 | : "+m" (var) \ |
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| 101 | : "qi" ((pto_T__)(val))); \ |
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| 102 | break; \ |
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| 103 | case 2: \ |
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| 104 | asm(op "w %1,"__percpu_arg(0) \ |
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| 105 | : "+m" (var) \ |
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| 106 | : "ri" ((pto_T__)(val))); \ |
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| 107 | break; \ |
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| 108 | case 4: \ |
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| 109 | asm(op "l %1,"__percpu_arg(0) \ |
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| 110 | : "+m" (var) \ |
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| 111 | : "ri" ((pto_T__)(val))); \ |
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| 112 | break; \ |
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| 113 | case 8: \ |
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| 114 | asm(op "q %1,"__percpu_arg(0) \ |
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| 115 | : "+m" (var) \ |
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| 116 | : "re" ((pto_T__)(val))); \ |
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| 117 | break; \ |
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| 118 | default: __bad_percpu_size(); \ |
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| 119 | } \ |
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| 120 | } while (0) |
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| 121 | |||
| 122 | /* |
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| 123 | * Generate a percpu add to memory instruction and optimize code |
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| 124 | * if one is added or subtracted. |
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| 125 | */ |
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| 126 | #define percpu_add_op(var, val) \ |
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| 127 | do { \ |
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| 128 | typedef typeof(var) pao_T__; \ |
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| 129 | const int pao_ID__ = (__builtin_constant_p(val) && \ |
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| 130 | ((val) == 1 || (val) == -1)) ? \ |
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| 131 | (int)(val) : 0; \ |
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| 132 | if (0) { \ |
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| 133 | pao_T__ pao_tmp__; \ |
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| 134 | pao_tmp__ = (val); \ |
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| 135 | (void)pao_tmp__; \ |
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| 136 | } \ |
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| 137 | switch (sizeof(var)) { \ |
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| 138 | case 1: \ |
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| 139 | if (pao_ID__ == 1) \ |
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| 140 | asm("incb "__percpu_arg(0) : "+m" (var)); \ |
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| 141 | else if (pao_ID__ == -1) \ |
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| 142 | asm("decb "__percpu_arg(0) : "+m" (var)); \ |
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| 143 | else \ |
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| 144 | asm("addb %1, "__percpu_arg(0) \ |
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| 145 | : "+m" (var) \ |
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| 146 | : "qi" ((pao_T__)(val))); \ |
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| 147 | break; \ |
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| 148 | case 2: \ |
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| 149 | if (pao_ID__ == 1) \ |
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| 150 | asm("incw "__percpu_arg(0) : "+m" (var)); \ |
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| 151 | else if (pao_ID__ == -1) \ |
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| 152 | asm("decw "__percpu_arg(0) : "+m" (var)); \ |
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| 153 | else \ |
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| 154 | asm("addw %1, "__percpu_arg(0) \ |
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| 155 | : "+m" (var) \ |
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| 156 | : "ri" ((pao_T__)(val))); \ |
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| 157 | break; \ |
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| 158 | case 4: \ |
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| 159 | if (pao_ID__ == 1) \ |
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| 160 | asm("incl "__percpu_arg(0) : "+m" (var)); \ |
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| 161 | else if (pao_ID__ == -1) \ |
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| 162 | asm("decl "__percpu_arg(0) : "+m" (var)); \ |
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| 163 | else \ |
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| 164 | asm("addl %1, "__percpu_arg(0) \ |
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| 165 | : "+m" (var) \ |
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| 166 | : "ri" ((pao_T__)(val))); \ |
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| 167 | break; \ |
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| 168 | case 8: \ |
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| 169 | if (pao_ID__ == 1) \ |
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| 170 | asm("incq "__percpu_arg(0) : "+m" (var)); \ |
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| 171 | else if (pao_ID__ == -1) \ |
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| 172 | asm("decq "__percpu_arg(0) : "+m" (var)); \ |
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| 173 | else \ |
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| 174 | asm("addq %1, "__percpu_arg(0) \ |
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| 175 | : "+m" (var) \ |
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| 176 | : "re" ((pao_T__)(val))); \ |
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| 177 | break; \ |
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| 178 | default: __bad_percpu_size(); \ |
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| 179 | } \ |
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| 180 | } while (0) |
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| 181 | |||
| 182 | #define percpu_from_op(op, var) \ |
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| 183 | ({ \ |
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| 184 | typeof(var) pfo_ret__; \ |
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| 185 | switch (sizeof(var)) { \ |
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| 186 | case 1: \ |
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| 187 | asm(op "b "__percpu_arg(1)",%0" \ |
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| 188 | : "=q" (pfo_ret__) \ |
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| 189 | : "m" (var)); \ |
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| 190 | break; \ |
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| 191 | case 2: \ |
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| 192 | asm(op "w "__percpu_arg(1)",%0" \ |
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| 193 | : "=r" (pfo_ret__) \ |
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| 194 | : "m" (var)); \ |
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| 195 | break; \ |
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| 196 | case 4: \ |
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| 197 | asm(op "l "__percpu_arg(1)",%0" \ |
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| 198 | : "=r" (pfo_ret__) \ |
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| 199 | : "m" (var)); \ |
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| 200 | break; \ |
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| 201 | case 8: \ |
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| 202 | asm(op "q "__percpu_arg(1)",%0" \ |
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| 203 | : "=r" (pfo_ret__) \ |
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| 204 | : "m" (var)); \ |
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| 205 | break; \ |
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| 206 | default: __bad_percpu_size(); \ |
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| 207 | } \ |
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| 208 | pfo_ret__; \ |
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| 209 | }) |
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| 210 | |||
| 211 | #define percpu_stable_op(op, var) \ |
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| 212 | ({ \ |
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| 213 | typeof(var) pfo_ret__; \ |
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| 214 | switch (sizeof(var)) { \ |
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| 215 | case 1: \ |
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| 216 | asm(op "b "__percpu_arg(P1)",%0" \ |
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| 217 | : "=q" (pfo_ret__) \ |
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| 218 | : "p" (&(var))); \ |
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| 219 | break; \ |
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| 220 | case 2: \ |
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| 221 | asm(op "w "__percpu_arg(P1)",%0" \ |
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| 222 | : "=r" (pfo_ret__) \ |
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| 223 | : "p" (&(var))); \ |
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| 224 | break; \ |
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| 225 | case 4: \ |
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| 226 | asm(op "l "__percpu_arg(P1)",%0" \ |
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| 227 | : "=r" (pfo_ret__) \ |
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| 228 | : "p" (&(var))); \ |
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| 229 | break; \ |
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| 230 | case 8: \ |
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| 231 | asm(op "q "__percpu_arg(P1)",%0" \ |
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| 232 | : "=r" (pfo_ret__) \ |
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| 233 | : "p" (&(var))); \ |
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| 234 | break; \ |
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| 235 | default: __bad_percpu_size(); \ |
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| 236 | } \ |
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| 237 | pfo_ret__; \ |
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| 238 | }) |
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| 239 | |||
| 240 | #define percpu_unary_op(op, var) \ |
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| 241 | ({ \ |
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| 242 | switch (sizeof(var)) { \ |
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| 243 | case 1: \ |
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| 244 | asm(op "b "__percpu_arg(0) \ |
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| 245 | : "+m" (var)); \ |
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| 246 | break; \ |
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| 247 | case 2: \ |
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| 248 | asm(op "w "__percpu_arg(0) \ |
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| 249 | : "+m" (var)); \ |
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| 250 | break; \ |
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| 251 | case 4: \ |
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| 252 | asm(op "l "__percpu_arg(0) \ |
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| 253 | : "+m" (var)); \ |
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| 254 | break; \ |
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| 255 | case 8: \ |
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| 256 | asm(op "q "__percpu_arg(0) \ |
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| 257 | : "+m" (var)); \ |
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| 258 | break; \ |
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| 259 | default: __bad_percpu_size(); \ |
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| 260 | } \ |
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| 261 | }) |
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| 262 | |||
| 263 | /* |
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| 264 | * Add return operation |
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| 265 | */ |
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| 266 | #define percpu_add_return_op(var, val) \ |
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| 267 | ({ \ |
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| 268 | typeof(var) paro_ret__ = val; \ |
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| 269 | switch (sizeof(var)) { \ |
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| 270 | case 1: \ |
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| 271 | asm("xaddb %0, "__percpu_arg(1) \ |
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| 272 | : "+q" (paro_ret__), "+m" (var) \ |
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| 273 | : : "memory"); \ |
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| 274 | break; \ |
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| 275 | case 2: \ |
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| 276 | asm("xaddw %0, "__percpu_arg(1) \ |
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| 277 | : "+r" (paro_ret__), "+m" (var) \ |
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| 278 | : : "memory"); \ |
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| 279 | break; \ |
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| 280 | case 4: \ |
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| 281 | asm("xaddl %0, "__percpu_arg(1) \ |
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| 282 | : "+r" (paro_ret__), "+m" (var) \ |
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| 283 | : : "memory"); \ |
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| 284 | break; \ |
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| 285 | case 8: \ |
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| 286 | asm("xaddq %0, "__percpu_arg(1) \ |
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| 287 | : "+re" (paro_ret__), "+m" (var) \ |
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| 288 | : : "memory"); \ |
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| 289 | break; \ |
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| 290 | default: __bad_percpu_size(); \ |
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| 291 | } \ |
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| 292 | paro_ret__ += val; \ |
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| 293 | paro_ret__; \ |
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| 294 | }) |
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| 295 | |||
| 296 | /* |
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| 297 | * xchg is implemented using cmpxchg without a lock prefix. xchg is |
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| 298 | * expensive due to the implied lock prefix. The processor cannot prefetch |
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| 299 | * cachelines if xchg is used. |
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| 300 | */ |
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| 301 | #define percpu_xchg_op(var, nval) \ |
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| 302 | ({ \ |
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| 303 | typeof(var) pxo_ret__; \ |
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| 304 | typeof(var) pxo_new__ = (nval); \ |
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| 305 | switch (sizeof(var)) { \ |
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| 306 | case 1: \ |
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| 307 | asm("\n\tmov "__percpu_arg(1)",%%al" \ |
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| 308 | "\n1:\tcmpxchgb %2, "__percpu_arg(1) \ |
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| 309 | "\n\tjnz 1b" \ |
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| 310 | : "=&a" (pxo_ret__), "+m" (var) \ |
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| 311 | : "q" (pxo_new__) \ |
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| 312 | : "memory"); \ |
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| 313 | break; \ |
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| 314 | case 2: \ |
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| 315 | asm("\n\tmov "__percpu_arg(1)",%%ax" \ |
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| 316 | "\n1:\tcmpxchgw %2, "__percpu_arg(1) \ |
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| 317 | "\n\tjnz 1b" \ |
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| 318 | : "=&a" (pxo_ret__), "+m" (var) \ |
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| 319 | : "r" (pxo_new__) \ |
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| 320 | : "memory"); \ |
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| 321 | break; \ |
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| 322 | case 4: \ |
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| 323 | asm("\n\tmov "__percpu_arg(1)",%%eax" \ |
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| 324 | "\n1:\tcmpxchgl %2, "__percpu_arg(1) \ |
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| 325 | "\n\tjnz 1b" \ |
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| 326 | : "=&a" (pxo_ret__), "+m" (var) \ |
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| 327 | : "r" (pxo_new__) \ |
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| 328 | : "memory"); \ |
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| 329 | break; \ |
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| 330 | case 8: \ |
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| 331 | asm("\n\tmov "__percpu_arg(1)",%%rax" \ |
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| 332 | "\n1:\tcmpxchgq %2, "__percpu_arg(1) \ |
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| 333 | "\n\tjnz 1b" \ |
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| 334 | : "=&a" (pxo_ret__), "+m" (var) \ |
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| 335 | : "r" (pxo_new__) \ |
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| 336 | : "memory"); \ |
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| 337 | break; \ |
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| 338 | default: __bad_percpu_size(); \ |
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| 339 | } \ |
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| 340 | pxo_ret__; \ |
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| 341 | }) |
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| 342 | |||
| 343 | /* |
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| 344 | * cmpxchg has no such implied lock semantics as a result it is much |
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| 345 | * more efficient for cpu local operations. |
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| 346 | */ |
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| 347 | #define percpu_cmpxchg_op(var, oval, nval) \ |
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| 348 | ({ \ |
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| 349 | typeof(var) pco_ret__; \ |
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| 350 | typeof(var) pco_old__ = (oval); \ |
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| 351 | typeof(var) pco_new__ = (nval); \ |
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| 352 | switch (sizeof(var)) { \ |
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| 353 | case 1: \ |
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| 354 | asm("cmpxchgb %2, "__percpu_arg(1) \ |
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| 355 | : "=a" (pco_ret__), "+m" (var) \ |
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| 356 | : "q" (pco_new__), "0" (pco_old__) \ |
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| 357 | : "memory"); \ |
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| 358 | break; \ |
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| 359 | case 2: \ |
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| 360 | asm("cmpxchgw %2, "__percpu_arg(1) \ |
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| 361 | : "=a" (pco_ret__), "+m" (var) \ |
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| 362 | : "r" (pco_new__), "0" (pco_old__) \ |
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| 363 | : "memory"); \ |
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| 364 | break; \ |
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| 365 | case 4: \ |
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| 366 | asm("cmpxchgl %2, "__percpu_arg(1) \ |
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| 367 | : "=a" (pco_ret__), "+m" (var) \ |
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| 368 | : "r" (pco_new__), "0" (pco_old__) \ |
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| 369 | : "memory"); \ |
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| 370 | break; \ |
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| 371 | case 8: \ |
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| 372 | asm("cmpxchgq %2, "__percpu_arg(1) \ |
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| 373 | : "=a" (pco_ret__), "+m" (var) \ |
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| 374 | : "r" (pco_new__), "0" (pco_old__) \ |
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| 375 | : "memory"); \ |
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| 376 | break; \ |
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| 377 | default: __bad_percpu_size(); \ |
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| 378 | } \ |
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| 379 | pco_ret__; \ |
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| 380 | }) |
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| 381 | |||
| 382 | /* |
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| 383 | * this_cpu_read() makes gcc load the percpu variable every time it is |
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| 384 | * accessed while this_cpu_read_stable() allows the value to be cached. |
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| 385 | * this_cpu_read_stable() is more efficient and can be used if its value |
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| 386 | * is guaranteed to be valid across cpus. The current users include |
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| 387 | * get_current() and get_thread_info() both of which are actually |
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| 388 | * per-thread variables implemented as per-cpu variables and thus |
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| 389 | * stable for the duration of the respective task. |
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| 390 | */ |
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| 391 | #define this_cpu_read_stable(var) percpu_stable_op("mov", var) |
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| 392 | |||
| 393 | #define raw_cpu_read_1(pcp) percpu_from_op("mov", pcp) |
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| 394 | #define raw_cpu_read_2(pcp) percpu_from_op("mov", pcp) |
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| 395 | #define raw_cpu_read_4(pcp) percpu_from_op("mov", pcp) |
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| 396 | |||
| 397 | #define raw_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 398 | #define raw_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 399 | #define raw_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 400 | #define raw_cpu_add_1(pcp, val) percpu_add_op((pcp), val) |
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| 401 | #define raw_cpu_add_2(pcp, val) percpu_add_op((pcp), val) |
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| 402 | #define raw_cpu_add_4(pcp, val) percpu_add_op((pcp), val) |
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| 403 | #define raw_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) |
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| 404 | #define raw_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) |
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| 405 | #define raw_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) |
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| 406 | #define raw_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) |
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| 407 | #define raw_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) |
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| 408 | #define raw_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) |
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| 409 | #define raw_cpu_xchg_1(pcp, val) percpu_xchg_op(pcp, val) |
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| 410 | #define raw_cpu_xchg_2(pcp, val) percpu_xchg_op(pcp, val) |
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| 411 | #define raw_cpu_xchg_4(pcp, val) percpu_xchg_op(pcp, val) |
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| 412 | |||
| 413 | #define this_cpu_read_1(pcp) percpu_from_op("mov", pcp) |
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| 414 | #define this_cpu_read_2(pcp) percpu_from_op("mov", pcp) |
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| 415 | #define this_cpu_read_4(pcp) percpu_from_op("mov", pcp) |
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| 416 | #define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 417 | #define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 418 | #define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 419 | #define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) |
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| 420 | #define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) |
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| 421 | #define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) |
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| 422 | #define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) |
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| 423 | #define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) |
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| 424 | #define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) |
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| 425 | #define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) |
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| 426 | #define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) |
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| 427 | #define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) |
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| 428 | #define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) |
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| 429 | #define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) |
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| 430 | #define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) |
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| 431 | |||
| 432 | #define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) |
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| 433 | #define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) |
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| 434 | #define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) |
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| 435 | #define raw_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 436 | #define raw_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 437 | #define raw_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 438 | |||
| 439 | #define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) |
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| 440 | #define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) |
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| 441 | #define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) |
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| 442 | #define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 443 | #define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 444 | #define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 445 | |||
| 446 | #ifdef CONFIG_X86_CMPXCHG64 |
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| 447 | #define percpu_cmpxchg8b_double(pcp1, pcp2, o1, o2, n1, n2) \ |
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| 448 | ({ \ |
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| 449 | bool __ret; \ |
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| 450 | typeof(pcp1) __o1 = (o1), __n1 = (n1); \ |
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| 451 | typeof(pcp2) __o2 = (o2), __n2 = (n2); \ |
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| 452 | asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \ |
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| 453 | : "=a" (__ret), "+m" (pcp1), "+m" (pcp2), "+d" (__o2) \ |
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| 454 | : "b" (__n1), "c" (__n2), "a" (__o1)); \ |
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| 455 | __ret; \ |
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| 456 | }) |
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| 457 | |||
| 458 | #define raw_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double |
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| 459 | #define this_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double |
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| 460 | #endif /* CONFIG_X86_CMPXCHG64 */ |
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| 461 | |||
| 462 | /* |
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| 463 | * Per cpu atomic 64 bit operations are only available under 64 bit. |
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| 464 | * 32 bit must fall back to generic operations. |
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| 465 | */ |
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| 466 | #ifdef CONFIG_X86_64 |
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| 467 | #define raw_cpu_read_8(pcp) percpu_from_op("mov", pcp) |
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| 468 | #define raw_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 469 | #define raw_cpu_add_8(pcp, val) percpu_add_op((pcp), val) |
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| 470 | #define raw_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) |
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| 471 | #define raw_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) |
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| 472 | #define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) |
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| 473 | #define raw_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) |
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| 474 | #define raw_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 475 | |||
| 476 | #define this_cpu_read_8(pcp) percpu_from_op("mov", pcp) |
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| 477 | #define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) |
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| 478 | #define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) |
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| 479 | #define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) |
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| 480 | #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) |
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| 481 | #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) |
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| 482 | #define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) |
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| 483 | #define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) |
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| 484 | |||
| 485 | /* |
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| 486 | * Pretty complex macro to generate cmpxchg16 instruction. The instruction |
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| 487 | * is not supported on early AMD64 processors so we must be able to emulate |
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| 488 | * it in software. The address used in the cmpxchg16 instruction must be |
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| 489 | * aligned to a 16 byte boundary. |
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| 490 | */ |
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| 491 | #define percpu_cmpxchg16b_double(pcp1, pcp2, o1, o2, n1, n2) \ |
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| 492 | ({ \ |
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| 493 | bool __ret; \ |
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| 494 | typeof(pcp1) __o1 = (o1), __n1 = (n1); \ |
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| 495 | typeof(pcp2) __o2 = (o2), __n2 = (n2); \ |
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| 496 | alternative_io("leaq %P1,%%rsi\n\tcall this_cpu_cmpxchg16b_emu\n\t", \ |
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| 497 | "cmpxchg16b " __percpu_arg(1) "\n\tsetz %0\n\t", \ |
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| 498 | X86_FEATURE_CX16, \ |
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| 499 | ASM_OUTPUT2("=a" (__ret), "+m" (pcp1), \ |
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| 500 | "+m" (pcp2), "+d" (__o2)), \ |
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| 501 | "b" (__n1), "c" (__n2), "a" (__o1) : "rsi"); \ |
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| 502 | __ret; \ |
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| 503 | }) |
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| 504 | |||
| 505 | #define raw_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double |
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| 506 | #define this_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double |
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| 507 | |||
| 508 | #endif |
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| 509 | |||
| 510 | /* This is not atomic against other CPUs -- CPU preemption needs to be off */ |
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| 511 | #define x86_test_and_clear_bit_percpu(bit, var) \ |
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| 512 | ({ \ |
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| 513 | int old__; \ |
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| 514 | asm volatile("btr %2,"__percpu_arg(1)"\n\tsbbl %0,%0" \ |
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| 515 | : "=r" (old__), "+m" (var) \ |
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| 516 | : "dIr" (bit)); \ |
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| 517 | old__; \ |
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| 518 | }) |
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| 519 | |||
| 520 | static __always_inline int x86_this_cpu_constant_test_bit(unsigned int nr, |
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| 521 | const unsigned long __percpu *addr) |
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| 522 | { |
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| 523 | unsigned long __percpu *a = (unsigned long *)addr + nr / BITS_PER_LONG; |
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| 524 | |||
| 525 | #ifdef CONFIG_X86_64 |
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| 526 | return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_8(*a)) != 0; |
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| 527 | #else |
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| 528 | return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_4(*a)) != 0; |
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| 529 | #endif |
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| 530 | } |
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| 531 | |||
| 532 | static inline int x86_this_cpu_variable_test_bit(int nr, |
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| 533 | const unsigned long __percpu *addr) |
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| 534 | { |
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| 535 | int oldbit; |
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| 536 | |||
| 537 | asm volatile("bt "__percpu_arg(2)",%1\n\t" |
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| 538 | "sbb %0,%0" |
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| 539 | : "=r" (oldbit) |
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| 540 | : "m" (*(unsigned long *)addr), "Ir" (nr)); |
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| 541 | |||
| 542 | return oldbit; |
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| 543 | } |
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| 544 | |||
| 545 | #define x86_this_cpu_test_bit(nr, addr) \ |
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| 546 | (__builtin_constant_p((nr)) \ |
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| 547 | ? x86_this_cpu_constant_test_bit((nr), (addr)) \ |
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| 548 | : x86_this_cpu_variable_test_bit((nr), (addr))) |
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| 549 | |||
| 550 | |||
| 551 | #include |
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| 552 | |||
| 553 | /* We can use this directly for local CPU (faster). */ |
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| 554 | DECLARE_PER_CPU_READ_MOSTLY(unsigned long, this_cpu_off); |
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| 555 | |||
| 556 | #endif /* !__ASSEMBLY__ */ |
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| 557 | |||
| 558 | #ifdef CONFIG_SMP |
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| 559 | |||
| 560 | /* |
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| 561 | * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu |
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| 562 | * variables that are initialized and accessed before there are per_cpu |
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| 563 | * areas allocated. |
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| 564 | */ |
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| 565 | |||
| 566 | #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ |
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| 567 | DEFINE_PER_CPU(_type, _name) = _initvalue; \ |
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| 568 | __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ |
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| 569 | { [0 ... NR_CPUS-1] = _initvalue }; \ |
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| 570 | __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map |
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| 571 | |||
| 572 | #define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \ |
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| 573 | DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue; \ |
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| 574 | __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ |
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| 575 | { [0 ... NR_CPUS-1] = _initvalue }; \ |
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| 576 | __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map |
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| 577 | |||
| 578 | #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ |
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| 579 | EXPORT_PER_CPU_SYMBOL(_name) |
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| 580 | |||
| 581 | #define DECLARE_EARLY_PER_CPU(_type, _name) \ |
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| 582 | DECLARE_PER_CPU(_type, _name); \ |
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| 583 | extern __typeof__(_type) *_name##_early_ptr; \ |
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| 584 | extern __typeof__(_type) _name##_early_map[] |
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| 585 | |||
| 586 | #define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \ |
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| 587 | DECLARE_PER_CPU_READ_MOSTLY(_type, _name); \ |
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| 588 | extern __typeof__(_type) *_name##_early_ptr; \ |
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| 589 | extern __typeof__(_type) _name##_early_map[] |
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| 590 | |||
| 591 | #define early_per_cpu_ptr(_name) (_name##_early_ptr) |
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| 592 | #define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx]) |
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| 593 | #define early_per_cpu(_name, _cpu) \ |
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| 594 | *(early_per_cpu_ptr(_name) ? \ |
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| 595 | &early_per_cpu_ptr(_name)[_cpu] : \ |
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| 596 | &per_cpu(_name, _cpu)) |
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| 597 | |||
| 598 | #else /* !CONFIG_SMP */ |
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| 599 | #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ |
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| 600 | DEFINE_PER_CPU(_type, _name) = _initvalue |
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| 601 | |||
| 602 | #define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \ |
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| 603 | DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue |
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| 604 | |||
| 605 | #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ |
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| 606 | EXPORT_PER_CPU_SYMBOL(_name) |
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| 607 | |||
| 608 | #define DECLARE_EARLY_PER_CPU(_type, _name) \ |
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| 609 | DECLARE_PER_CPU(_type, _name) |
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| 610 | |||
| 611 | #define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \ |
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| 612 | DECLARE_PER_CPU_READ_MOSTLY(_type, _name) |
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| 613 | |||
| 614 | #define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu) |
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| 615 | #define early_per_cpu_ptr(_name) NULL |
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| 616 | /* no early_per_cpu_map() */ |
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| 617 | |||
| 618 | #endif /* !CONFIG_SMP */ |
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| 619 | |||
| 620 | #endif /* _ASM_X86_PERCPU_H */ |