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5270 | serge | 1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H |
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3 | |||
4 | #include |
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5 | |||
6 | #ifndef __ASSEMBLY__ |
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7 | |||
8 | #include |
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9 | #include |
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10 | #include |
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11 | |||
12 | struct msr { |
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13 | union { |
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14 | struct { |
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15 | u32 l; |
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16 | u32 h; |
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17 | }; |
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18 | u64 q; |
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19 | }; |
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20 | }; |
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21 | |||
22 | struct msr_info { |
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23 | u32 msr_no; |
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24 | struct msr reg; |
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25 | struct msr *msrs; |
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26 | int err; |
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27 | }; |
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28 | |||
29 | struct msr_regs_info { |
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30 | u32 *regs; |
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31 | int err; |
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32 | }; |
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33 | |||
34 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
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35 | { |
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36 | unsigned long low, high; |
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37 | asm volatile(".byte 0x0f,0x01,0xf9" |
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38 | : "=a" (low), "=d" (high), "=c" (*aux)); |
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39 | return low | ((u64)high << 32); |
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40 | } |
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41 | |||
42 | /* |
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43 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
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44 | * constraint has different meanings. For i386, "A" means exactly |
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45 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, |
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46 | * it means rax *or* rdx. |
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47 | */ |
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48 | #ifdef CONFIG_X86_64 |
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49 | #define DECLARE_ARGS(val, low, high) unsigned low, high |
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50 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
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51 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
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52 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
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53 | #else |
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54 | #define DECLARE_ARGS(val, low, high) unsigned long long val |
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55 | #define EAX_EDX_VAL(val, low, high) (val) |
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56 | #define EAX_EDX_ARGS(val, low, high) "A" (val) |
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57 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
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58 | #endif |
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59 | |||
60 | static inline unsigned long long native_read_msr(unsigned int msr) |
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61 | { |
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62 | DECLARE_ARGS(val, low, high); |
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63 | |||
64 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
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65 | return EAX_EDX_VAL(val, low, high); |
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66 | } |
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67 | |||
68 | static inline unsigned long long native_read_msr_safe(unsigned int msr, |
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69 | int *err) |
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70 | { |
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71 | DECLARE_ARGS(val, low, high); |
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72 | |||
73 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
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74 | "1:\n\t" |
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75 | ".section .fixup,\"ax\"\n\t" |
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76 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
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77 | ".previous\n\t" |
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78 | _ASM_EXTABLE(2b, 3b) |
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79 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
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80 | : "c" (msr), [fault] "i" (-EIO)); |
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81 | return EAX_EDX_VAL(val, low, high); |
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82 | } |
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83 | |||
84 | static inline void native_write_msr(unsigned int msr, |
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85 | unsigned low, unsigned high) |
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86 | { |
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87 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
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88 | } |
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89 | |||
90 | /* Can be uninlined because referenced by paravirt */ |
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91 | notrace static inline int native_write_msr_safe(unsigned int msr, |
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92 | unsigned low, unsigned high) |
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93 | { |
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94 | int err; |
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95 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
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96 | "1:\n\t" |
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97 | ".section .fixup,\"ax\"\n\t" |
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98 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
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99 | ".previous\n\t" |
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100 | _ASM_EXTABLE(2b, 3b) |
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101 | : [err] "=a" (err) |
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102 | : "c" (msr), "0" (low), "d" (high), |
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103 | [fault] "i" (-EIO) |
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104 | : "memory"); |
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105 | return err; |
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106 | } |
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107 | |||
108 | extern unsigned long long native_read_tsc(void); |
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109 | |||
110 | extern int rdmsr_safe_regs(u32 regs[8]); |
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111 | extern int wrmsr_safe_regs(u32 regs[8]); |
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112 | |||
113 | static __always_inline unsigned long long __native_read_tsc(void) |
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114 | { |
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115 | DECLARE_ARGS(val, low, high); |
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116 | |||
117 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
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118 | |||
119 | return EAX_EDX_VAL(val, low, high); |
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120 | } |
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121 | |||
122 | static inline unsigned long long native_read_pmc(int counter) |
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123 | { |
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124 | DECLARE_ARGS(val, low, high); |
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125 | |||
126 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
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127 | return EAX_EDX_VAL(val, low, high); |
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128 | } |
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129 | |||
130 | #ifdef CONFIG_PARAVIRT |
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131 | #include |
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132 | #else |
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133 | #include |
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134 | /* |
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135 | * Access to machine-specific registers (available on 586 and better only) |
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136 | * Note: the rd* operations modify the parameters directly (without using |
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137 | * pointer indirection), this allows gcc to optimize better |
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138 | */ |
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139 | |||
140 | #define rdmsr(msr, low, high) \ |
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141 | do { \ |
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142 | u64 __val = native_read_msr((msr)); \ |
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143 | (void)((low) = (u32)__val); \ |
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144 | (void)((high) = (u32)(__val >> 32)); \ |
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145 | } while (0) |
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146 | |||
147 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
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148 | { |
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149 | native_write_msr(msr, low, high); |
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150 | } |
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151 | |||
152 | #define rdmsrl(msr, val) \ |
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153 | ((val) = native_read_msr((msr))) |
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154 | |||
155 | #define wrmsrl(msr, val) \ |
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156 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
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157 | |||
158 | /* wrmsr with exception handling */ |
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159 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
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160 | { |
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161 | return native_write_msr_safe(msr, low, high); |
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162 | } |
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163 | |||
164 | /* rdmsr with exception handling */ |
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165 | #define rdmsr_safe(msr, low, high) \ |
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166 | ({ \ |
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167 | int __err; \ |
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168 | u64 __val = native_read_msr_safe((msr), &__err); \ |
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169 | (*low) = (u32)__val; \ |
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170 | (*high) = (u32)(__val >> 32); \ |
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171 | __err; \ |
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172 | }) |
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173 | |||
174 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
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175 | { |
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176 | int err; |
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177 | |||
178 | *p = native_read_msr_safe(msr, &err); |
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179 | return err; |
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180 | } |
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181 | |||
182 | #define rdtscl(low) \ |
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183 | ((low) = (u32)__native_read_tsc()) |
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184 | |||
185 | #define rdtscll(val) \ |
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186 | ((val) = __native_read_tsc()) |
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187 | |||
188 | #define rdpmc(counter, low, high) \ |
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189 | do { \ |
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190 | u64 _l = native_read_pmc((counter)); \ |
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191 | (low) = (u32)_l; \ |
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192 | (high) = (u32)(_l >> 32); \ |
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193 | } while (0) |
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194 | |||
195 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
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196 | |||
197 | #define rdtscp(low, high, aux) \ |
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198 | do { \ |
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199 | unsigned long long _val = native_read_tscp(&(aux)); \ |
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200 | (low) = (u32)_val; \ |
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201 | (high) = (u32)(_val >> 32); \ |
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202 | } while (0) |
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203 | |||
204 | #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
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205 | |||
206 | #endif /* !CONFIG_PARAVIRT */ |
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207 | |||
208 | #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \ |
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209 | (u32)((val) >> 32)) |
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210 | |||
211 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
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212 | |||
213 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
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214 | |||
215 | struct msr *msrs_alloc(void); |
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216 | void msrs_free(struct msr *msrs); |
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217 | int msr_set_bit(u32 msr, u8 bit); |
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218 | int msr_clear_bit(u32 msr, u8 bit); |
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219 | |||
220 | #ifdef CONFIG_SMP |
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221 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
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222 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
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223 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
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224 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
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225 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
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226 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
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227 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
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228 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
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229 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
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230 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
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231 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
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232 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
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233 | #else /* CONFIG_SMP */ |
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234 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
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235 | { |
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236 | rdmsr(msr_no, *l, *h); |
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237 | return 0; |
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238 | } |
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239 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
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240 | { |
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241 | wrmsr(msr_no, l, h); |
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242 | return 0; |
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243 | } |
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244 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
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245 | { |
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246 | rdmsrl(msr_no, *q); |
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247 | return 0; |
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248 | } |
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249 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
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250 | { |
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251 | wrmsrl(msr_no, q); |
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252 | return 0; |
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253 | } |
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254 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
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255 | struct msr *msrs) |
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256 | { |
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257 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); |
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258 | } |
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259 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
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260 | struct msr *msrs) |
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261 | { |
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262 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); |
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263 | } |
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264 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
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265 | u32 *l, u32 *h) |
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266 | { |
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267 | return rdmsr_safe(msr_no, l, h); |
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268 | } |
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269 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
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270 | { |
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271 | return wrmsr_safe(msr_no, l, h); |
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272 | } |
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273 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
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274 | { |
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275 | return rdmsrl_safe(msr_no, q); |
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276 | } |
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277 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
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278 | { |
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279 | return wrmsrl_safe(msr_no, q); |
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280 | } |
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281 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
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282 | { |
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283 | return rdmsr_safe_regs(regs); |
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284 | } |
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285 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
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286 | { |
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287 | return wrmsr_safe_regs(regs); |
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288 | } |
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289 | #endif /* CONFIG_SMP */ |
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290 | #endif /* __ASSEMBLY__ */ |
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291 | #endif /* _ASM_X86_MSR_H */><>><> |