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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 7143 | serge | 1 | #ifndef _ASM_X86_CPUFEATURES_H |
| 2 | #define _ASM_X86_CPUFEATURES_H |
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| 3 | |||
| 4 | #ifndef _ASM_X86_REQUIRED_FEATURES_H |
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| 5 | #include |
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| 6 | #endif |
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| 7 | |||
| 8 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
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| 9 | #include |
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| 10 | #endif |
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| 11 | |||
| 12 | /* |
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| 13 | * Defines x86 CPU feature bits |
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| 14 | */ |
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| 15 | #define NCAPINTS 17 /* N 32-bit words worth of info */ |
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| 16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
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| 17 | |||
| 18 | /* |
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| 19 | * Note: If the comment begins with a quoted string, that string is used |
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| 20 | * in /proc/cpuinfo instead of the macro name. If the string is "", |
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| 21 | * this feature bit is not displayed in /proc/cpuinfo at all. |
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| 22 | */ |
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| 23 | |||
| 24 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ |
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| 25 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ |
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| 26 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ |
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| 27 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ |
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| 28 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ |
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| 29 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ |
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| 30 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ |
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| 31 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ |
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| 32 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ |
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| 33 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ |
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| 34 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ |
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| 35 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ |
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| 36 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ |
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| 37 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ |
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| 38 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ |
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| 39 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ |
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| 40 | /* (plus FCMOVcc, FCOMI with FPU) */ |
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| 41 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ |
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| 42 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ |
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| 43 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ |
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| 44 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ |
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| 45 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ |
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| 46 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ |
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| 47 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ |
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| 48 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
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| 49 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ |
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| 50 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ |
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| 51 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ |
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| 52 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ |
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| 53 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ |
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| 54 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ |
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| 55 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ |
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| 56 | |||
| 57 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
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| 58 | /* Don't duplicate feature flags which are redundant with Intel! */ |
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| 59 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
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| 60 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ |
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| 61 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ |
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| 62 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ |
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| 63 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
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| 64 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ |
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| 65 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ |
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| 66 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ |
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| 67 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ |
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| 68 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ |
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| 69 | |||
| 70 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
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| 71 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
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| 72 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ |
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| 73 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ |
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| 74 | |||
| 75 | /* Other features, Linux-defined mapping, word 3 */ |
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| 76 | /* This range is used for feature bits which conflict or are synthesized */ |
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| 77 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ |
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| 78 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
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| 79 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
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| 80 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
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| 81 | /* cpu types for specific tunings: */ |
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| 82 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
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| 83 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ |
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| 84 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ |
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| 85 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ |
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| 86 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ |
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| 87 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ |
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| 88 | #define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ |
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| 89 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
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| 90 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ |
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| 91 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ |
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| 92 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ |
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| 93 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ |
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| 94 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ |
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| 95 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ |
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| 96 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ |
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| 97 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ |
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| 98 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
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| 99 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ |
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| 100 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ |
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| 101 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ |
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| 102 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ |
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| 103 | /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ |
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| 104 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ |
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| 105 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ |
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| 106 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ |
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| 107 | #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
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| 108 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
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| 109 | #define X86_FEATURE_MCE_RECOVERY ( 3*32+31) /* cpu has recoverable machine checks */ |
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| 110 | |||
| 111 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
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| 112 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ |
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| 113 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ |
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| 114 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ |
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| 115 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ |
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| 116 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
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| 117 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ |
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| 118 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ |
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| 119 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ |
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| 120 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ |
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| 121 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ |
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| 122 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ |
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| 123 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ |
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| 124 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ |
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| 125 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ |
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| 126 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ |
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| 127 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ |
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| 128 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ |
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| 129 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ |
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| 130 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ |
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| 131 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ |
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| 132 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ |
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| 133 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ |
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| 134 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ |
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| 135 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ |
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| 136 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ |
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| 137 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
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| 138 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ |
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| 139 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ |
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| 140 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ |
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| 141 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ |
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| 142 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ |
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| 143 | |||
| 144 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
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| 145 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ |
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| 146 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ |
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| 147 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
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| 148 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ |
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| 149 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ |
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| 150 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ |
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| 151 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ |
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| 152 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ |
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| 153 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ |
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| 154 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ |
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| 155 | |||
| 156 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ |
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| 157 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ |
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| 158 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ |
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| 159 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ |
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| 160 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ |
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| 161 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ |
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| 162 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ |
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| 163 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ |
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| 164 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ |
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| 165 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ |
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| 166 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ |
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| 167 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ |
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| 168 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ |
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| 169 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ |
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| 170 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ |
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| 171 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ |
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| 172 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ |
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| 173 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ |
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| 174 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ |
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| 175 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ |
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| 176 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ |
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| 177 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ |
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| 178 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ |
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| 179 | #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ |
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| 180 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
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| 181 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ |
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| 182 | |||
| 183 | /* |
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| 184 | * Auxiliary flags: Linux defined - For features scattered in various |
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| 185 | * CPUID levels like 0x6, 0xA etc, word 7. |
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| 186 | * |
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| 187 | * Reuse free bits when adding new feature flags! |
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| 188 | */ |
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| 189 | |||
| 190 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
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| 191 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
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| 192 | |||
| 193 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
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| 194 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
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| 195 | |||
| 196 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
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| 197 | |||
| 198 | /* Virtualization flags: Linux defined, word 8 */ |
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| 199 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
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| 200 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
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| 201 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
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| 202 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
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| 203 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
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| 204 | |||
| 205 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
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| 206 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ |
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| 207 | |||
| 208 | |||
| 209 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
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| 210 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
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| 211 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ |
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| 212 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ |
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| 213 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ |
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| 214 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ |
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| 215 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ |
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| 216 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ |
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| 217 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
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| 218 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ |
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| 219 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ |
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| 220 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ |
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| 221 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ |
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| 222 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
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| 223 | #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ |
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| 224 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ |
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| 225 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ |
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| 226 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ |
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| 227 | #define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ |
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| 228 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
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| 229 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ |
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| 230 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ |
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| 231 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ |
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| 232 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ |
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| 233 | #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ |
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| 234 | #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ |
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| 235 | #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ |
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| 236 | |||
| 237 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ |
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| 238 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ |
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| 239 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ |
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| 240 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ |
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| 241 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ |
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| 242 | |||
| 243 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ |
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| 244 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ |
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| 245 | |||
| 246 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ |
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| 247 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ |
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| 248 | #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ |
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| 249 | #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ |
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| 250 | |||
| 251 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ |
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| 252 | #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ |
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| 253 | |||
| 254 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ |
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| 255 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
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| 256 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ |
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| 257 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ |
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| 258 | #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ |
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| 259 | #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ |
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| 260 | #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ |
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| 261 | #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ |
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| 262 | #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ |
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| 263 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ |
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| 264 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ |
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| 265 | |||
| 266 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ |
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| 267 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ |
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| 268 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ |
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| 269 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ |
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| 270 | #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ |
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| 271 | #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ |
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| 272 | #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ |
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| 273 | #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ |
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| 274 | #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ |
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| 275 | #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ |
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| 276 | #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ |
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| 277 | #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ |
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| 278 | |||
| 279 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ |
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| 280 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ |
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| 281 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ |
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| 282 | |||
| 283 | /* |
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| 284 | * BUG word(s) |
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| 285 | */ |
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| 286 | #define X86_BUG(x) (NCAPINTS*32 + (x)) |
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| 287 | |||
| 288 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ |
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| 289 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ |
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| 290 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ |
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| 291 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ |
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| 292 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ |
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| 293 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ |
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| 294 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ |
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| 295 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ |
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| 296 | #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ |
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| 297 | |||
| 298 | #ifdef CONFIG_X86_32 |
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| 299 | /* |
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| 300 | * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional |
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| 301 | * to avoid confusion. |
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| 302 | */ |
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| 303 | #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ |
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| 304 | #endif |
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| 305 | |||
| 306 | #endif /* _ASM_X86_CPUFEATURES_H */ |