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| Rev | Author | Line No. | Line |
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| 5270 | serge | 1 | /* |
| 2 | * Defines x86 CPU feature bits |
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| 3 | */ |
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| 4 | #ifndef _ASM_X86_CPUFEATURE_H |
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| 5 | #define _ASM_X86_CPUFEATURE_H |
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| 6 | |||
| 7 | #ifndef _ASM_X86_REQUIRED_FEATURES_H |
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| 8 | #include |
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| 9 | #endif |
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| 10 | |||
| 11 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
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| 12 | #include |
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| 13 | #endif |
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| 14 | |||
| 6082 | serge | 15 | #define NCAPINTS 14 /* N 32-bit words worth of info */ |
| 5270 | serge | 16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
| 17 | |||
| 18 | /* |
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| 19 | * Note: If the comment begins with a quoted string, that string is used |
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| 20 | * in /proc/cpuinfo instead of the macro name. If the string is "", |
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| 21 | * this feature bit is not displayed in /proc/cpuinfo at all. |
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| 22 | */ |
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| 23 | |||
| 24 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ |
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| 25 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ |
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| 26 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ |
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| 27 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ |
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| 28 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ |
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| 29 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ |
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| 30 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ |
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| 31 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ |
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| 32 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ |
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| 33 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ |
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| 34 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ |
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| 35 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ |
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| 36 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ |
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| 37 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ |
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| 38 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ |
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| 39 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ |
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| 40 | /* (plus FCMOVcc, FCOMI with FPU) */ |
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| 41 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ |
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| 42 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ |
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| 43 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ |
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| 44 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ |
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| 45 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ |
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| 46 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ |
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| 47 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ |
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| 48 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
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| 49 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ |
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| 50 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ |
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| 51 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ |
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| 52 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ |
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| 53 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ |
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| 54 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ |
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| 55 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ |
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| 56 | |||
| 57 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
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| 58 | /* Don't duplicate feature flags which are redundant with Intel! */ |
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| 59 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
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| 60 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ |
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| 61 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ |
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| 62 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ |
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| 63 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
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| 64 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ |
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| 65 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ |
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| 66 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ |
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| 67 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ |
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| 68 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ |
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| 69 | |||
| 70 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
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| 71 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
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| 72 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ |
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| 73 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ |
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| 74 | |||
| 75 | /* Other features, Linux-defined mapping, word 3 */ |
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| 76 | /* This range is used for feature bits which conflict or are synthesized */ |
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| 77 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ |
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| 78 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
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| 79 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
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| 80 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
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| 81 | /* cpu types for specific tunings: */ |
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| 82 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
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| 83 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ |
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| 84 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ |
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| 85 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ |
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| 86 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ |
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| 87 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ |
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| 88 | /* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ |
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| 89 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
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| 90 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ |
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| 91 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ |
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| 92 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ |
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| 93 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ |
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| 94 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ |
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| 95 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ |
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| 96 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ |
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| 97 | /* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ |
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| 98 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
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| 99 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ |
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| 100 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ |
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| 101 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ |
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| 102 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ |
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| 103 | /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ |
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| 104 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ |
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| 105 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ |
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| 106 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ |
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| 107 | #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
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| 108 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
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| 109 | |||
| 110 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
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| 111 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ |
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| 112 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ |
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| 113 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ |
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| 114 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ |
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| 115 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
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| 116 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ |
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| 117 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ |
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| 118 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ |
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| 119 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ |
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| 120 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ |
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| 121 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ |
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| 6082 | serge | 122 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ |
| 5270 | serge | 123 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ |
| 124 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ |
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| 125 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ |
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| 126 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ |
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| 127 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ |
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| 128 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ |
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| 129 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ |
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| 130 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ |
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| 131 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ |
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| 132 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ |
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| 133 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ |
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| 134 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ |
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| 135 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ |
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| 136 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
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| 137 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ |
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| 138 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ |
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| 139 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ |
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| 140 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ |
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| 141 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ |
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| 142 | |||
| 143 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
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| 144 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ |
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| 145 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ |
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| 146 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
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| 147 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ |
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| 148 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ |
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| 149 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ |
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| 150 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ |
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| 151 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ |
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| 152 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ |
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| 153 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ |
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| 154 | |||
| 155 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ |
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| 156 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ |
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| 157 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ |
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| 158 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ |
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| 159 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ |
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| 160 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ |
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| 161 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ |
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| 162 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ |
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| 163 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ |
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| 164 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ |
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| 165 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ |
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| 166 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ |
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| 167 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ |
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| 168 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ |
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| 169 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ |
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| 170 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ |
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| 171 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ |
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| 172 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ |
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| 173 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ |
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| 174 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ |
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| 175 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ |
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| 176 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ |
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| 177 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ |
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| 6082 | serge | 178 | #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ |
| 5270 | serge | 179 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
| 6082 | serge | 180 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ |
| 5270 | serge | 181 | |
| 182 | /* |
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| 183 | * Auxiliary flags: Linux defined - For features scattered in various |
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| 184 | * CPUID levels like 0x6, 0xA etc, word 7 |
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| 185 | */ |
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| 186 | #define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ |
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| 187 | #define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ |
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| 188 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
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| 189 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
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| 190 | #define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ |
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| 191 | #define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ |
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| 192 | #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ |
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| 193 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
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| 194 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
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| 195 | #define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ |
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| 6082 | serge | 196 | #define X86_FEATURE_HWP_NOTIFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ |
| 5270 | serge | 197 | #define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ |
| 198 | #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ |
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| 199 | #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ |
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| 6082 | serge | 200 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
| 5270 | serge | 201 | |
| 202 | /* Virtualization flags: Linux defined, word 8 */ |
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| 203 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
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| 204 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
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| 205 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
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| 206 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
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| 207 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
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| 208 | #define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ |
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| 209 | #define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ |
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| 210 | #define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
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| 211 | #define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
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| 212 | #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
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| 213 | #define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
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| 214 | #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ |
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| 215 | #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ |
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| 216 | #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ |
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| 217 | #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ |
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| 218 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
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| 6082 | serge | 219 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ |
| 5270 | serge | 220 | |
| 221 | |||
| 222 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
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| 223 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
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| 224 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ |
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| 225 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ |
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| 226 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ |
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| 227 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ |
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| 228 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ |
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| 229 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ |
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| 230 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
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| 231 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ |
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| 232 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ |
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| 6082 | serge | 233 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ |
| 5270 | serge | 234 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ |
| 235 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
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| 236 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ |
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| 237 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ |
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| 238 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ |
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| 6082 | serge | 239 | #define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ |
| 5270 | serge | 240 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
| 6082 | serge | 241 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ |
| 5270 | serge | 242 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ |
| 243 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ |
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| 244 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ |
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| 6082 | serge | 245 | #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ |
| 5270 | serge | 246 | |
| 247 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ |
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| 248 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ |
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| 249 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ |
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| 250 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ |
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| 251 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ |
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| 252 | |||
| 6082 | serge | 253 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ |
| 254 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ |
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| 255 | |||
| 256 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ |
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| 257 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ |
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| 258 | |||
| 259 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ |
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| 260 | #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ |
||
| 261 | |||
| 5270 | serge | 262 | /* |
| 263 | * BUG word(s) |
||
| 264 | */ |
||
| 265 | #define X86_BUG(x) (NCAPINTS*32 + (x)) |
||
| 266 | |||
| 267 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ |
||
| 268 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ |
||
| 269 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ |
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| 270 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ |
||
| 271 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ |
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| 272 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ |
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| 273 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ |
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| 274 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ |
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| 6082 | serge | 275 | #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ |
| 5270 | serge | 276 | |
| 277 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
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| 278 | |||
| 279 | #include |
||
| 280 | #include |
||
| 281 | |||
| 282 | #ifdef CONFIG_X86_FEATURE_NAMES |
||
| 283 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
||
| 284 | extern const char * const x86_power_flags[32]; |
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| 285 | #define X86_CAP_FMT "%s" |
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| 286 | #define x86_cap_flag(flag) x86_cap_flags[flag] |
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| 287 | #else |
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| 288 | #define X86_CAP_FMT "%d:%d" |
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| 289 | #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31) |
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| 290 | #endif |
||
| 291 | |||
| 292 | /* |
||
| 293 | * In order to save room, we index into this array by doing |
||
| 294 | * X86_BUG_ |
||
| 295 | */ |
||
| 296 | extern const char * const x86_bug_flags[NBUGINTS*32]; |
||
| 297 | |||
| 298 | #define test_cpu_cap(c, bit) \ |
||
| 299 | test_bit(bit, (unsigned long *)((c)->x86_capability)) |
||
| 300 | |||
| 301 | #define REQUIRED_MASK_BIT_SET(bit) \ |
||
| 302 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
||
| 303 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
||
| 304 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
||
| 305 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ |
||
| 306 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ |
||
| 307 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ |
||
| 308 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ |
||
| 309 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ |
||
| 310 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ |
||
| 311 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) |
||
| 312 | |||
| 313 | #define DISABLED_MASK_BIT_SET(bit) \ |
||
| 314 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \ |
||
| 315 | (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \ |
||
| 316 | (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \ |
||
| 317 | (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \ |
||
| 318 | (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \ |
||
| 319 | (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \ |
||
| 320 | (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \ |
||
| 321 | (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \ |
||
| 322 | (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \ |
||
| 323 | (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) ) |
||
| 324 | |||
| 325 | #define cpu_has(c, bit) \ |
||
| 326 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
||
| 327 | test_cpu_cap(c, bit)) |
||
| 328 | |||
| 329 | #define this_cpu_has(bit) \ |
||
| 330 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
||
| 331 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) |
||
| 332 | |||
| 333 | /* |
||
| 334 | * This macro is for detection of features which need kernel |
||
| 335 | * infrastructure to be used. It may *not* directly test the CPU |
||
| 336 | * itself. Use the cpu_has() family if you want true runtime |
||
| 337 | * testing of CPU features, like in hypervisor code where you are |
||
| 338 | * supporting a possible guest feature where host support for it |
||
| 339 | * is not relevant. |
||
| 340 | */ |
||
| 341 | #define cpu_feature_enabled(bit) \ |
||
| 342 | (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \ |
||
| 343 | cpu_has(&boot_cpu_data, bit)) |
||
| 344 | |||
| 345 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
||
| 346 | |||
| 347 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
||
| 348 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) |
||
| 349 | #define setup_clear_cpu_cap(bit) do { \ |
||
| 350 | clear_cpu_cap(&boot_cpu_data, bit); \ |
||
| 351 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
||
| 352 | } while (0) |
||
| 353 | #define setup_force_cpu_cap(bit) do { \ |
||
| 354 | set_cpu_cap(&boot_cpu_data, bit); \ |
||
| 355 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
||
| 356 | } while (0) |
||
| 357 | |||
| 358 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
||
| 359 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
||
| 360 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
||
| 361 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
||
| 362 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
||
| 363 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
||
| 364 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
||
| 365 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
||
| 366 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
||
| 367 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
||
| 368 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
||
| 369 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
||
| 370 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
||
| 371 | #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
||
| 372 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
||
| 373 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
||
| 374 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
||
| 375 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
||
| 376 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
||
| 377 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
||
| 378 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) |
||
| 379 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) |
||
| 380 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) |
||
| 381 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
||
| 382 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) |
||
| 383 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) |
||
| 384 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) |
||
| 385 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) |
||
| 386 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) |
||
| 387 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
||
| 388 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
||
| 389 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
||
| 390 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
||
| 391 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
||
| 392 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
||
| 393 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
||
| 394 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
||
| 395 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
||
| 396 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
||
| 397 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
||
| 398 | #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
||
| 399 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
||
| 400 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
||
| 401 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
||
| 402 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
||
| 403 | #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
||
| 404 | #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) |
||
| 405 | #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) |
||
| 406 | #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
||
| 407 | #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) |
||
| 408 | #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
||
| 409 | #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) |
||
| 6082 | serge | 410 | #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) |
| 5270 | serge | 411 | |
| 412 | #if __GNUC__ >= 4 |
||
| 413 | extern void warn_pre_alternatives(void); |
||
| 414 | extern bool __static_cpu_has_safe(u16 bit); |
||
| 415 | |||
| 416 | /* |
||
| 417 | * Static testing of CPU features. Used the same as boot_cpu_has(). |
||
| 418 | * These are only valid after alternatives have run, but will statically |
||
| 419 | * patch the target code for additional performance. |
||
| 420 | */ |
||
| 421 | static __always_inline __pure bool __static_cpu_has(u16 bit) |
||
| 422 | { |
||
| 423 | #ifdef CC_HAVE_ASM_GOTO |
||
| 424 | |||
| 425 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS |
||
| 426 | |||
| 427 | /* |
||
| 428 | * Catch too early usage of this before alternatives |
||
| 429 | * have run. |
||
| 430 | */ |
||
| 431 | asm_volatile_goto("1: jmp %l[t_warn]\n" |
||
| 432 | "2:\n" |
||
| 433 | ".section .altinstructions,\"a\"\n" |
||
| 434 | " .long 1b - .\n" |
||
| 435 | " .long 0\n" /* no replacement */ |
||
| 436 | " .word %P0\n" /* 1: do replace */ |
||
| 437 | " .byte 2b - 1b\n" /* source len */ |
||
| 438 | " .byte 0\n" /* replacement len */ |
||
| 6082 | serge | 439 | " .byte 0\n" /* pad len */ |
| 5270 | serge | 440 | ".previous\n" |
| 441 | /* skipping size check since replacement size = 0 */ |
||
| 442 | : : "i" (X86_FEATURE_ALWAYS) : : t_warn); |
||
| 443 | |||
| 444 | #endif |
||
| 445 | |||
| 446 | asm_volatile_goto("1: jmp %l[t_no]\n" |
||
| 447 | "2:\n" |
||
| 448 | ".section .altinstructions,\"a\"\n" |
||
| 449 | " .long 1b - .\n" |
||
| 450 | " .long 0\n" /* no replacement */ |
||
| 451 | " .word %P0\n" /* feature bit */ |
||
| 452 | " .byte 2b - 1b\n" /* source len */ |
||
| 453 | " .byte 0\n" /* replacement len */ |
||
| 6082 | serge | 454 | " .byte 0\n" /* pad len */ |
| 5270 | serge | 455 | ".previous\n" |
| 456 | /* skipping size check since replacement size = 0 */ |
||
| 457 | : : "i" (bit) : : t_no); |
||
| 458 | return true; |
||
| 459 | t_no: |
||
| 460 | return false; |
||
| 461 | |||
| 462 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS |
||
| 463 | t_warn: |
||
| 464 | warn_pre_alternatives(); |
||
| 465 | return false; |
||
| 466 | #endif |
||
| 467 | |||
| 468 | #else /* CC_HAVE_ASM_GOTO */ |
||
| 469 | |||
| 470 | u8 flag; |
||
| 471 | /* Open-coded due to __stringify() in ALTERNATIVE() */ |
||
| 472 | asm volatile("1: movb $0,%0\n" |
||
| 473 | "2:\n" |
||
| 474 | ".section .altinstructions,\"a\"\n" |
||
| 475 | " .long 1b - .\n" |
||
| 476 | " .long 3f - .\n" |
||
| 477 | " .word %P1\n" /* feature bit */ |
||
| 478 | " .byte 2b - 1b\n" /* source len */ |
||
| 479 | " .byte 4f - 3f\n" /* replacement len */ |
||
| 6082 | serge | 480 | " .byte 0\n" /* pad len */ |
| 5270 | serge | 481 | ".previous\n" |
| 482 | ".section .discard,\"aw\",@progbits\n" |
||
| 483 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ |
||
| 484 | ".previous\n" |
||
| 485 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 486 | "3: movb $1,%0\n" |
||
| 487 | "4:\n" |
||
| 488 | ".previous\n" |
||
| 489 | : "=qm" (flag) : "i" (bit)); |
||
| 490 | return flag; |
||
| 491 | |||
| 492 | #endif /* CC_HAVE_ASM_GOTO */ |
||
| 493 | } |
||
| 494 | |||
| 495 | #define static_cpu_has(bit) \ |
||
| 496 | ( \ |
||
| 497 | __builtin_constant_p(boot_cpu_has(bit)) ? \ |
||
| 498 | boot_cpu_has(bit) : \ |
||
| 499 | __builtin_constant_p(bit) ? \ |
||
| 500 | __static_cpu_has(bit) : \ |
||
| 501 | boot_cpu_has(bit) \ |
||
| 502 | ) |
||
| 503 | |||
| 504 | static __always_inline __pure bool _static_cpu_has_safe(u16 bit) |
||
| 505 | { |
||
| 506 | #ifdef CC_HAVE_ASM_GOTO |
||
| 6082 | serge | 507 | asm_volatile_goto("1: jmp %l[t_dynamic]\n" |
| 5270 | serge | 508 | "2:\n" |
| 6082 | serge | 509 | ".skip -(((5f-4f) - (2b-1b)) > 0) * " |
| 510 | "((5f-4f) - (2b-1b)),0x90\n" |
||
| 511 | "3:\n" |
||
| 5270 | serge | 512 | ".section .altinstructions,\"a\"\n" |
| 513 | " .long 1b - .\n" /* src offset */ |
||
| 6082 | serge | 514 | " .long 4f - .\n" /* repl offset */ |
| 5270 | serge | 515 | " .word %P1\n" /* always replace */ |
| 6082 | serge | 516 | " .byte 3b - 1b\n" /* src len */ |
| 517 | " .byte 5f - 4f\n" /* repl len */ |
||
| 518 | " .byte 3b - 2b\n" /* pad len */ |
||
| 5270 | serge | 519 | ".previous\n" |
| 520 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 6082 | serge | 521 | "4: jmp %l[t_no]\n" |
| 522 | "5:\n" |
||
| 5270 | serge | 523 | ".previous\n" |
| 524 | ".section .altinstructions,\"a\"\n" |
||
| 525 | " .long 1b - .\n" /* src offset */ |
||
| 526 | " .long 0\n" /* no replacement */ |
||
| 527 | " .word %P0\n" /* feature bit */ |
||
| 6082 | serge | 528 | " .byte 3b - 1b\n" /* src len */ |
| 5270 | serge | 529 | " .byte 0\n" /* repl len */ |
| 6082 | serge | 530 | " .byte 0\n" /* pad len */ |
| 5270 | serge | 531 | ".previous\n" |
| 532 | : : "i" (bit), "i" (X86_FEATURE_ALWAYS) |
||
| 533 | : : t_dynamic, t_no); |
||
| 534 | return true; |
||
| 535 | t_no: |
||
| 536 | return false; |
||
| 537 | t_dynamic: |
||
| 538 | return __static_cpu_has_safe(bit); |
||
| 539 | #else |
||
| 540 | u8 flag; |
||
| 541 | /* Open-coded due to __stringify() in ALTERNATIVE() */ |
||
| 542 | asm volatile("1: movb $2,%0\n" |
||
| 543 | "2:\n" |
||
| 544 | ".section .altinstructions,\"a\"\n" |
||
| 545 | " .long 1b - .\n" /* src offset */ |
||
| 546 | " .long 3f - .\n" /* repl offset */ |
||
| 547 | " .word %P2\n" /* always replace */ |
||
| 548 | " .byte 2b - 1b\n" /* source len */ |
||
| 549 | " .byte 4f - 3f\n" /* replacement len */ |
||
| 6082 | serge | 550 | " .byte 0\n" /* pad len */ |
| 5270 | serge | 551 | ".previous\n" |
| 552 | ".section .discard,\"aw\",@progbits\n" |
||
| 553 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ |
||
| 554 | ".previous\n" |
||
| 555 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 556 | "3: movb $0,%0\n" |
||
| 557 | "4:\n" |
||
| 558 | ".previous\n" |
||
| 559 | ".section .altinstructions,\"a\"\n" |
||
| 560 | " .long 1b - .\n" /* src offset */ |
||
| 561 | " .long 5f - .\n" /* repl offset */ |
||
| 562 | " .word %P1\n" /* feature bit */ |
||
| 563 | " .byte 4b - 3b\n" /* src len */ |
||
| 564 | " .byte 6f - 5f\n" /* repl len */ |
||
| 6082 | serge | 565 | " .byte 0\n" /* pad len */ |
| 5270 | serge | 566 | ".previous\n" |
| 567 | ".section .discard,\"aw\",@progbits\n" |
||
| 568 | " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ |
||
| 569 | ".previous\n" |
||
| 570 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 571 | "5: movb $1,%0\n" |
||
| 572 | "6:\n" |
||
| 573 | ".previous\n" |
||
| 574 | : "=qm" (flag) |
||
| 575 | : "i" (bit), "i" (X86_FEATURE_ALWAYS)); |
||
| 576 | return (flag == 2 ? __static_cpu_has_safe(bit) : flag); |
||
| 577 | #endif /* CC_HAVE_ASM_GOTO */ |
||
| 578 | } |
||
| 579 | |||
| 580 | #define static_cpu_has_safe(bit) \ |
||
| 581 | ( \ |
||
| 582 | __builtin_constant_p(boot_cpu_has(bit)) ? \ |
||
| 583 | boot_cpu_has(bit) : \ |
||
| 584 | _static_cpu_has_safe(bit) \ |
||
| 585 | ) |
||
| 586 | #else |
||
| 587 | /* |
||
| 588 | * gcc 3.x is too stupid to do the static test; fall back to dynamic. |
||
| 589 | */ |
||
| 590 | #define static_cpu_has(bit) boot_cpu_has(bit) |
||
| 591 | #define static_cpu_has_safe(bit) boot_cpu_has(bit) |
||
| 592 | #endif |
||
| 593 | |||
| 594 | #define cpu_has_bug(c, bit) cpu_has(c, (bit)) |
||
| 595 | #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) |
||
| 596 | #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) |
||
| 597 | |||
| 598 | #define static_cpu_has_bug(bit) static_cpu_has((bit)) |
||
| 599 | #define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit)) |
||
| 600 | #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) |
||
| 601 | |||
| 602 | #define MAX_CPU_FEATURES (NCAPINTS * 32) |
||
| 603 | #define cpu_have_feature boot_cpu_has |
||
| 604 | |||
| 605 | #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" |
||
| 606 | #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ |
||
| 607 | boot_cpu_data.x86_model |
||
| 608 | |||
| 609 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
||
| 610 | #endif /* _ASM_X86_CPUFEATURE_H */ |