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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5270 | serge | 1 | /* |
| 2 | * Defines x86 CPU feature bits |
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| 3 | */ |
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| 4 | #ifndef _ASM_X86_CPUFEATURE_H |
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| 5 | #define _ASM_X86_CPUFEATURE_H |
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| 6 | |||
| 7 | #ifndef _ASM_X86_REQUIRED_FEATURES_H |
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| 8 | #include |
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| 9 | #endif |
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| 10 | |||
| 11 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
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| 12 | #include |
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| 13 | #endif |
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| 14 | |||
| 15 | #define NCAPINTS 11 /* N 32-bit words worth of info */ |
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| 16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
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| 17 | |||
| 18 | /* |
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| 19 | * Note: If the comment begins with a quoted string, that string is used |
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| 20 | * in /proc/cpuinfo instead of the macro name. If the string is "", |
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| 21 | * this feature bit is not displayed in /proc/cpuinfo at all. |
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| 22 | */ |
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| 23 | |||
| 24 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ |
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| 25 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ |
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| 26 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ |
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| 27 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ |
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| 28 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ |
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| 29 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ |
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| 30 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ |
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| 31 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ |
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| 32 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ |
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| 33 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ |
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| 34 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ |
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| 35 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ |
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| 36 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ |
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| 37 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ |
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| 38 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ |
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| 39 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ |
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| 40 | /* (plus FCMOVcc, FCOMI with FPU) */ |
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| 41 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ |
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| 42 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ |
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| 43 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ |
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| 44 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ |
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| 45 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ |
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| 46 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ |
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| 47 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ |
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| 48 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
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| 49 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ |
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| 50 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ |
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| 51 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ |
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| 52 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ |
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| 53 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ |
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| 54 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ |
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| 55 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ |
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| 56 | |||
| 57 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
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| 58 | /* Don't duplicate feature flags which are redundant with Intel! */ |
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| 59 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
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| 60 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ |
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| 61 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ |
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| 62 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ |
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| 63 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
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| 64 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ |
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| 65 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ |
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| 66 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ |
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| 67 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ |
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| 68 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ |
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| 69 | |||
| 70 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
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| 71 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
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| 72 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ |
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| 73 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ |
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| 74 | |||
| 75 | /* Other features, Linux-defined mapping, word 3 */ |
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| 76 | /* This range is used for feature bits which conflict or are synthesized */ |
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| 77 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ |
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| 78 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
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| 79 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
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| 80 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
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| 81 | /* cpu types for specific tunings: */ |
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| 82 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
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| 83 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ |
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| 84 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ |
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| 85 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ |
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| 86 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ |
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| 87 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ |
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| 88 | /* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ |
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| 89 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
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| 90 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ |
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| 91 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ |
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| 92 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ |
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| 93 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ |
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| 94 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ |
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| 95 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ |
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| 96 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ |
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| 97 | /* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ |
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| 98 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
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| 99 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ |
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| 100 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ |
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| 101 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ |
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| 102 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ |
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| 103 | /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ |
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| 104 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ |
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| 105 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ |
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| 106 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ |
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| 107 | #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
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| 108 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
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| 109 | |||
| 110 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
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| 111 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ |
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| 112 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ |
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| 113 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ |
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| 114 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ |
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| 115 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
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| 116 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ |
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| 117 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ |
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| 118 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ |
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| 119 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ |
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| 120 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ |
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| 121 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ |
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| 122 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ |
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| 123 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ |
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| 124 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ |
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| 125 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ |
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| 126 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ |
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| 127 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ |
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| 128 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ |
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| 129 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ |
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| 130 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ |
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| 131 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ |
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| 132 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ |
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| 133 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ |
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| 134 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ |
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| 135 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
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| 136 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ |
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| 137 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ |
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| 138 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ |
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| 139 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ |
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| 140 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ |
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| 141 | |||
| 142 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
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| 143 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ |
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| 144 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ |
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| 145 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
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| 146 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ |
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| 147 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ |
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| 148 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ |
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| 149 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ |
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| 150 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ |
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| 151 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ |
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| 152 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ |
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| 153 | |||
| 154 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ |
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| 155 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ |
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| 156 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ |
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| 157 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ |
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| 158 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ |
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| 159 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ |
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| 160 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ |
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| 161 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ |
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| 162 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ |
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| 163 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ |
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| 164 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ |
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| 165 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ |
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| 166 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ |
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| 167 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ |
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| 168 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ |
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| 169 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ |
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| 170 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ |
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| 171 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ |
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| 172 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ |
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| 173 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ |
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| 174 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ |
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| 175 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ |
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| 176 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ |
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| 177 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
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| 178 | |||
| 179 | /* |
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| 180 | * Auxiliary flags: Linux defined - For features scattered in various |
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| 181 | * CPUID levels like 0x6, 0xA etc, word 7 |
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| 182 | */ |
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| 183 | #define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ |
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| 184 | #define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ |
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| 185 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
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| 186 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
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| 187 | #define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ |
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| 188 | #define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ |
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| 189 | #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ |
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| 190 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
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| 191 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
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| 192 | #define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ |
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| 193 | #define X86_FEATURE_HWP_NOITFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ |
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| 194 | #define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ |
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| 195 | #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ |
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| 196 | #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ |
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| 197 | |||
| 198 | /* Virtualization flags: Linux defined, word 8 */ |
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| 199 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
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| 200 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
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| 201 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
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| 202 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
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| 203 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
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| 204 | #define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ |
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| 205 | #define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ |
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| 206 | #define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
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| 207 | #define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
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| 208 | #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
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| 209 | #define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
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| 210 | #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ |
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| 211 | #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ |
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| 212 | #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ |
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| 213 | #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ |
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| 214 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
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| 215 | |||
| 216 | |||
| 217 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
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| 218 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
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| 219 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ |
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| 220 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ |
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| 221 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ |
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| 222 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ |
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| 223 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ |
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| 224 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ |
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| 225 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
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| 226 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ |
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| 227 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ |
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| 228 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ |
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| 229 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
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| 230 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ |
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| 231 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ |
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| 232 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ |
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| 233 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
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| 234 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ |
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| 235 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ |
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| 236 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ |
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| 237 | |||
| 238 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ |
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| 239 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ |
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| 240 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ |
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| 241 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ |
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| 242 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ |
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| 243 | |||
| 244 | /* |
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| 245 | * BUG word(s) |
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| 246 | */ |
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| 247 | #define X86_BUG(x) (NCAPINTS*32 + (x)) |
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| 248 | |||
| 249 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ |
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| 250 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ |
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| 251 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ |
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| 252 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ |
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| 253 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ |
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| 254 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ |
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| 255 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ |
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| 256 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ |
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| 257 | |||
| 258 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
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| 259 | |||
| 260 | #include |
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| 261 | #include |
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| 262 | |||
| 263 | #ifdef CONFIG_X86_FEATURE_NAMES |
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| 264 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
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| 265 | extern const char * const x86_power_flags[32]; |
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| 266 | #define X86_CAP_FMT "%s" |
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| 267 | #define x86_cap_flag(flag) x86_cap_flags[flag] |
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| 268 | #else |
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| 269 | #define X86_CAP_FMT "%d:%d" |
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| 270 | #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31) |
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| 271 | #endif |
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| 272 | |||
| 273 | /* |
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| 274 | * In order to save room, we index into this array by doing |
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| 275 | * X86_BUG_ |
||
| 276 | */ |
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| 277 | extern const char * const x86_bug_flags[NBUGINTS*32]; |
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| 278 | |||
| 279 | #define test_cpu_cap(c, bit) \ |
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| 280 | test_bit(bit, (unsigned long *)((c)->x86_capability)) |
||
| 281 | |||
| 282 | #define REQUIRED_MASK_BIT_SET(bit) \ |
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| 283 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
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| 284 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
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| 285 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
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| 286 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ |
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| 287 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ |
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| 288 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ |
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| 289 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ |
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| 290 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ |
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| 291 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ |
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| 292 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) |
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| 293 | |||
| 294 | #define DISABLED_MASK_BIT_SET(bit) \ |
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| 295 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \ |
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| 296 | (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \ |
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| 297 | (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \ |
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| 298 | (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \ |
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| 299 | (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \ |
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| 300 | (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \ |
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| 301 | (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \ |
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| 302 | (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \ |
||
| 303 | (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \ |
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| 304 | (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) ) |
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| 305 | |||
| 306 | #define cpu_has(c, bit) \ |
||
| 307 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
||
| 308 | test_cpu_cap(c, bit)) |
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| 309 | |||
| 310 | #define this_cpu_has(bit) \ |
||
| 311 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
||
| 312 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) |
||
| 313 | |||
| 314 | /* |
||
| 315 | * This macro is for detection of features which need kernel |
||
| 316 | * infrastructure to be used. It may *not* directly test the CPU |
||
| 317 | * itself. Use the cpu_has() family if you want true runtime |
||
| 318 | * testing of CPU features, like in hypervisor code where you are |
||
| 319 | * supporting a possible guest feature where host support for it |
||
| 320 | * is not relevant. |
||
| 321 | */ |
||
| 322 | #define cpu_feature_enabled(bit) \ |
||
| 323 | (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \ |
||
| 324 | cpu_has(&boot_cpu_data, bit)) |
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| 325 | |||
| 326 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
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| 327 | |||
| 328 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
||
| 329 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) |
||
| 330 | #define setup_clear_cpu_cap(bit) do { \ |
||
| 331 | clear_cpu_cap(&boot_cpu_data, bit); \ |
||
| 332 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
||
| 333 | } while (0) |
||
| 334 | #define setup_force_cpu_cap(bit) do { \ |
||
| 335 | set_cpu_cap(&boot_cpu_data, bit); \ |
||
| 336 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
||
| 337 | } while (0) |
||
| 338 | |||
| 339 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
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| 340 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
||
| 341 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
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| 342 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
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| 343 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
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| 344 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
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| 345 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
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| 346 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
||
| 347 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
||
| 348 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
||
| 349 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
||
| 350 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
||
| 351 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
||
| 352 | #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
||
| 353 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
||
| 354 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
||
| 355 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
||
| 356 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
||
| 357 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
||
| 358 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
||
| 359 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) |
||
| 360 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) |
||
| 361 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) |
||
| 362 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
||
| 363 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) |
||
| 364 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) |
||
| 365 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) |
||
| 366 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) |
||
| 367 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) |
||
| 368 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
||
| 369 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
||
| 370 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
||
| 371 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
||
| 372 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
||
| 373 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
||
| 374 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
||
| 375 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
||
| 376 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
||
| 377 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
||
| 378 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
||
| 379 | #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
||
| 380 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
||
| 381 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
||
| 382 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
||
| 383 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
||
| 384 | #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
||
| 385 | #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) |
||
| 386 | #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) |
||
| 387 | #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
||
| 388 | #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) |
||
| 389 | #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
||
| 390 | #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) |
||
| 391 | |||
| 392 | #if __GNUC__ >= 4 |
||
| 393 | extern void warn_pre_alternatives(void); |
||
| 394 | extern bool __static_cpu_has_safe(u16 bit); |
||
| 395 | |||
| 396 | /* |
||
| 397 | * Static testing of CPU features. Used the same as boot_cpu_has(). |
||
| 398 | * These are only valid after alternatives have run, but will statically |
||
| 399 | * patch the target code for additional performance. |
||
| 400 | */ |
||
| 401 | static __always_inline __pure bool __static_cpu_has(u16 bit) |
||
| 402 | { |
||
| 403 | #ifdef CC_HAVE_ASM_GOTO |
||
| 404 | |||
| 405 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS |
||
| 406 | |||
| 407 | /* |
||
| 408 | * Catch too early usage of this before alternatives |
||
| 409 | * have run. |
||
| 410 | */ |
||
| 411 | asm_volatile_goto("1: jmp %l[t_warn]\n" |
||
| 412 | "2:\n" |
||
| 413 | ".section .altinstructions,\"a\"\n" |
||
| 414 | " .long 1b - .\n" |
||
| 415 | " .long 0\n" /* no replacement */ |
||
| 416 | " .word %P0\n" /* 1: do replace */ |
||
| 417 | " .byte 2b - 1b\n" /* source len */ |
||
| 418 | " .byte 0\n" /* replacement len */ |
||
| 419 | ".previous\n" |
||
| 420 | /* skipping size check since replacement size = 0 */ |
||
| 421 | : : "i" (X86_FEATURE_ALWAYS) : : t_warn); |
||
| 422 | |||
| 423 | #endif |
||
| 424 | |||
| 425 | asm_volatile_goto("1: jmp %l[t_no]\n" |
||
| 426 | "2:\n" |
||
| 427 | ".section .altinstructions,\"a\"\n" |
||
| 428 | " .long 1b - .\n" |
||
| 429 | " .long 0\n" /* no replacement */ |
||
| 430 | " .word %P0\n" /* feature bit */ |
||
| 431 | " .byte 2b - 1b\n" /* source len */ |
||
| 432 | " .byte 0\n" /* replacement len */ |
||
| 433 | ".previous\n" |
||
| 434 | /* skipping size check since replacement size = 0 */ |
||
| 435 | : : "i" (bit) : : t_no); |
||
| 436 | return true; |
||
| 437 | t_no: |
||
| 438 | return false; |
||
| 439 | |||
| 440 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS |
||
| 441 | t_warn: |
||
| 442 | warn_pre_alternatives(); |
||
| 443 | return false; |
||
| 444 | #endif |
||
| 445 | |||
| 446 | #else /* CC_HAVE_ASM_GOTO */ |
||
| 447 | |||
| 448 | u8 flag; |
||
| 449 | /* Open-coded due to __stringify() in ALTERNATIVE() */ |
||
| 450 | asm volatile("1: movb $0,%0\n" |
||
| 451 | "2:\n" |
||
| 452 | ".section .altinstructions,\"a\"\n" |
||
| 453 | " .long 1b - .\n" |
||
| 454 | " .long 3f - .\n" |
||
| 455 | " .word %P1\n" /* feature bit */ |
||
| 456 | " .byte 2b - 1b\n" /* source len */ |
||
| 457 | " .byte 4f - 3f\n" /* replacement len */ |
||
| 458 | ".previous\n" |
||
| 459 | ".section .discard,\"aw\",@progbits\n" |
||
| 460 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ |
||
| 461 | ".previous\n" |
||
| 462 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 463 | "3: movb $1,%0\n" |
||
| 464 | "4:\n" |
||
| 465 | ".previous\n" |
||
| 466 | : "=qm" (flag) : "i" (bit)); |
||
| 467 | return flag; |
||
| 468 | |||
| 469 | #endif /* CC_HAVE_ASM_GOTO */ |
||
| 470 | } |
||
| 471 | |||
| 472 | #define static_cpu_has(bit) \ |
||
| 473 | ( \ |
||
| 474 | __builtin_constant_p(boot_cpu_has(bit)) ? \ |
||
| 475 | boot_cpu_has(bit) : \ |
||
| 476 | __builtin_constant_p(bit) ? \ |
||
| 477 | __static_cpu_has(bit) : \ |
||
| 478 | boot_cpu_has(bit) \ |
||
| 479 | ) |
||
| 480 | |||
| 481 | static __always_inline __pure bool _static_cpu_has_safe(u16 bit) |
||
| 482 | { |
||
| 483 | #ifdef CC_HAVE_ASM_GOTO |
||
| 484 | /* |
||
| 485 | * We need to spell the jumps to the compiler because, depending on the offset, |
||
| 486 | * the replacement jump can be bigger than the original jump, and this we cannot |
||
| 487 | * have. Thus, we force the jump to the widest, 4-byte, signed relative |
||
| 488 | * offset even though the last would often fit in less bytes. |
||
| 489 | */ |
||
| 490 | asm_volatile_goto("1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n" |
||
| 491 | "2:\n" |
||
| 492 | ".section .altinstructions,\"a\"\n" |
||
| 493 | " .long 1b - .\n" /* src offset */ |
||
| 494 | " .long 3f - .\n" /* repl offset */ |
||
| 495 | " .word %P1\n" /* always replace */ |
||
| 496 | " .byte 2b - 1b\n" /* src len */ |
||
| 497 | " .byte 4f - 3f\n" /* repl len */ |
||
| 498 | ".previous\n" |
||
| 499 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 500 | "3: .byte 0xe9\n .long %l[t_no] - 2b\n" |
||
| 501 | "4:\n" |
||
| 502 | ".previous\n" |
||
| 503 | ".section .altinstructions,\"a\"\n" |
||
| 504 | " .long 1b - .\n" /* src offset */ |
||
| 505 | " .long 0\n" /* no replacement */ |
||
| 506 | " .word %P0\n" /* feature bit */ |
||
| 507 | " .byte 2b - 1b\n" /* src len */ |
||
| 508 | " .byte 0\n" /* repl len */ |
||
| 509 | ".previous\n" |
||
| 510 | : : "i" (bit), "i" (X86_FEATURE_ALWAYS) |
||
| 511 | : : t_dynamic, t_no); |
||
| 512 | return true; |
||
| 513 | t_no: |
||
| 514 | return false; |
||
| 515 | t_dynamic: |
||
| 516 | return __static_cpu_has_safe(bit); |
||
| 517 | #else |
||
| 518 | u8 flag; |
||
| 519 | /* Open-coded due to __stringify() in ALTERNATIVE() */ |
||
| 520 | asm volatile("1: movb $2,%0\n" |
||
| 521 | "2:\n" |
||
| 522 | ".section .altinstructions,\"a\"\n" |
||
| 523 | " .long 1b - .\n" /* src offset */ |
||
| 524 | " .long 3f - .\n" /* repl offset */ |
||
| 525 | " .word %P2\n" /* always replace */ |
||
| 526 | " .byte 2b - 1b\n" /* source len */ |
||
| 527 | " .byte 4f - 3f\n" /* replacement len */ |
||
| 528 | ".previous\n" |
||
| 529 | ".section .discard,\"aw\",@progbits\n" |
||
| 530 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ |
||
| 531 | ".previous\n" |
||
| 532 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 533 | "3: movb $0,%0\n" |
||
| 534 | "4:\n" |
||
| 535 | ".previous\n" |
||
| 536 | ".section .altinstructions,\"a\"\n" |
||
| 537 | " .long 1b - .\n" /* src offset */ |
||
| 538 | " .long 5f - .\n" /* repl offset */ |
||
| 539 | " .word %P1\n" /* feature bit */ |
||
| 540 | " .byte 4b - 3b\n" /* src len */ |
||
| 541 | " .byte 6f - 5f\n" /* repl len */ |
||
| 542 | ".previous\n" |
||
| 543 | ".section .discard,\"aw\",@progbits\n" |
||
| 544 | " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ |
||
| 545 | ".previous\n" |
||
| 546 | ".section .altinstr_replacement,\"ax\"\n" |
||
| 547 | "5: movb $1,%0\n" |
||
| 548 | "6:\n" |
||
| 549 | ".previous\n" |
||
| 550 | : "=qm" (flag) |
||
| 551 | : "i" (bit), "i" (X86_FEATURE_ALWAYS)); |
||
| 552 | return (flag == 2 ? __static_cpu_has_safe(bit) : flag); |
||
| 553 | #endif /* CC_HAVE_ASM_GOTO */ |
||
| 554 | } |
||
| 555 | |||
| 556 | #define static_cpu_has_safe(bit) \ |
||
| 557 | ( \ |
||
| 558 | __builtin_constant_p(boot_cpu_has(bit)) ? \ |
||
| 559 | boot_cpu_has(bit) : \ |
||
| 560 | _static_cpu_has_safe(bit) \ |
||
| 561 | ) |
||
| 562 | #else |
||
| 563 | /* |
||
| 564 | * gcc 3.x is too stupid to do the static test; fall back to dynamic. |
||
| 565 | */ |
||
| 566 | #define static_cpu_has(bit) boot_cpu_has(bit) |
||
| 567 | #define static_cpu_has_safe(bit) boot_cpu_has(bit) |
||
| 568 | #endif |
||
| 569 | |||
| 570 | #define cpu_has_bug(c, bit) cpu_has(c, (bit)) |
||
| 571 | #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) |
||
| 572 | #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) |
||
| 573 | |||
| 574 | #define static_cpu_has_bug(bit) static_cpu_has((bit)) |
||
| 575 | #define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit)) |
||
| 576 | #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) |
||
| 577 | |||
| 578 | #define MAX_CPU_FEATURES (NCAPINTS * 32) |
||
| 579 | #define cpu_have_feature boot_cpu_has |
||
| 580 | |||
| 581 | #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" |
||
| 582 | #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ |
||
| 583 | boot_cpu_data.x86_model |
||
| 584 | |||
| 585 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
||
| 586 | #endif /* _ASM_X86_CPUFEATURE_H */ |