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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5270 | serge | 1 | #ifndef _ASM_X86_BARRIER_H |
| 2 | #define _ASM_X86_BARRIER_H |
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| 3 | |||
| 4 | #include |
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| 5 | #include |
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| 6 | |||
| 7 | /* |
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| 8 | * Force strict CPU ordering. |
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| 7143 | serge | 9 | * And yes, this might be required on UP too when we're talking |
| 5270 | serge | 10 | * to devices. |
| 11 | */ |
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| 12 | |||
| 13 | #ifdef CONFIG_X86_32 |
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| 14 | /* |
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| 15 | * Some non-Intel clones support out of order store. wmb() ceases to be a |
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| 16 | * nop for these. |
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| 17 | */ |
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| 18 | #define mb() asm volatile ("lock; addl $0,0(%esp)")/*, "mfence", X86_FEATURE_XMM2) */ |
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| 19 | #define rmb() asm volatile("lock; addl $0,0(%esp)")/*, "lfence", X86_FEATURE_XMM2) */ |
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| 20 | #define wmb() asm volatile("lock; addl $0,0(%esp)")/*, "sfence", X86_FEATURE_XMM) */ |
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| 21 | #else |
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| 22 | #define mb() asm volatile("mfence":::"memory") |
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| 23 | #define rmb() asm volatile("lfence":::"memory") |
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| 24 | #define wmb() asm volatile("sfence" ::: "memory") |
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| 25 | #endif |
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| 26 | |||
| 27 | #ifdef CONFIG_X86_PPRO_FENCE |
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| 28 | #define dma_rmb() rmb() |
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| 29 | #else |
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| 30 | #define dma_rmb() barrier() |
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| 31 | #endif |
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| 32 | #define dma_wmb() barrier() |
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| 33 | |||
| 7143 | serge | 34 | #define __smp_mb() mb() |
| 35 | #define __smp_rmb() dma_rmb() |
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| 36 | #define __smp_wmb() barrier() |
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| 37 | #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) |
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| 5270 | serge | 38 | |
| 39 | #if defined(CONFIG_X86_PPRO_FENCE) |
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| 40 | |||
| 41 | /* |
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| 42 | * For this option x86 doesn't have a strong TSO memory |
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| 43 | * model and we should fall back to full barriers. |
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| 44 | */ |
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| 45 | |||
| 6936 | serge | 46 | #define __smp_store_release(p, v) \ |
| 5270 | serge | 47 | do { \ |
| 48 | compiletime_assert_atomic_type(*p); \ |
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| 6936 | serge | 49 | __smp_mb(); \ |
| 6082 | serge | 50 | WRITE_ONCE(*p, v); \ |
| 5270 | serge | 51 | } while (0) |
| 52 | |||
| 6936 | serge | 53 | #define __smp_load_acquire(p) \ |
| 5270 | serge | 54 | ({ \ |
| 6082 | serge | 55 | typeof(*p) ___p1 = READ_ONCE(*p); \ |
| 5270 | serge | 56 | compiletime_assert_atomic_type(*p); \ |
| 6936 | serge | 57 | __smp_mb(); \ |
| 5270 | serge | 58 | ___p1; \ |
| 59 | }) |
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| 60 | |||
| 61 | #else /* regular x86 TSO memory ordering */ |
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| 62 | |||
| 6936 | serge | 63 | #define __smp_store_release(p, v) \ |
| 5270 | serge | 64 | do { \ |
| 65 | compiletime_assert_atomic_type(*p); \ |
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| 66 | barrier(); \ |
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| 6082 | serge | 67 | WRITE_ONCE(*p, v); \ |
| 5270 | serge | 68 | } while (0) |
| 69 | |||
| 6936 | serge | 70 | #define __smp_load_acquire(p) \ |
| 5270 | serge | 71 | ({ \ |
| 6082 | serge | 72 | typeof(*p) ___p1 = READ_ONCE(*p); \ |
| 5270 | serge | 73 | compiletime_assert_atomic_type(*p); \ |
| 74 | barrier(); \ |
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| 75 | ___p1; \ |
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| 76 | }) |
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| 77 | |||
| 78 | #endif |
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| 79 | |||
| 80 | /* Atomic operations are already serializing on x86 */ |
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| 6936 | serge | 81 | #define __smp_mb__before_atomic() barrier() |
| 82 | #define __smp_mb__after_atomic() barrier() |
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| 5270 | serge | 83 | |
| 6936 | serge | 84 | #include |
| 85 | |||
| 5270 | serge | 86 | #endif /* _ASM_X86_BARRIER_H */ |