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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5270 | serge | 1 | #ifndef _ASM_X86_BARRIER_H |
| 2 | #define _ASM_X86_BARRIER_H |
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| 3 | |||
| 4 | #include |
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| 5 | #include |
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| 6 | |||
| 7 | /* |
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| 8 | * Force strict CPU ordering. |
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| 9 | * And yes, this is required on UP too when we're talking |
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| 10 | * to devices. |
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| 11 | */ |
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| 12 | |||
| 13 | #ifdef CONFIG_X86_32 |
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| 14 | /* |
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| 15 | * Some non-Intel clones support out of order store. wmb() ceases to be a |
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| 16 | * nop for these. |
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| 17 | */ |
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| 18 | #define mb() asm volatile ("lock; addl $0,0(%esp)")/*, "mfence", X86_FEATURE_XMM2) */ |
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| 19 | #define rmb() asm volatile("lock; addl $0,0(%esp)")/*, "lfence", X86_FEATURE_XMM2) */ |
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| 20 | #define wmb() asm volatile("lock; addl $0,0(%esp)")/*, "sfence", X86_FEATURE_XMM) */ |
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| 21 | #else |
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| 22 | #define mb() asm volatile("mfence":::"memory") |
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| 23 | #define rmb() asm volatile("lfence":::"memory") |
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| 24 | #define wmb() asm volatile("sfence" ::: "memory") |
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| 25 | #endif |
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| 26 | |||
| 27 | #ifdef CONFIG_X86_PPRO_FENCE |
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| 28 | #define dma_rmb() rmb() |
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| 29 | #else |
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| 30 | #define dma_rmb() barrier() |
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| 31 | #endif |
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| 32 | #define dma_wmb() barrier() |
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| 33 | |||
| 34 | #ifdef CONFIG_SMP |
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| 35 | #define smp_mb() mb() |
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| 36 | #define smp_rmb() dma_rmb() |
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| 37 | #define smp_wmb() barrier() |
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| 6082 | serge | 38 | #define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) |
| 5270 | serge | 39 | #else /* !SMP */ |
| 40 | #define smp_mb() barrier() |
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| 41 | #define smp_rmb() barrier() |
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| 42 | #define smp_wmb() barrier() |
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| 6082 | serge | 43 | #define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0) |
| 5270 | serge | 44 | #endif /* SMP */ |
| 45 | |||
| 46 | #define read_barrier_depends() do { } while (0) |
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| 47 | #define smp_read_barrier_depends() do { } while (0) |
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| 48 | |||
| 49 | #if defined(CONFIG_X86_PPRO_FENCE) |
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| 50 | |||
| 51 | /* |
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| 52 | * For this option x86 doesn't have a strong TSO memory |
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| 53 | * model and we should fall back to full barriers. |
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| 54 | */ |
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| 55 | |||
| 6936 | serge | 56 | #define __smp_store_release(p, v) \ |
| 5270 | serge | 57 | do { \ |
| 58 | compiletime_assert_atomic_type(*p); \ |
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| 6936 | serge | 59 | __smp_mb(); \ |
| 6082 | serge | 60 | WRITE_ONCE(*p, v); \ |
| 5270 | serge | 61 | } while (0) |
| 62 | |||
| 6936 | serge | 63 | #define __smp_load_acquire(p) \ |
| 5270 | serge | 64 | ({ \ |
| 6082 | serge | 65 | typeof(*p) ___p1 = READ_ONCE(*p); \ |
| 5270 | serge | 66 | compiletime_assert_atomic_type(*p); \ |
| 6936 | serge | 67 | __smp_mb(); \ |
| 5270 | serge | 68 | ___p1; \ |
| 69 | }) |
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| 70 | |||
| 71 | #else /* regular x86 TSO memory ordering */ |
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| 72 | |||
| 6936 | serge | 73 | #define __smp_store_release(p, v) \ |
| 5270 | serge | 74 | do { \ |
| 75 | compiletime_assert_atomic_type(*p); \ |
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| 76 | barrier(); \ |
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| 6082 | serge | 77 | WRITE_ONCE(*p, v); \ |
| 5270 | serge | 78 | } while (0) |
| 79 | |||
| 6936 | serge | 80 | #define __smp_load_acquire(p) \ |
| 5270 | serge | 81 | ({ \ |
| 6082 | serge | 82 | typeof(*p) ___p1 = READ_ONCE(*p); \ |
| 5270 | serge | 83 | compiletime_assert_atomic_type(*p); \ |
| 84 | barrier(); \ |
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| 85 | ___p1; \ |
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| 86 | }) |
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| 87 | |||
| 88 | #endif |
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| 89 | |||
| 90 | /* Atomic operations are already serializing on x86 */ |
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| 6936 | serge | 91 | #define __smp_mb__before_atomic() barrier() |
| 92 | #define __smp_mb__after_atomic() barrier() |
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| 5270 | serge | 93 | |
| 6936 | serge | 94 | #include |
| 95 | |||
| 5270 | serge | 96 | #endif /* _ASM_X86_BARRIER_H */ |