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6588 | serge | 1 | #ifndef _ASM_X86_APICDEF_H |
2 | #define _ASM_X86_APICDEF_H |
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3 | |||
4 | /* |
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5 | * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) |
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6 | * |
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7 | * Alan Cox |
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8 | * Ingo Molnar |
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9 | */ |
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10 | |||
11 | #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 |
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12 | #define APIC_DEFAULT_PHYS_BASE 0xfee00000 |
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13 | |||
14 | /* |
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15 | * This is the IO-APIC register space as specified |
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16 | * by Intel docs: |
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17 | */ |
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18 | #define IO_APIC_SLOT_SIZE 1024 |
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19 | |||
20 | #define APIC_ID 0x20 |
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21 | |||
22 | #define APIC_LVR 0x30 |
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23 | #define APIC_LVR_MASK 0xFF00FF |
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24 | #define APIC_LVR_DIRECTED_EOI (1 << 24) |
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25 | #define GET_APIC_VERSION(x) ((x) & 0xFFu) |
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26 | #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) |
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27 | #ifdef CONFIG_X86_32 |
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28 | # define APIC_INTEGRATED(x) ((x) & 0xF0u) |
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29 | #else |
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30 | # define APIC_INTEGRATED(x) (1) |
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31 | #endif |
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32 | #define APIC_XAPIC(x) ((x) >= 0x14) |
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33 | #define APIC_EXT_SPACE(x) ((x) & 0x80000000) |
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34 | #define APIC_TASKPRI 0x80 |
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35 | #define APIC_TPRI_MASK 0xFFu |
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36 | #define APIC_ARBPRI 0x90 |
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37 | #define APIC_ARBPRI_MASK 0xFFu |
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38 | #define APIC_PROCPRI 0xA0 |
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39 | #define APIC_EOI 0xB0 |
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40 | #define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ |
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41 | #define APIC_RRR 0xC0 |
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42 | #define APIC_LDR 0xD0 |
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43 | #define APIC_LDR_MASK (0xFFu << 24) |
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44 | #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) |
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45 | #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) |
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46 | #define APIC_ALL_CPUS 0xFFu |
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47 | #define APIC_DFR 0xE0 |
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48 | #define APIC_DFR_CLUSTER 0x0FFFFFFFul |
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49 | #define APIC_DFR_FLAT 0xFFFFFFFFul |
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50 | #define APIC_SPIV 0xF0 |
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51 | #define APIC_SPIV_DIRECTED_EOI (1 << 12) |
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52 | #define APIC_SPIV_FOCUS_DISABLED (1 << 9) |
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53 | #define APIC_SPIV_APIC_ENABLED (1 << 8) |
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54 | #define APIC_ISR 0x100 |
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55 | #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ |
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56 | #define APIC_TMR 0x180 |
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57 | #define APIC_IRR 0x200 |
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58 | #define APIC_ESR 0x280 |
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59 | #define APIC_ESR_SEND_CS 0x00001 |
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60 | #define APIC_ESR_RECV_CS 0x00002 |
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61 | #define APIC_ESR_SEND_ACC 0x00004 |
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62 | #define APIC_ESR_RECV_ACC 0x00008 |
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63 | #define APIC_ESR_SENDILL 0x00020 |
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64 | #define APIC_ESR_RECVILL 0x00040 |
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65 | #define APIC_ESR_ILLREGA 0x00080 |
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66 | #define APIC_LVTCMCI 0x2f0 |
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67 | #define APIC_ICR 0x300 |
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68 | #define APIC_DEST_SELF 0x40000 |
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69 | #define APIC_DEST_ALLINC 0x80000 |
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70 | #define APIC_DEST_ALLBUT 0xC0000 |
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71 | #define APIC_ICR_RR_MASK 0x30000 |
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72 | #define APIC_ICR_RR_INVALID 0x00000 |
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73 | #define APIC_ICR_RR_INPROG 0x10000 |
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74 | #define APIC_ICR_RR_VALID 0x20000 |
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75 | #define APIC_INT_LEVELTRIG 0x08000 |
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76 | #define APIC_INT_ASSERT 0x04000 |
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77 | #define APIC_ICR_BUSY 0x01000 |
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78 | #define APIC_DEST_LOGICAL 0x00800 |
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79 | #define APIC_DEST_PHYSICAL 0x00000 |
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80 | #define APIC_DM_FIXED 0x00000 |
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81 | #define APIC_DM_FIXED_MASK 0x00700 |
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82 | #define APIC_DM_LOWEST 0x00100 |
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83 | #define APIC_DM_SMI 0x00200 |
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84 | #define APIC_DM_REMRD 0x00300 |
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85 | #define APIC_DM_NMI 0x00400 |
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86 | #define APIC_DM_INIT 0x00500 |
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87 | #define APIC_DM_STARTUP 0x00600 |
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88 | #define APIC_DM_EXTINT 0x00700 |
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89 | #define APIC_VECTOR_MASK 0x000FF |
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90 | #define APIC_ICR2 0x310 |
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91 | #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) |
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92 | #define SET_APIC_DEST_FIELD(x) ((x) << 24) |
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93 | #define APIC_LVTT 0x320 |
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94 | #define APIC_LVTTHMR 0x330 |
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95 | #define APIC_LVTPC 0x340 |
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96 | #define APIC_LVT0 0x350 |
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97 | #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) |
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98 | #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) |
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99 | #define SET_APIC_TIMER_BASE(x) (((x) << 18)) |
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100 | #define APIC_TIMER_BASE_CLKIN 0x0 |
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101 | #define APIC_TIMER_BASE_TMBASE 0x1 |
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102 | #define APIC_TIMER_BASE_DIV 0x2 |
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103 | #define APIC_LVT_TIMER_ONESHOT (0 << 17) |
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104 | #define APIC_LVT_TIMER_PERIODIC (1 << 17) |
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105 | #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) |
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106 | #define APIC_LVT_MASKED (1 << 16) |
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107 | #define APIC_LVT_LEVEL_TRIGGER (1 << 15) |
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108 | #define APIC_LVT_REMOTE_IRR (1 << 14) |
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109 | #define APIC_INPUT_POLARITY (1 << 13) |
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110 | #define APIC_SEND_PENDING (1 << 12) |
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111 | #define APIC_MODE_MASK 0x700 |
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112 | #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) |
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113 | #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) |
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114 | #define APIC_MODE_FIXED 0x0 |
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115 | #define APIC_MODE_NMI 0x4 |
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116 | #define APIC_MODE_EXTINT 0x7 |
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117 | #define APIC_LVT1 0x360 |
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118 | #define APIC_LVTERR 0x370 |
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119 | #define APIC_TMICT 0x380 |
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120 | #define APIC_TMCCT 0x390 |
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121 | #define APIC_TDCR 0x3E0 |
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122 | #define APIC_SELF_IPI 0x3F0 |
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123 | #define APIC_TDR_DIV_TMBASE (1 << 2) |
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124 | #define APIC_TDR_DIV_1 0xB |
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125 | #define APIC_TDR_DIV_2 0x0 |
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126 | #define APIC_TDR_DIV_4 0x1 |
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127 | #define APIC_TDR_DIV_8 0x2 |
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128 | #define APIC_TDR_DIV_16 0x3 |
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129 | #define APIC_TDR_DIV_32 0x8 |
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130 | #define APIC_TDR_DIV_64 0x9 |
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131 | #define APIC_TDR_DIV_128 0xA |
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132 | #define APIC_EFEAT 0x400 |
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133 | #define APIC_ECTRL 0x410 |
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134 | #define APIC_EILVTn(n) (0x500 + 0x10 * n) |
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135 | #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ |
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136 | #define APIC_EILVT_NR_AMD_10H 4 |
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137 | #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H |
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138 | #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) |
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139 | #define APIC_EILVT_MSG_FIX 0x0 |
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140 | #define APIC_EILVT_MSG_SMI 0x2 |
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141 | #define APIC_EILVT_MSG_NMI 0x4 |
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142 | #define APIC_EILVT_MSG_EXT 0x7 |
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143 | #define APIC_EILVT_MASKED (1 << 16) |
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144 | |||
145 | #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
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146 | #define APIC_BASE_MSR 0x800 |
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147 | #define XAPIC_ENABLE (1UL << 11) |
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148 | #define X2APIC_ENABLE (1UL << 10) |
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149 | |||
150 | #ifdef CONFIG_X86_32 |
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151 | # define MAX_IO_APICS 64 |
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152 | # define MAX_LOCAL_APIC 256 |
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153 | #else |
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154 | # define MAX_IO_APICS 128 |
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155 | # define MAX_LOCAL_APIC 32768 |
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156 | #endif |
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157 | |||
158 | /* |
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159 | * All x86-64 systems are xAPIC compatible. |
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160 | * In the following, "apicid" is a physical APIC ID. |
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161 | */ |
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162 | #define XAPIC_DEST_CPUS_SHIFT 4 |
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163 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) |
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164 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) |
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165 | #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) |
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166 | #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) |
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167 | #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) |
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168 | #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) |
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169 | |||
170 | /* |
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171 | * the local APIC register structure, memory mapped. Not terribly well |
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172 | * tested, but we might eventually use this one in the future - the |
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173 | * problem why we cannot use it right now is the P5 APIC, it has an |
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174 | * errata which cannot take 8-bit reads and writes, only 32-bit ones ... |
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175 | */ |
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176 | #define u32 unsigned int |
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177 | |||
178 | struct local_apic { |
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179 | |||
180 | /*000*/ struct { u32 __reserved[4]; } __reserved_01; |
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181 | |||
182 | /*010*/ struct { u32 __reserved[4]; } __reserved_02; |
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183 | |||
184 | /*020*/ struct { /* APIC ID Register */ |
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185 | u32 __reserved_1 : 24, |
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186 | phys_apic_id : 4, |
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187 | __reserved_2 : 4; |
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188 | u32 __reserved[3]; |
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189 | } id; |
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190 | |||
191 | /*030*/ const |
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192 | struct { /* APIC Version Register */ |
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193 | u32 version : 8, |
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194 | __reserved_1 : 8, |
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195 | max_lvt : 8, |
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196 | __reserved_2 : 8; |
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197 | u32 __reserved[3]; |
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198 | } version; |
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199 | |||
200 | /*040*/ struct { u32 __reserved[4]; } __reserved_03; |
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201 | |||
202 | /*050*/ struct { u32 __reserved[4]; } __reserved_04; |
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203 | |||
204 | /*060*/ struct { u32 __reserved[4]; } __reserved_05; |
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205 | |||
206 | /*070*/ struct { u32 __reserved[4]; } __reserved_06; |
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207 | |||
208 | /*080*/ struct { /* Task Priority Register */ |
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209 | u32 priority : 8, |
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210 | __reserved_1 : 24; |
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211 | u32 __reserved_2[3]; |
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212 | } tpr; |
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213 | |||
214 | /*090*/ const |
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215 | struct { /* Arbitration Priority Register */ |
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216 | u32 priority : 8, |
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217 | __reserved_1 : 24; |
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218 | u32 __reserved_2[3]; |
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219 | } apr; |
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220 | |||
221 | /*0A0*/ const |
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222 | struct { /* Processor Priority Register */ |
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223 | u32 priority : 8, |
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224 | __reserved_1 : 24; |
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225 | u32 __reserved_2[3]; |
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226 | } ppr; |
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227 | |||
228 | /*0B0*/ struct { /* End Of Interrupt Register */ |
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229 | u32 eoi; |
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230 | u32 __reserved[3]; |
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231 | } eoi; |
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232 | |||
233 | /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; |
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234 | |||
235 | /*0D0*/ struct { /* Logical Destination Register */ |
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236 | u32 __reserved_1 : 24, |
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237 | logical_dest : 8; |
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238 | u32 __reserved_2[3]; |
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239 | } ldr; |
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240 | |||
241 | /*0E0*/ struct { /* Destination Format Register */ |
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242 | u32 __reserved_1 : 28, |
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243 | model : 4; |
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244 | u32 __reserved_2[3]; |
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245 | } dfr; |
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246 | |||
247 | /*0F0*/ struct { /* Spurious Interrupt Vector Register */ |
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248 | u32 spurious_vector : 8, |
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249 | apic_enabled : 1, |
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250 | focus_cpu : 1, |
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251 | __reserved_2 : 22; |
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252 | u32 __reserved_3[3]; |
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253 | } svr; |
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254 | |||
255 | /*100*/ struct { /* In Service Register */ |
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256 | /*170*/ u32 bitfield; |
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257 | u32 __reserved[3]; |
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258 | } isr [8]; |
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259 | |||
260 | /*180*/ struct { /* Trigger Mode Register */ |
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261 | /*1F0*/ u32 bitfield; |
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262 | u32 __reserved[3]; |
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263 | } tmr [8]; |
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264 | |||
265 | /*200*/ struct { /* Interrupt Request Register */ |
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266 | /*270*/ u32 bitfield; |
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267 | u32 __reserved[3]; |
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268 | } irr [8]; |
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269 | |||
270 | /*280*/ union { /* Error Status Register */ |
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271 | struct { |
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272 | u32 send_cs_error : 1, |
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273 | receive_cs_error : 1, |
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274 | send_accept_error : 1, |
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275 | receive_accept_error : 1, |
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276 | __reserved_1 : 1, |
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277 | send_illegal_vector : 1, |
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278 | receive_illegal_vector : 1, |
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279 | illegal_register_address : 1, |
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280 | __reserved_2 : 24; |
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281 | u32 __reserved_3[3]; |
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282 | } error_bits; |
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283 | struct { |
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284 | u32 errors; |
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285 | u32 __reserved_3[3]; |
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286 | } all_errors; |
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287 | } esr; |
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288 | |||
289 | /*290*/ struct { u32 __reserved[4]; } __reserved_08; |
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290 | |||
291 | /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; |
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292 | |||
293 | /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; |
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294 | |||
295 | /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; |
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296 | |||
297 | /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; |
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298 | |||
299 | /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; |
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300 | |||
301 | /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; |
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302 | |||
303 | /*300*/ struct { /* Interrupt Command Register 1 */ |
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304 | u32 vector : 8, |
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305 | delivery_mode : 3, |
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306 | destination_mode : 1, |
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307 | delivery_status : 1, |
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308 | __reserved_1 : 1, |
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309 | level : 1, |
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310 | trigger : 1, |
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311 | __reserved_2 : 2, |
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312 | shorthand : 2, |
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313 | __reserved_3 : 12; |
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314 | u32 __reserved_4[3]; |
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315 | } icr1; |
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316 | |||
317 | /*310*/ struct { /* Interrupt Command Register 2 */ |
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318 | union { |
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319 | u32 __reserved_1 : 24, |
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320 | phys_dest : 4, |
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321 | __reserved_2 : 4; |
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322 | u32 __reserved_3 : 24, |
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323 | logical_dest : 8; |
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324 | } dest; |
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325 | u32 __reserved_4[3]; |
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326 | } icr2; |
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327 | |||
328 | /*320*/ struct { /* LVT - Timer */ |
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329 | u32 vector : 8, |
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330 | __reserved_1 : 4, |
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331 | delivery_status : 1, |
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332 | __reserved_2 : 3, |
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333 | mask : 1, |
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334 | timer_mode : 1, |
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335 | __reserved_3 : 14; |
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336 | u32 __reserved_4[3]; |
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337 | } lvt_timer; |
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338 | |||
339 | /*330*/ struct { /* LVT - Thermal Sensor */ |
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340 | u32 vector : 8, |
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341 | delivery_mode : 3, |
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342 | __reserved_1 : 1, |
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343 | delivery_status : 1, |
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344 | __reserved_2 : 3, |
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345 | mask : 1, |
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346 | __reserved_3 : 15; |
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347 | u32 __reserved_4[3]; |
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348 | } lvt_thermal; |
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349 | |||
350 | /*340*/ struct { /* LVT - Performance Counter */ |
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351 | u32 vector : 8, |
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352 | delivery_mode : 3, |
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353 | __reserved_1 : 1, |
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354 | delivery_status : 1, |
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355 | __reserved_2 : 3, |
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356 | mask : 1, |
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357 | __reserved_3 : 15; |
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358 | u32 __reserved_4[3]; |
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359 | } lvt_pc; |
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360 | |||
361 | /*350*/ struct { /* LVT - LINT0 */ |
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362 | u32 vector : 8, |
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363 | delivery_mode : 3, |
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364 | __reserved_1 : 1, |
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365 | delivery_status : 1, |
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366 | polarity : 1, |
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367 | remote_irr : 1, |
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368 | trigger : 1, |
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369 | mask : 1, |
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370 | __reserved_2 : 15; |
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371 | u32 __reserved_3[3]; |
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372 | } lvt_lint0; |
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373 | |||
374 | /*360*/ struct { /* LVT - LINT1 */ |
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375 | u32 vector : 8, |
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376 | delivery_mode : 3, |
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377 | __reserved_1 : 1, |
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378 | delivery_status : 1, |
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379 | polarity : 1, |
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380 | remote_irr : 1, |
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381 | trigger : 1, |
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382 | mask : 1, |
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383 | __reserved_2 : 15; |
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384 | u32 __reserved_3[3]; |
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385 | } lvt_lint1; |
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386 | |||
387 | /*370*/ struct { /* LVT - Error */ |
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388 | u32 vector : 8, |
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389 | __reserved_1 : 4, |
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390 | delivery_status : 1, |
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391 | __reserved_2 : 3, |
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392 | mask : 1, |
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393 | __reserved_3 : 15; |
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394 | u32 __reserved_4[3]; |
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395 | } lvt_error; |
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396 | |||
397 | /*380*/ struct { /* Timer Initial Count Register */ |
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398 | u32 initial_count; |
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399 | u32 __reserved_2[3]; |
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400 | } timer_icr; |
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401 | |||
402 | /*390*/ const |
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403 | struct { /* Timer Current Count Register */ |
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404 | u32 curr_count; |
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405 | u32 __reserved_2[3]; |
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406 | } timer_ccr; |
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407 | |||
408 | /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; |
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409 | |||
410 | /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; |
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411 | |||
412 | /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; |
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413 | |||
414 | /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; |
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415 | |||
416 | /*3E0*/ struct { /* Timer Divide Configuration Register */ |
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417 | u32 divisor : 4, |
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418 | __reserved_1 : 28; |
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419 | u32 __reserved_2[3]; |
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420 | } timer_dcr; |
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421 | |||
422 | /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; |
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423 | |||
424 | } __attribute__ ((packed)); |
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425 | |||
426 | #undef u32 |
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427 | |||
428 | #ifdef CONFIG_X86_32 |
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429 | #define BAD_APICID 0xFFu |
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430 | #else |
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431 | #define BAD_APICID 0xFFFFu |
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432 | #endif |
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433 | |||
434 | enum ioapic_irq_destination_types { |
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435 | dest_Fixed = 0, |
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436 | dest_LowestPrio = 1, |
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437 | dest_SMI = 2, |
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438 | dest__reserved_1 = 3, |
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439 | dest_NMI = 4, |
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440 | dest_INIT = 5, |
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441 | dest__reserved_2 = 6, |
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442 | dest_ExtINT = 7 |
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443 | }; |
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444 | |||
445 | #endif /* _ASM_X86_APICDEF_H */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |