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3545 hidnplayr 1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2
;;                                                                  ;;
5363 yogev_ezra 3
;; Copyright (C) KolibriOS team 2004-2015. All rights reserved.     ;;
3545 hidnplayr 4
;; Distributed under terms of the GNU General Public License        ;;
5
;;                                                                  ;;
6
;;  AMD PCnet driver for KolibriOS                                  ;;
7
;;                                                                  ;;
8
;;  By hidnplayr & clevermouse                                      ;;
9
;;                                                                  ;;
10
;;  Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar      ;;
11
;;                                                                  ;;
12
;;          GNU GENERAL PUBLIC LICENSE                              ;;
13
;;             Version 2, June 1991                                 ;;
14
;;                                                                  ;;
15
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
16
 
4532 hidnplayr 17
format PE DLL native
18
entry START
3545 hidnplayr 19
 
4532 hidnplayr 20
        CURRENT_API             = 0x0200
21
        COMPATIBLE_API          = 0x0100
22
        API_VERSION             = (COMPATIBLE_API shl 16) + CURRENT_API
3545 hidnplayr 23
 
4532 hidnplayr 24
        MAX_DEVICES             = 16
25
 
3545 hidnplayr 26
        __DEBUG__               = 1
4582 hidnplayr 27
        __DEBUG_LEVEL__         = 2             ; 1 = verbose, 2 = errors only
3545 hidnplayr 28
 
29
        TX_RING_SIZE            = 4
30
        RX_RING_SIZE            = 4
31
 
4532 hidnplayr 32
section '.flat' readable writable executable
33
 
4467 hidnplayr 34
include '../struct.inc'
35
include '../macros.inc'
3545 hidnplayr 36
include '../proc32.inc'
37
include '../fdo.inc'
5074 hidnplayr 38
include '../netdrv.inc'
3545 hidnplayr 39
 
40
 
41
        PORT_AUI                = 0x00
42
        PORT_10BT               = 0x01
43
        PORT_GPSI               = 0x02
44
        PORT_MII                = 0x03
45
        PORT_PORTSEL            = 0x03
46
        PORT_ASEL               = 0x04
47
        PORT_100                = 0x40
48
        PORT_FD                 = 0x80
49
 
50
        DMA_MASK                = 0xffffffff
51
 
52
        LOG_TX_BUFFERS          = 2             ; FIXME
53
        LOG_RX_BUFFERS          = 2
54
 
55
        TX_RING_MOD_MASK        = (TX_RING_SIZE-1)
56
        TX_RING_LEN_BITS        = (LOG_TX_BUFFERS shl 12)
57
 
58
        RX_RING_MOD_MASK        = (RX_RING_SIZE-1)
59
        RX_RING_LEN_BITS        = (LOG_RX_BUFFERS shl 4)
60
 
61
        PKT_BUF_SZ              = 1544
62
 
63
        WIO_RDP                 = 0x10
64
        WIO_RAP                 = 0x12
65
        WIO_RESET               = 0x14
66
        WIO_BDP                 = 0x16
67
 
68
        DWIO_RDP                = 0x10
69
        DWIO_RAP                = 0x14
70
        DWIO_RESET              = 0x18
71
        DWIO_BDP                = 0x1C
72
 
73
; CSR registers
74
 
75
        CSR_CSR                 = 0x00
76
        CSR_IAB0                = 0x01
77
        CSR_IAB1                = 0x02
78
        CSR_IMR                 = 0x03
79
        CSR_TFEAT               = 0x04
80
        CSR_EXTCTL1             = 0x05
81
        CSR_DTBLLEN             = 0x06
82
        CSR_EXTCTL2             = 0x07
83
        CSR_MAR0                = 0x08
84
        CSR_MAR1                = 0x09
85
        CSR_MAR2                = 0x0A
86
        CSR_MAR3                = 0x0B
87
        CSR_PAR0                = 0x0C
88
        CSR_PAR1                = 0x0D
89
        CSR_PAR2                = 0x0E
90
        CSR_MODE                = 0x0F
91
        CSR_RXADDR0             = 0x18
92
        CSR_RXADDR1             = 0x19
93
        CSR_TXADDR0             = 0x1E
94
        CSR_TXADDR1             = 0x1F
95
        CSR_TXPOLL              = 0x2F
96
        CSR_RXPOLL              = 0x31
97
        CSR_RXRINGLEN           = 0x4C
98
        CSR_TXRINGLEN           = 0x4E
99
        CSR_DMACTL              = 0x50
100
        CSR_BUSTIMER            = 0x52
101
        CSR_MEMERRTIMEO         = 0x64
102
        CSR_ONNOWMISC           = 0x74
103
        CSR_ADVFEAT             = 0x7A
104
        CSR_MACCFG              = 0x7D
105
        CSR_CHIPID0             = 0x58
106
        CSR_CHIPID1             = 0x59
107
 
108
; Control and Status Register (CSR0)
109
 
5004 hidnplayr 110
        CSR_INIT                = 0x0001 ;1 shl 0
111
        CSR_START               = 0x0002 ;1 shl 1
112
        CSR_STOP                = 0x0004 ;1 shl 2
113
        CSR_TX                  = 0x0008 ;1 shl 3
114
        CSR_TXON                = 0x0010 ;1 shl 4
115
        CSR_RXON                = 0x0020 ;1 shl 5
116
        CSR_INTEN               = 0x0040 ;1 shl 6
117
        CSR_INTR                = 0x0080 ;1 shl 7
118
        CSR_IDONE               = 0x0100 ;1 shl 8
119
        CSR_TINT                = 0x0200 ;1 shl 9
120
        CSR_RINT                = 0x0400 ;1 shl 10
121
        CSR_MERR                = 0x0800 ;1 shl 11
122
        CSR_MISS                = 0x1000 ;1 shl 12
123
        CSR_CERR                = 0x2000 ;1 shl 13
3545 hidnplayr 124
 
125
; Interrupt masks and deferral control (CSR3)
126
 
127
        IMR_BSWAP               = 0x0004
128
        IMR_ENMBA               = 0x0008  ; enable modified backoff alg
129
        IMR_DXMT2PD             = 0x0010
130
        IMR_LAPPEN              = 0x0020  ; lookahead packet processing enb
131
        IMR_DXSUFLO             = 0x0040  ; disable TX stop on underflow
132
        IMR_IDONE               = 0x0100
133
        IMR_TINT                = 0x0200
134
        IMR_RINT                = 0x0400
135
        IMR_MERR                = 0x0800
136
        IMR_MISS                = 0x1000
137
 
5004 hidnplayr 138
        ; Masked interrupts will be disabled.
139
        IMR                     = 0 ;IMR_IDONE ;or IMR_TINT or IMR_RINT or IMR_MERR or IMR_MISS
3545 hidnplayr 140
 
141
; Test and features control (CSR4)
142
 
143
        TFEAT_TXSTRTMASK        = 0x0004
144
        TFEAT_TXSTRT            = 0x0008
145
        TFEAT_RXCCOFLOWM        = 0x0010  ; Rx collision counter oflow
146
        TFEAT_RXCCOFLOW         = 0x0020
147
        TFEAT_UINT              = 0x0040
148
        TFEAT_UINTREQ           = 0x0080
149
        TFEAT_MISSOFLOWM        = 0x0100
150
        TFEAT_MISSOFLOW         = 0x0200
151
        TFEAT_STRIP_FCS         = 0x0400
152
        TFEAT_PAD_TX            = 0x0800
153
        TFEAT_TXDPOLL           = 0x1000
154
        TFEAT_DMAPLUS           = 0x4000
155
 
156
; Extended control and interrupt 1 (CSR5)
157
 
158
        EXTCTL1_SPND            = 0x0001  ; suspend
159
        EXTCTL1_MPMODE          = 0x0002  ; magic packet mode
160
        EXTCTL1_MPENB           = 0x0004  ; magic packet enable
161
        EXTCTL1_MPINTEN         = 0x0008  ; magic packet interrupt enable
162
        EXTCTL1_MPINT           = 0x0010  ; magic packet interrupt
163
        EXTCTL1_MPPLBA          = 0x0020  ; magic packet phys. logical bcast
164
        EXTCTL1_EXDEFEN         = 0x0040  ; excessive deferral interrupt enb.
165
        EXTCTL1_EXDEF           = 0x0080  ; excessive deferral interrupt
166
        EXTCTL1_SINTEN          = 0x0400  ; system interrupt enable
167
        EXTCTL1_SINT            = 0x0800  ; system interrupt
168
        EXTCTL1_LTINTEN         = 0x4000  ; last TX interrupt enb
169
        EXTCTL1_TXOKINTD        = 0x8000  ; TX OK interrupt disable
170
 
171
; RX/TX descriptor len (CSR6)
172
 
173
        DTBLLEN_RLEN            = 0x0F00
174
        DTBLLEN_TLEN            = 0xF000
175
 
176
; Extended control and interrupt 2 (CSR7)
177
 
178
        EXTCTL2_MIIPDTINTE      = 0x0001
179
        EXTCTL2_MIIPDTINT       = 0x0002
180
        EXTCTL2_MCCIINTE        = 0x0004
181
        EXTCTL2_MCCIINT         = 0x0008
182
        EXTCTL2_MCCINTE         = 0x0010
183
        EXTCTL2_MCCINT          = 0x0020
184
        EXTCTL2_MAPINTE         = 0x0040
185
        EXTCTL2_MAPINT          = 0x0080
186
        EXTCTL2_MREINTE         = 0x0100
187
        EXTCTL2_MREINT          = 0x0200
188
        EXTCTL2_STINTE          = 0x0400
189
        EXTCTL2_STINT           = 0x0800
190
        EXTCTL2_RXDPOLL         = 0x1000
191
        EXTCTL2_RDMD            = 0x2000
192
        EXTCTL2_RXFRTG          = 0x4000
193
        EXTCTL2_FASTSPNDE       = 0x8000
194
 
195
; Mode (CSR15)
196
 
197
        MODE_RXD                = 0x0001  ; RX disable
198
        MODE_TXD                = 0x0002  ; TX disable
199
        MODE_LOOP               = 0x0004  ; loopback enable
200
        MODE_TXCRCD             = 0x0008
201
        MODE_FORCECOLL          = 0x0010
202
        MODE_RETRYD             = 0x0020
203
        MODE_INTLOOP            = 0x0040
204
        MODE_PORTSEL            = 0x0180
205
        MODE_RXVPAD             = 0x2000
206
        MODE_RXNOBROAD          = 0x4000
207
        MODE_PROMISC            = 0x8000
208
 
209
; BCR (Bus Control Registers)
210
 
211
        BCR_MMRA                = 0x00    ; Master Mode Read Active
212
        BCR_MMW                 = 0x01    ; Master Mode Write Active
213
        BCR_MISCCFG             = 0x02
214
        BCR_LED0                = 0x04
215
        BCR_LED1                = 0x05
216
        BCR_LED2                = 0x06
217
        BCR_LED3                = 0x07
218
        BCR_DUPLEX              = 0x09
219
        BCR_BUSCTL              = 0x12
220
        BCR_EECTL               = 0x13
221
        BCR_SSTYLE              = 0x14
222
        BCR_PCILAT              = 0x16
223
        BCR_PCISUBVENID         = 0x17
224
        BCR_PCISUBSYSID         = 0x18
225
        BCR_SRAMSIZE            = 0x19
226
        BCR_SRAMBOUND           = 0x1A
227
        BCR_SRAMCTL             = 0x1B
228
        BCR_MIICTL              = 0x20
229
        BCR_MIIADDR             = 0x21
230
        BCR_MIIDATA             = 0x22
231
        BCR_PCIVENID            = 0x23
232
        BCR_PCIPCAP             = 0x24
233
        BCR_DATA0               = 0x25
234
        BCR_DATA1               = 0x26
235
        BCR_DATA2               = 0x27
236
        BCR_DATA3               = 0x28
237
        BCR_DATA4               = 0x29
238
        BCR_DATA5               = 0x2A
239
        BCR_DATA6               = 0x2B
240
        BCR_DATA7               = 0x2C
241
        BCR_ONNOWPAT0           = 0x2D
242
        BCR_ONNOWPAT1           = 0x2E
243
        BCR_ONNOWPAT2           = 0x2F
244
        BCR_PHYSEL              = 0x31
245
 
246
; RX status register
247
 
248
        RXSTAT_BPE              = 0x0080        ; bus parity error
249
        RXSTAT_ENP              = 0x0100        ; end of packet
250
        RXSTAT_STP              = 0x0200        ; start of packet
251
        RXSTAT_BUFF             = 0x0400        ; buffer error
252
        RXSTAT_CRC              = 0x0800        ; CRC error
253
        RXSTAT_OFLOW            = 0x1000        ; rx overrun
254
        RXSTAT_FRAM             = 0x2000        ; framing error
255
        RXSTAT_ERR              = 0x4000        ; error summary
256
        RXSTAT_OWN              = 0x8000
257
 
258
; TX status register
259
 
260
        TXSTAT_TRC              = 0x0000000F    ; transmit retries
261
        TXSTAT_RTRY             = 0x04000000    ; retry
262
        TXSTAT_LCAR             = 0x08000000    ; lost carrier
263
        TXSTAT_LCOL             = 0x10000000    ; late collision
264
        TXSTAT_EXDEF            = 0x20000000    ; excessive deferrals
265
        TXSTAT_UFLOW            = 0x40000000    ; transmit underrun
266
        TXSTAT_BUFF             = 0x80000000    ; buffer error
267
 
268
        TXCTL_OWN               = 0x8000
269
        TXCTL_ERR               = 0x4000        ; error summary
270
        TXCTL_ADD_FCS           = 0x2000        ; add FCS to pkt
271
        TXCTL_MORE_LTINT        = 0x1000
272
        TXCTL_ONE               = 0x0800
273
        TXCTL_DEF               = 0x0400
274
        TXCTL_STP               = 0x0200
275
        TXCTL_ENP               = 0x0100
276
        TXCTL_BPE               = 0x0080
277
 
278
        TXCTL_MBO               = 0x0000F000
279
        TXCTL_BUFSZ             = 0x00000FFF
280
 
281
        MAX_PHYS                = 32
282
 
283
 
4532 hidnplayr 284
struct  device          ETH_DEVICE
3545 hidnplayr 285
 
4532 hidnplayr 286
        rb 0x100-($ and 0xff)   ; align 256
3545 hidnplayr 287
 
4532 hidnplayr 288
; Pcnet configuration structure
289
        mode            dw ?
290
        tlen_rlen       dw ?
291
        phys_addr       dp ?
292
        reserved        dw ?
293
        filter          dq ?
294
        rx_ring_phys    dd ?
295
        tx_ring_phys    dd ?
296
; end of pcnet config struct
3545 hidnplayr 297
 
4532 hidnplayr 298
        rb 0x100-($ and 0xff)   ; align 256
3545 hidnplayr 299
 
4532 hidnplayr 300
        rx_ring         rb RX_RING_SIZE * sizeof.descriptor
3545 hidnplayr 301
 
4532 hidnplayr 302
        rb 0x100-($ and 0xff)   ; align 256
3545 hidnplayr 303
 
4532 hidnplayr 304
        tx_ring         rb TX_RING_SIZE * sizeof.descriptor
3545 hidnplayr 305
 
4532 hidnplayr 306
        cur_rx          db ?
307
        cur_tx          db ?
308
        last_tx         db ?
309
        options         dd ?
310
        full_duplex     db ?
311
        chip_version    dw ?
312
        mii             db ?
313
        ltint           db ?
314
        dxsuflo         db ?
315
        fset            db ?
316
        fdx             db ?
3545 hidnplayr 317
 
4532 hidnplayr 318
        io_addr         dd ?
319
        irq_line        db ?
320
        pci_bus         dd ?
321
        pci_dev         dd ?
3545 hidnplayr 322
 
4532 hidnplayr 323
        phy             dw ?
3545 hidnplayr 324
 
4532 hidnplayr 325
        read_csr        dd ?
326
        write_csr       dd ?
327
        read_bcr        dd ?
328
        write_bcr       dd ?
329
        read_rap        dd ?
330
        write_rap       dd ?
331
        sw_reset        dd ?
3545 hidnplayr 332
 
4532 hidnplayr 333
ends
3545 hidnplayr 334
 
4532 hidnplayr 335
struct  descriptor
3545 hidnplayr 336
 
4532 hidnplayr 337
        base            dd ?
338
        length          dw ?
339
        status          dw ?
340
        msg_length      dw ?
341
        misc            dw ?
342
        virtual         dd ?
3545 hidnplayr 343
 
4532 hidnplayr 344
ends
3545 hidnplayr 345
 
346
 
347
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
348
;;                        ;;
349
;; proc START             ;;
350
;;                        ;;
351
;; (standard driver proc) ;;
352
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
353
 
4532 hidnplayr 354
proc START c, reason:dword, cmdline:dword
3545 hidnplayr 355
 
4532 hidnplayr 356
        cmp     [reason], DRV_ENTRY
357
        jne     .fail
3545 hidnplayr 358
 
4532 hidnplayr 359
        DEBUGF  2,"Loading driver\n"
360
        invoke  RegService, my_service, service_proc
3545 hidnplayr 361
        ret
362
 
363
  .fail:
364
        xor eax, eax
365
        ret
366
 
367
endp
368
 
369
 
370
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
371
;;                        ;;
372
;; proc SERVICE_PROC      ;;
373
;;                        ;;
374
;; (standard driver proc) ;;
375
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
376
 
377
align 4
378
proc service_proc stdcall, ioctl:dword
379
 
380
        mov     edx, [ioctl]
4470 hidnplayr 381
        mov     eax, [edx + IOCTL.io_code]
3545 hidnplayr 382
 
383
;------------------------------------------------------
384
 
385
        cmp     eax, 0 ;SRV_GETVERSION
386
        jne     @F
387
 
4470 hidnplayr 388
        cmp     [edx + IOCTL.out_size], 4
3545 hidnplayr 389
        jb      .fail
4470 hidnplayr 390
        mov     eax, [edx + IOCTL.output]
3545 hidnplayr 391
        mov     [eax], dword API_VERSION
392
 
393
        xor     eax, eax
394
        ret
395
 
396
;------------------------------------------------------
397
  @@:
398
        cmp     eax, 1 ;SRV_HOOK
399
        jne     .fail
400
 
4532 hidnplayr 401
        cmp     [edx + IOCTL.inp_size], 3               ; Data input must be at least 3 bytes
3545 hidnplayr 402
        jb      .fail
403
 
4470 hidnplayr 404
        mov     eax, [edx + IOCTL.input]
4532 hidnplayr 405
        cmp     byte[eax], 1                            ; 1 means device number and bus number (pci) are given
3545 hidnplayr 406
        jne     .fail                                   ; other types arent supported for this card yet
407
 
408
; check if the device is already listed
409
 
410
        mov     ecx, [devices]
411
        test    ecx, ecx
412
        jz      .firstdevice
413
 
414
        mov     esi, device_list
4470 hidnplayr 415
;        mov     eax, [edx + IOCTL.input]                ; get the pci bus and device numbers
416
        mov     ax, [eax+1]                             ;
3545 hidnplayr 417
  .nextdevice:
418
        mov     ebx, [esi]
4532 hidnplayr 419
        cmp     al, byte[ebx + device.pci_bus]
3545 hidnplayr 420
        jne     @f
4532 hidnplayr 421
        cmp     ah, byte[ebx + device.pci_dev]
3545 hidnplayr 422
        je      .find_devicenum                         ; Device is already loaded, let's find it's device number
423
       @@:
424
        add     esi, 4
425
        loop    .nextdevice
426
 
427
; This device doesnt have its own eth_device structure yet, lets create one
428
 
429
  .firstdevice:
430
        cmp     [devices], MAX_DEVICES                  ; First check if the driver can handle one more card
431
        jae     .fail
432
 
4532 hidnplayr 433
        allocate_and_clear ebx, sizeof.device, .fail
3545 hidnplayr 434
 
435
; Fill in the direct call addresses into the struct
436
 
4532 hidnplayr 437
        mov     [ebx + device.reset], reset
438
        mov     [ebx + device.transmit], transmit
439
        mov     [ebx + device.unload], unload
440
        mov     [ebx + device.name], my_service
3545 hidnplayr 441
 
442
; save the pci bus and device numbers
443
 
4470 hidnplayr 444
        mov     eax, [edx + IOCTL.input]
3545 hidnplayr 445
        movzx   ecx, byte[eax+1]
4532 hidnplayr 446
        mov     [ebx + device.pci_bus], ecx
3545 hidnplayr 447
        movzx   ecx, byte[eax+2]
4532 hidnplayr 448
        mov     [ebx + device.pci_dev], ecx
3545 hidnplayr 449
 
450
; Now, it's time to find the base io addres of the PCI device
451
 
4532 hidnplayr 452
        stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
453
        mov     [ebx + device.io_addr], eax
3545 hidnplayr 454
 
455
; We've found the io address, find IRQ now
456
 
4532 hidnplayr 457
        invoke  PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
458
        mov     [ebx + device.irq_line], al
3545 hidnplayr 459
 
460
        DEBUGF  1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
4532 hidnplayr 461
        [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:4
3545 hidnplayr 462
 
463
; Ok, the eth_device structure is ready, let's probe the device
464
; Because initialization fires IRQ, IRQ handler must be aware of this device
465
        mov     eax, [devices]                                          ; Add the device structure to our device list
466
        mov     [device_list+4*eax], ebx                                ; (IRQ handler uses this list to find device)
467
        inc     [devices]                                               ;
468
 
469
        call    probe                                                   ; this function will output in eax
470
        test    eax, eax
471
        jnz     .destroy                                                ; If an error occured, exit
472
 
4532 hidnplayr 473
        mov     [ebx + device.type], NET_TYPE_ETH
474
        invoke  NetRegDev
3545 hidnplayr 475
        cmp     eax, -1
476
        je      .destroy
477
 
478
        ret
479
 
480
; If the device was already loaded, find the device number and return it in eax
481
 
482
  .find_devicenum:
483
        DEBUGF  1,"Trying to find device number of already registered device\n"
4532 hidnplayr 484
        invoke  NetPtrToNum                                             ; This kernel procedure converts a pointer to device struct in ebx
3545 hidnplayr 485
                                                                        ; into a device number in edi
486
        mov     eax, edi                                                ; Application wants it in eax instead
487
        DEBUGF  1,"Kernel says: %u\n", eax
488
        ret
489
 
490
; If an error occured, remove all allocated data and exit (returning -1 in eax)
491
 
492
  .destroy:
493
        ; todo: reset device into virgin state
5522 hidnplayr 494
        add     eax, NET_BUFF.data
3545 hidnplayr 495
        dec     [devices]
496
  .err:
3855 hidnplayr 497
        DEBUGF  2,"Error, removing all data !\n"
4532 hidnplayr 498
        invoke  KernelFree, ebx
3545 hidnplayr 499
 
500
  .fail:
501
        or      eax, -1
502
        ret
503
 
504
;------------------------------------------------------
505
endp
506
 
507
 
508
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
509
;;                                                                        ;;
510
;;        Actual Hardware dependent code starts here                      ;;
511
;;                                                                        ;;
512
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
513
 
514
align 4
515
unload:
516
        ; TODO: (in this particular order)
517
        ;
518
        ; - Stop the device
519
        ; - Detach int handler
4532 hidnplayr 520
        ; - Remove device from local list (device_list)
3545 hidnplayr 521
        ; - call unregister function in kernel
522
        ; - Remove all allocated structures and buffers the card used
523
 
5522 hidnplayr 524
        or      eax, -1
525
        ret
3545 hidnplayr 526
 
527
 
528
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
529
;;
530
;;  probe: enables the device (if it really is a PCnet device)
531
;;
532
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
533
 
534
align 4
535
probe:
536
 
4532 hidnplayr 537
        mov     edx, [ebx + device.io_addr]
3545 hidnplayr 538
 
539
        call    wio_reset
540
 
541
        xor     ecx, ecx
542
        call    wio_read_csr
543
        cmp     eax, 4
544
        jne     .try_dwio
545
 
546
        ; Try Word I/O
547
        mov     ax, 88
548
        add     edx, WIO_RAP
549
        out     dx, ax
550
        nop
551
        nop
552
        in      ax, dx
553
        sub     edx, WIO_RAP
554
        cmp     ax, 88
555
        jne     .try_dwio
556
 
557
        call    switch_to_wio
558
 
559
        jmp     .L1
560
 
561
  .try_dwio:
562
        call    dwio_reset
563
 
564
        xor     ecx, ecx
565
        call    dwio_read_csr
566
        cmp     eax, 4
567
        jne     .no_dev
568
 
569
        ; Try Dword I/O
570
        add     edx, DWIO_RAP
571
        mov     eax, 88
572
        out     dx, eax
573
        nop
574
        nop
575
        in      eax, dx
576
        sub     edx, DWIO_RAP
577
        and     eax, 0xffff
578
        cmp     eax, 88
579
        jne     .no_dev
580
 
581
        call    switch_to_dwio
582
 
583
        jmp     .L1
584
 
585
  .no_dev:
4532 hidnplayr 586
        DEBUGF  2,"device not found!\n"
3545 hidnplayr 587
        mov     eax, 1
588
        ret
589
 
590
  .L1:
591
        mov     ecx, CSR_CHIPID0
4532 hidnplayr 592
        call    [ebx + device.read_csr]
3545 hidnplayr 593
 
594
        mov     esi, eax
595
        shr     esi, 12
596
 
597
        and     ax, 0xfff
598
        cmp     ax, 3
599
        jne     .no_dev
600
 
601
        mov     ecx, CSR_CHIPID1
4532 hidnplayr 602
        call    [ebx + device.read_csr]
3545 hidnplayr 603
        shl     eax, 4
604
        or      eax, esi
4532 hidnplayr 605
        mov     [ebx + device.chip_version], ax
3545 hidnplayr 606
 
4532 hidnplayr 607
        mov     [ebx + device.fdx], 0
608
        mov     [ebx + device.mii], 0
609
        mov     [ebx + device.fset], 0
610
        mov     [ebx + device.dxsuflo], 0
611
        mov     [ebx + device.ltint], 0
3545 hidnplayr 612
 
613
        cmp     ax, 0x2420
614
        je      .L2
615
        cmp     ax, 0x2430
616
        je      .L2
617
 
4532 hidnplayr 618
        mov     [ebx + device.fdx], 1
3545 hidnplayr 619
 
620
        cmp     ax, 0x2621
621
        je      .L4
622
        cmp     ax, 0x2623
623
        je      .L5
624
        cmp     ax, 0x2624
625
        je      .L6
626
        cmp     ax, 0x2625
627
        je      .L7
628
        cmp     ax, 0x2626
629
        je      .L8
630
        cmp     ax, 0x2627
631
        je      .L9
632
 
5065 hidnplayr 633
        DEBUGF  2,"Invalid chip rev\n"
3545 hidnplayr 634
        jmp     .no_dev
635
  .L2:
4532 hidnplayr 636
        mov     [ebx + device.name], device_l2
3545 hidnplayr 637
        jmp     .L10
638
  .L4:
4532 hidnplayr 639
        mov     [ebx + device.name], device_l4
640
;        mov     [ebx + device.fdx], 1
3545 hidnplayr 641
        jmp     .L10
642
  .L5:
4532 hidnplayr 643
        mov     [ebx + device.name], device_l5
644
;        mov     [ebx + device.fdx], 1
645
        mov     [ebx + device.mii], 1
646
        mov     [ebx + device.fset], 1
647
        mov     [ebx + device.ltint], 1
3545 hidnplayr 648
        jmp     .L10
649
  .L6:
4532 hidnplayr 650
        mov     [ebx + device.name], device_l6
651
;        mov     [ebx + device.fdx], 1
652
        mov     [ebx + device.mii], 1
653
        mov     [ebx + device.fset], 1
3545 hidnplayr 654
        jmp     .L10
655
  .L7:
4532 hidnplayr 656
        mov     [ebx + device.name], device_l7
657
;        mov     [ebx + device.fdx], 1
658
        mov     [ebx + device.mii], 1
3545 hidnplayr 659
        jmp     .L10
660
  .L8:
4532 hidnplayr 661
        mov     [ebx + device.name], device_l8
662
;        mov     [ebx + device.fdx], 1
3545 hidnplayr 663
        mov     ecx, CSR_RXPOLL
4532 hidnplayr 664
        call    dword [ebx + device.read_bcr]
665
        call    dword [ebx + device.write_bcr]
3545 hidnplayr 666
        jmp     .L10
667
  .L9:
4532 hidnplayr 668
        mov     [ebx + device.name], device_l9
669
;        mov     [ebx + device.fdx], 1
670
        mov     [ebx + device.mii], 1
3545 hidnplayr 671
  .L10:
4532 hidnplayr 672
        DEBUGF  1,"device name: %s\n", [ebx + device.name]
3545 hidnplayr 673
 
4532 hidnplayr 674
        cmp     [ebx + device.fset], 1
3545 hidnplayr 675
        jne     .L11
676
        mov     ecx, BCR_BUSCTL
4532 hidnplayr 677
        call    [ebx + device.read_bcr]
3545 hidnplayr 678
        or      eax, 0x800
4532 hidnplayr 679
        call    [ebx + device.write_bcr]
3545 hidnplayr 680
 
681
        mov     ecx, CSR_DMACTL
4532 hidnplayr 682
        call    [ebx + device.read_csr]
3545 hidnplayr 683
;        and     eax, 0xc00
684
;        or      eax, 0xc00
685
        mov     eax, 0xc00
4532 hidnplayr 686
        call    [ebx + device.write_csr]
3545 hidnplayr 687
 
4532 hidnplayr 688
        mov     [ebx + device.dxsuflo],1
689
        mov     [ebx + device.ltint],1
3545 hidnplayr 690
  .L11:
691
 
4532 hidnplayr 692
; Make the device a bus master
693
        invoke  PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
694
        or      al, PCI_CMD_MASTER
695
        invoke  PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
3545 hidnplayr 696
 
4532 hidnplayr 697
        mov     [ebx + device.options], PORT_ASEL
698
        mov     [ebx + device.mode], MODE_RXD + MODE_TXD     ; disable receive and transmit
699
        mov     [ebx + device.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
3545 hidnplayr 700
 
4532 hidnplayr 701
        mov     dword[ebx + device.filter], 0
702
        mov     dword[ebx + device.filter+4], 0
3545 hidnplayr 703
 
704
align 4
705
reset:
706
 
707
; attach int handler
708
 
4532 hidnplayr 709
        movzx   eax, [ebx + device.irq_line]
3545 hidnplayr 710
        DEBUGF  1,"Attaching int handler to irq %x\n", eax:1
4532 hidnplayr 711
        invoke  AttachIntHandler, eax, int_handler, ebx
3545 hidnplayr 712
        test    eax, eax
713
        jnz     @f
3855 hidnplayr 714
        DEBUGF  2,"Could not attach int handler!\n"
4532 hidnplayr 715
        or      eax, -1
716
        ret
3545 hidnplayr 717
  @@:
718
 
4532 hidnplayr 719
        mov     edx, [ebx + device.io_addr]
720
        call    [ebx + device.sw_reset]
3545 hidnplayr 721
 
722
        ; Switch pcnet32 to 32bit mode
723
        mov     ecx, BCR_SSTYLE
724
        mov     eax, 2
4532 hidnplayr 725
        call    [ebx + device.write_bcr]
3545 hidnplayr 726
 
727
        ; set/reset autoselect bit
728
        mov     ecx, BCR_MISCCFG
4532 hidnplayr 729
        call    [ebx + device.read_bcr]
3545 hidnplayr 730
        and     eax, not 2
4532 hidnplayr 731
        test    [ebx + device.options], PORT_ASEL
3545 hidnplayr 732
        jz      @f
733
        or      eax, 2
734
  @@:
4532 hidnplayr 735
        call    [ebx + device.write_bcr]
3545 hidnplayr 736
 
737
        ; Handle full duplex setting
4532 hidnplayr 738
        cmp     byte [ebx + device.full_duplex], 0
3545 hidnplayr 739
        je      .duplex_ok
740
        mov     ecx, BCR_DUPLEX
4532 hidnplayr 741
        call    [ebx + device.read_bcr]
3545 hidnplayr 742
        and     eax, not 3
4532 hidnplayr 743
        test    [ebx + device.options], PORT_FD
3545 hidnplayr 744
        jz      @f
745
        or      eax, 1
4532 hidnplayr 746
        cmp     [ebx + device.options], PORT_FD or PORT_AUI
3545 hidnplayr 747
        jne     .set_duplex
748
        or      eax, 2
749
        jmp     .set_duplex
750
  @@:
4532 hidnplayr 751
        test    [ebx + device.options], PORT_ASEL
3545 hidnplayr 752
        jz      .set_duplex
4532 hidnplayr 753
        cmp     [ebx + device.chip_version], 0x2627
3545 hidnplayr 754
        jne     .set_duplex
755
        or      eax, 3
756
  .set_duplex:
757
        mov     ecx, BCR_DUPLEX
4532 hidnplayr 758
        call    [ebx + device.write_bcr]
3545 hidnplayr 759
  .duplex_ok:
760
 
761
        ; set/reset GPSI bit in test register
762
        mov     ecx, 124
4532 hidnplayr 763
        call    [ebx + device.read_csr]
764
        mov     ecx, [ebx + device.options]
3545 hidnplayr 765
        and     ecx, PORT_PORTSEL
766
        cmp     ecx, PORT_GPSI
767
        jne     @f
768
        or      eax, 0x10
769
  @@:
4532 hidnplayr 770
        call    [ebx + device.write_csr]
771
        cmp     [ebx + device.mii], 0
3545 hidnplayr 772
        je      .L6
4532 hidnplayr 773
        test    [ebx + device.options], PORT_ASEL
3545 hidnplayr 774
        jnz     .L6
775
        mov     ecx, BCR_MIICTL
4532 hidnplayr 776
        call    [ebx + device.read_bcr]
3545 hidnplayr 777
        and     eax, not 0x38
4532 hidnplayr 778
        test    [ebx + device.options], PORT_FD
3545 hidnplayr 779
        jz      @f
780
        or      eax, 0x10
781
  @@:
4532 hidnplayr 782
        test    [ebx + device.options], PORT_100
3545 hidnplayr 783
        jz      @f
784
        or      eax, 0x08
785
  @@:
4532 hidnplayr 786
        call    [ebx + device.write_bcr]
3545 hidnplayr 787
        jmp     .L9
788
  .L6:
4532 hidnplayr 789
        test    [ebx + device.options], PORT_ASEL
3545 hidnplayr 790
        jz      .L9
791
        mov     ecx, BCR_MIICTL
3855 hidnplayr 792
        DEBUGF  1,"ASEL, enable auto-negotiation\n"
4532 hidnplayr 793
        call    [ebx + device.read_bcr]
3545 hidnplayr 794
        and     eax, not 0x98
795
        or      eax, 0x20
4532 hidnplayr 796
        call    [ebx + device.write_bcr]
3545 hidnplayr 797
  .L9:
4532 hidnplayr 798
        cmp     [ebx + device.ltint], 0
3545 hidnplayr 799
        je      @f
800
        mov     ecx, 5
4532 hidnplayr 801
        call    [ebx + device.read_csr]
3545 hidnplayr 802
        or      eax, (1 shl 14)
4532 hidnplayr 803
        call    [ebx + device.write_csr]
3545 hidnplayr 804
  @@:
4532 hidnplayr 805
        mov     eax, [ebx + device.options]
3545 hidnplayr 806
        and     eax, PORT_PORTSEL
807
        shl     eax, 7
4532 hidnplayr 808
        mov     [ebx + device.mode], ax
809
        mov     dword [ebx + device.filter], -1
810
        mov     dword [ebx + device.filter+4], -1
3545 hidnplayr 811
 
812
 
813
 
814
;-----------------------------
815
 
4532 hidnplayr 816
        test    [ebx + device.mii], 1
3545 hidnplayr 817
        jz      .no_mii
818
 
4532 hidnplayr 819
        mov     [ebx + device.phy], 0
3545 hidnplayr 820
 
821
  .mii_loop:
822
        mov     ecx, MII_PHYSID1
823
        call    mdio_read
824
        cmp     ax, 0xffff
825
        je      .next
826
 
827
        DEBUGF  1, "0x%x\n", ax
828
 
829
        mov     ecx, MII_PHYSID2
830
        call    mdio_read
831
        cmp     ax, 0xffff
832
        je      .next
833
 
834
        DEBUGF  1, "0x%x\n", ax
835
 
836
        jmp     .got_phy
837
 
4532 hidnplayr 838
        cmp     [ebx + device.phy], 31
3545 hidnplayr 839
        jne     .next
4532 hidnplayr 840
        mov     ax, [ebx + device.chip_version]
3545 hidnplayr 841
        inc     ax
842
        and     ax, 0xfffe
843
        cmp     ax, 0x2624              ; 79c971 & 79c972 have phantom phy at id 31
844
        je      .got_phy
845
 
846
  .next:
4532 hidnplayr 847
        inc     [ebx + device.phy]
848
        cmp     [ebx + device.phy], MAX_PHYS
3545 hidnplayr 849
        jb      .mii_loop
850
 
3855 hidnplayr 851
        DEBUGF  2, "No PHY found!\n"
3545 hidnplayr 852
        or      eax, -1
853
        ret
854
 
855
  .got_phy:
4532 hidnplayr 856
        DEBUGF  1, "Found PHY at 0x%x\n", [ebx + device.phy]:4
3545 hidnplayr 857
 
858
  .no_mii:
859
 
860
;-----------------------------------------------
861
 
862
        call    read_mac
863
 
4532 hidnplayr 864
        lea     esi, [ebx + device.mac]
865
        lea     edi, [ebx + device.phys_addr]
3545 hidnplayr 866
        movsd
867
        movsw
868
 
869
        call    init_ring
5522 hidnplayr 870
        test    eax, eax
871
        jnz     .fail
3545 hidnplayr 872
 
4532 hidnplayr 873
        mov     edx, [ebx + device.io_addr]   ; init ring destroys edx
3545 hidnplayr 874
 
4532 hidnplayr 875
        lea     eax, [ebx + device.mode]
876
        invoke  GetPhysAddr
3545 hidnplayr 877
        push    eax
878
        and     eax, 0xffff
879
        mov     ecx, 1
4532 hidnplayr 880
        call    [ebx + device.write_csr]
3545 hidnplayr 881
        pop     eax
882
        shr     eax, 16
883
        mov     ecx, 2
4532 hidnplayr 884
        call    [ebx + device.write_csr]
3545 hidnplayr 885
 
886
        mov     ecx, 4
887
        mov     eax, 0x0915
4532 hidnplayr 888
        call    [ebx + device.write_csr]
3545 hidnplayr 889
 
890
; Set the interrupt mask
891
        mov     ecx, CSR_IMR
892
        mov     eax, IMR
4532 hidnplayr 893
        call    [ebx + device.write_csr]
3545 hidnplayr 894
 
895
; Initialise the device
896
        xor     ecx, ecx
897
        mov     eax, CSR_INIT
4532 hidnplayr 898
        call    [ebx + device.write_csr]
3545 hidnplayr 899
 
900
        mov     esi, 100
901
;        xor     ecx, ecx
902
  @@:
4532 hidnplayr 903
        call    [ebx + device.read_csr]
3545 hidnplayr 904
        test    ax, CSR_IDONE
905
        jnz     @f
906
 
907
        dec     esi
908
        jnz     @r
3855 hidnplayr 909
        DEBUGF  2,"Initialize timeout!\n"
3545 hidnplayr 910
  @@:
911
 
912
; Start the device and enable interrupts
913
        xor     ecx, ecx
914
        mov     eax, CSR_START + CSR_INTEN
4532 hidnplayr 915
        call    [ebx + device.write_csr]
3545 hidnplayr 916
 
917
; Set the mtu, kernel will be able to send now
4532 hidnplayr 918
        mov     [ebx + device.mtu], 1514
3545 hidnplayr 919
 
920
; get link status
4580 hidnplayr 921
        mov     [ebx + device.state], ETH_LINK_UNKNOWN
3545 hidnplayr 922
 
923
        call    check_media
924
 
3855 hidnplayr 925
        DEBUGF  1,"reset complete\n"
3545 hidnplayr 926
        xor     eax, eax
5522 hidnplayr 927
  .fail:
3545 hidnplayr 928
        ret
929
 
930
 
931
align 4
932
init_ring:
933
 
3855 hidnplayr 934
        DEBUGF  1,"init ring\n"
3545 hidnplayr 935
 
4532 hidnplayr 936
        lea     edi, [ebx + device.rx_ring]
3545 hidnplayr 937
        mov     eax, edi
4532 hidnplayr 938
        invoke  GetPhysAddr
939
        mov     [ebx + device.rx_ring_phys], eax
3545 hidnplayr 940
        mov     ecx, RX_RING_SIZE
941
  .rx_init:
942
        push    ecx
5522 hidnplayr 943
        invoke  NetAlloc, PKT_BUF_SZ+NET_BUFF.data
3545 hidnplayr 944
        pop     ecx
5522 hidnplayr 945
        test    eax, eax
946
        jz      .out_of_mem
3545 hidnplayr 947
        mov     [edi + descriptor.virtual], eax
4532 hidnplayr 948
        invoke  GetPhysAddr
5522 hidnplayr 949
        add     eax, NET_BUFF.data
3545 hidnplayr 950
        mov     [edi + descriptor.base], eax
951
        mov     [edi + descriptor.length], - PKT_BUF_SZ
952
        mov     [edi + descriptor.status], RXSTAT_OWN
4532 hidnplayr 953
        mov     dword[edi + descriptor.msg_length], 0    ; also clears misc field
954
        add     edi, sizeof.descriptor
3545 hidnplayr 955
        dec     ecx
956
        jnz     .rx_init
957
 
4532 hidnplayr 958
        lea     edi, [ebx + device.tx_ring]
3545 hidnplayr 959
        mov     eax, edi
4532 hidnplayr 960
        invoke  GetPhysAddr
961
        mov     [ebx + device.tx_ring_phys], eax
3545 hidnplayr 962
        mov     ecx, TX_RING_SIZE
963
  .tx_init:
964
        mov     [edi + descriptor.status], 0
4532 hidnplayr 965
        add     edi, sizeof.descriptor
3545 hidnplayr 966
        dec     ecx
967
        jnz     .tx_init
968
 
4532 hidnplayr 969
        mov     [ebx + device.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
3545 hidnplayr 970
 
4532 hidnplayr 971
        mov     [ebx + device.cur_tx], 0
972
        mov     [ebx + device.last_tx], 0
973
        mov     [ebx + device.cur_rx], 0
3545 hidnplayr 974
 
5522 hidnplayr 975
        xor     eax, eax
3545 hidnplayr 976
        ret
977
 
5522 hidnplayr 978
  .out_of_mem:
979
        DEBUGF  2,"Out of memory!\n"
3545 hidnplayr 980
 
5522 hidnplayr 981
        or      eax, -1
982
        ret
3545 hidnplayr 983
 
984
 
5522 hidnplayr 985
 
986
 
3545 hidnplayr 987
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
988
;;                                         ;;
989
;; Transmit                                ;;
990
;;                                         ;;
4532 hidnplayr 991
;; In: pointer to device structure in ebx  ;;
3545 hidnplayr 992
;;                                         ;;
993
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
994
 
5522 hidnplayr 995
proc transmit stdcall bufferptr
4532 hidnplayr 996
 
997
        pushf
998
        cli
999
 
5522 hidnplayr 1000
        mov     esi, [bufferptr]
1001
        DEBUGF  1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [esi + NET_BUFF.length]
1002
        lea     eax, [esi + NET_BUFF.data]
3545 hidnplayr 1003
        DEBUGF  1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
1004
        [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
1005
        [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
1006
        [eax+13]:2,[eax+12]:2
1007
 
5522 hidnplayr 1008
        cmp     [esi + NET_BUFF.length], 1514
4532 hidnplayr 1009
        ja      .fail
5522 hidnplayr 1010
        cmp     [esi + NET_BUFF.length], 60
4532 hidnplayr 1011
        jb      .fail
3545 hidnplayr 1012
 
1013
; check descriptor
4532 hidnplayr 1014
        lea     edi, [ebx + device.tx_ring]
5522 hidnplayr 1015
        movzx   ecx, [ebx + device.cur_tx]
1016
        shl     ecx, 4
1017
        add     edi, ecx
3545 hidnplayr 1018
 
1019
        test    [edi + descriptor.status], TXCTL_OWN
4532 hidnplayr 1020
        jnz     .fail
3545 hidnplayr 1021
; descriptor is free, use it
5522 hidnplayr 1022
        mov     [edi + descriptor.virtual], esi
1023
        mov     eax, esi
1024
        add     eax, [eax + NET_BUFF.offset]
4532 hidnplayr 1025
        invoke  GetPhysAddr
3545 hidnplayr 1026
        mov     [edi + descriptor.base], eax
1027
; set length
5522 hidnplayr 1028
        mov     eax, [esi + NET_BUFF.length]
3545 hidnplayr 1029
        neg     eax
1030
        mov     [edi + descriptor.length], ax
1031
; put to transfer queue
1032
        mov     [edi + descriptor.status], TXCTL_OWN + TXCTL_STP + TXCTL_ENP
1033
 
1034
; trigger an immediate send
4532 hidnplayr 1035
        mov     edx, [ebx + device.io_addr]
3545 hidnplayr 1036
        xor     ecx, ecx                        ; CSR0
4532 hidnplayr 1037
        call    [ebx + device.read_csr]
3545 hidnplayr 1038
        or      eax, CSR_TX
4532 hidnplayr 1039
        call    [ebx + device.write_csr]
3545 hidnplayr 1040
 
1041
; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ...
4532 hidnplayr 1042
        inc     [ebx + device.cur_tx]
1043
        and     [ebx + device.cur_tx], TX_RING_SIZE - 1
3545 hidnplayr 1044
 
1045
; Update stats
4532 hidnplayr 1046
        inc     [ebx + device.packets_tx]
5522 hidnplayr 1047
        mov     eax, [esi + NET_BUFF.length]
4532 hidnplayr 1048
        add     dword[ebx + device.bytes_tx], eax
1049
        adc     dword[ebx + device.bytes_tx + 4], 0
3545 hidnplayr 1050
 
1051
  .finish:
4532 hidnplayr 1052
        popf
3545 hidnplayr 1053
        xor     eax, eax
4532 hidnplayr 1054
        ret
3545 hidnplayr 1055
 
4532 hidnplayr 1056
  .fail:
1057
        DEBUGF  2, "Send failed\n"
5522 hidnplayr 1058
        invoke  NetFree, [bufferptr]
4532 hidnplayr 1059
        popf
3545 hidnplayr 1060
        or      eax, -1
4532 hidnplayr 1061
        ret
3545 hidnplayr 1062
 
4532 hidnplayr 1063
endp
3545 hidnplayr 1064
 
1065
 
1066
;;;;;;;;;;;;;;;;;;;;;;;
1067
;;                   ;;
1068
;; Interrupt handler ;;
1069
;;                   ;;
1070
;;;;;;;;;;;;;;;;;;;;;;;
1071
 
1072
align 4
1073
int_handler:
1074
 
1075
        push    ebx esi edi
1076
 
3855 hidnplayr 1077
        DEBUGF  1,"INT\n"
3545 hidnplayr 1078
 
1079
; find pointer of device wich made IRQ occur
1080
 
1081
        mov     ecx, [devices]
1082
        test    ecx, ecx
1083
        jz      .nothing
1084
        mov     esi, device_list
1085
  .nextdevice:
1086
        mov     ebx, [esi]
4532 hidnplayr 1087
        mov     edx, [ebx + device.io_addr]
3545 hidnplayr 1088
        push    ecx
1089
        xor     ecx, ecx                        ; CSR0
4532 hidnplayr 1090
        call    [ebx + device.read_csr]         ; get IRQ reason
1091
        call    [ebx + device.write_csr]        ; write it back to ACK
3545 hidnplayr 1092
        pop     ecx
5004 hidnplayr 1093
;;;        and     ax, CSR_RINT or CSR_TINT
1094
        test    ax, ax
3545 hidnplayr 1095
        jnz     .got_it
1096
  .continue:
1097
        add     esi, 4
1098
        dec     ecx
1099
        jnz     .nextdevice
1100
  .nothing:
1101
        pop     edi esi ebx
1102
        xor     eax, eax
1103
 
1104
        ret
1105
 
1106
  .got_it:
5065 hidnplayr 1107
        DEBUGF  1,"Device: %x status: %x\n", ebx, eax:4
3545 hidnplayr 1108
 
1109
        push    ax
1110
        test    ax, CSR_RINT
1111
        jz      .not_receive
1112
 
1113
        push    ebx
1114
  .rx_loop:
1115
        pop     ebx
4532 hidnplayr 1116
        movzx   eax, [ebx + device.cur_rx]
3545 hidnplayr 1117
        shl     eax, 4
4532 hidnplayr 1118
        lea     edi, [ebx + device.rx_ring]
3545 hidnplayr 1119
        add     edi, eax                        ; edi now points to current rx ring entry
1120
 
1121
        mov     ax, [edi + descriptor.status]
1122
        DEBUGF  1,"RX packet status: %x\n", eax:4
1123
 
1124
        test    ax, RXSTAT_OWN                  ; If this bit is set, the controller OWN's the packet, if not, we do
1125
        jnz     .not_receive
1126
 
1127
        test    ax, RXSTAT_ENP
1128
        jz      .not_receive
1129
 
1130
        test    ax, RXSTAT_STP
1131
        jz      .not_receive
1132
 
1133
        movzx   ecx, [edi + descriptor.msg_length]      ; get packet length in ecx
4532 hidnplayr 1134
        sub     ecx, 4                                  ; We dont need the CRC
1135
        DEBUGF  1,"Got %u bytes\n", ecx
3545 hidnplayr 1136
 
1137
; Set pointers for ETH_input
1138
        push    ebx
1139
 
1140
        push    .rx_loop                                ; return address
5522 hidnplayr 1141
        mov     eax, [edi + descriptor.virtual]
1142
        push    eax                                     ; packet address
1143
        mov     [eax + NET_BUFF.length], ecx
1144
        mov     [eax + NET_BUFF.device], ebx
1145
        mov     [eax + NET_BUFF.offset], NET_BUFF.data
3545 hidnplayr 1146
 
1147
; Update stats
4532 hidnplayr 1148
        add     dword[ebx + device.bytes_rx], ecx
1149
        adc     dword[ebx + device.bytes_rx + 4], 0
1150
        inc     [ebx + device.packets_rx]
3545 hidnplayr 1151
 
1152
; now allocate a new buffer
5522 hidnplayr 1153
        invoke  NetAlloc, PKT_BUF_SZ+NET_BUFF.data      ; Allocate a buffer for the next packet
1154
        test    eax, eax
1155
        jz      .out_of_mem
3545 hidnplayr 1156
        mov     [edi + descriptor.virtual], eax         ; set virtual address
4532 hidnplayr 1157
        invoke  GetPhysAddr
5522 hidnplayr 1158
        add     eax, NET_BUFF.data
4532 hidnplayr 1159
        mov     [edi + descriptor.base], eax            ; and physical address
3545 hidnplayr 1160
        mov     [edi + descriptor.status], RXSTAT_OWN   ; give it back to PCnet controller
1161
 
4532 hidnplayr 1162
        inc     [ebx + device.cur_rx]                   ; set next receive descriptor
1163
        and     [ebx + device.cur_rx], RX_RING_SIZE - 1
3545 hidnplayr 1164
 
5522 hidnplayr 1165
        jmp     [EthInput]
3545 hidnplayr 1166
 
5522 hidnplayr 1167
  .out_of_mem:
1168
        DEBUGF  2,"Out of memory!\n"
1169
 
1170
        inc     [ebx + device.cur_rx]                   ; set next receive descriptor
1171
        and     [ebx + device.cur_rx], RX_RING_SIZE - 1
1172
 
1173
        jmp     [EthInput]
1174
 
3545 hidnplayr 1175
  .not_receive:
1176
        pop     ax
1177
 
1178
        test    ax, CSR_TINT
1179
        jz      .not_transmit
1180
 
1181
  .tx_loop:
4532 hidnplayr 1182
        lea     edi, [ebx + device.tx_ring]
1183
        movzx   eax, [ebx + device.last_tx]
3545 hidnplayr 1184
        shl     eax, 4
1185
        add     edi, eax
1186
 
1187
        test    [edi + descriptor.status], TXCTL_OWN
1188
        jnz     .not_transmit
1189
 
1190
        mov     eax, [edi + descriptor.virtual]
1191
        test    eax, eax
1192
        jz      .not_transmit
1193
 
1194
        mov     [edi + descriptor.virtual], 0
1195
 
1196
        DEBUGF  1,"Removing packet %x from memory\n", eax
1197
 
5522 hidnplayr 1198
        invoke  NetFree, eax
3545 hidnplayr 1199
 
4532 hidnplayr 1200
        inc     [ebx + device.last_tx]
1201
        and     [ebx + device.last_tx], TX_RING_SIZE - 1
3545 hidnplayr 1202
        jmp     .tx_loop
1203
 
1204
  .not_transmit:
1205
        pop     edi esi ebx
1206
        xor     eax, eax
1207
        inc     eax
1208
 
1209
        ret
1210
 
1211
 
1212
 
1213
 
1214
;;;;;;;;;;;;;;;;;;;;;;;
1215
;;                   ;;
1216
;; Write MAC address ;;
1217
;;                   ;;
1218
;;;;;;;;;;;;;;;;;;;;;;;
1219
 
1220
align 4
1221
write_mac:      ; in: mac pushed onto stack (as 3 words)
1222
 
4532 hidnplayr 1223
        DEBUGF  1,"Writing MAC: %x-%x-%x-%x-%x-%x\n",\
1224
        [esp+0]:2,[esp+1]:2,[esp+2]:2,[esp+3]:2,[esp+4]:2,[esp+5]:2
3545 hidnplayr 1225
 
4532 hidnplayr 1226
        mov     edx, [ebx + device.io_addr]
3545 hidnplayr 1227
        add     dx, 2
1228
        xor     eax, eax
1229
 
1230
        mov     ecx, CSR_PAR0
1231
       @@:
1232
        pop     ax
4532 hidnplayr 1233
        call    [ebx + device.write_csr]
3545 hidnplayr 1234
        inc     ecx
1235
        cmp     ecx, CSR_PAR2
1236
        jb      @r
1237
 
1238
; Notice this procedure does not ret, but continues to read_mac instead.
1239
 
1240
;;;;;;;;;;;;;;;;;;;;;;
1241
;;                  ;;
1242
;; Read MAC address ;;
1243
;;                  ;;
1244
;;;;;;;;;;;;;;;;;;;;;;
1245
align 4
1246
read_mac:
4532 hidnplayr 1247
        DEBUGF  1,"Reading MAC\n"
3545 hidnplayr 1248
 
4532 hidnplayr 1249
        mov     edx, [ebx + device.io_addr]
1250
        lea     edi, [ebx + device.mac]
3545 hidnplayr 1251
        in      ax, dx
4532 hidnplayr 1252
        stosw
3545 hidnplayr 1253
 
4532 hidnplayr 1254
        inc     dx
1255
        inc     dx
1256
        in      ax, dx
1257
        stosw
3545 hidnplayr 1258
 
4532 hidnplayr 1259
        inc     dx
1260
        inc     dx
1261
        in      ax, dx
3545 hidnplayr 1262
        stosw
1263
 
4532 hidnplayr 1264
        DEBUGF  1,"MAC = %x-%x-%x-%x-%x-%x\n",\
1265
        [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,\
1266
        [ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
1267
 
3545 hidnplayr 1268
        ret
1269
 
1270
align 4
1271
switch_to_wio:
1272
 
1273
        DEBUGF  1,"Switching to 16-bit mode\n"
1274
 
4532 hidnplayr 1275
        mov     [ebx + device.read_csr], wio_read_csr
1276
        mov     [ebx + device.write_csr], wio_write_csr
1277
        mov     [ebx + device.read_bcr], wio_read_bcr
1278
        mov     [ebx + device.write_bcr], wio_write_bcr
1279
        mov     [ebx + device.read_rap], wio_read_rap
1280
        mov     [ebx + device.write_rap], wio_write_rap
1281
        mov     [ebx + device.sw_reset], wio_reset
3545 hidnplayr 1282
 
1283
        ret
1284
 
1285
align 4
1286
switch_to_dwio:
1287
 
1288
        DEBUGF  1,"Switching to 32-bit mode\n"
1289
 
4532 hidnplayr 1290
        mov     [ebx + device.read_csr], dwio_read_csr
1291
        mov     [ebx + device.write_csr], dwio_write_csr
1292
        mov     [ebx + device.read_bcr], dwio_read_bcr
1293
        mov     [ebx + device.write_bcr], dwio_write_bcr
1294
        mov     [ebx + device.read_rap], dwio_read_rap
1295
        mov     [ebx + device.write_rap], dwio_write_rap
1296
        mov     [ebx + device.sw_reset], dwio_reset
3545 hidnplayr 1297
 
1298
        ret
1299
 
1300
 
1301
; ecx - index
1302
; return:
1303
; eax - data
1304
align 4
1305
wio_read_csr:
1306
 
1307
        add     edx, WIO_RAP
1308
        mov     ax, cx
1309
        out     dx, ax
1310
        add     edx, WIO_RDP - WIO_RAP
1311
        in      ax, dx
1312
        and     eax, 0xffff
1313
        sub     edx, WIO_RDP
1314
 
1315
        ret
1316
 
1317
 
1318
; eax - data
1319
; ecx - index
1320
align 4
1321
wio_write_csr:
1322
 
1323
        add     edx, WIO_RAP
1324
        xchg    eax, ecx
1325
        out     dx, ax
1326
        xchg    eax, ecx
1327
        add     edx, WIO_RDP - WIO_RAP
1328
        out     dx, ax
1329
        sub     edx, WIO_RDP
1330
 
1331
        ret
1332
 
1333
 
1334
; ecx - index
1335
; return:
1336
; eax - data
1337
align 4
1338
wio_read_bcr:
1339
 
1340
        add     edx, WIO_RAP
1341
        mov     ax, cx
1342
        out     dx, ax
1343
        add     edx, WIO_BDP - WIO_RAP
1344
        in      ax, dx
1345
        and     eax, 0xffff
1346
        sub     edx, WIO_BDP
1347
 
1348
        ret
1349
 
1350
 
1351
; eax - data
1352
; ecx - index
1353
align 4
1354
wio_write_bcr:
1355
 
1356
        add     edx, WIO_RAP
1357
        xchg    eax, ecx
1358
        out     dx, ax
1359
        xchg    eax, ecx
1360
        add     edx, WIO_BDP - WIO_RAP
1361
        out     dx, ax
1362
        sub     edx, WIO_BDP
1363
 
1364
        ret
1365
 
1366
align 4
1367
wio_read_rap:
1368
 
1369
        add     edx, WIO_RAP
1370
        in      ax, dx
1371
        and     eax, 0xffff
1372
        sub     edx, WIO_RAP
1373
 
1374
        ret
1375
 
1376
; eax - val
1377
align 4
1378
wio_write_rap:
1379
 
1380
        add     edx, WIO_RAP
1381
        out     dx, ax
1382
        sub     edx, WIO_RAP
1383
 
1384
        ret
1385
 
1386
align 4
1387
wio_reset:
1388
 
1389
        push    eax
1390
        add     edx, WIO_RESET
1391
        in      ax, dx
1392
        pop     eax
1393
        sub     edx, WIO_RESET
1394
 
1395
        ret
1396
 
1397
 
1398
 
1399
; ecx - index
1400
; return:
1401
; eax - data
1402
align 4
1403
dwio_read_csr:
1404
 
1405
        add     edx, DWIO_RAP
1406
        mov     eax, ecx
1407
        out     dx, eax
1408
        add     edx, DWIO_RDP - DWIO_RAP
1409
        in      eax, dx
1410
        and     eax, 0xffff
1411
        sub     edx, DWIO_RDP
1412
 
1413
        ret
1414
 
1415
 
1416
; ecx - index
1417
; eax - data
1418
align 4
1419
dwio_write_csr:
1420
 
1421
        add     edx, DWIO_RAP
1422
        xchg    eax, ecx
1423
        out     dx, eax
1424
        add     edx, DWIO_RDP - DWIO_RAP
1425
        xchg    eax, ecx
1426
        out     dx, eax
1427
        sub     edx, DWIO_RDP
1428
 
1429
        ret
1430
 
1431
; ecx - index
1432
; return:
1433
; eax - data
1434
align 4
1435
dwio_read_bcr:
1436
 
1437
        add     edx, DWIO_RAP
1438
        mov     eax, ecx
1439
        out     dx, eax
1440
        add     edx, DWIO_BDP - DWIO_RAP
1441
        in      eax, dx
1442
        and     eax, 0xffff
1443
        sub     edx, DWIO_BDP
1444
 
1445
        ret
1446
 
1447
 
1448
; ecx - index
1449
; eax - data
1450
align 4
1451
dwio_write_bcr:
1452
 
1453
        add     edx, DWIO_RAP
1454
        xchg    eax, ecx
1455
        out     dx, eax
1456
        add     edx, DWIO_BDP - DWIO_RAP
1457
        xchg    eax, ecx
1458
        out     dx, eax
1459
        sub     edx, DWIO_BDP
1460
 
1461
        ret
1462
 
1463
align 4
1464
dwio_read_rap:
1465
 
1466
        add     edx, DWIO_RAP
1467
        in      eax, dx
1468
        and     eax, 0xffff
1469
        sub     edx, DWIO_RAP
1470
 
1471
        ret
1472
 
1473
 
1474
; eax - val
1475
align 4
1476
dwio_write_rap:
1477
 
1478
        add     edx, DWIO_RAP
1479
        out     dx, eax
1480
        sub     edx, DWIO_RAP
1481
 
1482
        ret
1483
 
1484
align 4
1485
dwio_reset:
1486
 
1487
        push    eax
1488
        add     edx, DWIO_RESET
1489
        in      eax, dx
1490
        pop     eax
1491
        sub     edx, DWIO_RESET
1492
 
1493
        ret
1494
 
1495
 
1496
align 4
1497
mdio_read:
1498
 
1499
        and     ecx, 0x1f
4532 hidnplayr 1500
        mov     ax, [ebx + device.phy]
3545 hidnplayr 1501
        and     ax, 0x1f
1502
        shl     ax, 5
1503
        or      ax, cx
1504
 
1505
        mov     ecx, BCR_MIIADDR
4532 hidnplayr 1506
        call    [ebx + device.write_bcr]
3545 hidnplayr 1507
 
1508
        mov     ecx, BCR_MIIDATA
4532 hidnplayr 1509
        call    [ebx + device.read_bcr]
3545 hidnplayr 1510
 
1511
        ret
1512
 
1513
 
1514
align 4
1515
mdio_write:
1516
 
1517
        push    eax
1518
        and     ecx, 0x1f
4532 hidnplayr 1519
        mov     ax, [ebx + device.phy]
3545 hidnplayr 1520
        and     ax, 0x1f
1521
        shl     ax, 5
1522
        or      ax, cx
1523
 
1524
        mov     ecx, BCR_MIIADDR
4532 hidnplayr 1525
        call    [ebx + device.write_bcr]
3545 hidnplayr 1526
 
1527
        pop     eax
1528
        mov     ecx, BCR_MIIDATA
4532 hidnplayr 1529
        call    [ebx + device.write_bcr]
3545 hidnplayr 1530
 
1531
        ret
1532
 
1533
 
1534
align 4
1535
check_media:
1536
 
1537
        DEBUGF  1, "check_media\n"
1538
 
4532 hidnplayr 1539
        test    [ebx + device.mii], 1
3855 hidnplayr 1540
        jnz     mii_link_ok
3545 hidnplayr 1541
 
1542
        mov     ecx, BCR_LED0
4532 hidnplayr 1543
        call    [ebx + device.read_bcr]
3545 hidnplayr 1544
        cmp     eax, 0xc0
1545
 
5004 hidnplayr 1546
        DEBUGF  2, "link status=0x%x\n", ax
3545 hidnplayr 1547
 
1548
        ret
1549
 
1550
 
1551
 
1552
; End of code
1553
 
1554
 
4532 hidnplayr 1555
data fixups
1556
end data
3545 hidnplayr 1557
 
4532 hidnplayr 1558
include '../peimport.inc'
1559
 
4629 hidnplayr 1560
my_service    db 'PCNET32',0            ; max 16 chars include zero
4532 hidnplayr 1561
 
3545 hidnplayr 1562
device_l2     db "PCnet/PCI 79C970",0
1563
device_l4     db "PCnet/PCI II 79C970A",0
1564
device_l5     db "PCnet/FAST 79C971",0
1565
device_l6     db "PCnet/FAST+ 79C972",0
1566
device_l7     db "PCnet/FAST III 79C973",0
1567
device_l8     db "PCnet/Home 79C978",0
1568
device_l9     db "PCnet/FAST III 79C975",0
1569
 
1570
options_mapping:
1571
dd PORT_ASEL                            ; 0 Auto-select
1572
dd PORT_AUI                             ; 1 BNC/AUI
1573
dd PORT_AUI                             ; 2 AUI/BNC
1574
dd PORT_ASEL                            ; 3 not supported
1575
dd PORT_10BT or PORT_FD                 ; 4 10baseT-FD
1576
dd PORT_ASEL                            ; 5 not supported
1577
dd PORT_ASEL                            ; 6 not supported
1578
dd PORT_ASEL                            ; 7 not supported
1579
dd PORT_ASEL                            ; 8 not supported
1580
dd PORT_MII                             ; 9 MII 10baseT
1581
dd PORT_MII or PORT_FD                  ; 10 MII 10baseT-FD
1582
dd PORT_MII                             ; 11 MII (autosel)
1583
dd PORT_10BT                            ; 12 10BaseT
1584
dd PORT_MII or PORT_100                 ; 13 MII 100BaseTx
1585
dd PORT_MII or PORT_100 or PORT_FD      ; 14 MII 100BaseTx-FD
1586
dd PORT_ASEL                            ; 15 not supported
1587
 
1588
include_debug_strings                                   ; All data wich FDO uses will be included here
1589
 
1590
 
4532 hidnplayr 1591
align 4
1592
devices     dd 0
3545 hidnplayr 1593
device_list rd MAX_DEVICES                              ; This list contains all pointers to device structures the driver is handling