WebSVN – Kolibri OS – Blame – /drivers/ethernet/i8254x.asm

Rev	Author	Line No.	Line
3545	hidnplayr	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
7250	hidnplayr	3	;; Copyright (C) KolibriOS team 2004-2018. All rights reserved. ;;
3545	hidnplayr	4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;; i8254x driver for KolibriOS ;;
		7	;; ;;
		8	;; based on i8254x.asm from baremetal os ;;
		9	;; ;;
		10	;; Written by hidnplayr (hidnplayr@gmail.com) ;;
		11	;; ;;
		12	;; GNU GENERAL PUBLIC LICENSE ;;
		13	;; Version 2, June 1991 ;;
		14	;; ;;
		15	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		16
4522	hidnplayr	17	format PE DLL native
		18	entry START
3545	hidnplayr	19
4522	hidnplayr	20	CURRENT_API = 0x0200
		21	COMPATIBLE_API = 0x0100
		22	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
3545	hidnplayr	23
		24	MAX_DEVICES = 16
		25
		26	__DEBUG__ = 1
3855	hidnplayr	27	__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only
3545	hidnplayr	28
5527	hidnplayr	29	MAX_PKT_SIZE = 1514 ; Maximum packet size
3545	hidnplayr	30
4519	hidnplayr	31	RX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8
		32	TX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8
4512	hidnplayr	33
4522	hidnplayr	34	section '.flat' readable writable executable
		35
		36	include '../proc32.inc'
4467	hidnplayr	37	include '../struct.inc'
		38	include '../macros.inc'
3545	hidnplayr	39	include '../fdo.inc'
5074	hidnplayr	40	include '../netdrv.inc'
3545	hidnplayr	41
		42	; Register list
		43	REG_CTRL = 0x0000 ; Control Register
		44	REG_STATUS = 0x0008 ; Device Status Register
		45	REG_CTRLEXT = 0x0018 ; Extended Control Register
		46	REG_MDIC = 0x0020 ; MDI Control Register
		47	REG_FCAL = 0x0028 ; Flow Control Address Low
		48	REG_FCAH = 0x002C ; Flow Control Address High
		49	REG_FCT = 0x0030 ; Flow Control Type
		50	REG_VET = 0x0038 ; VLAN Ether Type
		51	REG_ICR = 0x00C0 ; Interrupt Cause Read
		52	REG_ITR = 0x00C4 ; Interrupt Throttling Register
		53	REG_ICS = 0x00C8 ; Interrupt Cause Set Register
		54	REG_IMS = 0x00D0 ; Interrupt Mask Set/Read Register
		55	REG_IMC = 0x00D8 ; Interrupt Mask Clear Register
		56	REG_RCTL = 0x0100 ; Receive Control Register
		57	REG_FCTTV = 0x0170 ; Flow Control Transmit Timer Value
		58	REG_TXCW = 0x0178 ; Transmit Configuration Word
		59	REG_RXCW = 0x0180 ; Receive Configuration Word
		60	REG_TCTL = 0x0400 ; Transmit Control Register
		61	REG_TIPG = 0x0410 ; Transmit Inter Packet Gap
		62
		63	REG_LEDCTL = 0x0E00 ; LED Control
		64	REG_PBA = 0x1000 ; Packet Buffer Allocation
		65
		66	REG_RDBAL = 0x2800 ; RX Descriptor Base Address Low
		67	REG_RDBAH = 0x2804 ; RX Descriptor Base Address High
		68	REG_RDLEN = 0x2808 ; RX Descriptor Length
		69	REG_RDH = 0x2810 ; RX Descriptor Head
		70	REG_RDT = 0x2818 ; RX Descriptor Tail
		71	REG_RDTR = 0x2820 ; RX Delay Timer Register
		72	REG_RXDCTL = 0x3828 ; RX Descriptor Control
		73	REG_RADV = 0x282C ; RX Int. Absolute Delay Timer
		74	REG_RSRPD = 0x2C00 ; RX Small Packet Detect Interrupt
		75
		76	REG_TXDMAC = 0x3000 ; TX DMA Control
		77	REG_TDBAL = 0x3800 ; TX Descriptor Base Address Low
		78	REG_TDBAH = 0x3804 ; TX Descriptor Base Address High
		79	REG_TDLEN = 0x3808 ; TX Descriptor Length
		80	REG_TDH = 0x3810 ; TX Descriptor Head
		81	REG_TDT = 0x3818 ; TX Descriptor Tail
		82	REG_TIDV = 0x3820 ; TX Interrupt Delay Value
		83	REG_TXDCTL = 0x3828 ; TX Descriptor Control
		84	REG_TADV = 0x382C ; TX Absolute Interrupt Delay Value
		85	REG_TSPMT = 0x3830 ; TCP Segmentation Pad & Min Threshold
		86
		87	REG_RXCSUM = 0x5000 ; RX Checksum Control
		88
		89	; Register list for i8254x
		90	I82542_REG_RDTR = 0x0108 ; RX Delay Timer Register
		91	I82542_REG_RDBAL = 0x0110 ; RX Descriptor Base Address Low
		92	I82542_REG_RDBAH = 0x0114 ; RX Descriptor Base Address High
		93	I82542_REG_RDLEN = 0x0118 ; RX Descriptor Length
		94	I82542_REG_RDH = 0x0120 ; RDH for i82542
		95	I82542_REG_RDT = 0x0128 ; RDT for i82542
		96	I82542_REG_TDBAL = 0x0420 ; TX Descriptor Base Address Low
		97	I82542_REG_TDBAH = 0x0424 ; TX Descriptor Base Address Low
		98	I82542_REG_TDLEN = 0x0428 ; TX Descriptor Length
		99	I82542_REG_TDH = 0x0430 ; TDH for i82542
		100	I82542_REG_TDT = 0x0438 ; TDT for i82542
		101
		102	; CTRL - Control Register (0x0000)
		103	CTRL_FD = 0x00000001 ; Full Duplex
		104	CTRL_LRST = 0x00000008 ; Link Reset
		105	CTRL_ASDE = 0x00000020 ; Auto-speed detection
		106	CTRL_SLU = 0x00000040 ; Set Link Up
		107	CTRL_ILOS = 0x00000080 ; Invert Loss of Signal
		108	CTRL_SPEED_MASK = 0x00000300 ; Speed selection
		109	CTRL_SPEED_SHIFT = 8
		110	CTRL_FRCSPD = 0x00000800 ; Force Speed
		111	CTRL_FRCDPLX = 0x00001000 ; Force Duplex
		112	CTRL_SDP0_DATA = 0x00040000 ; SDP0 data
		113	CTRL_SDP1_DATA = 0x00080000 ; SDP1 data
		114	CTRL_SDP0_IODIR = 0x00400000 ; SDP0 direction
		115	CTRL_SDP1_IODIR = 0x00800000 ; SDP1 direction
		116	CTRL_RST = 0x04000000 ; Device Reset
		117	CTRL_RFCE = 0x08000000 ; RX Flow Ctrl Enable
		118	CTRL_TFCE = 0x10000000 ; TX Flow Ctrl Enable
		119	CTRL_VME = 0x40000000 ; VLAN Mode Enable
		120	CTRL_PHY_RST = 0x80000000 ; PHY reset
		121
		122	; STATUS - Device Status Register (0x0008)
		123	STATUS_FD = 0x00000001 ; Full Duplex
		124	STATUS_LU = 0x00000002 ; Link Up
		125	STATUS_TXOFF = 0x00000010 ; Transmit paused
		126	STATUS_TBIMODE = 0x00000020 ; TBI Mode
		127	STATUS_SPEED_MASK = 0x000000C0 ; Link Speed setting
		128	STATUS_SPEED_SHIFT = 6
		129	STATUS_ASDV_MASK = 0x00000300 ; Auto Speed Detection
		130	STATUS_ASDV_SHIFT = 8
		131	STATUS_PCI66 = 0x00000800 ; PCI bus speed
		132	STATUS_BUS64 = 0x00001000 ; PCI bus width
		133	STATUS_PCIX_MODE = 0x00002000 ; PCI-X mode
		134	STATUS_PCIXSPD_MASK = 0x0000C000 ; PCI-X speed
		135	STATUS_PCIXSPD_SHIFT = 14
		136
		137	; CTRL_EXT - Extended Device Control Register (0x0018)
		138	CTRLEXT_PHY_INT = 0x00000020 ; PHY interrupt
		139	CTRLEXT_SDP6_DATA = 0x00000040 ; SDP6 data
		140	CTRLEXT_SDP7_DATA = 0x00000080 ; SDP7 data
		141	CTRLEXT_SDP6_IODIR = 0x00000400 ; SDP6 direction
		142	CTRLEXT_SDP7_IODIR = 0x00000800 ; SDP7 direction
		143	CTRLEXT_ASDCHK = 0x00001000 ; Auto-Speed Detect Chk
		144	CTRLEXT_EE_RST = 0x00002000 ; EEPROM reset
		145	CTRLEXT_SPD_BYPS = 0x00008000 ; Speed Select Bypass
		146	CTRLEXT_RO_DIS = 0x00020000 ; Relaxed Ordering Dis.
		147	CTRLEXT_LNKMOD_MASK = 0x00C00000 ; Link Mode
		148	CTRLEXT_LNKMOD_SHIFT = 22
		149
		150	; MDIC - MDI Control Register (0x0020)
		151	MDIC_DATA_MASK = 0x0000FFFF ; Data
		152	MDIC_REG_MASK = 0x001F0000 ; PHY Register
		153	MDIC_REG_SHIFT = 16
		154	MDIC_PHY_MASK = 0x03E00000 ; PHY Address
		155	MDIC_PHY_SHIFT = 21
		156	MDIC_OP_MASK = 0x0C000000 ; Opcode
		157	MDIC_OP_SHIFT = 26
		158	MDIC_R = 0x10000000 ; Ready
		159	MDIC_I = 0x20000000 ; Interrupt Enable
		160	MDIC_E = 0x40000000 ; Error
		161
		162	; ICR - Interrupt Cause Read (0x00c0)
		163	ICR_TXDW = 0x00000001 ; TX Desc Written back
		164	ICR_TXQE = 0x00000002 ; TX Queue Empty
		165	ICR_LSC = 0x00000004 ; Link Status Change
		166	ICR_RXSEQ = 0x00000008 ; RX Sence Error
		167	ICR_RXDMT0 = 0x00000010 ; RX Desc min threshold reached
		168	ICR_RXO = 0x00000040 ; RX Overrun
		169	ICR_RXT0 = 0x00000080 ; RX Timer Interrupt
		170	ICR_MDAC = 0x00000200 ; MDIO Access Complete
		171	ICR_RXCFG = 0x00000400
		172	ICR_PHY_INT = 0x00001000 ; PHY Interrupt
		173	ICR_GPI_SDP6 = 0x00002000 ; GPI on SDP6
		174	ICR_GPI_SDP7 = 0x00004000 ; GPI on SDP7
		175	ICR_TXD_LOW = 0x00008000 ; TX Desc low threshold hit
		176	ICR_SRPD = 0x00010000 ; Small RX packet detected
		177
		178	; RCTL - Receive Control Register (0x0100)
		179	RCTL_EN = 0x00000002 ; Receiver Enable
		180	RCTL_SBP = 0x00000004 ; Store Bad Packets
		181	RCTL_UPE = 0x00000008 ; Unicast Promiscuous Enabled
		182	RCTL_MPE = 0x00000010 ; Xcast Promiscuous Enabled
		183	RCTL_LPE = 0x00000020 ; Long Packet Reception Enable
		184	RCTL_LBM_MASK = 0x000000C0 ; Loopback Mode
		185	RCTL_LBM_SHIFT = 6
		186	RCTL_RDMTS_MASK = 0x00000300 ; RX Desc Min Threshold Size
		187	RCTL_RDMTS_SHIFT = 8
		188	RCTL_MO_MASK = 0x00003000 ; Multicast Offset
		189	RCTL_MO_SHIFT = 12
		190	RCTL_BAM = 0x00008000 ; Broadcast Accept Mode
		191	RCTL_BSIZE_MASK = 0x00030000 ; RX Buffer Size
		192	RCTL_BSIZE_SHIFT = 16
		193	RCTL_VFE = 0x00040000 ; VLAN Filter Enable
		194	RCTL_CFIEN = 0x00080000 ; CFI Enable
		195	RCTL_CFI = 0x00100000 ; Canonical Form Indicator Bit
		196	RCTL_DPF = 0x00400000 ; Discard Pause Frames
		197	RCTL_PMCF = 0x00800000 ; Pass MAC Control Frames
		198	RCTL_BSEX = 0x02000000 ; Buffer Size Extension
		199	RCTL_SECRC = 0x04000000 ; Strip Ethernet CRC
		200
		201	; TCTL - Transmit Control Register (0x0400)
		202	TCTL_EN = 0x00000002 ; Transmit Enable
		203	TCTL_PSP = 0x00000008 ; Pad short packets
		204	TCTL_SWXOFF = 0x00400000 ; Software XOFF Transmission
		205
		206	; PBA - Packet Buffer Allocation (0x1000)
		207	PBA_RXA_MASK = 0x0000FFFF ; RX Packet Buffer
		208	PBA_RXA_SHIFT = 0
		209	PBA_TXA_MASK = 0xFFFF0000 ; TX Packet Buffer
		210	PBA_TXA_SHIFT = 16
		211
		212	; Flow Control Type
		213	FCT_TYPE_DEFAULT = 0x8808
		214
		215
4519	hidnplayr	216
		217	; === TX Descriptor ===
		218
		219	struct TDESC
		220	addr_l dd ?
		221	addr_h dd ?
		222	length_cso_cmd dd ? ; 16 bits length + 8 bits cso + 8 bits cmd
		223	status dd ? ; status, checksum start field, special
		224	ends
		225
3545	hidnplayr	226	; TX Packet Length (word 2)
		227	TXDESC_LEN_MASK = 0x0000ffff
		228
		229	; TX Descriptor CMD field (word 2)
		230	TXDESC_IDE = 0x80000000 ; Interrupt Delay Enable
		231	TXDESC_VLE = 0x40000000 ; VLAN Packet Enable
		232	TXDESC_DEXT = 0x20000000 ; Extension
		233	TXDESC_RPS = 0x10000000 ; Report Packet Sent
		234	TXDESC_RS = 0x08000000 ; Report Status
		235	TXDESC_IC = 0x04000000 ; Insert Checksum
		236	TXDESC_IFCS = 0x02000000 ; Insert FCS

Subversion Repositories Kolibri OS

(root)/drivers/ethernet/i8254x.asm – Rev 7522