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Rev | Author | Line No. | Line |
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3545 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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4467 | hidnplayr | 3 | ;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;; |
3545 | hidnplayr | 4 | ;; Distributed under terms of the GNU General Public License ;; |
5 | ;; ;; |
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6 | ;; i8254x driver for KolibriOS ;; |
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7 | ;; ;; |
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8 | ;; based on i8254x.asm from baremetal os ;; |
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9 | ;; ;; |
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10 | ;; Written by hidnplayr (hidnplayr@gmail.com) ;; |
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11 | ;; ;; |
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12 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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13 | ;; Version 2, June 1991 ;; |
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14 | ;; ;; |
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15 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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16 | |||
17 | ; TODO: make better use of the available descriptors |
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18 | |||
19 | format MS COFF |
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20 | |||
21 | API_VERSION = 0x01000100 |
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22 | DRIVER_VERSION = 5 |
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23 | |||
24 | MAX_DEVICES = 16 |
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25 | |||
26 | DEBUG = 1 |
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27 | __DEBUG__ = 1 |
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3855 | hidnplayr | 28 | __DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only |
3545 | hidnplayr | 29 | |
4512 | hidnplayr | 30 | MAX_PKT_SIZE = 4096 ; Maximum packet size |
3545 | hidnplayr | 31 | |
4512 | hidnplayr | 32 | RX_RING_SIZE = 8 ; Must be a multiple of 8 |
33 | |||
4467 | hidnplayr | 34 | include '../struct.inc' |
35 | include '../macros.inc' |
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3545 | hidnplayr | 36 | include '../proc32.inc' |
37 | include '../imports.inc' |
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38 | include '../fdo.inc' |
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39 | include '../netdrv.inc' |
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40 | |||
41 | public START |
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42 | public service_proc |
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43 | public version |
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44 | |||
45 | |||
46 | |||
47 | ; Register list |
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48 | REG_CTRL = 0x0000 ; Control Register |
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49 | REG_STATUS = 0x0008 ; Device Status Register |
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50 | REG_CTRLEXT = 0x0018 ; Extended Control Register |
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51 | REG_MDIC = 0x0020 ; MDI Control Register |
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52 | REG_FCAL = 0x0028 ; Flow Control Address Low |
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53 | REG_FCAH = 0x002C ; Flow Control Address High |
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54 | REG_FCT = 0x0030 ; Flow Control Type |
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55 | REG_VET = 0x0038 ; VLAN Ether Type |
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56 | REG_ICR = 0x00C0 ; Interrupt Cause Read |
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57 | REG_ITR = 0x00C4 ; Interrupt Throttling Register |
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58 | REG_ICS = 0x00C8 ; Interrupt Cause Set Register |
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59 | REG_IMS = 0x00D0 ; Interrupt Mask Set/Read Register |
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60 | REG_IMC = 0x00D8 ; Interrupt Mask Clear Register |
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61 | REG_RCTL = 0x0100 ; Receive Control Register |
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62 | REG_FCTTV = 0x0170 ; Flow Control Transmit Timer Value |
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63 | REG_TXCW = 0x0178 ; Transmit Configuration Word |
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64 | REG_RXCW = 0x0180 ; Receive Configuration Word |
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65 | REG_TCTL = 0x0400 ; Transmit Control Register |
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66 | REG_TIPG = 0x0410 ; Transmit Inter Packet Gap |
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67 | |||
68 | REG_LEDCTL = 0x0E00 ; LED Control |
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69 | REG_PBA = 0x1000 ; Packet Buffer Allocation |
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70 | |||
71 | REG_RDBAL = 0x2800 ; RX Descriptor Base Address Low |
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72 | REG_RDBAH = 0x2804 ; RX Descriptor Base Address High |
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73 | REG_RDLEN = 0x2808 ; RX Descriptor Length |
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74 | REG_RDH = 0x2810 ; RX Descriptor Head |
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75 | REG_RDT = 0x2818 ; RX Descriptor Tail |
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76 | REG_RDTR = 0x2820 ; RX Delay Timer Register |
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77 | REG_RXDCTL = 0x3828 ; RX Descriptor Control |
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78 | REG_RADV = 0x282C ; RX Int. Absolute Delay Timer |
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79 | REG_RSRPD = 0x2C00 ; RX Small Packet Detect Interrupt |
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80 | |||
81 | REG_TXDMAC = 0x3000 ; TX DMA Control |
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82 | REG_TDBAL = 0x3800 ; TX Descriptor Base Address Low |
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83 | REG_TDBAH = 0x3804 ; TX Descriptor Base Address High |
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84 | REG_TDLEN = 0x3808 ; TX Descriptor Length |
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85 | REG_TDH = 0x3810 ; TX Descriptor Head |
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86 | REG_TDT = 0x3818 ; TX Descriptor Tail |
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87 | REG_TIDV = 0x3820 ; TX Interrupt Delay Value |
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88 | REG_TXDCTL = 0x3828 ; TX Descriptor Control |
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89 | REG_TADV = 0x382C ; TX Absolute Interrupt Delay Value |
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90 | REG_TSPMT = 0x3830 ; TCP Segmentation Pad & Min Threshold |
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91 | |||
92 | REG_RXCSUM = 0x5000 ; RX Checksum Control |
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93 | |||
94 | ; Register list for i8254x |
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95 | I82542_REG_RDTR = 0x0108 ; RX Delay Timer Register |
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96 | I82542_REG_RDBAL = 0x0110 ; RX Descriptor Base Address Low |
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97 | I82542_REG_RDBAH = 0x0114 ; RX Descriptor Base Address High |
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98 | I82542_REG_RDLEN = 0x0118 ; RX Descriptor Length |
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99 | I82542_REG_RDH = 0x0120 ; RDH for i82542 |
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100 | I82542_REG_RDT = 0x0128 ; RDT for i82542 |
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101 | I82542_REG_TDBAL = 0x0420 ; TX Descriptor Base Address Low |
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102 | I82542_REG_TDBAH = 0x0424 ; TX Descriptor Base Address Low |
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103 | I82542_REG_TDLEN = 0x0428 ; TX Descriptor Length |
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104 | I82542_REG_TDH = 0x0430 ; TDH for i82542 |
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105 | I82542_REG_TDT = 0x0438 ; TDT for i82542 |
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106 | |||
107 | ; CTRL - Control Register (0x0000) |
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108 | CTRL_FD = 0x00000001 ; Full Duplex |
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109 | CTRL_LRST = 0x00000008 ; Link Reset |
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110 | CTRL_ASDE = 0x00000020 ; Auto-speed detection |
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111 | CTRL_SLU = 0x00000040 ; Set Link Up |
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112 | CTRL_ILOS = 0x00000080 ; Invert Loss of Signal |
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113 | CTRL_SPEED_MASK = 0x00000300 ; Speed selection |
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114 | CTRL_SPEED_SHIFT = 8 |
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115 | CTRL_FRCSPD = 0x00000800 ; Force Speed |
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116 | CTRL_FRCDPLX = 0x00001000 ; Force Duplex |
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117 | CTRL_SDP0_DATA = 0x00040000 ; SDP0 data |
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118 | CTRL_SDP1_DATA = 0x00080000 ; SDP1 data |
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119 | CTRL_SDP0_IODIR = 0x00400000 ; SDP0 direction |
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120 | CTRL_SDP1_IODIR = 0x00800000 ; SDP1 direction |
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121 | CTRL_RST = 0x04000000 ; Device Reset |
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122 | CTRL_RFCE = 0x08000000 ; RX Flow Ctrl Enable |
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123 | CTRL_TFCE = 0x10000000 ; TX Flow Ctrl Enable |
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124 | CTRL_VME = 0x40000000 ; VLAN Mode Enable |
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125 | CTRL_PHY_RST = 0x80000000 ; PHY reset |
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126 | |||
127 | ; STATUS - Device Status Register (0x0008) |
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128 | STATUS_FD = 0x00000001 ; Full Duplex |
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129 | STATUS_LU = 0x00000002 ; Link Up |
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130 | STATUS_TXOFF = 0x00000010 ; Transmit paused |
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131 | STATUS_TBIMODE = 0x00000020 ; TBI Mode |
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132 | STATUS_SPEED_MASK = 0x000000C0 ; Link Speed setting |
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133 | STATUS_SPEED_SHIFT = 6 |
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134 | STATUS_ASDV_MASK = 0x00000300 ; Auto Speed Detection |
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135 | STATUS_ASDV_SHIFT = 8 |
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136 | STATUS_PCI66 = 0x00000800 ; PCI bus speed |
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137 | STATUS_BUS64 = 0x00001000 ; PCI bus width |
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138 | STATUS_PCIX_MODE = 0x00002000 ; PCI-X mode |
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139 | STATUS_PCIXSPD_MASK = 0x0000C000 ; PCI-X speed |
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140 | STATUS_PCIXSPD_SHIFT = 14 |
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141 | |||
142 | ; CTRL_EXT - Extended Device Control Register (0x0018) |
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143 | CTRLEXT_PHY_INT = 0x00000020 ; PHY interrupt |
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144 | CTRLEXT_SDP6_DATA = 0x00000040 ; SDP6 data |
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145 | CTRLEXT_SDP7_DATA = 0x00000080 ; SDP7 data |
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146 | CTRLEXT_SDP6_IODIR = 0x00000400 ; SDP6 direction |
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147 | CTRLEXT_SDP7_IODIR = 0x00000800 ; SDP7 direction |
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148 | CTRLEXT_ASDCHK = 0x00001000 ; Auto-Speed Detect Chk |
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149 | CTRLEXT_EE_RST = 0x00002000 ; EEPROM reset |
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150 | CTRLEXT_SPD_BYPS = 0x00008000 ; Speed Select Bypass |
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151 | CTRLEXT_RO_DIS = 0x00020000 ; Relaxed Ordering Dis. |
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152 | CTRLEXT_LNKMOD_MASK = 0x00C00000 ; Link Mode |
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153 | CTRLEXT_LNKMOD_SHIFT = 22 |
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154 | |||
155 | ; MDIC - MDI Control Register (0x0020) |
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156 | MDIC_DATA_MASK = 0x0000FFFF ; Data |
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157 | MDIC_REG_MASK = 0x001F0000 ; PHY Register |
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158 | MDIC_REG_SHIFT = 16 |
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159 | MDIC_PHY_MASK = 0x03E00000 ; PHY Address |
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160 | MDIC_PHY_SHIFT = 21 |
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161 | MDIC_OP_MASK = 0x0C000000 ; Opcode |
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162 | MDIC_OP_SHIFT = 26 |
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163 | MDIC_R = 0x10000000 ; Ready |
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164 | MDIC_I = 0x20000000 ; Interrupt Enable |
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165 | MDIC_E = 0x40000000 ; Error |
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166 | |||
167 | ; ICR - Interrupt Cause Read (0x00c0) |
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168 | ICR_TXDW = 0x00000001 ; TX Desc Written back |
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169 | ICR_TXQE = 0x00000002 ; TX Queue Empty |
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170 | ICR_LSC = 0x00000004 ; Link Status Change |
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171 | ICR_RXSEQ = 0x00000008 ; RX Sence Error |
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172 | ICR_RXDMT0 = 0x00000010 ; RX Desc min threshold reached |
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173 | ICR_RXO = 0x00000040 ; RX Overrun |
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174 | ICR_RXT0 = 0x00000080 ; RX Timer Interrupt |
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175 | ICR_MDAC = 0x00000200 ; MDIO Access Complete |
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176 | ICR_RXCFG = 0x00000400 |
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177 | ICR_PHY_INT = 0x00001000 ; PHY Interrupt |
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178 | ICR_GPI_SDP6 = 0x00002000 ; GPI on SDP6 |
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179 | ICR_GPI_SDP7 = 0x00004000 ; GPI on SDP7 |
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180 | ICR_TXD_LOW = 0x00008000 ; TX Desc low threshold hit |
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181 | ICR_SRPD = 0x00010000 ; Small RX packet detected |
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182 | |||
183 | ; RCTL - Receive Control Register (0x0100) |
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184 | RCTL_EN = 0x00000002 ; Receiver Enable |
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185 | RCTL_SBP = 0x00000004 ; Store Bad Packets |
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186 | RCTL_UPE = 0x00000008 ; Unicast Promiscuous Enabled |
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187 | RCTL_MPE = 0x00000010 ; Xcast Promiscuous Enabled |
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188 | RCTL_LPE = 0x00000020 ; Long Packet Reception Enable |
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189 | RCTL_LBM_MASK = 0x000000C0 ; Loopback Mode |
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190 | RCTL_LBM_SHIFT = 6 |
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191 | RCTL_RDMTS_MASK = 0x00000300 ; RX Desc Min Threshold Size |
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192 | RCTL_RDMTS_SHIFT = 8 |
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193 | RCTL_MO_MASK = 0x00003000 ; Multicast Offset |
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194 | RCTL_MO_SHIFT = 12 |
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195 | RCTL_BAM = 0x00008000 ; Broadcast Accept Mode |
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196 | RCTL_BSIZE_MASK = 0x00030000 ; RX Buffer Size |
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197 | RCTL_BSIZE_SHIFT = 16 |
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198 | RCTL_VFE = 0x00040000 ; VLAN Filter Enable |
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199 | RCTL_CFIEN = 0x00080000 ; CFI Enable |
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200 | RCTL_CFI = 0x00100000 ; Canonical Form Indicator Bit |
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201 | RCTL_DPF = 0x00400000 ; Discard Pause Frames |
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202 | RCTL_PMCF = 0x00800000 ; Pass MAC Control Frames |
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203 | RCTL_BSEX = 0x02000000 ; Buffer Size Extension |
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204 | RCTL_SECRC = 0x04000000 ; Strip Ethernet CRC |
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205 | |||
206 | ; TCTL - Transmit Control Register (0x0400) |
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207 | TCTL_EN = 0x00000002 ; Transmit Enable |
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208 | TCTL_PSP = 0x00000008 ; Pad short packets |
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209 | TCTL_SWXOFF = 0x00400000 ; Software XOFF Transmission |
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210 | |||
211 | ; PBA - Packet Buffer Allocation (0x1000) |
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212 | PBA_RXA_MASK = 0x0000FFFF ; RX Packet Buffer |
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213 | PBA_RXA_SHIFT = 0 |
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214 | PBA_TXA_MASK = 0xFFFF0000 ; TX Packet Buffer |
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215 | PBA_TXA_SHIFT = 16 |
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216 | |||
217 | ; Flow Control Type |
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218 | FCT_TYPE_DEFAULT = 0x8808 |
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219 | |||
220 | ; === TX Descriptor fields === |
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221 | |||
222 | ; TX Packet Length (word 2) |
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223 | TXDESC_LEN_MASK = 0x0000ffff |
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224 | |||
225 | ; TX Descriptor CMD field (word 2) |
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226 | TXDESC_IDE = 0x80000000 ; Interrupt Delay Enable |
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227 | TXDESC_VLE = 0x40000000 ; VLAN Packet Enable |
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228 | TXDESC_DEXT = 0x20000000 ; Extension |
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229 | TXDESC_RPS = 0x10000000 ; Report Packet Sent |
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230 | TXDESC_RS = 0x08000000 ; Report Status |
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231 | TXDESC_IC = 0x04000000 ; Insert Checksum |
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232 | TXDESC_IFCS = 0x02000000 ; Insert FCS |
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233 | TXDESC_EOP = 0x01000000 ; End Of Packet |
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234 | |||
235 | ; TX Descriptor STA field (word 3) |
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236 | TXDESC_TU = 0x00000008 ; Transmit Underrun |
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237 | TXDESC_LC = 0x00000004 ; Late Collision |
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238 | TXDESC_EC = 0x00000002 ; Excess Collisions |
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239 | TXDESC_DD = 0x00000001 ; Descriptor Done |
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240 | |||
241 | ; === RX Descriptor fields === |
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242 | |||
243 | ; RX Packet Length (word 2) |
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244 | RXDESC_LEN_MASK = 0x0000ffff |
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245 | |||
246 | ; RX Descriptor STA field (word 3) |
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247 | RXDESC_PIF = 0x00000080 ; Passed In-exact Filter |
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248 | RXDESC_IPCS = 0x00000040 ; IP cksum calculated |
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249 | RXDESC_TCPCS = 0x00000020 ; TCP cksum calculated |
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250 | RXDESC_VP = 0x00000008 ; Packet is 802.1Q |
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251 | RXDESC_IXSM = 0x00000004 ; Ignore cksum indication |
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252 | RXDESC_EOP = 0x00000002 ; End Of Packet |
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253 | RXDESC_DD = 0x00000001 ; Descriptor Done |
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254 | |||
255 | |||
256 | virtual at ebx |
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257 | device: |
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258 | ETH_DEVICE |
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259 | |||
260 | .mmio_addr dd ? |
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261 | .pci_bus dd ? |
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262 | .pci_dev dd ? |
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263 | .irq_line db ? |
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264 | |||
4512 | hidnplayr | 265 | .cur_rx dd ? |
3545 | hidnplayr | 266 | .cur_tx dd ? |
267 | .last_tx dd ? |
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268 | |||
269 | rb 0x100 - (($ - device) and 0xff) |
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4512 | hidnplayr | 270 | .rx_desc rd RX_RING_SIZE*8 |
3545 | hidnplayr | 271 | |
272 | rb 0x100 - (($ - device) and 0xff) |
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273 | .tx_desc rd 256/8 |
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274 | |||
275 | sizeof.device_struct = $ - device |
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276 | |||
277 | end virtual |
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278 | |||
4512 | hidnplayr | 279 | |
3545 | hidnplayr | 280 | section '.flat' code readable align 16 |
281 | |||
282 | |||
283 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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284 | ;; ;; |
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285 | ;; proc START ;; |
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286 | ;; ;; |
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287 | ;; (standard driver proc) ;; |
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288 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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289 | |||
290 | align 4 |
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291 | proc START stdcall, state:dword |
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292 | |||
293 | cmp [state], 1 |
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294 | jne .exit |
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295 | |||
296 | .entry: |
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297 | |||
3855 | hidnplayr | 298 | DEBUGF 1,"Loading driver\n" |
3545 | hidnplayr | 299 | stdcall RegService, my_service, service_proc |
300 | ret |
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301 | |||
302 | .fail: |
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303 | .exit: |
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304 | xor eax, eax |
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305 | ret |
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306 | |||
307 | endp |
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308 | |||
309 | |||
310 | |||
311 | |||
312 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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313 | ;; ;; |
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314 | ;; proc SERVICE_PROC ;; |
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315 | ;; ;; |
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316 | ;; (standard driver proc) ;; |
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317 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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318 | |||
319 | align 4 |
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320 | proc service_proc stdcall, ioctl:dword |
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321 | |||
322 | mov edx, [ioctl] |
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4470 | hidnplayr | 323 | mov eax, [edx + IOCTL.io_code] |
3545 | hidnplayr | 324 | |
325 | ;------------------------------------------------------ |
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326 | |||
327 | cmp eax, 0 ;SRV_GETVERSION |
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328 | jne @F |
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329 | |||
4470 | hidnplayr | 330 | cmp [edx + IOCTL.out_size], 4 |
3545 | hidnplayr | 331 | jb .fail |
4470 | hidnplayr | 332 | mov eax, [edx + IOCTL.output] |
3545 | hidnplayr | 333 | mov [eax], dword API_VERSION |
334 | |||
335 | xor eax, eax |
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336 | ret |
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337 | |||
338 | ;------------------------------------------------------ |
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339 | @@: |
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340 | cmp eax, 1 ;SRV_HOOK |
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341 | jne .fail |
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342 | |||
4470 | hidnplayr | 343 | cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes |
3545 | hidnplayr | 344 | jb .fail |
345 | |||
4470 | hidnplayr | 346 | mov eax, [edx + IOCTL.input] |
3545 | hidnplayr | 347 | cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given |
348 | jne .fail ; other types arent supported for this card yet |
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349 | |||
350 | ; check if the device is already listed |
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351 | |||
352 | mov esi, device_list |
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353 | mov ecx, [devices] |
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354 | test ecx, ecx |
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355 | jz .firstdevice |
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356 | |||
4470 | hidnplayr | 357 | ; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers |
3545 | hidnplayr | 358 | mov ax, [eax+1] ; |
359 | .nextdevice: |
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360 | mov ebx, [esi] |
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361 | cmp al, byte [device.pci_bus] |
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362 | jne .next |
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363 | cmp ah, byte [device.pci_dev] |
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364 | je .find_devicenum ; Device is already loaded, let's find it's device number |
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365 | .next: |
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366 | add esi, 4 |
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367 | loop .nextdevice |
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368 | |||
369 | |||
370 | ; This device doesnt have its own eth_device structure yet, lets create one |
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371 | .firstdevice: |
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372 | cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card |
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373 | jae .fail |
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374 | |||
375 | allocate_and_clear ebx, sizeof.device_struct, .fail ; Allocate the buffer for device structure |
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376 | |||
377 | ; Fill in the direct call addresses into the struct |
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378 | |||
379 | mov [device.reset], reset |
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380 | mov [device.transmit], transmit |
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381 | mov [device.unload], unload |
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382 | mov [device.name], my_service |
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383 | |||
384 | ; save the pci bus and device numbers |
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385 | |||
4470 | hidnplayr | 386 | mov eax, [edx + IOCTL.input] |
3545 | hidnplayr | 387 | movzx ecx, byte [eax+1] |
388 | mov [device.pci_bus], ecx |
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389 | movzx ecx, byte [eax+2] |
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390 | mov [device.pci_dev], ecx |
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391 | |||
392 | ; Now, it's time to find the base mmio addres of the PCI device |
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393 | |||
394 | PCI_find_mmio32 |
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395 | |||
396 | ; Create virtual mapping of the physical memory |
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397 | |||
398 | push 1Bh ; PG_SW+PG_NOCACHE |
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399 | push 10000h ; size of the map |
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400 | push eax |
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401 | call MapIoMem |
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402 | mov [device.mmio_addr], eax |
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403 | |||
404 | ; We've found the mmio address, find IRQ now |
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405 | |||
406 | PCI_find_irq |
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407 | |||
408 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
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409 | [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.mmio_addr]:8 |
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410 | |||
411 | ; Ok, the eth_device structure is ready, let's probe the device |
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412 | call probe ; this function will output in eax |
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413 | test eax, eax |
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414 | jnz .err ; If an error occured, exit |
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415 | |||
416 | mov eax, [devices] ; Add the device structure to our device list |
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417 | mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device) |
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418 | inc [devices] ; |
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419 | |||
420 | call start_i8254x |
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421 | |||
422 | mov [device.type], NET_TYPE_ETH |
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423 | call NetRegDev |
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424 | |||
425 | cmp eax, -1 |
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426 | je .destroy |
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427 | |||
428 | ret |
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429 | |||
430 | ; If the device was already loaded, find the device number and return it in eax |
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431 | |||
432 | .find_devicenum: |
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433 | DEBUGF 1,"Trying to find device number of already registered device\n" |
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434 | call NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx |
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435 | ; into a device number in edi |
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436 | mov eax, edi ; Application wants it in eax instead |
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437 | DEBUGF 1,"Kernel says: %u\n", eax |
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438 | ret |
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439 | |||
440 | ; If an error occured, remove all allocated data and exit (returning -1 in eax) |
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441 | |||
442 | .destroy: |
||
443 | ; todo: reset device into virgin state |
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444 | |||
445 | .err: |
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446 | stdcall KernelFree, ebx |
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447 | |||
448 | .fail: |
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449 | or eax, -1 |
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450 | ret |
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451 | |||
452 | ;------------------------------------------------------ |
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453 | endp |
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454 | |||
455 | |||
456 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
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457 | ;; ;; |
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458 | ;; Actual Hardware dependent code starts here ;; |
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459 | ;; ;; |
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460 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
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461 | |||
462 | |||
463 | align 4 |
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464 | unload: |
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465 | ; TODO: (in this particular order) |
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466 | ; |
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467 | ; - Stop the device |
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468 | ; - Detach int handler |
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469 | ; - Remove device from local list (device_list) |
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470 | ; - call unregister function in kernel |
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471 | ; - Remove all allocated structures and buffers the card used |
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472 | |||
473 | or eax, -1 |
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474 | |||
475 | ret |
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476 | |||
477 | |||
478 | |||
479 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
480 | ;; |
||
481 | ;; probe: enables the device (if it really is I8254X) |
||
482 | ;; |
||
483 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
484 | align 4 |
||
485 | probe: |
||
486 | |||
487 | DEBUGF 1,"Probe\n" |
||
488 | |||
489 | PCI_make_bus_master |
||
490 | |||
491 | ; TODO: validate the device |
||
492 | |||
493 | call read_mac |
||
494 | |||
495 | movzx eax, [device.irq_line] |
||
496 | DEBUGF 1,"Attaching int handler to irq %x\n", eax:1 |
||
497 | stdcall AttachIntHandler, eax, int_handler, dword 0 |
||
498 | test eax, eax |
||
499 | jnz @f |
||
3855 | hidnplayr | 500 | DEBUGF 2,"Could not attach int handler!\n" |
3545 | hidnplayr | 501 | ; or eax, -1 |
502 | ; ret |
||
503 | @@: |
||
504 | |||
505 | |||
506 | reset_dontstart: |
||
507 | DEBUGF 1,"Reset\n" |
||
508 | |||
509 | mov esi, [device.mmio_addr] |
||
510 | |||
4512 | hidnplayr | 511 | or dword[esi + REG_CTRL], CTRL_RST ; reset device |
3545 | hidnplayr | 512 | .loop: |
513 | push esi |
||
514 | xor esi, esi |
||
515 | inc esi |
||
516 | call Sleep |
||
517 | pop esi |
||
4512 | hidnplayr | 518 | test dword[esi + REG_CTRL], CTRL_RST |
3545 | hidnplayr | 519 | jnz .loop |
520 | |||
521 | mov dword [esi + REG_IMC], 0xffffffff ; Disable all interrupt causes |
||
522 | mov eax, dword [esi + REG_ICR] ; Clear any pending interrupts |
||
523 | mov dword [esi + REG_ITR], 0 ; Disable interrupt throttling logic |
||
524 | |||
4512 | hidnplayr | 525 | mov dword [esi + REG_PBA], 0x00000004 ; PBA: set the RX buffer size to 4KB (TX buffer is calculated as 64-RX buffer) |
3545 | hidnplayr | 526 | mov dword [esi + REG_RDTR], 0 ; RDTR: set no delay |
527 | |||
528 | mov dword [esi + REG_TXCW], 0x08008060 ; TXCW: set ANE, TxConfigWord (Half/Full duplex, Next Page Reqest) |
||
529 | |||
530 | mov eax, [esi + REG_CTRL] |
||
531 | or eax, 1 shl 6 + 1 shl 5 |
||
532 | and eax, not (1 shl 3 + 1 shl 7 + 1 shl 30 + 1 shl 31) |
||
533 | mov dword [esi + REG_CTRL], eax ; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS |
||
534 | |||
535 | lea edi, [esi + 0x5200] ; MTA: reset |
||
536 | mov eax, 0xffffffff |
||
537 | stosd |
||
538 | stosd |
||
539 | stosd |
||
540 | stosd |
||
541 | |||
4512 | hidnplayr | 542 | call init_rx |
543 | call init_tx |
||
544 | |||
545 | xor eax, eax |
||
546 | ret |
||
547 | |||
548 | |||
549 | |||
550 | align 4 |
||
551 | init_rx: |
||
552 | |||
553 | lea edi, [device.rx_desc] |
||
554 | mov ecx, RX_RING_SIZE |
||
555 | .loop: |
||
556 | push ecx |
||
557 | push edi |
||
558 | stdcall KernelAlloc, MAX_PKT_SIZE |
||
559 | DEBUGF 1,"RX buffer: 0x%x\n", eax |
||
560 | pop edi |
||
561 | mov dword[edi + 16*RX_RING_SIZE], eax |
||
562 | push edi |
||
3545 | hidnplayr | 563 | GetRealAddr |
4512 | hidnplayr | 564 | pop edi |
565 | mov dword[edi], eax ; addres low |
||
566 | mov dword[edi + 4], 0 ; addres high |
||
567 | mov dword[edi + 8], 0 |
||
568 | mov dword[edi + 12], 0 |
||
569 | add edi, 16 |
||
570 | pop ecx |
||
571 | dec ecx |
||
572 | jnz .loop |
||
3545 | hidnplayr | 573 | |
4512 | hidnplayr | 574 | mov [device.cur_rx], 0 |
575 | |||
3545 | hidnplayr | 576 | lea eax, [device.rx_desc] |
577 | GetRealAddr |
||
4512 | hidnplayr | 578 | mov dword[esi + REG_RDBAL], eax ; Receive Descriptor Base Address Low |
579 | mov dword[esi + REG_RDBAH], 0 ; Receive Descriptor Base Address High |
||
580 | mov dword[esi + REG_RDLEN], 16*RX_RING_SIZE ; Receive Descriptor Length |
||
581 | mov dword[esi + REG_RDH], 0 ; Receive Descriptor Head |
||
582 | mov dword[esi + REG_RDT], RX_RING_SIZE-1 ; Receive Descriptor Tail |
||
583 | mov dword[esi + REG_RCTL], RCTL_SBP or RCTL_BAM or RCTL_SECRC or RCTL_UPE or RCTL_MPE |
||
584 | ; Store Bad Packets, Broadcast Accept Mode, Strip Ethernet CRC from incoming packet, Promiscuous mode |
||
3545 | hidnplayr | 585 | |
4512 | hidnplayr | 586 | ret |
3545 | hidnplayr | 587 | |
4512 | hidnplayr | 588 | |
589 | |||
590 | align 4 |
||
591 | init_tx: |
||
592 | |||
593 | mov dword[device.tx_desc], 0 |
||
594 | mov dword[device.tx_desc + 4], 0 |
||
595 | mov dword[device.tx_desc + 16], 0 |
||
596 | |||
3545 | hidnplayr | 597 | lea eax, [device.tx_desc] |
598 | GetRealAddr |
||
4512 | hidnplayr | 599 | mov dword[esi + REG_TDBAL], eax ; Transmit Descriptor Base Address Low |
600 | mov dword[esi + REG_TDBAH], 0 ; Transmit Descriptor Base Address High |
||
601 | mov dword[esi + REG_TDLEN], (1 * 128) ; Transmit Descriptor Length |
||
602 | mov dword[esi + REG_TDH], 0 ; Transmit Descriptor Head |
||
603 | mov dword[esi + REG_TDT], 0 ; Transmit Descriptor Tail |
||
604 | mov dword[esi + REG_TCTL], 0x010400fa ; Enabled, Pad Short Packets, 15 retrys, 64-byte COLD, Re-transmit on Late Collision |
||
605 | mov dword[esi + REG_TIPG], 0x0060200A ; IPGT 10, IPGR1 8, IPGR2 6 |
||
3545 | hidnplayr | 606 | |
607 | ret |
||
608 | |||
4512 | hidnplayr | 609 | |
3545 | hidnplayr | 610 | align 4 |
611 | reset: |
||
612 | call reset_dontstart |
||
613 | |||
614 | start_i8254x: |
||
615 | |||
4512 | hidnplayr | 616 | mov esi, [device.mmio_addr] |
617 | or dword[esi + REG_RCTL], RCTL_EN |
||
618 | |||
3545 | hidnplayr | 619 | xor eax, eax |
620 | mov [esi + REG_RDTR], eax ; Clear the Receive Delay Timer Register |
||
621 | mov [esi + REG_RADV], eax ; Clear the Receive Interrupt Absolute Delay Timer |
||
622 | mov [esi + REG_RSRPD], eax ; Clear the Receive Small Packet Detect Interrupt |
||
623 | |||
4512 | hidnplayr | 624 | mov dword[esi + REG_IMS], 0x1F6DC ; Enable interrupt types |
625 | mov eax, [esi + REG_ICR] ; Clear pending interrupts |
||
626 | |||
3545 | hidnplayr | 627 | mov [device.mtu], 1514 |
628 | |||
629 | ; Set link state to unknown |
||
630 | mov [device.state], ETH_LINK_UNKOWN |
||
631 | |||
632 | xor eax, eax |
||
633 | ret |
||
634 | |||
635 | |||
636 | |||
637 | |||
638 | align 4 |
||
639 | read_mac: |
||
640 | |||
641 | DEBUGF 1,"Read MAC\n" |
||
642 | |||
643 | mov esi, [device.mmio_addr] |
||
644 | |||
645 | mov eax, [esi+0x5400] ; RAL |
||
646 | test eax, eax |
||
647 | jz .try_eeprom |
||
648 | |||
649 | mov dword [device.mac], eax |
||
650 | mov eax, [esi+0x5404] ; RAH |
||
651 | mov word [device.mac+4], ax |
||
652 | |||
653 | jmp .mac_ok |
||
654 | |||
655 | .try_eeprom: |
||
656 | mov dword [esi+0x14], 0x00000001 |
||
657 | mov eax, [esi+0x14] |
||
658 | shr eax, 16 |
||
659 | mov word [device.mac], ax |
||
660 | |||
661 | mov dword [esi+0x14], 0x00000101 |
||
662 | mov eax, [esi+0x14] |
||
663 | shr eax, 16 |
||
664 | mov word [device.mac+2], ax |
||
665 | |||
666 | mov dword [esi+0x14], 0x00000201 |
||
667 | mov eax, [esi+0x14] |
||
668 | shr eax, 16 |
||
669 | mov word [device.mac+4], ax |
||
670 | |||
671 | .mac_ok: |
||
672 | DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\ |
||
673 | [device.mac+0]:2,[device.mac+1]:2,[device.mac+2]:2,[device.mac+3]:2,[device.mac+4]:2,[device.mac+5]:2 |
||
674 | |||
675 | ret |
||
676 | |||
677 | |||
678 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
679 | ;; ;; |
||
680 | ;; Transmit ;; |
||
681 | ;; ;; |
||
4512 | hidnplayr | 682 | ;; In: pointer to device structure in ebx ;; |
3545 | hidnplayr | 683 | ;; ;; |
684 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
4512 | hidnplayr | 685 | |
686 | proc transmit stdcall bufferptr, buffersize |
||
687 | |||
688 | DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [buffersize] |
||
689 | mov eax, [bufferptr] |
||
3788 | hidnplayr | 690 | DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\ |
3545 | hidnplayr | 691 | [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\ |
692 | [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\ |
||
693 | [eax+13]:2,[eax+12]:2 |
||
694 | |||
4512 | hidnplayr | 695 | cmp [buffersize], 1514 |
3545 | hidnplayr | 696 | ja .fail |
4512 | hidnplayr | 697 | cmp [buffersize], 60 |
3545 | hidnplayr | 698 | jb .fail |
699 | |||
700 | ; Program the descriptor (use legacy mode) |
||
701 | lea edi, [device.tx_desc] ; Transmit Descriptor Base Address |
||
4512 | hidnplayr | 702 | mov dword[edi + 16], eax ; Store the data location (for driver) |
3545 | hidnplayr | 703 | GetRealAddr ; |
4512 | hidnplayr | 704 | mov dword[edi], eax ; Real addr (for i8254x) |
705 | mov dword[edi + 4], 0x00000000 ; |
||
3545 | hidnplayr | 706 | |
4512 | hidnplayr | 707 | mov ecx, [buffersize] |
3545 | hidnplayr | 708 | or ecx, 1 shl 24 + 1 shl 25 + 1 shl 27 ; EOP + IFCS + RS |
4512 | hidnplayr | 709 | mov dword[edi + 8], ecx ; Packet size |
710 | mov dword[edi + 12], 0x00000000 |
||
3545 | hidnplayr | 711 | |
712 | ; Tell i8254x wich descriptor(s) we programmed |
||
713 | mov edi, [device.mmio_addr] |
||
4512 | hidnplayr | 714 | mov dword[edi + REG_TDH], 0 ; TDH - Transmit Descriptor Head |
715 | mov dword[edi + REG_TDT], 1 ; TDT - Transmit Descriptor Tail |
||
3545 | hidnplayr | 716 | |
717 | ; Update stats |
||
718 | inc [device.packets_tx] |
||
4512 | hidnplayr | 719 | mov eax, [buffersize] |
720 | add dword[device.bytes_tx], eax |
||
721 | adc dword[device.bytes_tx + 4], 0 |
||
3545 | hidnplayr | 722 | |
4334 | hidnplayr | 723 | xor eax, eax |
4512 | hidnplayr | 724 | ret |
3545 | hidnplayr | 725 | |
726 | .fail: |
||
3788 | hidnplayr | 727 | DEBUGF 2,"Send failed\n" |
4512 | hidnplayr | 728 | stdcall KernelFree, [bufferptr] |
4334 | hidnplayr | 729 | or eax, -1 |
4512 | hidnplayr | 730 | ret |
3545 | hidnplayr | 731 | |
4512 | hidnplayr | 732 | endp |
3545 | hidnplayr | 733 | |
4512 | hidnplayr | 734 | |
3545 | hidnplayr | 735 | ;;;;;;;;;;;;;;;;;;;;;;; |
736 | ;; ;; |
||
737 | ;; Interrupt handler ;; |
||
738 | ;; ;; |
||
739 | ;;;;;;;;;;;;;;;;;;;;;;; |
||
740 | |||
741 | align 4 |
||
742 | int_handler: |
||
743 | |||
744 | push ebx esi edi |
||
745 | |||
3855 | hidnplayr | 746 | DEBUGF 1,"INT\n" |
3545 | hidnplayr | 747 | ;------------------------------------------- |
748 | ; Find pointer of device wich made IRQ occur |
||
749 | |||
750 | mov ecx, [devices] |
||
751 | test ecx, ecx |
||
752 | jz .nothing |
||
753 | mov esi, device_list |
||
754 | .nextdevice: |
||
755 | mov ebx, [esi] |
||
756 | |||
757 | mov edi, [device.mmio_addr] |
||
758 | mov eax, [edi + REG_ICR] |
||
759 | test eax, eax |
||
760 | jnz .got_it |
||
761 | .continue: |
||
762 | add esi, 4 |
||
763 | dec ecx |
||
764 | jnz .nextdevice |
||
765 | .nothing: |
||
766 | pop edi esi ebx |
||
767 | xor eax, eax |
||
768 | |||
769 | ret |
||
770 | |||
771 | .got_it: |
||
772 | |||
4512 | hidnplayr | 773 | DEBUGF 1,"Device: %x Status: %x\n", ebx, eax |
3545 | hidnplayr | 774 | |
775 | ;--------- |
||
776 | ; RX done? |
||
777 | |||
4512 | hidnplayr | 778 | test eax, ICR_RXDMT0 + ICR_RXT0 |
3545 | hidnplayr | 779 | jz .no_rx |
780 | |||
781 | push eax ebx |
||
4512 | hidnplayr | 782 | .retaddr: |
783 | pop ebx eax |
||
3545 | hidnplayr | 784 | ; Get last descriptor addr |
4512 | hidnplayr | 785 | mov esi, [device.cur_rx] |
786 | shl esi, 4 |
||
787 | lea esi, [device.rx_desc + esi] |
||
788 | cmp byte[esi + 12], 0 ; Check status field |
||
789 | je .no_rx |
||
3545 | hidnplayr | 790 | |
4512 | hidnplayr | 791 | push eax ebx |
792 | push .retaddr |
||
793 | movzx ecx, word[esi + 8] ; Get the packet length |
||
3788 | hidnplayr | 794 | DEBUGF 1,"got %u bytes\n", ecx |
3545 | hidnplayr | 795 | push ecx |
4512 | hidnplayr | 796 | push dword[esi + 16*RX_RING_SIZE] ; Get packet pointer |
3545 | hidnplayr | 797 | |
798 | ; Update stats |
||
4512 | hidnplayr | 799 | add dword[device.bytes_rx], ecx |
800 | adc dword[device.bytes_rx + 4], 0 |
||
801 | inc dword[device.packets_rx] |
||
3545 | hidnplayr | 802 | |
4512 | hidnplayr | 803 | ; Allocate new descriptor |
804 | push esi |
||
805 | stdcall KernelAlloc, MAX_PKT_SIZE |
||
806 | pop esi |
||
807 | mov dword[esi + 16*RX_RING_SIZE], eax |
||
3545 | hidnplayr | 808 | GetRealAddr |
4512 | hidnplayr | 809 | mov dword[esi], eax |
810 | mov dword[esi + 8], 0 |
||
811 | mov dword[esi + 12], 0 |
||
3545 | hidnplayr | 812 | |
4512 | hidnplayr | 813 | ; Move the receive descriptor tail |
3545 | hidnplayr | 814 | mov esi, [device.mmio_addr] |
4512 | hidnplayr | 815 | mov eax, [device.cur_rx] |
816 | mov [esi + REG_RDT], eax |
||
3545 | hidnplayr | 817 | |
4512 | hidnplayr | 818 | ; Move to next rx desc |
819 | inc [device.cur_rx] |
||
820 | and [device.cur_rx], RX_RING_SIZE-1 |
||
821 | |||
3545 | hidnplayr | 822 | jmp Eth_input |
823 | .no_rx: |
||
824 | |||
825 | ;-------------- |
||
826 | ; Link Changed? |
||
827 | |||
828 | test eax, ICR_LSC |
||
829 | jz .no_link |
||
830 | |||
4512 | hidnplayr | 831 | DEBUGF 2,"Link Changed\n" |
3545 | hidnplayr | 832 | |
833 | .no_link: |
||
834 | |||
835 | ;--------------- |
||
836 | ; Transmit done? |
||
837 | |||
838 | test eax, ICR_TXDW |
||
839 | jz .no_tx |
||
840 | |||
3788 | hidnplayr | 841 | DEBUGF 1,"Transmit done\n" |
3545 | hidnplayr | 842 | |
843 | lea edi, [device.tx_desc] ; Transmit Descriptor Base Address |
||
4512 | hidnplayr | 844 | push dword[edi + 16] |
3545 | hidnplayr | 845 | call KernelFree |
846 | |||
847 | .no_tx: |
||
848 | .fail: |
||
849 | pop edi esi ebx |
||
850 | xor eax, eax |
||
851 | inc eax |
||
852 | |||
853 | ret |
||
854 | |||
855 | |||
856 | |||
857 | |||
858 | ; End of code |
||
859 | |||
860 | section '.data' data readable writable align 16 |
||
861 | align 4 |
||
862 | |||
863 | devices dd 0 |
||
864 | version dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF) |
||
865 | my_service db 'I8254X',0 ; max 16 chars include zero |
||
866 | |||
867 | include_debug_strings ; All data wich FDO uses will be included here |
||
868 | |||
869 | device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling |
||
870 |