Rev 7809 | Rev 9146 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
7827 | hidnplayr | 1 | ALX_VEN_ID = 0x1969 |
2 | |||
3 | ALX_DEV_ID_AR8131 = 0x1063 |
||
7809 | hidnplayr | 4 | ALX_DEV_ID_AR8161 = 0x1091 |
5 | ALX_DEV_ID_E2200 = 0xe091 |
||
6 | ALX_DEV_ID_E2400 = 0xe0a1 |
||
7 | ALX_DEV_ID_E2500 = 0xe0b1 |
||
8 | ALX_DEV_ID_AR8162 = 0x1090 |
||
9 | ALX_DEV_ID_AR8171 = 0x10A1 |
||
10 | ALX_DEV_ID_AR8172 = 0x10A0 |
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11 | |||
12 | ; rev definition, |
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13 | ; bit0: with xD support |
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14 | ; bit1: with Card Reader function |
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15 | ; bit(7:2): real revision |
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16 | |||
17 | ALX_PCI_REVID_SHIFT = 3 |
||
18 | ALX_REV_A0 = 0 |
||
19 | ALX_REV_A1 = 1 |
||
20 | ALX_REV_B0 = 2 |
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21 | ALX_REV_C0 = 3 |
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22 | |||
23 | ALX_DEV_CTRL = 0x0060 |
||
24 | ALX_DEV_CTRL_MAXRRS_MIN = 2 |
||
25 | |||
26 | ALX_MSIX_MASK = 0x0090 |
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27 | |||
28 | ALX_UE_SVRT = 0x010C |
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29 | ALX_UE_SVRT_FCPROTERR = (1 shl 13) |
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30 | ALX_UE_SVRT_DLPROTERR = (1 shl 4) |
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31 | |||
32 | ; eeprom & flash load register |
||
33 | ALX_EFLD = 0x0204 |
||
34 | ALX_EFLD_F_EXIST = (1 shl 10) |
||
35 | ALX_EFLD_E_EXIST = (1 shl 9) |
||
36 | ALX_EFLD_STAT = (1 shl 5) |
||
37 | ALX_EFLD_START = (1 shl 0) |
||
38 | |||
39 | ; eFuse load register |
||
40 | ALX_SLD = 0x0218 |
||
41 | ALX_SLD_STAT = (1 shl 12) |
||
42 | ALX_SLD_START = (1 shl 11) |
||
43 | ALX_SLD_MAX_TO = 100 |
||
44 | |||
45 | ALX_PDLL_TRNS1 = 0x1104 |
||
46 | ALX_PDLL_TRNS1_D3PLLOFF_EN = (1 shl 11) |
||
47 | |||
48 | ALX_PMCTRL = 0x12F8 |
||
49 | ALX_PMCTRL_HOTRST_WTEN = (1 shl 31) |
||
50 | ; bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) |
||
51 | ALX_PMCTRL_ASPM_FCEN = (1 shl 30) |
||
52 | ALX_PMCTRL_SADLY_EN = (1 shl 29) |
||
53 | ALX_PMCTRL_LCKDET_TIMER_MASK = 0xF |
||
54 | ALX_PMCTRL_LCKDET_TIMER_SHIFT = 24 |
||
55 | ALX_PMCTRL_LCKDET_TIMER_DEF = 0xC |
||
56 | ; bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 |
||
57 | ALX_PMCTRL_L1REQ_TO_MASK = 0xF |
||
58 | ALX_PMCTRL_L1REQ_TO_SHIFT = 20 |
||
59 | ALX_PMCTRL_L1REG_TO_DEF = 0xF |
||
60 | ALX_PMCTRL_TXL1_AFTER_L0S = (1 shl 19) |
||
61 | ALX_PMCTRL_L1_TIMER_MASK = 0x7 |
||
62 | ALX_PMCTRL_L1_TIMER_SHIFT = 16 |
||
63 | ALX_PMCTRL_L1_TIMER_16US = 4 |
||
64 | ALX_PMCTRL_RCVR_WT_1US = (1 shl 15) |
||
65 | ; bit13: enable pcie clk switch in L1 state |
||
66 | ALX_PMCTRL_L1_CLKSW_EN = (1 shl 13) |
||
67 | ALX_PMCTRL_L0S_EN = (1 shl 12) |
||
68 | ALX_PMCTRL_RXL1_AFTER_L0S = (1 shl 11) |
||
69 | ALX_PMCTRL_L1_BUFSRX_EN = (1 shl 7) |
||
70 | ; bit6: power down serdes RX |
||
71 | ALX_PMCTRL_L1_SRDSRX_PWD = (1 shl 6) |
||
72 | ALX_PMCTRL_L1_SRDSPLL_EN = (1 shl 5) |
||
73 | ALX_PMCTRL_L1_SRDS_EN = (1 shl 4) |
||
74 | ALX_PMCTRL_L1_EN = (1 shl 3) |
||
75 | |||
76 | ;****************************************************** |
||
77 | ; following registers are mapped only to memory space |
||
78 | ;****************************************************** |
||
79 | |||
80 | ALX_MASTER = 0x1400 |
||
81 | ; bit12: 1:alwys select pclk from serdes, not sw to 25M |
||
82 | ALX_MASTER_PCLKSEL_SRDS = (1 shl 12) |
||
83 | ; bit11: irq moduration for rx |
||
84 | ALX_MASTER_IRQMOD2_EN = (1 shl 11) |
||
85 | ; bit10: irq moduration for tx/rx |
||
86 | ALX_MASTER_IRQMOD1_EN = (1 shl 10) |
||
87 | ALX_MASTER_SYSALVTIMER_EN = (1 shl 7) |
||
88 | ALX_MASTER_OOB_DIS = (1 shl 6) |
||
89 | ; bit5: wakeup without pcie clk |
||
90 | ALX_MASTER_WAKEN_25M = (1 shl 5) |
||
91 | ; bit0: MAC & DMA reset |
||
92 | ALX_MASTER_DMA_MAC_RST = (1 shl 0) |
||
93 | ALX_DMA_MAC_RST_TO = 50 |
||
94 | |||
95 | ALX_IRQ_MODU_TIMER = 0x1408 |
||
96 | ALX_IRQ_MODU_TIMER1_MASK = 0xFFFF |
||
97 | ALX_IRQ_MODU_TIMER1_SHIFT = 0 |
||
98 | |||
99 | ALX_PHY_CTRL = 0x140C |
||
100 | ALX_PHY_CTRL_100AB_EN = (1 shl 17) |
||
101 | ; bit14: affect MAC & PHY, go to low power sts |
||
102 | ALX_PHY_CTRL_POWER_DOWN = (1 shl 14) |
||
103 | ; bit13: 1:pll always ON, 0:can switch in lpw |
||
104 | ALX_PHY_CTRL_PLL_ON = (1 shl 13) |
||
105 | ALX_PHY_CTRL_RST_ANALOG = (1 shl 12) |
||
106 | ALX_PHY_CTRL_HIB_PULSE = (1 shl 11) |
||
107 | ALX_PHY_CTRL_HIB_EN = (1 shl 10) |
||
108 | ALX_PHY_CTRL_IDDQ = (1 shl 7) |
||
109 | ALX_PHY_CTRL_GATE_25M = (1 shl 5) |
||
110 | ALX_PHY_CTRL_LED_MODE = (1 shl 2) |
||
111 | ; bit0: out of dsp RST state |
||
112 | ALX_PHY_CTRL_DSPRST_OUT = (1 shl 0) |
||
113 | ALX_PHY_CTRL_DSPRST_TO = 80 |
||
114 | ALX_PHY_CTRL_CLS = (ALX_PHY_CTRL_LED_MODE or ALX_PHY_CTRL_100AB_EN or ALX_PHY_CTRL_PLL_ON) |
||
115 | |||
116 | ALX_MAC_STS = 0x1410 |
||
117 | ALX_MAC_STS_TXQ_BUSY = (1 shl 3) |
||
118 | ALX_MAC_STS_RXQ_BUSY = (1 shl 2) |
||
119 | ALX_MAC_STS_TXMAC_BUSY = (1 shl 1) |
||
120 | ALX_MAC_STS_RXMAC_BUSY = (1 shl 0) |
||
121 | ALX_MAC_STS_IDLE = (ALX_MAC_STS_TXQ_BUSY or ALX_MAC_STS_RXQ_BUSY or ALX_MAC_STS_TXMAC_BUSY or ALX_MAC_STS_RXMAC_BUSY) |
||
122 | |||
123 | ALX_MDIO = 0x1414 |
||
124 | ALX_MDIO_MODE_EXT = (1 shl 30) |
||
125 | ALX_MDIO_BUSY = (1 shl 27) |
||
126 | ALX_MDIO_CLK_SEL_MASK = 0x7 |
||
127 | ALX_MDIO_CLK_SEL_SHIFT = 24 |
||
128 | ALX_MDIO_CLK_SEL_25MD4 = 0 |
||
129 | ALX_MDIO_CLK_SEL_25MD128 = 7 |
||
130 | ALX_MDIO_START = (1 shl 23) |
||
131 | ALX_MDIO_SPRES_PRMBL = (1 shl 22) |
||
132 | ; bit21: 1:read,0:write |
||
133 | ALX_MDIO_OP_READ = (1 shl 21) |
||
134 | ALX_MDIO_REG_MASK = 0x1F |
||
135 | ALX_MDIO_REG_SHIFT = 16 |
||
136 | ALX_MDIO_DATA_MASK = 0xFFFF |
||
137 | ALX_MDIO_DATA_SHIFT = 0 |
||
138 | ALX_MDIO_MAX_AC_TO = 120 |
||
139 | |||
140 | ALX_MDIO_EXTN = 0x1448 |
||
141 | ALX_MDIO_EXTN_DEVAD_MASK = 0x1F |
||
142 | ALX_MDIO_EXTN_DEVAD_SHIFT = 16 |
||
143 | ALX_MDIO_EXTN_REG_MASK = 0xFFFF |
||
144 | ALX_MDIO_EXTN_REG_SHIFT = 0 |
||
145 | |||
146 | ALX_SERDES = 0x1424 |
||
147 | ALX_SERDES_PHYCLK_SLWDWN = (1 shl 18) |
||
148 | ALX_SERDES_MACCLK_SLWDWN = (1 shl 17) |
||
149 | |||
150 | ALX_LPI_CTRL = 0x1440 |
||
151 | ALX_LPI_CTRL_EN = (1 shl 0) |
||
152 | |||
153 | ; for B0+, bit[13..] for C0+ |
||
154 | ALX_HRTBT_EXT_CTRL = 0x1AD0 |
||
155 | L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK = 0x3F |
||
156 | L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT = 24 |
||
157 | L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN = (1 shl 23) |
||
158 | L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED = (1 shl 22) |
||
159 | L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED = (1 shl 21) |
||
160 | L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN = (1 shl 20) |
||
161 | L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN = (1 shl 19) |
||
162 | L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 = (1 shl 18) |
||
163 | L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 = (1 shl 17) |
||
164 | L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN = (1 shl 16) |
||
165 | L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN = (1 shl 15) |
||
166 | L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 = (1 shl 14) |
||
167 | L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 = (1 shl 13) |
||
168 | ALX_HRTBT_EXT_CTRL_NS_EN = (1 shl 12) |
||
169 | ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK = 0xFF |
||
170 | ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT = 4 |
||
171 | ALX_HRTBT_EXT_CTRL_IS_8023 = (1 shl 3) |
||
172 | ALX_HRTBT_EXT_CTRL_IS_IPV6 = (1 shl 2) |
||
173 | ALX_HRTBT_EXT_CTRL_WAKEUP_EN = (1 shl 1) |
||
174 | ALX_HRTBT_EXT_CTRL_ARP_EN = (1 shl 0) |
||
175 | |||
176 | ALX_HRTBT_REM_IPV4_ADDR = 0x1AD4 |
||
177 | ALX_HRTBT_HOST_IPV4_ADDR = 0x1478 |
||
178 | ALX_HRTBT_REM_IPV6_ADDR3 = 0x1AD8 |
||
179 | ALX_HRTBT_REM_IPV6_ADDR2 = 0x1ADC |
||
180 | ALX_HRTBT_REM_IPV6_ADDR1 = 0x1AE0 |
||
181 | ALX_HRTBT_REM_IPV6_ADDR0 = 0x1AE4 |
||
182 | |||
183 | ; 1B8C ~ 1B94 for C0+ |
||
184 | ALX_SWOI_ACER_CTRL = 0x1B8C |
||
185 | ALX_SWOI_ORIG_ACK_NAK_EN = (1 shl 20) |
||
186 | ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK = 0xFF |
||
187 | ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT = 12 |
||
188 | ALX_SWOI_ORIG_ACK_ADDR_MASK = 0xFFF |
||
189 | ALX_SWOI_ORIG_ACK_ADDR_SHIFT = 0 |
||
190 | |||
191 | ALX_SWOI_IOAC_CTRL_2 = 0x1B90 |
||
192 | ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK = 0xFF |
||
193 | ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT = 24 |
||
194 | ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK = 0xFFF |
||
195 | ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT = 12 |
||
196 | ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK = 0xFFF |
||
197 | ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT = 0 |
||
198 | |||
199 | ALX_SWOI_IOAC_CTRL_3 = 0x1B94 |
||
200 | ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK = 0xFF |
||
201 | ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT = 24 |
||
202 | ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK = 0xFFF |
||
203 | ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT = 12 |
||
204 | ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK = 0xFFF |
||
205 | ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT = 0 |
||
206 | |||
207 | ; for B0 |
||
208 | ALX_IDLE_DECISN_TIMER = 0x1474 |
||
209 | ; 1ms |
||
210 | ALX_IDLE_DECISN_TIMER_DEF = 0x400 |
||
211 | |||
212 | ALX_MAC_CTRL = 0x1480 |
||
213 | ALX_MAC_CTRL_FAST_PAUSE = (1 shl 31) |
||
214 | ALX_MAC_CTRL_WOLSPED_SWEN = (1 shl 30) |
||
215 | ; bit29: 1:legacy(hi5b), 0:marvl(lo5b) |
||
216 | ALX_MAC_CTRL_MHASH_ALG_HI5B = (1 shl 29) |
||
217 | ALX_MAC_CTRL_BRD_EN = (1 shl 26) |
||
218 | ALX_MAC_CTRL_MULTIALL_EN = (1 shl 25) |
||
219 | ALX_MAC_CTRL_SPEED_MASK = 0x3 |
||
220 | ALX_MAC_CTRL_SPEED_SHIFT = 20 |
||
221 | ALX_MAC_CTRL_SPEED_10_100 = 1 |
||
222 | ALX_MAC_CTRL_SPEED_1000 = 2 |
||
223 | ALX_MAC_CTRL_PROMISC_EN = (1 shl 15) |
||
224 | ALX_MAC_CTRL_VLANSTRIP = (1 shl 14) |
||
225 | ALX_MAC_CTRL_PRMBLEN_MASK = 0xF |
||
226 | ALX_MAC_CTRL_PRMBLEN_SHIFT = 10 |
||
227 | ALX_MAC_CTRL_PCRCE = (1 shl 7) |
||
228 | ALX_MAC_CTRL_CRCE = (1 shl 6) |
||
229 | ALX_MAC_CTRL_FULLD = (1 shl 5) |
||
230 | ALX_MAC_CTRL_RXFC_EN = (1 shl 3) |
||
231 | ALX_MAC_CTRL_TXFC_EN = (1 shl 2) |
||
232 | ALX_MAC_CTRL_RX_EN = (1 shl 1) |
||
233 | ALX_MAC_CTRL_TX_EN = (1 shl 0) |
||
234 | |||
235 | ALX_STAD0 = 0x1488 |
||
236 | ALX_STAD1 = 0x148C |
||
237 | |||
238 | ALX_HASH_TBL0 = 0x1490 |
||
239 | ALX_HASH_TBL1 = 0x1494 |
||
240 | |||
241 | ALX_MTU = 0x149C |
||
242 | ALX_MTU_JUMBO_TH = 1514 |
||
243 | ALX_MTU_STD_ALGN = 1536 |
||
244 | |||
245 | ALX_SRAM5 = 0x1524 |
||
246 | ALX_SRAM_RXF_LEN_MASK = 0xFFF |
||
247 | ALX_SRAM_RXF_LEN_SHIFT = 0 |
||
248 | ALX_SRAM_RXF_LEN_8K = (8*1024) |
||
249 | |||
250 | ALX_SRAM9 = 0x1534 |
||
251 | ALX_SRAM_LOAD_PTR = (1 shl 0) |
||
252 | |||
253 | ALX_RX_BASE_ADDR_HI = 0x1540 |
||
254 | |||
255 | ALX_TX_BASE_ADDR_HI = 0x1544 |
||
256 | |||
257 | ALX_RFD_ADDR_LO = 0x1550 |
||
258 | ALX_RFD_RING_SZ = 0x1560 |
||
259 | ALX_RFD_BUF_SZ = 0x1564 |
||
260 | |||
261 | ALX_RRD_ADDR_LO = 0x1568 |
||
262 | ALX_RRD_RING_SZ = 0x1578 |
||
263 | |||
264 | ; pri3: highest, pri0: lowest |
||
265 | ALX_TPD_PRI3_ADDR_LO = 0x14E4 |
||
266 | ALX_TPD_PRI2_ADDR_LO = 0x14E0 |
||
267 | ALX_TPD_PRI1_ADDR_LO = 0x157C |
||
268 | ALX_TPD_PRI0_ADDR_LO = 0x1580 |
||
269 | |||
270 | ; producer index is 16bit |
||
271 | ALX_TPD_PRI3_PIDX = 0x1618 |
||
272 | ALX_TPD_PRI2_PIDX = 0x161A |
||
273 | ALX_TPD_PRI1_PIDX = 0x15F0 |
||
274 | ALX_TPD_PRI0_PIDX = 0x15F2 |
||
275 | |||
276 | ; consumer index is 16bit |
||
277 | ALX_TPD_PRI3_CIDX = 0x161C |
||
278 | ALX_TPD_PRI2_CIDX = 0x161E |
||
279 | ALX_TPD_PRI1_CIDX = 0x15F4 |
||
280 | ALX_TPD_PRI0_CIDX = 0x15F6 |
||
281 | |||
282 | ALX_TPD_RING_SZ = 0x1584 |
||
283 | |||
284 | ALX_TXQ0 = 0x1590 |
||
285 | ALX_TXQ0_TXF_BURST_PREF_MASK = 0xFFFF |
||
286 | ALX_TXQ0_TXF_BURST_PREF_SHIFT = 16 |
||
287 | ALX_TXQ_TXF_BURST_PREF_DEF = 0x200 |
||
288 | ALX_TXQ0_LSO_8023_EN = (1 shl 7) |
||
289 | ALX_TXQ0_MODE_ENHANCE = (1 shl 6) |
||
290 | ALX_TXQ0_EN = (1 shl 5) |
||
291 | ALX_TXQ0_SUPT_IPOPT = (1 shl 4) |
||
292 | ALX_TXQ0_TPD_BURSTPREF_MASK = 0xF |
||
293 | ALX_TXQ0_TPD_BURSTPREF_SHIFT = 0 |
||
294 | ALX_TXQ_TPD_BURSTPREF_DEF = 5 |
||
295 | |||
296 | ALX_TXQ1 = 0x1594 |
||
297 | ; bit11: drop large packet, len > (rfd buf) |
||
298 | ALX_TXQ1_ERRLGPKT_DROP_EN = (1 shl 11) |
||
299 | ALX_TXQ1_JUMBO_TSO_TH = (7*1024) |
||
300 | |||
301 | ALX_RXQ0 = 0x15A0 |
||
302 | ALX_RXQ0_EN = (1 shl 31) |
||
303 | ALX_RXQ0_RSS_HASH_EN = (1 shl 29) |
||
304 | ALX_RXQ0_RSS_MODE_MASK = 0x3 |
||
305 | ALX_RXQ0_RSS_MODE_SHIFT = 26 |
||
306 | ALX_RXQ0_RSS_MODE_DIS = 0 |
||
307 | ALX_RXQ0_RSS_MODE_MQMI = 3 |
||
308 | ALX_RXQ0_NUM_RFD_PREF_MASK = 0x3F |
||
309 | ALX_RXQ0_NUM_RFD_PREF_SHIFT = 20 |
||
310 | ALX_RXQ0_NUM_RFD_PREF_DEF = 8 |
||
311 | ALX_RXQ0_IDT_TBL_SIZE_MASK = 0x1FF |
||
312 | ALX_RXQ0_IDT_TBL_SIZE_SHIFT = 8 |
||
313 | ALX_RXQ0_IDT_TBL_SIZE_DEF = 0x100 |
||
314 | ALX_RXQ0_IDT_TBL_SIZE_NORMAL = 128 |
||
315 | ALX_RXQ0_IPV6_PARSE_EN = (1 shl 7) |
||
316 | ALX_RXQ0_RSS_HSTYP_MASK = 0xF |
||
317 | ALX_RXQ0_RSS_HSTYP_SHIFT = 2 |
||
318 | ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN = (1 shl 5) |
||
319 | ALX_RXQ0_RSS_HSTYP_IPV6_EN = (1 shl 4) |
||
320 | ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN = (1 shl 3) |
||
321 | ALX_RXQ0_RSS_HSTYP_IPV4_EN = (1 shl 2) |
||
322 | ALX_RXQ0_RSS_HSTYP_ALL = (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN or ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN or ALX_RXQ0_RSS_HSTYP_IPV6_EN or ALX_RXQ0_RSS_HSTYP_IPV4_EN) |
||
323 | ALX_RXQ0_ASPM_THRESH_MASK = 0x3 |
||
324 | ALX_RXQ0_ASPM_THRESH_SHIFT = 0 |
||
325 | ALX_RXQ0_ASPM_THRESH_100M = 3 |
||
326 | |||
327 | ALX_RXQ2 = 0x15A8 |
||
328 | ALX_RXQ2_RXF_XOFF_THRESH_MASK = 0xFFF |
||
329 | ALX_RXQ2_RXF_XOFF_THRESH_SHIFT = 16 |
||
330 | ALX_RXQ2_RXF_XON_THRESH_MASK = 0xFFF |
||
331 | ALX_RXQ2_RXF_XON_THRESH_SHIFT = 0 |
||
332 | ; Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + |
||
333 | ; rx-packet(1522) + delay-of-link(64) |
||
334 | ; = 3212. |
||
335 | |||
336 | ALX_RXQ2_RXF_FLOW_CTRL_RSVD = 3212 |
||
337 | |||
338 | ALX_DMA = 0x15C0 |
||
339 | ALX_DMA_RCHNL_SEL_MASK = 0x3 |
||
340 | ALX_DMA_RCHNL_SEL_SHIFT = 26 |
||
341 | ALX_DMA_WDLY_CNT_MASK = 0xF |
||
342 | ALX_DMA_WDLY_CNT_SHIFT = 16 |
||
343 | ALX_DMA_WDLY_CNT_DEF = 4 |
||
344 | ALX_DMA_RDLY_CNT_MASK = 0x1F |
||
345 | ALX_DMA_RDLY_CNT_SHIFT = 11 |
||
346 | ALX_DMA_RDLY_CNT_DEF = 15 |
||
347 | ; bit10: 0:tpd with pri, 1: data |
||
348 | ALX_DMA_RREQ_PRI_DATA = (1 shl 10) |
||
349 | ALX_DMA_RREQ_BLEN_MASK = 0x7 |
||
350 | ALX_DMA_RREQ_BLEN_SHIFT = 4 |
||
351 | ALX_DMA_RORDER_MODE_MASK = 0x7 |
||
352 | ALX_DMA_RORDER_MODE_SHIFT = 0 |
||
353 | ALX_DMA_RORDER_MODE_OUT = 4 |
||
354 | |||
355 | ALX_WOL0 = 0x14A0 |
||
356 | ALX_WOL0_PME_LINK = (1 shl 5) |
||
357 | ALX_WOL0_LINK_EN = (1 shl 4) |
||
358 | ALX_WOL0_PME_MAGIC_EN = (1 shl 3) |
||
359 | ALX_WOL0_MAGIC_EN = (1 shl 2) |
||
360 | |||
361 | ; RFD Producer index |
||
362 | ALX_RFD_PIDX = 0x15E0 |
||
363 | |||
364 | ; RFD Consumer indef |
||
365 | ALX_RFD_CIDX = 0x15F8 |
||
366 | |||
367 | ; MIB |
||
368 | ALX_MIB_BASE = 0x1700 |
||
369 | |||
370 | ALX_MIB_RX_OK = (ALX_MIB_BASE + 0) |
||
371 | ALX_MIB_RX_BCAST = (ALX_MIB_BASE + 4) |
||
372 | ALX_MIB_RX_MCAST = (ALX_MIB_BASE + 8) |
||
373 | ALX_MIB_RX_PAUSE = (ALX_MIB_BASE + 12) |
||
374 | ALX_MIB_RX_CTRL = (ALX_MIB_BASE + 16) |
||
375 | ALX_MIB_RX_FCS_ERR = (ALX_MIB_BASE + 20) |
||
376 | ALX_MIB_RX_LEN_ERR = (ALX_MIB_BASE + 24) |
||
377 | ALX_MIB_RX_BYTE_CNT = (ALX_MIB_BASE + 28) |
||
378 | ALX_MIB_RX_RUNT = (ALX_MIB_BASE + 32) |
||
379 | ALX_MIB_RX_FRAG = (ALX_MIB_BASE + 36) |
||
380 | ALX_MIB_RX_SZ_64B = (ALX_MIB_BASE + 40) |
||
381 | ALX_MIB_RX_SZ_127B = (ALX_MIB_BASE + 44) |
||
382 | ALX_MIB_RX_SZ_255B = (ALX_MIB_BASE + 48) |
||
383 | ALX_MIB_RX_SZ_511B = (ALX_MIB_BASE + 52) |
||
384 | ALX_MIB_RX_SZ_1023B = (ALX_MIB_BASE + 56) |
||
385 | ALX_MIB_RX_SZ_1518B = (ALX_MIB_BASE + 60) |
||
386 | ALX_MIB_RX_SZ_MAX = (ALX_MIB_BASE + 64) |
||
387 | ALX_MIB_RX_OV_SZ = (ALX_MIB_BASE + 68) |
||
388 | ALX_MIB_RX_OV_RXF = (ALX_MIB_BASE + 72) |
||
389 | ALX_MIB_RX_OV_RRD = (ALX_MIB_BASE + 76) |
||
390 | ALX_MIB_RX_ALIGN_ERR = (ALX_MIB_BASE + 80) |
||
391 | ALX_MIB_RX_BCCNT = (ALX_MIB_BASE + 84) |
||
392 | ALX_MIB_RX_MCCNT = (ALX_MIB_BASE + 88) |
||
393 | ALX_MIB_RX_ERRADDR = (ALX_MIB_BASE + 92) |
||
394 | |||
395 | ALX_MIB_TX_OK = (ALX_MIB_BASE + 96) |
||
396 | ALX_MIB_TX_BCAST = (ALX_MIB_BASE + 100) |
||
397 | ALX_MIB_TX_MCAST = (ALX_MIB_BASE + 104) |
||
398 | ALX_MIB_TX_PAUSE = (ALX_MIB_BASE + 108) |
||
399 | ALX_MIB_TX_EXC_DEFER = (ALX_MIB_BASE + 112) |
||
400 | ALX_MIB_TX_CTRL = (ALX_MIB_BASE + 116) |
||
401 | ALX_MIB_TX_DEFER = (ALX_MIB_BASE + 120) |
||
402 | ALX_MIB_TX_BYTE_CNT = (ALX_MIB_BASE + 124) |
||
403 | ALX_MIB_TX_SZ_64B = (ALX_MIB_BASE + 128) |
||
404 | ALX_MIB_TX_SZ_127B = (ALX_MIB_BASE + 132) |
||
405 | ALX_MIB_TX_SZ_255B = (ALX_MIB_BASE + 136) |
||
406 | ALX_MIB_TX_SZ_511B = (ALX_MIB_BASE + 140) |
||
407 | ALX_MIB_TX_SZ_1023B = (ALX_MIB_BASE + 144) |
||
408 | ALX_MIB_TX_SZ_1518B = (ALX_MIB_BASE + 148) |
||
409 | ALX_MIB_TX_SZ_MAX = (ALX_MIB_BASE + 152) |
||
410 | ALX_MIB_TX_SINGLE_COL = (ALX_MIB_BASE + 156) |
||
411 | ALX_MIB_TX_MULTI_COL = (ALX_MIB_BASE + 160) |
||
412 | ALX_MIB_TX_LATE_COL = (ALX_MIB_BASE + 164) |
||
413 | ALX_MIB_TX_ABORT_COL = (ALX_MIB_BASE + 168) |
||
414 | ALX_MIB_TX_UNDERRUN = (ALX_MIB_BASE + 172) |
||
415 | ALX_MIB_TX_TRD_EOP = (ALX_MIB_BASE + 176) |
||
416 | ALX_MIB_TX_LEN_ERR = (ALX_MIB_BASE + 180) |
||
417 | ALX_MIB_TX_TRUNC = (ALX_MIB_BASE + 184) |
||
418 | ALX_MIB_TX_BCCNT = (ALX_MIB_BASE + 188) |
||
419 | ALX_MIB_TX_MCCNT = (ALX_MIB_BASE + 192) |
||
420 | ALX_MIB_UPDATE = (ALX_MIB_BASE + 196) |
||
421 | |||
422 | |||
423 | ALX_ISR = 0x1600 |
||
424 | ALX_ISR_DIS = (1 shl 31) |
||
425 | ALX_ISR_RX_Q7 = (1 shl 30) |
||
426 | ALX_ISR_RX_Q6 = (1 shl 29) |
||
427 | ALX_ISR_RX_Q5 = (1 shl 28) |
||
428 | ALX_ISR_RX_Q4 = (1 shl 27) |
||
429 | ALX_ISR_PCIE_LNKDOWN = (1 shl 26) |
||
430 | ALX_ISR_RX_Q3 = (1 shl 19) |
||
431 | ALX_ISR_RX_Q2 = (1 shl 18) |
||
432 | ALX_ISR_RX_Q1 = (1 shl 17) |
||
433 | ALX_ISR_RX_Q0 = (1 shl 16) |
||
434 | ALX_ISR_TX_Q0 = (1 shl 15) |
||
435 | ALX_ISR_PHY = (1 shl 12) |
||
436 | ALX_ISR_DMAW = (1 shl 10) |
||
437 | ALX_ISR_DMAR = (1 shl 9) |
||
438 | ALX_ISR_TXF_UR = (1 shl 8) |
||
439 | ALX_ISR_TX_Q3 = (1 shl 7) |
||
440 | ALX_ISR_TX_Q2 = (1 shl 6) |
||
441 | ALX_ISR_TX_Q1 = (1 shl 5) |
||
442 | ALX_ISR_RFD_UR = (1 shl 4) |
||
443 | ALX_ISR_RXF_OV = (1 shl 3) |
||
444 | ALX_ISR_MANU = (1 shl 2) |
||
445 | ALX_ISR_TIMER = (1 shl 1) |
||
446 | ALX_ISR_SMB = (1 shl 0) |
||
447 | |||
448 | ALX_IMR = 0x1604 |
||
449 | |||
450 | ; re-send assert msg if SW no response |
||
451 | ALX_INT_RETRIG = 0x1608 |
||
452 | ; 40ms |
||
453 | ALX_INT_RETRIG_TO = 20000 |
||
454 | |||
455 | ALX_SMB_TIMER = 0x15C4 |
||
456 | |||
457 | ALX_TINT_TPD_THRSHLD = 0x15C8 |
||
458 | |||
459 | ALX_TINT_TIMER = 0x15CC |
||
460 | |||
461 | ALX_CLK_GATE = 0x1814 |
||
462 | ALX_CLK_GATE_RXMAC = (1 shl 5) |
||
463 | ALX_CLK_GATE_TXMAC = (1 shl 4) |
||
464 | ALX_CLK_GATE_RXQ = (1 shl 3) |
||
465 | ALX_CLK_GATE_TXQ = (1 shl 2) |
||
466 | ALX_CLK_GATE_DMAR = (1 shl 1) |
||
467 | ALX_CLK_GATE_DMAW = (1 shl 0) |
||
468 | ALX_CLK_GATE_ALL = (ALX_CLK_GATE_RXMAC or ALX_CLK_GATE_TXMAC or ALX_CLK_GATE_RXQ or ALX_CLK_GATE_TXQ or ALX_CLK_GATE_DMAR or ALX_CLK_GATE_DMAW) |
||
469 | |||
470 | ; interop between drivers |
||
471 | ALX_DRV = 0x1804 |
||
472 | ALX_DRV_PHY_AUTO = (1 shl 28) |
||
473 | ALX_DRV_PHY_1000 = (1 shl 27) |
||
474 | ALX_DRV_PHY_100 = (1 shl 26) |
||
475 | ALX_DRV_PHY_10 = (1 shl 25) |
||
476 | ALX_DRV_PHY_DUPLEX = (1 shl 24) |
||
477 | ; bit23: adv Pause |
||
478 | ALX_DRV_PHY_PAUSE = (1 shl 23) |
||
479 | ; bit22: adv Asym Pause |
||
480 | ALX_DRV_PHY_MASK = 0xFF |
||
481 | ALX_DRV_PHY_SHIFT = 21 |
||
482 | ALX_DRV_PHY_UNKNOWN = 0 |
||
483 | |||
484 | ; flag of phy inited |
||
485 | ALX_PHY_INITED = 0x003F |
||
486 | |||
487 | ; reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection |
||
488 | ALX_WOL_CTRL2 = 0x1830 |
||
489 | ALX_WOL_CTRL2_DATA_STORE = (1 shl 3) |
||
490 | ALX_WOL_CTRL2_PTRN_EVT = (1 shl 2) |
||
491 | ALX_WOL_CTRL2_PME_PTRN_EN = (1 shl 1) |
||
492 | ALX_WOL_CTRL2_PTRN_EN = (1 shl 0) |
||
493 | |||
494 | ALX_WOL_CTRL3 = 0x1834 |
||
495 | ALX_WOL_CTRL3_PTRN_ADDR_MASK = 0xFFFFF |
||
496 | ALX_WOL_CTRL3_PTRN_ADDR_SHIFT = 0 |
||
497 | |||
498 | ALX_WOL_CTRL4 = 0x1838 |
||
499 | ALX_WOL_CTRL4_PT15_MATCH = (1 shl 31) |
||
500 | ALX_WOL_CTRL4_PT14_MATCH = (1 shl 30) |
||
501 | ALX_WOL_CTRL4_PT13_MATCH = (1 shl 29) |
||
502 | ALX_WOL_CTRL4_PT12_MATCH = (1 shl 28) |
||
503 | ALX_WOL_CTRL4_PT11_MATCH = (1 shl 27) |
||
504 | ALX_WOL_CTRL4_PT10_MATCH = (1 shl 26) |
||
505 | ALX_WOL_CTRL4_PT9_MATCH = (1 shl 25) |
||
506 | ALX_WOL_CTRL4_PT8_MATCH = (1 shl 24) |
||
507 | ALX_WOL_CTRL4_PT7_MATCH = (1 shl 23) |
||
508 | ALX_WOL_CTRL4_PT6_MATCH = (1 shl 22) |
||
509 | ALX_WOL_CTRL4_PT5_MATCH = (1 shl 21) |
||
510 | ALX_WOL_CTRL4_PT4_MATCH = (1 shl 20) |
||
511 | ALX_WOL_CTRL4_PT3_MATCH = (1 shl 19) |
||
512 | ALX_WOL_CTRL4_PT2_MATCH = (1 shl 18) |
||
513 | ALX_WOL_CTRL4_PT1_MATCH = (1 shl 17) |
||
514 | ALX_WOL_CTRL4_PT0_MATCH = (1 shl 16) |
||
515 | ALX_WOL_CTRL4_PT15_EN = (1 shl 15) |
||
516 | ALX_WOL_CTRL4_PT14_EN = (1 shl 14) |
||
517 | ALX_WOL_CTRL4_PT13_EN = (1 shl 13) |
||
518 | ALX_WOL_CTRL4_PT12_EN = (1 shl 12) |
||
519 | ALX_WOL_CTRL4_PT11_EN = (1 shl 11) |
||
520 | ALX_WOL_CTRL4_PT10_EN = (1 shl 10) |
||
521 | ALX_WOL_CTRL4_PT9_EN = (1 shl 9) |
||
522 | ALX_WOL_CTRL4_PT8_EN = (1 shl 8) |
||
523 | ALX_WOL_CTRL4_PT7_EN = (1 shl 7) |
||
524 | ALX_WOL_CTRL4_PT6_EN = (1 shl 6) |
||
525 | ALX_WOL_CTRL4_PT5_EN = (1 shl 5) |
||
526 | ALX_WOL_CTRL4_PT4_EN = (1 shl 4) |
||
527 | ALX_WOL_CTRL4_PT3_EN = (1 shl 3) |
||
528 | ALX_WOL_CTRL4_PT2_EN = (1 shl 2) |
||
529 | ALX_WOL_CTRL4_PT1_EN = (1 shl 1) |
||
530 | ALX_WOL_CTRL4_PT0_EN = (1 shl 0) |
||
531 | |||
532 | ALX_WOL_CTRL5 = 0x183C |
||
533 | ALX_WOL_CTRL5_PT3_LEN_MASK = 0xFF |
||
534 | ALX_WOL_CTRL5_PT3_LEN_SHIFT = 24 |
||
535 | ALX_WOL_CTRL5_PT2_LEN_MASK = 0xFF |
||
536 | ALX_WOL_CTRL5_PT2_LEN_SHIFT = 16 |
||
537 | ALX_WOL_CTRL5_PT1_LEN_MASK = 0xFF |
||
538 | ALX_WOL_CTRL5_PT1_LEN_SHIFT = 8 |
||
539 | ALX_WOL_CTRL5_PT0_LEN_MASK = 0xFF |
||
540 | ALX_WOL_CTRL5_PT0_LEN_SHIFT = 0 |
||
541 | |||
542 | ALX_WOL_CTRL6 = 0x1840 |
||
543 | ALX_WOL_CTRL5_PT7_LEN_MASK = 0xFF |
||
544 | ALX_WOL_CTRL5_PT7_LEN_SHIFT = 24 |
||
545 | ALX_WOL_CTRL5_PT6_LEN_MASK = 0xFF |
||
546 | ALX_WOL_CTRL5_PT6_LEN_SHIFT = 16 |
||
547 | ALX_WOL_CTRL5_PT5_LEN_MASK = 0xFF |
||
548 | ALX_WOL_CTRL5_PT5_LEN_SHIFT = 8 |
||
549 | ALX_WOL_CTRL5_PT4_LEN_MASK = 0xFF |
||
550 | ALX_WOL_CTRL5_PT4_LEN_SHIFT = 0 |
||
551 | |||
552 | ALX_WOL_CTRL7 = 0x1844 |
||
553 | ALX_WOL_CTRL5_PT11_LEN_MASK = 0xFF |
||
554 | ALX_WOL_CTRL5_PT11_LEN_SHIFT = 24 |
||
555 | ALX_WOL_CTRL5_PT10_LEN_MASK = 0xFF |
||
556 | ALX_WOL_CTRL5_PT10_LEN_SHIFT = 16 |
||
557 | ALX_WOL_CTRL5_PT9_LEN_MASK = 0xFF |
||
558 | ALX_WOL_CTRL5_PT9_LEN_SHIFT = 8 |
||
559 | ALX_WOL_CTRL5_PT8_LEN_MASK = 0xFF |
||
560 | ALX_WOL_CTRL5_PT8_LEN_SHIFT = 0 |
||
561 | |||
562 | ALX_WOL_CTRL8 = 0x1848 |
||
563 | ALX_WOL_CTRL5_PT15_LEN_MASK = 0xFF |
||
564 | ALX_WOL_CTRL5_PT15_LEN_SHIFT = 24 |
||
565 | ALX_WOL_CTRL5_PT14_LEN_MASK = 0xFF |
||
566 | ALX_WOL_CTRL5_PT14_LEN_SHIFT = 16 |
||
567 | ALX_WOL_CTRL5_PT13_LEN_MASK = 0xFF |
||
568 | ALX_WOL_CTRL5_PT13_LEN_SHIFT = 8 |
||
569 | ALX_WOL_CTRL5_PT12_LEN_MASK = 0xFF |
||
570 | ALX_WOL_CTRL5_PT12_LEN_SHIFT = 0 |
||
571 | |||
572 | ALX_ACER_FIXED_PTN0 = 0x1850 |
||
573 | ALX_ACER_FIXED_PTN0_MASK = 0xFFFFFFFF |
||
574 | ALX_ACER_FIXED_PTN0_SHIFT = 0 |
||
575 | |||
576 | ALX_ACER_FIXED_PTN1 = 0x1854 |
||
577 | ALX_ACER_FIXED_PTN1_MASK = 0xFFFF |
||
578 | ALX_ACER_FIXED_PTN1_SHIFT = 0 |
||
579 | |||
580 | ALX_ACER_RANDOM_NUM0 = 0x1858 |
||
581 | ALX_ACER_RANDOM_NUM0_MASK = 0xFFFFFFFF |
||
582 | ALX_ACER_RANDOM_NUM0_SHIFT = 0 |
||
583 | |||
584 | ALX_ACER_RANDOM_NUM1 = 0x185C |
||
585 | ALX_ACER_RANDOM_NUM1_MASK = 0xFFFFFFFF |
||
586 | ALX_ACER_RANDOM_NUM1_SHIFT = 0 |
||
587 | |||
588 | ALX_ACER_RANDOM_NUM2 = 0x1860 |
||
589 | ALX_ACER_RANDOM_NUM2_MASK = 0xFFFFFFFF |
||
590 | ALX_ACER_RANDOM_NUM2_SHIFT = 0 |
||
591 | |||
592 | ALX_ACER_RANDOM_NUM3 = 0x1864 |
||
593 | ALX_ACER_RANDOM_NUM3_MASK = 0xFFFFFFFF |
||
594 | ALX_ACER_RANDOM_NUM3_SHIFT = 0 |
||
595 | |||
596 | ALX_ACER_MAGIC = 0x1868 |
||
597 | ALX_ACER_MAGIC_EN = (1 shl 31) |
||
598 | ALX_ACER_MAGIC_PME_EN = (1 shl 30) |
||
599 | ALX_ACER_MAGIC_MATCH = (1 shl 29) |
||
600 | ALX_ACER_MAGIC_FF_CHECK = (1 shl 10) |
||
601 | ALX_ACER_MAGIC_RAN_LEN_MASK = 0x1F |
||
602 | ALX_ACER_MAGIC_RAN_LEN_SHIFT = 5 |
||
603 | ALX_ACER_MAGIC_FIX_LEN_MASK = 0x1F |
||
604 | ALX_ACER_MAGIC_FIX_LEN_SHIFT = 0 |
||
605 | |||
606 | ALX_ACER_TIMER = 0x186C |
||
607 | ALX_ACER_TIMER_EN = (1 shl 31) |
||
608 | ALX_ACER_TIMER_PME_EN = (1 shl 30) |
||
609 | ALX_ACER_TIMER_MATCH = (1 shl 29) |
||
610 | ALX_ACER_TIMER_THRES_MASK = 0x1FFFF |
||
611 | ALX_ACER_TIMER_THRES_SHIFT = 0 |
||
612 | ALX_ACER_TIMER_THRES_DEF = 1 |
||
613 | |||
614 | ; RSS definitions |
||
615 | ALX_RSS_KEY0 = 0x14B0 |
||
616 | ALX_RSS_KEY1 = 0x14B4 |
||
617 | ALX_RSS_KEY2 = 0x14B8 |
||
618 | ALX_RSS_KEY3 = 0x14BC |
||
619 | ALX_RSS_KEY4 = 0x14C0 |
||
620 | ALX_RSS_KEY5 = 0x14C4 |
||
621 | ALX_RSS_KEY6 = 0x14C8 |
||
622 | ALX_RSS_KEY7 = 0x14CC |
||
623 | ALX_RSS_KEY8 = 0x14D0 |
||
624 | ALX_RSS_KEY9 = 0x14D4 |
||
625 | |||
626 | ALX_RSS_IDT_TBL0 = 0x1B00 |
||
627 | |||
628 | ALX_MSI_MAP_TBL1 = 0x15D0 |
||
629 | ALX_MSI_MAP_TBL1_TXQ1_SHIFT = 20 |
||
630 | ALX_MSI_MAP_TBL1_TXQ0_SHIFT = 16 |
||
631 | ALX_MSI_MAP_TBL1_RXQ3_SHIFT = 12 |
||
632 | ALX_MSI_MAP_TBL1_RXQ2_SHIFT = 8 |
||
633 | ALX_MSI_MAP_TBL1_RXQ1_SHIFT = 4 |
||
634 | ALX_MSI_MAP_TBL1_RXQ0_SHIFT = 0 |
||
635 | |||
636 | ALX_MSI_MAP_TBL2 = 0x15D8 |
||
637 | ALX_MSI_MAP_TBL2_TXQ3_SHIFT = 20 |
||
638 | ALX_MSI_MAP_TBL2_TXQ2_SHIFT = 16 |
||
639 | ALX_MSI_MAP_TBL2_RXQ7_SHIFT = 12 |
||
640 | ALX_MSI_MAP_TBL2_RXQ6_SHIFT = 8 |
||
641 | ALX_MSI_MAP_TBL2_RXQ5_SHIFT = 4 |
||
642 | ALX_MSI_MAP_TBL2_RXQ4_SHIFT = 0 |
||
643 | |||
644 | ALX_MSI_ID_MAP = 0x15D4 |
||
645 | |||
646 | ALX_MSI_RETRANS_TIMER = 0x1920 |
||
647 | ; bit16: 1:line,0:standard |
||
648 | ALX_MSI_MASK_SEL_LINE = (1 shl 16) |
||
649 | ALX_MSI_RETRANS_TM_MASK = 0xFFFF |
||
650 | ALX_MSI_RETRANS_TM_SHIFT = 0 |
||
651 | |||
652 | ; CR DMA ctrl |
||
653 | |||
654 | ; TX QoS |
||
655 | ALX_WRR = 0x1938 |
||
656 | ALX_WRR_PRI_MASK = 0x3 |
||
657 | ALX_WRR_PRI_SHIFT = 29 |
||
658 | ALX_WRR_PRI_RESTRICT_NONE = 3 |
||
659 | ALX_WRR_PRI3_MASK = 0x1F |
||
660 | ALX_WRR_PRI3_SHIFT = 24 |
||
661 | ALX_WRR_PRI2_MASK = 0x1F |
||
662 | ALX_WRR_PRI2_SHIFT = 16 |
||
663 | ALX_WRR_PRI1_MASK = 0x1F |
||
664 | ALX_WRR_PRI1_SHIFT = 8 |
||
665 | ALX_WRR_PRI0_MASK = 0x1F |
||
666 | ALX_WRR_PRI0_SHIFT = 0 |
||
667 | |||
668 | ALX_HQTPD = 0x193C |
||
669 | ALX_HQTPD_BURST_EN = (1 shl 31) |
||
670 | ALX_HQTPD_Q3_NUMPREF_MASK = 0xF |
||
671 | ALX_HQTPD_Q3_NUMPREF_SHIFT = 8 |
||
672 | ALX_HQTPD_Q2_NUMPREF_MASK = 0xF |
||
673 | ALX_HQTPD_Q2_NUMPREF_SHIFT = 4 |
||
674 | ALX_HQTPD_Q1_NUMPREF_MASK = 0xF |
||
675 | ALX_HQTPD_Q1_NUMPREF_SHIFT = 0 |
||
676 | |||
677 | ALX_MISC = 0x19C0 |
||
678 | ALX_MISC_PSW_OCP_MASK = 0x7 |
||
679 | ALX_MISC_PSW_OCP_SHIFT = 21 |
||
680 | ALX_MISC_PSW_OCP_DEF = 0x7 |
||
681 | ALX_MISC_ISO_EN = (1 shl 12) |
||
682 | ALX_MISC_INTNLOSC_OPEN = (1 shl 3) |
||
683 | |||
684 | ALX_MSIC2 = 0x19C8 |
||
685 | ALX_MSIC2_CALB_START = (1 shl 0) |
||
686 | |||
687 | ALX_MISC3 = 0x19CC |
||
688 | ; bit1: 1:Software control 25M |
||
689 | ALX_MISC3_25M_BY_SW = (1 shl 1) |
||
690 | ; bit0: 25M switch to intnl OSC |
||
691 | ALX_MISC3_25M_NOTO_INTNL = (1 shl 0) |
||
692 | |||
693 | ; MSIX tbl in memory space |
||
694 | ALX_MSIX_ENTRY_BASE = 0x2000 |
||
695 | |||
696 | ;******************** PHY regs definition;************************** |
||
697 | |||
698 | ; PHY Specific Status Register |
||
699 | ALX_MII_GIGA_PSSR = 0x11 |
||
700 | ALX_GIGA_PSSR_SPD_DPLX_RESOLVED = 0x0800 |
||
701 | ALX_GIGA_PSSR_DPLX = 0x2000 |
||
702 | ALX_GIGA_PSSR_SPEED = 0xC000 |
||
703 | ALX_GIGA_PSSR_10MBS = 0x0000 |
||
704 | ALX_GIGA_PSSR_100MBS = 0x4000 |
||
705 | ALX_GIGA_PSSR_1000MBS = 0x8000 |
||
706 | |||
707 | ; PHY Interrupt Enable Register |
||
708 | ALX_MII_IER = 0x12 |
||
709 | ALX_IER_LINK_UP = 0x0400 |
||
710 | ALX_IER_LINK_DOWN = 0x0800 |
||
711 | |||
712 | ; PHY Interrupt Status Register |
||
713 | ALX_MII_ISR = 0x13 |
||
714 | |||
715 | ALX_MII_DBG_ADDR = 0x1D |
||
716 | ALX_MII_DBG_DATA = 0x1E |
||
717 | |||
718 | ;**************************** debug port;************************************ |
||
719 | |||
720 | ALX_MIIDBG_ANACTRL = 0x00 |
||
721 | ALX_ANACTRL_DEF = 0x02EF |
||
722 | |||
723 | ALX_MIIDBG_SYSMODCTRL = 0x04 |
||
724 | ; en half bias |
||
725 | ALX_SYSMODCTRL_IECHOADJ_DEF = 0xBB8B |
||
726 | |||
727 | ALX_MIIDBG_SRDSYSMOD = 0x05 |
||
728 | ALX_SRDSYSMOD_DEEMP_EN = 0x0040 |
||
729 | ALX_SRDSYSMOD_DEF = 0x2C46 |
||
730 | |||
731 | ALX_MIIDBG_HIBNEG = 0x0B |
||
732 | ALX_HIBNEG_PSHIB_EN = 0x8000 |
||
733 | ALX_HIBNEG_HIB_PSE = 0x1000 |
||
734 | ALX_HIBNEG_DEF = 0xBC40 |
||
735 | ALX_HIBNEG_NOHIB = (ALX_HIBNEG_DEF and not(ALX_HIBNEG_PSHIB_EN or ALX_HIBNEG_HIB_PSE)) |
||
736 | |||
737 | ALX_MIIDBG_TST10BTCFG = 0x12 |
||
738 | ALX_TST10BTCFG_DEF = 0x4C04 |
||
739 | |||
740 | ALX_MIIDBG_AZ_ANADECT = 0x15 |
||
741 | ALX_AZ_ANADECT_DEF = 0x3220 |
||
742 | ALX_AZ_ANADECT_LONG = 0x3210 |
||
743 | |||
744 | ALX_MIIDBG_MSE16DB = 0x18 |
||
745 | ALX_MSE16DB_UP = 0x05EA |
||
746 | ALX_MSE16DB_DOWN = 0x02EA |
||
747 | |||
748 | ALX_MIIDBG_MSE20DB = 0x1C |
||
749 | ALX_MSE20DB_TH_MASK = 0x7F |
||
750 | ALX_MSE20DB_TH_SHIFT = 2 |
||
751 | ALX_MSE20DB_TH_DEF = 0x2E |
||
752 | ALX_MSE20DB_TH_HI = 0x54 |
||
753 | |||
754 | ALX_MIIDBG_AGC = 0x23 |
||
755 | ALX_AGC_2_VGA_MASK = 0x3F |
||
756 | ALX_AGC_2_VGA_SHIFT = 8 |
||
757 | ALX_AGC_LONG1G_LIMT = 40 |
||
758 | ALX_AGC_LONG100M_LIMT = 44 |
||
759 | |||
760 | ALX_MIIDBG_LEGCYPS = 0x29 |
||
761 | ALX_LEGCYPS_EN = 0x8000 |
||
762 | ALX_LEGCYPS_DEF = 0x129D |
||
763 | |||
764 | ALX_MIIDBG_TST100BTCFG = 0x36 |
||
765 | ALX_TST100BTCFG_DEF = 0xE12C |
||
766 | |||
767 | ALX_MIIDBG_GREENCFG = 0x3B |
||
768 | ALX_GREENCFG_DEF = 0x7078 |
||
769 | |||
770 | ALX_MIIDBG_GREENCFG2 = 0x3D |
||
771 | ALX_GREENCFG2_BP_GREEN = 0x8000 |
||
772 | ALX_GREENCFG2_GATE_DFSE_EN = 0x0080 |
||
773 | |||
774 | ;****** dev 3;******** |
||
775 | ALX_MIIEXT_PCS = 3 |
||
776 | |||
777 | ALX_MIIEXT_CLDCTRL3 = 0x8003 |
||
778 | ALX_CLDCTRL3_BP_CABLE1TH_DET_GT = 0x8000 |
||
779 | |||
780 | ALX_MIIEXT_CLDCTRL5 = 0x8005 |
||
781 | ALX_CLDCTRL5_BP_VD_HLFBIAS = 0x4000 |
||
782 | |||
783 | ALX_MIIEXT_CLDCTRL6 = 0x8006 |
||
784 | ALX_CLDCTRL6_CAB_LEN_MASK = 0xFF |
||
785 | ALX_CLDCTRL6_CAB_LEN_SHIFT = 0 |
||
786 | ALX_CLDCTRL6_CAB_LEN_SHORT1G = 116 |
||
787 | ALX_CLDCTRL6_CAB_LEN_SHORT100M = 152 |
||
788 | |||
789 | ALX_MIIEXT_VDRVBIAS = 0x8062 |
||
790 | ALX_VDRVBIAS_DEF = 0x3 |
||
791 | |||
792 | ;******** dev 7;********* |
||
793 | ALX_MIIEXT_ANEG = 7 |
||
794 | |||
795 | ALX_MIIEXT_LOCAL_EEEADV = 0x3C |
||
796 | ALX_LOCAL_EEEADV_1000BT = 0x0004 |
||
797 | ALX_LOCAL_EEEADV_100BT = 0x0002 |
||
798 | |||
799 | ALX_MIIEXT_AFE = 0x801A |
||
800 | ALX_AFE_10BT_100M_TH = 0x0040 |
||
801 | |||
802 | ALX_MIIEXT_S3DIG10 = 0x8023 |
||
803 | ; bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx |
||
804 | ALX_MIIEXT_S3DIG10_SL = 0x0001 |
||
805 | ALX_MIIEXT_S3DIG10_DEF = 0 |
||
806 | |||
807 | ALX_MIIEXT_NLP78 = 0x8027 |
||
808 | ALX_MIIEXT_NLP78_120M_DEF = 0x8A05 |
||
809 | |||
810 | |||
811 | ; tpd word 1 |
||
812 | TPD_CXSUMSTART_MASK = 0x00FF |
||
813 | TPD_CXSUMSTART_SHIFT = 0 |
||
814 | TPD_L4HDROFFSET_MASK = 0x00FF |
||
815 | TPD_L4HDROFFSET_SHIFT = 0 |
||
816 | TPD_CXSUM_EN_MASK = 0x0001 |
||
817 | TPD_CXSUM_EN_SHIFT = 8 |
||
818 | TPD_IP_XSUM_MASK = 0x0001 |
||
819 | TPD_IP_XSUM_SHIFT = 9 |
||
820 | TPD_TCP_XSUM_MASK = 0x0001 |
||
821 | TPD_TCP_XSUM_SHIFT = 10 |
||
822 | TPD_UDP_XSUM_MASK = 0x0001 |
||
823 | TPD_UDP_XSUM_SHIFT = 11 |
||
824 | TPD_LSO_EN_MASK = 0x0001 |
||
825 | TPD_LSO_EN_SHIFT = 12 |
||
826 | TPD_LSO_V2_MASK = 0x0001 |
||
827 | TPD_LSO_V2_SHIFT = 13 |
||
828 | TPD_VLTAGGED_MASK = 0x0001 |
||
829 | TPD_VLTAGGED_SHIFT = 14 |
||
830 | TPD_INS_VLTAG_MASK = 0x0001 |
||
831 | TPD_INS_VLTAG_SHIFT = 15 |
||
832 | TPD_IPV4_MASK = 0x0001 |
||
833 | TPD_IPV4_SHIFT = 16 |
||
834 | TPD_ETHTYPE_MASK = 0x0001 |
||
835 | TPD_ETHTYPE_SHIFT = 17 |
||
836 | TPD_CXSUMOFFSET_MASK = 0x00FF |
||
837 | TPD_CXSUMOFFSET_SHIFT = 18 |
||
838 | TPD_MSS_MASK = 0x1FFF |
||
839 | TPD_MSS_SHIFT = 18 |
||
840 | TPD_EOP_MASK = 0x0001 |
||
841 | TPD_EOP_SHIFT = 31 |
||
842 | |||
843 | |||
844 | ; rrd word 0 |
||
845 | RRD_XSUM_MASK = 0xFFFF |
||
846 | RRD_XSUM_SHIFT = 0 |
||
847 | RRD_NOR_MASK = 0x000F |
||
848 | RRD_NOR_SHIFT = 16 |
||
849 | RRD_SI_MASK = 0x0FFF |
||
850 | RRD_SI_SHIFT = 20 |
||
851 | |||
852 | ; rrd word 2 |
||
853 | RRD_VLTAG_MASK = 0xFFFF |
||
854 | RRD_VLTAG_SHIFT = 0 |
||
855 | RRD_PID_MASK = 0x00FF |
||
856 | RRD_PID_SHIFT = 16 |
||
857 | ; non-ip packet |
||
858 | RRD_PID_NONIP = 0 |
||
859 | ; ipv4(only) |
||
860 | RRD_PID_IPV4 = 1 |
||
861 | ; tcp/ipv6 |
||
862 | RRD_PID_IPV6TCP = 2 |
||
863 | ; tcp/ipv4 |
||
864 | RRD_PID_IPV4TCP = 3 |
||
865 | ; udp/ipv6 |
||
866 | RRD_PID_IPV6UDP = 4 |
||
867 | ; udp/ipv4 |
||
868 | RRD_PID_IPV4UDP = 5 |
||
869 | ; ipv6(only) |
||
870 | RRD_PID_IPV6 = 6 |
||
871 | ; LLDP packet |
||
872 | RRD_PID_LLDP = 7 |
||
873 | ; 1588 packet |
||
874 | RRD_PID_1588 = 8 |
||
875 | RRD_RSSQ_MASK = 0x0007 |
||
876 | RRD_RSSQ_SHIFT = 25 |
||
877 | RRD_RSSALG_MASK = 0x000F |
||
878 | RRD_RSSALG_SHIFT = 28 |
||
879 | RRD_RSSALG_TCPV6 = 0x1 |
||
880 | RRD_RSSALG_IPV6 = 0x2 |
||
881 | RRD_RSSALG_TCPV4 = 0x4 |
||
882 | RRD_RSSALG_IPV4 = 0x8 |
||
883 | |||
884 | ; rrd word 3 |
||
885 | RRD_PKTLEN_MASK = 0x3FFF |
||
886 | RRD_PKTLEN_SHIFT = 0 |
||
887 | RRD_ERR_L4_MASK = 0x0001 |
||
888 | RRD_ERR_L4_SHIFT = 14 |
||
889 | RRD_ERR_IPV4_MASK = 0x0001 |
||
890 | RRD_ERR_IPV4_SHIFT = 15 |
||
891 | RRD_VLTAGGED_MASK = 0x0001 |
||
892 | RRD_VLTAGGED_SHIFT = 16 |
||
893 | RRD_OLD_PID_MASK = 0x0007 |
||
894 | RRD_OLD_PID_SHIFT = 17 |
||
895 | RRD_ERR_RES_MASK = 0x0001 |
||
896 | RRD_ERR_RES_SHIFT = 20 |
||
897 | RRD_ERR_FCS_MASK = 0x0001 |
||
898 | RRD_ERR_FCS_SHIFT = 21 |
||
899 | RRD_ERR_FAE_MASK = 0x0001 |
||
900 | RRD_ERR_FAE_SHIFT = 22 |
||
901 | RRD_ERR_TRUNC_MASK = 0x0001 |
||
902 | RRD_ERR_TRUNC_SHIFT = 23 |
||
903 | RRD_ERR_RUNT_MASK = 0x0001 |
||
904 | RRD_ERR_RUNT_SHIFT = 24 |
||
905 | RRD_ERR_ICMP_MASK = 0x0001 |
||
906 | RRD_ERR_ICMP_SHIFT = 25 |
||
907 | RRD_BCAST_MASK = 0x0001 |
||
908 | RRD_BCAST_SHIFT = 26 |
||
909 | RRD_MCAST_MASK = 0x0001 |
||
910 | RRD_MCAST_SHIFT = 27 |
||
911 | RRD_ETHTYPE_MASK = 0x0001 |
||
912 | RRD_ETHTYPE_SHIFT = 28 |
||
913 | RRD_ERR_FIFOV_MASK = 0x0001 |
||
914 | RRD_ERR_FIFOV_SHIFT = 29 |
||
915 | RRD_ERR_LEN_MASK = 0x0001 |
||
916 | RRD_ERR_LEN_SHIFT = 30 |
||
917 | RRD_UPDATED_MASK = 0x0001 |
||
918 | RRD_UPDATED_SHIFT = 31 |
||
919 | |||
920 | |||
921 | ALX_ISR_MISC = ALX_ISR_PCIE_LNKDOWN or ALX_ISR_DMAW or ALX_ISR_DMAR or ALX_ISR_SMB or ALX_ISR_MANU or ALX_ISR_TIMER |
||
922 | |||
923 | ALX_ISR_FATAL = ALX_ISR_PCIE_LNKDOWN or ALX_ISR_DMAW or ALX_ISR_DMAR |
||
924 | |||
925 | ALX_ISR_ALERT = ALX_ISR_RXF_OV or ALX_ISR_TXF_UR or ALX_ISR_RFD_UR |
||
926 | |||
927 | ALX_ISR_ALL_QUEUES = ALX_ISR_TX_Q0 or ALX_ISR_TX_Q1 or ALX_ISR_TX_Q2 or ALX_ISR_TX_Q3 or ALX_ISR_RX_Q0 or ALX_ISR_RX_Q1 or ALX_ISR_RX_Q2 or ALX_ISR_RX_Q3 or ALX_ISR_RX_Q4 or ALX_ISR_RX_Q5 or ALX_ISR_RX_Q6 or ALX_ISR_RX_Q7 |