WebSVN – Kolibri OS – Blame – /drivers/ethernet/ar81xx.inc

Rev	Author	Line No.	Line
7809	hidnplayr	1	ALX_DEV_ID_AR8161 = 0x1091
		2	ALX_DEV_ID_E2200 = 0xe091
		3	ALX_DEV_ID_E2400 = 0xe0a1
		4	ALX_DEV_ID_E2500 = 0xe0b1
		5	ALX_DEV_ID_AR8162 = 0x1090
		6	ALX_DEV_ID_AR8171 = 0x10A1
		7	ALX_DEV_ID_AR8172 = 0x10A0
		8
		9	; rev definition,
		10	; bit0: with xD support
		11	; bit1: with Card Reader function
		12	; bit(7:2): real revision
		13
		14	ALX_PCI_REVID_SHIFT = 3
		15	ALX_REV_A0 = 0
		16	ALX_REV_A1 = 1
		17	ALX_REV_B0 = 2
		18	ALX_REV_C0 = 3
		19
		20	ALX_DEV_CTRL = 0x0060
		21	ALX_DEV_CTRL_MAXRRS_MIN = 2
		22
		23	ALX_MSIX_MASK = 0x0090
		24
		25	ALX_UE_SVRT = 0x010C
		26	ALX_UE_SVRT_FCPROTERR = (1 shl 13)
		27	ALX_UE_SVRT_DLPROTERR = (1 shl 4)
		28
		29	; eeprom & flash load register
		30	ALX_EFLD = 0x0204
		31	ALX_EFLD_F_EXIST = (1 shl 10)
		32	ALX_EFLD_E_EXIST = (1 shl 9)
		33	ALX_EFLD_STAT = (1 shl 5)
		34	ALX_EFLD_START = (1 shl 0)
		35
		36	; eFuse load register
		37	ALX_SLD = 0x0218
		38	ALX_SLD_STAT = (1 shl 12)
		39	ALX_SLD_START = (1 shl 11)
		40	ALX_SLD_MAX_TO = 100
		41
		42	ALX_PDLL_TRNS1 = 0x1104
		43	ALX_PDLL_TRNS1_D3PLLOFF_EN = (1 shl 11)
		44
		45	ALX_PMCTRL = 0x12F8
		46	ALX_PMCTRL_HOTRST_WTEN = (1 shl 31)
		47	; bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0)
		48	ALX_PMCTRL_ASPM_FCEN = (1 shl 30)
		49	ALX_PMCTRL_SADLY_EN = (1 shl 29)
		50	ALX_PMCTRL_LCKDET_TIMER_MASK = 0xF
		51	ALX_PMCTRL_LCKDET_TIMER_SHIFT = 24
		52	ALX_PMCTRL_LCKDET_TIMER_DEF = 0xC
		53	; bit[23:20] if pm_request_l1 time > @, then enter L0s not L1
		54	ALX_PMCTRL_L1REQ_TO_MASK = 0xF
		55	ALX_PMCTRL_L1REQ_TO_SHIFT = 20
		56	ALX_PMCTRL_L1REG_TO_DEF = 0xF
		57	ALX_PMCTRL_TXL1_AFTER_L0S = (1 shl 19)
		58	ALX_PMCTRL_L1_TIMER_MASK = 0x7
		59	ALX_PMCTRL_L1_TIMER_SHIFT = 16
		60	ALX_PMCTRL_L1_TIMER_16US = 4
		61	ALX_PMCTRL_RCVR_WT_1US = (1 shl 15)
		62	; bit13: enable pcie clk switch in L1 state
		63	ALX_PMCTRL_L1_CLKSW_EN = (1 shl 13)
		64	ALX_PMCTRL_L0S_EN = (1 shl 12)
		65	ALX_PMCTRL_RXL1_AFTER_L0S = (1 shl 11)
		66	ALX_PMCTRL_L1_BUFSRX_EN = (1 shl 7)
		67	; bit6: power down serdes RX
		68	ALX_PMCTRL_L1_SRDSRX_PWD = (1 shl 6)
		69	ALX_PMCTRL_L1_SRDSPLL_EN = (1 shl 5)
		70	ALX_PMCTRL_L1_SRDS_EN = (1 shl 4)
		71	ALX_PMCTRL_L1_EN = (1 shl 3)
		72
		73	;******************************************************
		74	; following registers are mapped only to memory space
		75	;******************************************************
		76
		77	ALX_MASTER = 0x1400
		78	; bit12: 1:alwys select pclk from serdes, not sw to 25M
		79	ALX_MASTER_PCLKSEL_SRDS = (1 shl 12)
		80	; bit11: irq moduration for rx
		81	ALX_MASTER_IRQMOD2_EN = (1 shl 11)
		82	; bit10: irq moduration for tx/rx
		83	ALX_MASTER_IRQMOD1_EN = (1 shl 10)
		84	ALX_MASTER_SYSALVTIMER_EN = (1 shl 7)
		85	ALX_MASTER_OOB_DIS = (1 shl 6)
		86	; bit5: wakeup without pcie clk
		87	ALX_MASTER_WAKEN_25M = (1 shl 5)
		88	; bit0: MAC & DMA reset
		89	ALX_MASTER_DMA_MAC_RST = (1 shl 0)
		90	ALX_DMA_MAC_RST_TO = 50
		91
		92	ALX_IRQ_MODU_TIMER = 0x1408
		93	ALX_IRQ_MODU_TIMER1_MASK = 0xFFFF
		94	ALX_IRQ_MODU_TIMER1_SHIFT = 0
		95
		96	ALX_PHY_CTRL = 0x140C
		97	ALX_PHY_CTRL_100AB_EN = (1 shl 17)
		98	; bit14: affect MAC & PHY, go to low power sts
		99	ALX_PHY_CTRL_POWER_DOWN = (1 shl 14)
		100	; bit13: 1:pll always ON, 0:can switch in lpw
		101	ALX_PHY_CTRL_PLL_ON = (1 shl 13)
		102	ALX_PHY_CTRL_RST_ANALOG = (1 shl 12)
		103	ALX_PHY_CTRL_HIB_PULSE = (1 shl 11)
		104	ALX_PHY_CTRL_HIB_EN = (1 shl 10)
		105	ALX_PHY_CTRL_IDDQ = (1 shl 7)
		106	ALX_PHY_CTRL_GATE_25M = (1 shl 5)
		107	ALX_PHY_CTRL_LED_MODE = (1 shl 2)
		108	; bit0: out of dsp RST state
		109	ALX_PHY_CTRL_DSPRST_OUT = (1 shl 0)
		110	ALX_PHY_CTRL_DSPRST_TO = 80
		111	ALX_PHY_CTRL_CLS = (ALX_PHY_CTRL_LED_MODE or ALX_PHY_CTRL_100AB_EN or ALX_PHY_CTRL_PLL_ON)
		112
		113	ALX_MAC_STS = 0x1410
		114	ALX_MAC_STS_TXQ_BUSY = (1 shl 3)
		115	ALX_MAC_STS_RXQ_BUSY = (1 shl 2)
		116	ALX_MAC_STS_TXMAC_BUSY = (1 shl 1)
		117	ALX_MAC_STS_RXMAC_BUSY = (1 shl 0)
		118	ALX_MAC_STS_IDLE = (ALX_MAC_STS_TXQ_BUSY or ALX_MAC_STS_RXQ_BUSY or ALX_MAC_STS_TXMAC_BUSY or ALX_MAC_STS_RXMAC_BUSY)
		119
		120	ALX_MDIO = 0x1414
		121	ALX_MDIO_MODE_EXT = (1 shl 30)
		122	ALX_MDIO_BUSY = (1 shl 27)
		123	ALX_MDIO_CLK_SEL_MASK = 0x7
		124	ALX_MDIO_CLK_SEL_SHIFT = 24
		125	ALX_MDIO_CLK_SEL_25MD4 = 0
		126	ALX_MDIO_CLK_SEL_25MD128 = 7
		127	ALX_MDIO_START = (1 shl 23)
		128	ALX_MDIO_SPRES_PRMBL = (1 shl 22)
		129	; bit21: 1:read,0:write
		130	ALX_MDIO_OP_READ = (1 shl 21)
		131	ALX_MDIO_REG_MASK = 0x1F
		132	ALX_MDIO_REG_SHIFT = 16
		133	ALX_MDIO_DATA_MASK = 0xFFFF
		134	ALX_MDIO_DATA_SHIFT = 0
		135	ALX_MDIO_MAX_AC_TO = 120
		136
		137	ALX_MDIO_EXTN = 0x1448
		138	ALX_MDIO_EXTN_DEVAD_MASK = 0x1F
		139	ALX_MDIO_EXTN_DEVAD_SHIFT = 16
		140	ALX_MDIO_EXTN_REG_MASK = 0xFFFF
		141	ALX_MDIO_EXTN_REG_SHIFT = 0
		142
		143	ALX_SERDES = 0x1424
		144	ALX_SERDES_PHYCLK_SLWDWN = (1 shl 18)
		145	ALX_SERDES_MACCLK_SLWDWN = (1 shl 17)
		146
		147	ALX_LPI_CTRL = 0x1440
		148	ALX_LPI_CTRL_EN = (1 shl 0)
		149
		150	; for B0+, bit[13..] for C0+
		151	ALX_HRTBT_EXT_CTRL = 0x1AD0
		152	L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK = 0x3F
		153	L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT = 24
		154	L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN = (1 shl 23)
		155	L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED = (1 shl 22)
		156	L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED = (1 shl 21)
		157	L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN = (1 shl 20)
		158	L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN = (1 shl 19)
		159	L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 = (1 shl 18)
		160	L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 = (1 shl 17)
		161	L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN = (1 shl 16)
		162	L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN = (1 shl 15)
		163	L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 = (1 shl 14)
		164	L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 = (1 shl 13)
		165	ALX_HRTBT_EXT_CTRL_NS_EN = (1 shl 12)
		166	ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK = 0xFF
		167	ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT = 4
		168	ALX_HRTBT_EXT_CTRL_IS_8023 = (1 shl 3)
		169	ALX_HRTBT_EXT_CTRL_IS_IPV6 = (1 shl 2)
		170	ALX_HRTBT_EXT_CTRL_WAKEUP_EN = (1 shl 1)
		171	ALX_HRTBT_EXT_CTRL_ARP_EN = (1 shl 0)
		172
		173	ALX_HRTBT_REM_IPV4_ADDR = 0x1AD4
		174	ALX_HRTBT_HOST_IPV4_ADDR = 0x1478
		175	ALX_HRTBT_REM_IPV6_ADDR3 = 0x1AD8
		176	ALX_HRTBT_REM_IPV6_ADDR2 = 0x1ADC
		177	ALX_HRTBT_REM_IPV6_ADDR1 = 0x1AE0
		178	ALX_HRTBT_REM_IPV6_ADDR0 = 0x1AE4
		179
		180	; 1B8C ~ 1B94 for C0+
		181	ALX_SWOI_ACER_CTRL = 0x1B8C
		182	ALX_SWOI_ORIG_ACK_NAK_EN = (1 shl 20)
		183	ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK = 0xFF
		184	ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT = 12
		185	ALX_SWOI_ORIG_ACK_ADDR_MASK = 0xFFF
		186	ALX_SWOI_ORIG_ACK_ADDR_SHIFT = 0
		187
		188	ALX_SWOI_IOAC_CTRL_2 = 0x1B90
		189	ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK = 0xFF
		190	ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT = 24
		191	ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK = 0xFFF
		192	ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT = 12
		193	ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK = 0xFFF
		194	ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT = 0
		195
		196	ALX_SWOI_IOAC_CTRL_3 = 0x1B94
		197	ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK = 0xFF
		198	ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT = 24
		199	ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK = 0xFFF
		200	ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT = 12
		201	ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK = 0xFFF
		202	ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT = 0
		203
		204	; for B0
		205	ALX_IDLE_DECISN_TIMER = 0x1474
		206	; 1ms
		207	ALX_IDLE_DECISN_TIMER_DEF = 0x400
		208
		209	ALX_MAC_CTRL = 0x1480
		210	ALX_MAC_CTRL_FAST_PAUSE = (1 shl 31)
		211	ALX_MAC_CTRL_WOLSPED_SWEN = (1 shl 30)
		212	; bit29: 1:legacy(hi5b), 0:marvl(lo5b)
		213	ALX_MAC_CTRL_MHASH_ALG_HI5B = (1 shl 29)
		214	ALX_MAC_CTRL_BRD_EN = (1 shl 26)
		215	ALX_MAC_CTRL_MULTIALL_EN = (1 shl 25)
		216	ALX_MAC_CTRL_SPEED_MASK = 0x3
		217	ALX_MAC_CTRL_SPEED_SHIFT = 20
		218	ALX_MAC_CTRL_SPEED_10_100 = 1
		219	ALX_MAC_CTRL_SPEED_1000 = 2
		220	ALX_MAC_CTRL_PROMISC_EN = (1 shl 15)
		221	ALX_MAC_CTRL_VLANSTRIP = (1 shl 14)
		222	ALX_MAC_CTRL_PRMBLEN_MASK = 0xF
		223	ALX_MAC_CTRL_PRMBLEN_SHIFT = 10
		224	ALX_MAC_CTRL_PCRCE = (1 shl 7)
		225	ALX_MAC_CTRL_CRCE = (1 shl 6)
		226	ALX_MAC_CTRL_FULLD = (1 shl 5)
		227	ALX_MAC_CTRL_RXFC_EN = (1 shl 3)
		228	ALX_MAC_CTRL_TXFC_EN = (1 shl 2)
		229	ALX_MAC_CTRL_RX_EN = (1 shl 1)
		230	ALX_MAC_CTRL_TX_EN = (1 shl 0)
		231
		232	ALX_STAD0 = 0x1488
		233	ALX_STAD1 = 0x148C
		234
		235	ALX_HASH_TBL0 = 0x1490
		236	ALX_HASH_TBL1 = 0x1494
		237
		238	ALX_MTU = 0x149C
		239	ALX_MTU_JUMBO_TH = 1514
		240	ALX_MTU_STD_ALGN = 1536
		241
		242	ALX_SRAM5 = 0x1524
		243	ALX_SRAM_RXF_LEN_MASK = 0xFFF
		244	ALX_SRAM_RXF_LEN_SHIFT = 0
		245	ALX_SRAM_RXF_LEN_8K = (8*1024)
		246
		247	ALX_SRAM9 = 0x1534
		248	ALX_SRAM_LOAD_PTR = (1 shl 0)
		249
		250	ALX_RX_BASE_ADDR_HI = 0x1540
		251
		252	ALX_TX_BASE_ADDR_HI = 0x1544
		253
		254	ALX_RFD_ADDR_LO = 0x1550
		255	ALX_RFD_RING_SZ = 0x1560
		256	ALX_RFD_BUF_SZ = 0x1564
		257
		258	ALX_RRD_ADDR_LO = 0x1568
		259	ALX_RRD_RING_SZ = 0x1578
		260
		261	; pri3: highest, pri0: lowest
		262	ALX_TPD_PRI3_ADDR_LO = 0x14E4
		263	ALX_TPD_PRI2_ADDR_LO = 0x14E0
		264	ALX_TPD_PRI1_ADDR_LO = 0x157C
		265	ALX_TPD_PRI0_ADDR_LO = 0x1580
		266
		267	; producer index is 16bit
		268	ALX_TPD_PRI3_PIDX = 0x1618
		269	ALX_TPD_PRI2_PIDX = 0x161A
		270	ALX_TPD_PRI1_PIDX = 0x15F0
		271	ALX_TPD_PRI0_PIDX = 0x15F2
		272
		273	; consumer index is 16bit
		274	ALX_TPD_PRI3_CIDX = 0x161C
		275	ALX_TPD_PRI2_CIDX = 0x161E
		276	ALX_TPD_PRI1_CIDX = 0x15F4
		277	ALX_TPD_PRI0_CIDX = 0x15F6
		278
		279	ALX_TPD_RING_SZ = 0x1584
		280
		281	ALX_TXQ0 = 0x1590
		282	ALX_TXQ0_TXF_BURST_PREF_MASK = 0xFFFF
		283	ALX_TXQ0_TXF_BURST_PREF_SHIFT = 16
		284	ALX_TXQ_TXF_BURST_PREF_DEF = 0x200
		285	ALX_TXQ0_LSO_8023_EN = (1 shl 7)
		286	ALX_TXQ0_MODE_ENHANCE = (1 shl 6)
		287	ALX_TXQ0_EN = (1 shl 5)
		288	ALX_TXQ0_SUPT_IPOPT = (1 shl 4)
		289	ALX_TXQ0_TPD_BURSTPREF_MASK = 0xF
		290	ALX_TXQ0_TPD_BURSTPREF_SHIFT = 0
		291	ALX_TXQ_TPD_BURSTPREF_DEF = 5
		292
		293	ALX_TXQ1 = 0x1594
		294	; bit11: drop large packet, len > (rfd buf)
		295	ALX_TXQ1_ERRLGPKT_DROP_EN = (1 shl 11)
		296	ALX_TXQ1_JUMBO_TSO_TH = (7*1024)
		297
		298	ALX_RXQ0 = 0x15A0
		299	ALX_RXQ0_EN = (1 shl 31)
		300	ALX_RXQ0_RSS_HASH_EN = (1 shl 29)
		301	ALX_RXQ0_RSS_MODE_MASK = 0x3
		302	ALX_RXQ0_RSS_MODE_SHIFT = 26
		303	ALX_RXQ0_RSS_MODE_DIS = 0
		304	ALX_RXQ0_RSS_MODE_MQMI = 3
		305	ALX_RXQ0_NUM_RFD_PREF_MASK = 0x3F
		306	ALX_RXQ0_NUM_RFD_PREF_SHIFT = 20
		307	ALX_RXQ0_NUM_RFD_PREF_DEF = 8
		308	ALX_RXQ0_IDT_TBL_SIZE_MASK = 0x1FF
		309	ALX_RXQ0_IDT_TBL_SIZE_SHIFT = 8
		310	ALX_RXQ0_IDT_TBL_SIZE_DEF = 0x100
		311	ALX_RXQ0_IDT_TBL_SIZE_NORMAL = 128
		312	ALX_RXQ0_IPV6_PARSE_EN = (1 shl 7)
		313	ALX_RXQ0_RSS_HSTYP_MASK = 0xF
		314	ALX_RXQ0_RSS_HSTYP_SHIFT = 2
		315	ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN = (1 shl 5)
		316	ALX_RXQ0_RSS_HSTYP_IPV6_EN = (1 shl 4)
		317	ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN = (1 shl 3)
		318	ALX_RXQ0_RSS_HSTYP_IPV4_EN = (1 shl 2)
		319	ALX_RXQ0_RSS_HSTYP_ALL = (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN or ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN or ALX_RXQ0_RSS_HSTYP_IPV6_EN or ALX_RXQ0_RSS_HSTYP_IPV4_EN)
		320	ALX_RXQ0_ASPM_THRESH_MASK = 0x3
		321	ALX_RXQ0_ASPM_THRESH_SHIFT = 0
		322	ALX_RXQ0_ASPM_THRESH_100M = 3
		323
		324	ALX_RXQ2 = 0x15A8
		325	ALX_RXQ2_RXF_XOFF_THRESH_MASK = 0xFFF
		326	ALX_RXQ2_RXF_XOFF_THRESH_SHIFT = 16
		327	ALX_RXQ2_RXF_XON_THRESH_MASK = 0xFFF
		328	ALX_RXQ2_RXF_XON_THRESH_SHIFT = 0
		329	; Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
		330	; rx-packet(1522) + delay-of-link(64)
		331	; = 3212.
		332
		333	ALX_RXQ2_RXF_FLOW_CTRL_RSVD = 3212
		334
		335	ALX_DMA = 0x15C0
		336	ALX_DMA_RCHNL_SEL_MASK = 0x3
		337	ALX_DMA_RCHNL_SEL_SHIFT = 26
		338	ALX_DMA_WDLY_CNT_MASK = 0xF
		339	ALX_DMA_WDLY_CNT_SHIFT = 16
		340	ALX_DMA_WDLY_CNT_DEF = 4
		341	ALX_DMA_RDLY_CNT_MASK = 0x1F
		342	ALX_DMA_RDLY_CNT_SHIFT = 11
		343	ALX_DMA_RDLY_CNT_DEF = 15
		344	; bit10: 0:tpd with pri, 1: data
		345	ALX_DMA_RREQ_PRI_DATA = (1 shl 10)
		346	ALX_DMA_RREQ_BLEN_MASK = 0x7
		347	ALX_DMA_RREQ_BLEN_SHIFT = 4
		348	ALX_DMA_RORDER_MODE_MASK = 0x7
		349	ALX_DMA_RORDER_MODE_SHIFT = 0
		350	ALX_DMA_RORDER_MODE_OUT = 4
		351
		352	ALX_WOL0 = 0x14A0
		353	ALX_WOL0_PME_LINK = (1 shl 5)
		354	ALX_WOL0_LINK_EN = (1 shl 4)
		355	ALX_WOL0_PME_MAGIC_EN = (1 shl 3)
		356	ALX_WOL0_MAGIC_EN = (1 shl 2)
		357
		358	; RFD Producer index
		359	ALX_RFD_PIDX = 0x15E0
		360
		361	; RFD Consumer indef
		362	ALX_RFD_CIDX = 0x15F8
		363
		364	; MIB
		365	ALX_MIB_BASE = 0x1700
		366
		367	ALX_MIB_RX_OK = (ALX_MIB_BASE + 0)
		368	ALX_MIB_RX_BCAST = (ALX_MIB_BASE + 4)
		369	ALX_MIB_RX_MCAST = (ALX_MIB_BASE + 8)
		370	ALX_MIB_RX_PAUSE = (ALX_MIB_BASE + 12)
		371	ALX_MIB_RX_CTRL = (ALX_MIB_BASE + 16)
		372	ALX_MIB_RX_FCS_ERR = (ALX_MIB_BASE + 20)
		373	ALX_MIB_RX_LEN_ERR = (ALX_MIB_BASE + 24)
		374	ALX_MIB_RX_BYTE_CNT = (ALX_MIB_BASE + 28)
		375	ALX_MIB_RX_RUNT = (ALX_MIB_BASE + 32)
		376	ALX_MIB_RX_FRAG = (ALX_MIB_BASE + 36)
		377	ALX_MIB_RX_SZ_64B = (ALX_MIB_BASE + 40)
		378	ALX_MIB_RX_SZ_127B = (ALX_MIB_BASE + 44)
		379	ALX_MIB_RX_SZ_255B = (ALX_MIB_BASE + 48)
		380	ALX_MIB_RX_SZ_511B = (ALX_MIB_BASE + 52)
		381	ALX_MIB_RX_SZ_1023B = (ALX_MIB_BASE + 56)
		382	ALX_MIB_RX_SZ_1518B = (ALX_MIB_BASE + 60)
		383	ALX_MIB_RX_SZ_MAX = (ALX_MIB_BASE + 64)
		384	ALX_MIB_RX_OV_SZ = (ALX_MIB_BASE + 68)
		385	ALX_MIB_RX_OV_RXF = (ALX_MIB_BASE + 72)
		386	ALX_MIB_RX_OV_RRD = (ALX_MIB_BASE + 76)
		387	ALX_MIB_RX_ALIGN_ERR = (ALX_MIB_BASE + 80)
		388	ALX_MIB_RX_BCCNT = (ALX_MIB_BASE + 84)
		389	ALX_MIB_RX_MCCNT = (ALX_MIB_BASE + 88)
		390	ALX_MIB_RX_ERRADDR = (ALX_MIB_BASE + 92)
		391
		392	ALX_MIB_TX_OK = (ALX_MIB_BASE + 96)
		393	ALX_MIB_TX_BCAST = (ALX_MIB_BASE + 100)
		394	ALX_MIB_TX_MCAST = (ALX_MIB_BASE + 104)
		395	ALX_MIB_TX_PAUSE = (ALX_MIB_BASE + 108)
		396	ALX_MIB_TX_EXC_DEFER = (ALX_MIB_BASE + 112)
		397	ALX_MIB_TX_CTRL = (ALX_MIB_BASE + 116)
		398	ALX_MIB_TX_DEFER = (ALX_MIB_BASE + 120)
		399	ALX_MIB_TX_BYTE_CNT = (ALX_MIB_BASE + 124)
		400	ALX_MIB_TX_SZ_64B = (ALX_MIB_BASE + 128)
		401	ALX_MIB_TX_SZ_127B = (ALX_MIB_BASE + 132)
		402	ALX_MIB_TX_SZ_255B = (ALX_MIB_BASE + 136)
		403	ALX_MIB_TX_SZ_511B = (ALX_MIB_BASE + 140)
		404	ALX_MIB_TX_SZ_1023B = (ALX_MIB_BASE + 144)
		405	ALX_MIB_TX_SZ_1518B = (ALX_MIB_BASE + 148)
		406	ALX_MIB_TX_SZ_MAX = (ALX_MIB_BASE + 152)
		407	ALX_MIB_TX_SINGLE_COL = (ALX_MIB_BASE + 156)
		408	ALX_MIB_TX_MULTI_COL = (ALX_MIB_BASE + 160)
		409	ALX_MIB_TX_LATE_COL = (ALX_MIB_BASE + 164)
		410	ALX_MIB_TX_ABORT_COL = (ALX_MIB_BASE + 168)
		411	ALX_MIB_TX_UNDERRUN = (ALX_MIB_BASE + 172)
		412	ALX_MIB_TX_TRD_EOP = (ALX_MIB_BASE + 176)
		413	ALX_MIB_TX_LEN_ERR = (ALX_MIB_BASE + 180)
		414	ALX_MIB_TX_TRUNC = (ALX_MIB_BASE + 184)
		415	ALX_MIB_TX_BCCNT = (ALX_MIB_BASE + 188)
		416	ALX_MIB_TX_MCCNT = (ALX_MIB_BASE + 192)
		417	ALX_MIB_UPDATE = (ALX_MIB_BASE + 196)
		418
		419
		420	ALX_ISR = 0x1600
		421	ALX_ISR_DIS = (1 shl 31)
		422	ALX_ISR_RX_Q7 = (1 shl 30)
		423	ALX_ISR_RX_Q6 = (1 shl 29)
		424	ALX_ISR_RX_Q5 = (1 shl 28)
		425	ALX_ISR_RX_Q4 = (1 shl 27)
		426	ALX_ISR_PCIE_LNKDOWN = (1 shl 26)
		427	ALX_ISR_RX_Q3 = (1 shl 19)
		428	ALX_ISR_RX_Q2 = (1 shl 18)
		429	ALX_ISR_RX_Q1 = (1 shl 17)
		430	ALX_ISR_RX_Q0 = (1 shl 16)
		431	ALX_ISR_TX_Q0 = (1 shl 15)
		432	ALX_ISR_PHY = (1 shl 12)
		433	ALX_ISR_DMAW = (1 shl 10)
		434	ALX_ISR_DMAR = (1 shl 9)
		435	ALX_ISR_TXF_UR = (1 shl 8)
		436	ALX_ISR_TX_Q3 = (1 shl 7)
		437	ALX_ISR_TX_Q2 = (1 shl 6)
		438	ALX_ISR_TX_Q1 = (1 shl 5)
		439	ALX_ISR_RFD_UR = (1 shl 4)
		440	ALX_ISR_RXF_OV = (1 shl 3)
		441	ALX_ISR_MANU = (1 shl 2)
		442	ALX_ISR_TIMER = (1 shl 1)
		443	ALX_ISR_SMB = (1 shl 0)
		444
		445	ALX_IMR = 0x1604
		446
		447	; re-send assert msg if SW no response
		448	ALX_INT_RETRIG = 0x1608
		449	; 40ms
		450	ALX_INT_RETRIG_TO = 20000
		451
		452	ALX_SMB_TIMER = 0x15C4
		453
		454	ALX_TINT_TPD_THRSHLD = 0x15C8
		455
		456	ALX_TINT_TIMER = 0x15CC
		457
		458	ALX_CLK_GATE = 0x1814
		459	ALX_CLK_GATE_RXMAC = (1 shl 5)
		460	ALX_CLK_GATE_TXMAC = (1 shl 4)
		461	ALX_CLK_GATE_RXQ = (1 shl 3)
		462	ALX_CLK_GATE_TXQ = (1 shl 2)
		463	ALX_CLK_GATE_DMAR = (1 shl 1)
		464	ALX_CLK_GATE_DMAW = (1 shl 0)
		465	ALX_CLK_GATE_ALL = (ALX_CLK_GATE_RXMAC or ALX_CLK_GATE_TXMAC or ALX_CLK_GATE_RXQ or ALX_CLK_GATE_TXQ or ALX_CLK_GATE_DMAR or ALX_CLK_GATE_DMAW)
		466
		467	; interop between drivers
		468	ALX_DRV = 0x1804
		469	ALX_DRV_PHY_AUTO = (1 shl 28)
		470	ALX_DRV_PHY_1000 = (1 shl 27)
		471	ALX_DRV_PHY_100 = (1 shl 26)
		472	ALX_DRV_PHY_10 = (1 shl 25)
		473	ALX_DRV_PHY_DUPLEX = (1 shl 24)
		474	; bit23: adv Pause
		475	ALX_DRV_PHY_PAUSE = (1 shl 23)
		476	; bit22: adv Asym Pause
		477	ALX_DRV_PHY_MASK = 0xFF
		478	ALX_DRV_PHY_SHIFT = 21
		479	ALX_DRV_PHY_UNKNOWN = 0
		480
		481	; flag of phy inited
		482	ALX_PHY_INITED = 0x003F
		483
		484	; reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection
		485	ALX_WOL_CTRL2 = 0x1830
		486	ALX_WOL_CTRL2_DATA_STORE = (1 shl 3)
		487	ALX_WOL_CTRL2_PTRN_EVT = (1 shl 2)
		488	ALX_WOL_CTRL2_PME_PTRN_EN = (1 shl 1)
		489	ALX_WOL_CTRL2_PTRN_EN = (1 shl 0)
		490
		491	ALX_WOL_CTRL3 = 0x1834
		492	ALX_WOL_CTRL3_PTRN_ADDR_MASK = 0xFFFFF
		493	ALX_WOL_CTRL3_PTRN_ADDR_SHIFT = 0
		494
		495	ALX_WOL_CTRL4 = 0x1838
		496	ALX_WOL_CTRL4_PT15_MATCH = (1 shl 31)
		497	ALX_WOL_CTRL4_PT14_MATCH = (1 shl 30)
		498	ALX_WOL_CTRL4_PT13_MATCH = (1 shl 29)
		499	ALX_WOL_CTRL4_PT12_MATCH = (1 shl 28)
		500	ALX_WOL_CTRL4_PT11_MATCH = (1 shl 27)
		501	ALX_WOL_CTRL4_PT10_MATCH = (1 shl 26)
		502	ALX_WOL_CTRL4_PT9_MATCH = (1 shl 25)
		503	ALX_WOL_CTRL4_PT8_MATCH = (1 shl 24)
		504	ALX_WOL_CTRL4_PT7_MATCH = (1 shl 23)
		505	ALX_WOL_CTRL4_PT6_MATCH = (1 shl 22)
		506	ALX_WOL_CTRL4_PT5_MATCH = (1 shl 21)
		507	ALX_WOL_CTRL4_PT4_MATCH = (1 shl 20)
		508	ALX_WOL_CTRL4_PT3_MATCH = (1 shl 19)
		509	ALX_WOL_CTRL4_PT2_MATCH = (1 shl 18)
		510	ALX_WOL_CTRL4_PT1_MATCH = (1 shl 17)
		511	ALX_WOL_CTRL4_PT0_MATCH = (1 shl 16)
		512	ALX_WOL_CTRL4_PT15_EN = (1 shl 15)
		513	ALX_WOL_CTRL4_PT14_EN = (1 shl 14)
		514	ALX_WOL_CTRL4_PT13_EN = (1 shl 13)
		515	ALX_WOL_CTRL4_PT12_EN = (1 shl 12)
		516	ALX_WOL_CTRL4_PT11_EN = (1 shl 11)
		517	ALX_WOL_CTRL4_PT10_EN = (1 shl 10)
		518	ALX_WOL_CTRL4_PT9_EN = (1 shl 9)
		519	ALX_WOL_CTRL4_PT8_EN = (1 shl 8)
		520	ALX_WOL_CTRL4_PT7_EN = (1 shl 7)
		521	ALX_WOL_CTRL4_PT6_EN = (1 shl 6)
		522	ALX_WOL_CTRL4_PT5_EN = (1 shl 5)
		523	ALX_WOL_CTRL4_PT4_EN = (1 shl 4)
		524	ALX_WOL_CTRL4_PT3_EN = (1 shl 3)
		525	ALX_WOL_CTRL4_PT2_EN = (1 shl 2)
		526	ALX_WOL_CTRL4_PT1_EN = (1 shl 1)
		527	ALX_WOL_CTRL4_PT0_EN = (1 shl 0)
		528
		529	ALX_WOL_CTRL5 = 0x183C
		530	ALX_WOL_CTRL5_PT3_LEN_MASK = 0xFF
		531	ALX_WOL_CTRL5_PT3_LEN_SHIFT = 24
		532	ALX_WOL_CTRL5_PT2_LEN_MASK = 0xFF
		533	ALX_WOL_CTRL5_PT2_LEN_SHIFT = 16
		534	ALX_WOL_CTRL5_PT1_LEN_MASK = 0xFF
		535	ALX_WOL_CTRL5_PT1_LEN_SHIFT = 8
		536	ALX_WOL_CTRL5_PT0_LEN_MASK = 0xFF
		537	ALX_WOL_CTRL5_PT0_LEN_SHIFT = 0
		538
		539	ALX_WOL_CTRL6 = 0x1840
		540	ALX_WOL_CTRL5_PT7_LEN_MASK = 0xFF
		541	ALX_WOL_CTRL5_PT7_LEN_SHIFT = 24
		542	ALX_WOL_CTRL5_PT6_LEN_MASK = 0xFF
		543	ALX_WOL_CTRL5_PT6_LEN_SHIFT = 16
		544	ALX_WOL_CTRL5_PT5_LEN_MASK = 0xFF
		545	ALX_WOL_CTRL5_PT5_LEN_SHIFT = 8
		546	ALX_WOL_CTRL5_PT4_LEN_MASK = 0xFF
		547	ALX_WOL_CTRL5_PT4_LEN_SHIFT = 0
		548
		549	ALX_WOL_CTRL7 = 0x1844
		550	ALX_WOL_CTRL5_PT11_LEN_MASK = 0xFF
		551	ALX_WOL_CTRL5_PT11_LEN_SHIFT = 24
		552	ALX_WOL_CTRL5_PT10_LEN_MASK = 0xFF
		553	ALX_WOL_CTRL5_PT10_LEN_SHIFT = 16
		554	ALX_WOL_CTRL5_PT9_LEN_MASK = 0xFF
		555	ALX_WOL_CTRL5_PT9_LEN_SHIFT = 8
		556	ALX_WOL_CTRL5_PT8_LEN_MASK = 0xFF
		557	ALX_WOL_CTRL5_PT8_LEN_SHIFT = 0
		558
		559	ALX_WOL_CTRL8 = 0x1848
		560	ALX_WOL_CTRL5_PT15_LEN_MASK = 0xFF
		561	ALX_WOL_CTRL5_PT15_LEN_SHIFT = 24
		562	ALX_WOL_CTRL5_PT14_LEN_MASK = 0xFF
		563	ALX_WOL_CTRL5_PT14_LEN_SHIFT = 16
		564	ALX_WOL_CTRL5_PT13_LEN_MASK = 0xFF
		565	ALX_WOL_CTRL5_PT13_LEN_SHIFT = 8
		566	ALX_WOL_CTRL5_PT12_LEN_MASK = 0xFF
		567	ALX_WOL_CTRL5_PT12_LEN_SHIFT = 0
		568
		569	ALX_ACER_FIXED_PTN0 = 0x1850
		570	ALX_ACER_FIXED_PTN0_MASK = 0xFFFFFFFF
		571	ALX_ACER_FIXED_PTN0_SHIFT = 0
		572
		573	ALX_ACER_FIXED_PTN1 = 0x1854
		574	ALX_ACER_FIXED_PTN1_MASK = 0xFFFF
		575	ALX_ACER_FIXED_PTN1_SHIFT = 0
		576
		577	ALX_ACER_RANDOM_NUM0 = 0x1858
		578	ALX_ACER_RANDOM_NUM0_MASK = 0xFFFFFFFF
		579	ALX_ACER_RANDOM_NUM0_SHIFT = 0
		580
		581	ALX_ACER_RANDOM_NUM1 = 0x185C
		582	ALX_ACER_RANDOM_NUM1_MASK = 0xFFFFFFFF
		583	ALX_ACER_RANDOM_NUM1_SHIFT = 0
		584
		585	ALX_ACER_RANDOM_NUM2 = 0x1860
		586	ALX_ACER_RANDOM_NUM2_MASK = 0xFFFFFFFF
		587	ALX_ACER_RANDOM_NUM2_SHIFT = 0
		588
		589	ALX_ACER_RANDOM_NUM3 = 0x1864
		590	ALX_ACER_RANDOM_NUM3_MASK = 0xFFFFFFFF
		591	ALX_ACER_RANDOM_NUM3_SHIFT = 0
		592
		593	ALX_ACER_MAGIC = 0x1868
		594	ALX_ACER_MAGIC_EN = (1 shl 31)
		595	ALX_ACER_MAGIC_PME_EN = (1 shl 30)
		596	ALX_ACER_MAGIC_MATCH = (1 shl 29)
		597	ALX_ACER_MAGIC_FF_CHECK = (1 shl 10)
		598	ALX_ACER_MAGIC_RAN_LEN_MASK = 0x1F
		599	ALX_ACER_MAGIC_RAN_LEN_SHIFT = 5
		600	ALX_ACER_MAGIC_FIX_LEN_MASK = 0x1F
		601	ALX_ACER_MAGIC_FIX_LEN_SHIFT = 0
		602
		603	ALX_ACER_TIMER = 0x186C
		604	ALX_ACER_TIMER_EN = (1 shl 31)
		605	ALX_ACER_TIMER_PME_EN = (1 shl 30)
		606	ALX_ACER_TIMER_MATCH = (1 shl 29)
		607	ALX_ACER_TIMER_THRES_MASK = 0x1FFFF
		608	ALX_ACER_TIMER_THRES_SHIFT = 0
		609	ALX_ACER_TIMER_THRES_DEF = 1
		610
		611	; RSS definitions
		612	ALX_RSS_KEY0 = 0x14B0
		613	ALX_RSS_KEY1 = 0x14B4
		614	ALX_RSS_KEY2 = 0x14B8
		615	ALX_RSS_KEY3 = 0x14BC
		616	ALX_RSS_KEY4 = 0x14C0
		617	ALX_RSS_KEY5 = 0x14C4
		618	ALX_RSS_KEY6 = 0x14C8
		619	ALX_RSS_KEY7 = 0x14CC
		620	ALX_RSS_KEY8 = 0x14D0
		621	ALX_RSS_KEY9 = 0x14D4
		622
		623	ALX_RSS_IDT_TBL0 = 0x1B00
		624
		625	ALX_MSI_MAP_TBL1 = 0x15D0
		626	ALX_MSI_MAP_TBL1_TXQ1_SHIFT = 20
		627	ALX_MSI_MAP_TBL1_TXQ0_SHIFT = 16
		628	ALX_MSI_MAP_TBL1_RXQ3_SHIFT = 12
		629	ALX_MSI_MAP_TBL1_RXQ2_SHIFT = 8
		630	ALX_MSI_MAP_TBL1_RXQ1_SHIFT = 4
		631	ALX_MSI_MAP_TBL1_RXQ0_SHIFT = 0
		632
		633	ALX_MSI_MAP_TBL2 = 0x15D8
		634	ALX_MSI_MAP_TBL2_TXQ3_SHIFT = 20
		635	ALX_MSI_MAP_TBL2_TXQ2_SHIFT = 16
		636	ALX_MSI_MAP_TBL2_RXQ7_SHIFT = 12
		637	ALX_MSI_MAP_TBL2_RXQ6_SHIFT = 8
		638	ALX_MSI_MAP_TBL2_RXQ5_SHIFT = 4
		639	ALX_MSI_MAP_TBL2_RXQ4_SHIFT = 0
		640
		641	ALX_MSI_ID_MAP = 0x15D4
		642
		643	ALX_MSI_RETRANS_TIMER = 0x1920
		644	; bit16: 1:line,0:standard
		645	ALX_MSI_MASK_SEL_LINE = (1 shl 16)
		646	ALX_MSI_RETRANS_TM_MASK = 0xFFFF
		647	ALX_MSI_RETRANS_TM_SHIFT = 0
		648
		649	; CR DMA ctrl
		650
		651	; TX QoS
		652	ALX_WRR = 0x1938
		653	ALX_WRR_PRI_MASK = 0x3
		654	ALX_WRR_PRI_SHIFT = 29
		655	ALX_WRR_PRI_RESTRICT_NONE = 3
		656	ALX_WRR_PRI3_MASK = 0x1F
		657	ALX_WRR_PRI3_SHIFT = 24
		658	ALX_WRR_PRI2_MASK = 0x1F
		659	ALX_WRR_PRI2_SHIFT = 16
		660	ALX_WRR_PRI1_MASK = 0x1F
		661	ALX_WRR_PRI1_SHIFT = 8
		662	ALX_WRR_PRI0_MASK = 0x1F
		663	ALX_WRR_PRI0_SHIFT = 0
		664
		665	ALX_HQTPD = 0x193C
		666	ALX_HQTPD_BURST_EN = (1 shl 31)
		667	ALX_HQTPD_Q3_NUMPREF_MASK = 0xF
		668	ALX_HQTPD_Q3_NUMPREF_SHIFT = 8
		669	ALX_HQTPD_Q2_NUMPREF_MASK = 0xF
		670	ALX_HQTPD_Q2_NUMPREF_SHIFT = 4
		671	ALX_HQTPD_Q1_NUMPREF_MASK = 0xF
		672	ALX_HQTPD_Q1_NUMPREF_SHIFT = 0
		673
		674	ALX_MISC = 0x19C0
		675	ALX_MISC_PSW_OCP_MASK = 0x7
		676	ALX_MISC_PSW_OCP_SHIFT = 21
		677	ALX_MISC_PSW_OCP_DEF = 0x7
		678	ALX_MISC_ISO_EN = (1 shl 12)
		679	ALX_MISC_INTNLOSC_OPEN = (1 shl 3)
		680
		681	ALX_MSIC2 = 0x19C8
		682	ALX_MSIC2_CALB_START = (1 shl 0)
		683
		684	ALX_MISC3 = 0x19CC
		685	; bit1: 1:Software control 25M
		686	ALX_MISC3_25M_BY_SW = (1 shl 1)
		687	; bit0: 25M switch to intnl OSC
		688	ALX_MISC3_25M_NOTO_INTNL = (1 shl 0)
		689
		690	; MSIX tbl in memory space
		691	ALX_MSIX_ENTRY_BASE = 0x2000
		692
		693	;****************** PHY regs definition;************************
		694
		695	; PHY Specific Status Register
		696	ALX_MII_GIGA_PSSR = 0x11
		697	ALX_GIGA_PSSR_SPD_DPLX_RESOLVED = 0x0800
		698	ALX_GIGA_PSSR_DPLX = 0x2000
		699	ALX_GIGA_PSSR_SPEED = 0xC000
		700	ALX_GIGA_PSSR_10MBS = 0x0000
		701	ALX_GIGA_PSSR_100MBS = 0x4000
		702	ALX_GIGA_PSSR_1000MBS = 0x8000
		703
		704	; PHY Interrupt Enable Register
		705	ALX_MII_IER = 0x12
		706	ALX_IER_LINK_UP = 0x0400
		707	ALX_IER_LINK_DOWN = 0x0800
		708
		709	; PHY Interrupt Status Register
		710	ALX_MII_ISR = 0x13
		711
		712	ALX_MII_DBG_ADDR = 0x1D
		713	ALX_MII_DBG_DATA = 0x1E
		714
		715	;************************** debug port;**********************************
		716
		717	ALX_MIIDBG_ANACTRL = 0x00
		718	ALX_ANACTRL_DEF = 0x02EF
		719
		720	ALX_MIIDBG_SYSMODCTRL = 0x04
		721	; en half bias
		722	ALX_SYSMODCTRL_IECHOADJ_DEF = 0xBB8B
		723
		724	ALX_MIIDBG_SRDSYSMOD = 0x05
		725	ALX_SRDSYSMOD_DEEMP_EN = 0x0040
		726	ALX_SRDSYSMOD_DEF = 0x2C46
		727
		728	ALX_MIIDBG_HIBNEG = 0x0B
		729	ALX_HIBNEG_PSHIB_EN = 0x8000
		730	ALX_HIBNEG_HIB_PSE = 0x1000
		731	ALX_HIBNEG_DEF = 0xBC40
		732	ALX_HIBNEG_NOHIB = (ALX_HIBNEG_DEF and not(ALX_HIBNEG_PSHIB_EN or ALX_HIBNEG_HIB_PSE))
		733
		734	ALX_MIIDBG_TST10BTCFG = 0x12
		735	ALX_TST10BTCFG_DEF = 0x4C04
		736
		737	ALX_MIIDBG_AZ_ANADECT = 0x15
		738	ALX_AZ_ANADECT_DEF = 0x3220
		739	ALX_AZ_ANADECT_LONG = 0x3210
		740
		741	ALX_MIIDBG_MSE16DB = 0x18
		742	ALX_MSE16DB_UP = 0x05EA
		743	ALX_MSE16DB_DOWN = 0x02EA
		744
		745	ALX_MIIDBG_MSE20DB = 0x1C
		746	ALX_MSE20DB_TH_MASK = 0x7F
		747	ALX_MSE20DB_TH_SHIFT = 2
		748	ALX_MSE20DB_TH_DEF = 0x2E
		749	ALX_MSE20DB_TH_HI = 0x54
		750
		751	ALX_MIIDBG_AGC = 0x23
		752	ALX_AGC_2_VGA_MASK = 0x3F
		753	ALX_AGC_2_VGA_SHIFT = 8
		754	ALX_AGC_LONG1G_LIMT = 40
		755	ALX_AGC_LONG100M_LIMT = 44
		756
		757	ALX_MIIDBG_LEGCYPS = 0x29
		758	ALX_LEGCYPS_EN = 0x8000
		759	ALX_LEGCYPS_DEF = 0x129D
		760
		761	ALX_MIIDBG_TST100BTCFG = 0x36
		762	ALX_TST100BTCFG_DEF = 0xE12C
		763
		764	ALX_MIIDBG_GREENCFG = 0x3B
		765	ALX_GREENCFG_DEF = 0x7078
		766
		767	ALX_MIIDBG_GREENCFG2 = 0x3D
		768	ALX_GREENCFG2_BP_GREEN = 0x8000
		769	ALX_GREENCFG2_GATE_DFSE_EN = 0x0080
		770
		771	;**** dev 3;******
		772	ALX_MIIEXT_PCS = 3
		773
		774	ALX_MIIEXT_CLDCTRL3 = 0x8003
		775	ALX_CLDCTRL3_BP_CABLE1TH_DET_GT = 0x8000
		776
		777	ALX_MIIEXT_CLDCTRL5 = 0x8005
		778	ALX_CLDCTRL5_BP_VD_HLFBIAS = 0x4000
		779
		780	ALX_MIIEXT_CLDCTRL6 = 0x8006
		781	ALX_CLDCTRL6_CAB_LEN_MASK = 0xFF
		782	ALX_CLDCTRL6_CAB_LEN_SHIFT = 0
		783	ALX_CLDCTRL6_CAB_LEN_SHORT1G = 116
		784	ALX_CLDCTRL6_CAB_LEN_SHORT100M = 152
		785
		786	ALX_MIIEXT_VDRVBIAS = 0x8062
		787	ALX_VDRVBIAS_DEF = 0x3
		788
		789	;****** dev 7;*******
		790	ALX_MIIEXT_ANEG = 7
		791
		792	ALX_MIIEXT_LOCAL_EEEADV = 0x3C
		793	ALX_LOCAL_EEEADV_1000BT = 0x0004
		794	ALX_LOCAL_EEEADV_100BT = 0x0002
		795
		796	ALX_MIIEXT_AFE = 0x801A
		797	ALX_AFE_10BT_100M_TH = 0x0040
		798
		799	ALX_MIIEXT_S3DIG10 = 0x8023
		800	; bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx
		801	ALX_MIIEXT_S3DIG10_SL = 0x0001
		802	ALX_MIIEXT_S3DIG10_DEF = 0
		803
		804	ALX_MIIEXT_NLP78 = 0x8027
		805	ALX_MIIEXT_NLP78_120M_DEF = 0x8A05
		806
		807
		808	; tpd word 1
		809	TPD_CXSUMSTART_MASK = 0x00FF
		810	TPD_CXSUMSTART_SHIFT = 0
		811	TPD_L4HDROFFSET_MASK = 0x00FF
		812	TPD_L4HDROFFSET_SHIFT = 0
		813	TPD_CXSUM_EN_MASK = 0x0001
		814	TPD_CXSUM_EN_SHIFT = 8
		815	TPD_IP_XSUM_MASK = 0x0001
		816	TPD_IP_XSUM_SHIFT = 9
		817	TPD_TCP_XSUM_MASK = 0x0001
		818	TPD_TCP_XSUM_SHIFT = 10
		819	TPD_UDP_XSUM_MASK = 0x0001
		820	TPD_UDP_XSUM_SHIFT = 11
		821	TPD_LSO_EN_MASK = 0x0001
		822	TPD_LSO_EN_SHIFT = 12
		823	TPD_LSO_V2_MASK = 0x0001
		824	TPD_LSO_V2_SHIFT = 13
		825	TPD_VLTAGGED_MASK = 0x0001
		826	TPD_VLTAGGED_SHIFT = 14
		827	TPD_INS_VLTAG_MASK = 0x0001
		828	TPD_INS_VLTAG_SHIFT = 15
		829	TPD_IPV4_MASK = 0x0001
		830	TPD_IPV4_SHIFT = 16
		831	TPD_ETHTYPE_MASK = 0x0001
		832	TPD_ETHTYPE_SHIFT = 17
		833	TPD_CXSUMOFFSET_MASK = 0x00FF
		834	TPD_CXSUMOFFSET_SHIFT = 18
		835	TPD_MSS_MASK = 0x1FFF
		836	TPD_MSS_SHIFT = 18
		837	TPD_EOP_MASK = 0x0001
		838	TPD_EOP_SHIFT = 31
		839
		840
		841	; rrd word 0
		842	RRD_XSUM_MASK = 0xFFFF
		843	RRD_XSUM_SHIFT = 0
		844	RRD_NOR_MASK = 0x000F
		845	RRD_NOR_SHIFT = 16
		846	RRD_SI_MASK = 0x0FFF
		847	RRD_SI_SHIFT = 20
		848
		849	; rrd word 2
		850	RRD_VLTAG_MASK = 0xFFFF
		851	RRD_VLTAG_SHIFT = 0
		852	RRD_PID_MASK = 0x00FF
		853	RRD_PID_SHIFT = 16
		854	; non-ip packet
		855	RRD_PID_NONIP = 0
		856	; ipv4(only)
		857	RRD_PID_IPV4 = 1
		858	; tcp/ipv6
		859	RRD_PID_IPV6TCP = 2
		860	; tcp/ipv4
		861	RRD_PID_IPV4TCP = 3
		862	; udp/ipv6
		863	RRD_PID_IPV6UDP = 4
		864	; udp/ipv4
		865	RRD_PID_IPV4UDP = 5
		866	; ipv6(only)
		867	RRD_PID_IPV6 = 6
		868	; LLDP packet
		869	RRD_PID_LLDP = 7
		870	; 1588 packet
		871	RRD_PID_1588 = 8
		872	RRD_RSSQ_MASK = 0x0007
		873	RRD_RSSQ_SHIFT = 25
		874	RRD_RSSALG_MASK = 0x000F
		875	RRD_RSSALG_SHIFT = 28
		876	RRD_RSSALG_TCPV6 = 0x1
		877	RRD_RSSALG_IPV6 = 0x2
		878	RRD_RSSALG_TCPV4 = 0x4
		879	RRD_RSSALG_IPV4 = 0x8
		880
		881	; rrd word 3
		882	RRD_PKTLEN_MASK = 0x3FFF
		883	RRD_PKTLEN_SHIFT = 0
		884	RRD_ERR_L4_MASK = 0x0001
		885	RRD_ERR_L4_SHIFT = 14
		886	RRD_ERR_IPV4_MASK = 0x0001
		887	RRD_ERR_IPV4_SHIFT = 15
		888	RRD_VLTAGGED_MASK = 0x0001
		889	RRD_VLTAGGED_SHIFT = 16
		890	RRD_OLD_PID_MASK = 0x0007
		891	RRD_OLD_PID_SHIFT = 17
		892	RRD_ERR_RES_MASK = 0x0001
		893	RRD_ERR_RES_SHIFT = 20
		894	RRD_ERR_FCS_MASK = 0x0001
		895	RRD_ERR_FCS_SHIFT = 21
		896	RRD_ERR_FAE_MASK = 0x0001
		897	RRD_ERR_FAE_SHIFT = 22
		898	RRD_ERR_TRUNC_MASK = 0x0001
		899	RRD_ERR_TRUNC_SHIFT = 23
		900	RRD_ERR_RUNT_MASK = 0x0001
		901	RRD_ERR_RUNT_SHIFT = 24
		902	RRD_ERR_ICMP_MASK = 0x0001
		903	RRD_ERR_ICMP_SHIFT = 25
		904	RRD_BCAST_MASK = 0x0001
		905	RRD_BCAST_SHIFT = 26
		906	RRD_MCAST_MASK = 0x0001
		907	RRD_MCAST_SHIFT = 27
		908	RRD_ETHTYPE_MASK = 0x0001
		909	RRD_ETHTYPE_SHIFT = 28
		910	RRD_ERR_FIFOV_MASK = 0x0001
		911	RRD_ERR_FIFOV_SHIFT = 29
		912	RRD_ERR_LEN_MASK = 0x0001
		913	RRD_ERR_LEN_SHIFT = 30
		914	RRD_UPDATED_MASK = 0x0001
		915	RRD_UPDATED_SHIFT = 31
		916
		917
		918	ALX_ISR_MISC = ALX_ISR_PCIE_LNKDOWN or ALX_ISR_DMAW or ALX_ISR_DMAR or ALX_ISR_SMB or ALX_ISR_MANU or ALX_ISR_TIMER
		919
		920	ALX_ISR_FATAL = ALX_ISR_PCIE_LNKDOWN or ALX_ISR_DMAW or ALX_ISR_DMAR
		921
		922	ALX_ISR_ALERT = ALX_ISR_RXF_OV or ALX_ISR_TXF_UR or ALX_ISR_RFD_UR
		923
		924	ALX_ISR_ALL_QUEUES = ALX_ISR_TX_Q0 or ALX_ISR_TX_Q1 or ALX_ISR_TX_Q2 or ALX_ISR_TX_Q3 or ALX_ISR_RX_Q0 or ALX_ISR_RX_Q1 or ALX_ISR_RX_Q2 or ALX_ISR_RX_Q3 or ALX_ISR_RX_Q4 or ALX_ISR_RX_Q5 or ALX_ISR_RX_Q6 or ALX_ISR_RX_Q7

Subversion Repositories Kolibri OS

(root)/drivers/ethernet/ar81xx.inc @ 7827 – Rev 7809