WebSVN – Kolibri OS – Blame – /drivers/ethernet/RTL8169.asm

Rev	Author	Line No.	Line
3545	hidnplayr	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
7250	hidnplayr	3	;; Copyright (C) KolibriOS team 2004-2018. All rights reserved. ;;
3545	hidnplayr	4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;; RTL8169 driver for KolibriOS ;;
		7	;; ;;
		8	;; Copyright 2007 mike.dld, ;;
		9	;; mike.dld@gmail.com ;;
		10	;; ;;
6119	hidnplayr	11	;; Port to the new network stack by hidnplayr ;;
3545	hidnplayr	12	;; ;;
		13	;; References: ;;
6124	hidnplayr	14	;; r8169.c - linux driver ;;
3545	hidnplayr	15	;; ;;
		16	;; GNU GENERAL PUBLIC LICENSE ;;
		17	;; Version 2, June 1991 ;;
		18	;; ;;
		19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		20
5050	hidnplayr	21	format PE DLL native
		22	entry START
3545	hidnplayr	23
5050	hidnplayr	24	CURRENT_API = 0x0200
		25	COMPATIBLE_API = 0x0100
		26	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
3545	hidnplayr	27
		28	MAX_DEVICES = 16
		29
		30	__DEBUG__ = 1
5050	hidnplayr	31	__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only
3545	hidnplayr	32
		33	NUM_TX_DESC = 4
		34	NUM_RX_DESC = 4
		35
5050	hidnplayr	36	section '.flat' readable writable executable
		37
		38	include '../proc32.inc'
4467	hidnplayr	39	include '../struct.inc'
		40	include '../macros.inc'
3545	hidnplayr	41	include '../fdo.inc'
5074	hidnplayr	42	include '../netdrv.inc'
3545	hidnplayr	43
		44	REG_MAC0 = 0x0 ; Ethernet hardware address
		45	REG_MAR0 = 0x8 ; Multicast filter
		46	REG_TxDescStartAddr = 0x20
		47	REG_TxHDescStartAddr = 0x28
		48	REG_FLASH = 0x30
		49	REG_ERSR = 0x36
		50	REG_ChipCmd = 0x37
		51	REG_TxPoll = 0x38
		52	REG_IntrMask = 0x3C
		53	REG_IntrStatus = 0x3E
		54	REG_TxConfig = 0x40
		55	REG_RxConfig = 0x44
		56	REG_RxMissed = 0x4C
		57	REG_Cfg9346 = 0x50
		58	REG_Config0 = 0x51
		59	REG_Config1 = 0x52
		60	REG_Config2 = 0x53
		61	REG_Config3 = 0x54
		62	REG_Config4 = 0x55
		63	REG_Config5 = 0x56
		64	REG_MultiIntr = 0x5C
		65	REG_PHYAR = 0x60
		66	REG_TBICSR = 0x64
		67	REG_TBI_ANAR = 0x68
		68	REG_TBI_LPAR = 0x6A
		69	REG_PHYstatus = 0x6C
		70	REG_RxMaxSize = 0xDA
		71	REG_CPlusCmd = 0xE0
		72	REG_RxDescStartAddr = 0xE4
		73	REG_ETThReg = 0xEC
		74	REG_FuncEvent = 0xF0
		75	REG_FuncEventMask = 0xF4
		76	REG_FuncPresetState = 0xF8
		77	REG_FuncForceEvent = 0xFC
		78
		79	; InterruptStatusBits
		80	ISB_SYSErr = 0x8000
		81	ISB_PCSTimeout = 0x4000
		82	ISB_SWInt = 0x0100
		83	ISB_TxDescUnavail = 0x80
		84	ISB_RxFIFOOver = 0x40
		85	ISB_LinkChg = 0x20
		86	ISB_RxOverflow = 0x10
		87	ISB_TxErr = 0x08
		88	ISB_TxOK = 0x04
		89	ISB_RxErr = 0x02
		90	ISB_RxOK = 0x01
		91
		92	; RxStatusDesc
		93	SD_RxRES = 0x00200000
		94	SD_RxCRC = 0x00080000
		95	SD_RxRUNT = 0x00100000
		96	SD_RxRWT = 0x00400000
		97
		98	; ChipCmdBits
		99	CMD_Reset = 0x10
		100	CMD_RxEnb = 0x08
		101	CMD_TxEnb = 0x04
		102	CMD_RxBufEmpty = 0x01
		103
		104	; Cfg9346Bits
		105	CFG_9346_Lock = 0x00
		106	CFG_9346_Unlock = 0xC0
		107
		108	; rx_mode_bits
		109	RXM_AcceptErr = 0x20
		110	RXM_AcceptRunt = 0x10
		111	RXM_AcceptBroadcast = 0x08
		112	RXM_AcceptMulticast = 0x04
		113	RXM_AcceptMyPhys = 0x02
		114	RXM_AcceptAllPhys = 0x01
		115
		116	; RxConfigBits
		117	RXC_FIFOShift = 13
		118	RXC_DMAShift = 8
		119
		120	; TxConfigBits
		121	TXC_InterFrameGapShift = 24
		122	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
		123
		124	; PHYstatus
		125	PHYS_TBI_Enable = 0x80
		126	PHYS_TxFlowCtrl = 0x40
		127	PHYS_RxFlowCtrl = 0x20
		128	PHYS_1000bpsF = 0x10
		129	PHYS_100bps = 0x08
		130	PHYS_10bps = 0x04
		131	PHYS_LinkStatus = 0x02
		132	PHYS_FullDup = 0x01
		133
		134	; GIGABIT_PHY_registers
		135	PHY_CTRL_REG = 0
		136	PHY_STAT_REG = 1
		137	PHY_AUTO_NEGO_REG = 4
		138	PHY_1000_CTRL_REG = 9
		139
		140	; GIGABIT_PHY_REG_BIT
		141	PHY_Restart_Auto_Nego = 0x0200
		142	PHY_Enable_Auto_Nego = 0x1000
		143
		144	; PHY_STAT_REG = 1
		145	PHY_Auto_Neco_Comp = 0x0020
		146
		147	; PHY_AUTO_NEGO_REG = 4
		148	PHY_Cap_10_Half = 0x0020
		149	PHY_Cap_10_Full = 0x0040
		150	PHY_Cap_100_Half = 0x0080
		151	PHY_Cap_100_Full = 0x0100
		152
		153	; PHY_1000_CTRL_REG = 9
		154	PHY_Cap_1000_Full = 0x0200
		155	PHY_Cap_1000_Half = 0x0100
		156
		157	PHY_Cap_PAUSE = 0x0400
		158	PHY_Cap_ASYM_PAUSE = 0x0800
		159
		160	PHY_Cap_Null = 0x0
		161
		162	; _MediaType
		163	MT_10_Half = 0x01
		164	MT_10_Full = 0x02
		165	MT_100_Half = 0x04
		166	MT_100_Full = 0x08
		167	MT_1000_Full = 0x10
		168
		169	; _TBICSRBit
5567	hidnplayr	170	TBI_RESET = 0x80000000
		171	TBI_LOOPBACK = 0x40000000
		172	TBI_NW_ENABLE = 0x20000000
		173	TBI_NW_RESTART = 0x10000000
		174	TBI_LINK_OK = 0x02000000
		175	TBI_NW_COMPLETE = 0x01000000
3545	hidnplayr	176
		177	; _DescStatusBit
		178	DSB_OWNbit = 0x80000000
		179	DSB_EORbit = 0x40000000
		180	DSB_FSbit = 0x20000000
		181	DSB_LSbit = 0x10000000
		182
5522	hidnplayr	183	RX_BUF_SIZE = 1514 ; Rx Buffer size
3545	hidnplayr	184
		185	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
5522	hidnplayr	186	MAX_ETH_FRAME_SIZE = 1514
3545	hidnplayr	187
		188	TX_FIFO_THRESH = 256 ; In bytes
		189
		190	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
		191	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		192	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		193	ETTh = 0x3F ; 0x3F means NO threshold
		194
		195	EarlyTxThld = 0x3F ; 0x3F means NO early transmit
		196	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
		197	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
		198
		199	HZ = 1000
		200
		201	RTL_MIN_IO_SIZE = 0x80
		202	TX_TIMEOUT = (6*HZ)
		203
		204	TIMER_EXPIRE_TIME = 100
		205
		206	ETH_HDR_LEN = 14
		207	DEFAULT_MTU = 1500
5522	hidnplayr	208	DEFAULT_RX_BUF_LEN = 1514
3545	hidnplayr	209
		210
		211	;ifdef JUMBO_FRAME_SUPPORT
		212	; MAX_JUMBO_FRAME_MTU = 10000
		213	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
		214	;else
		215	MAX_RX_SKBDATA_SIZE = 1600
		216	;end if
		217
		218	MCFG_METHOD_01 = 0x01
		219	MCFG_METHOD_02 = 0x02
		220	MCFG_METHOD_03 = 0x03
		221	MCFG_METHOD_04 = 0x04
		222	MCFG_METHOD_05 = 0x05
		223	MCFG_METHOD_11 = 0x0b
		224	MCFG_METHOD_12 = 0x0c
		225	MCFG_METHOD_13 = 0x0d
		226	MCFG_METHOD_14 = 0x0e
		227	MCFG_METHOD_15 = 0x0f
		228
		229	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
		230	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
		231	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
		232
5050	hidnplayr	233	struct tx_desc
		234	status dd ?
		235	vlan_tag dd ?
		236	buf_addr dq ?
		237	ends
		238	tx_desc.buf_soft_addr = NUM_TX_DESC*sizeof.tx_desc
3545	hidnplayr	239
5050	hidnplayr	240	struct rx_desc
		241	status dd ?
		242	vlan_tag dd ?
		243	buf_addr dq ?
		244	ends
		245	rx_desc.buf_soft_addr = NUM_RX_DESC*sizeof.rx_desc
3545	hidnplayr	246
5050	hidnplayr	247	struct device ETH_DEVICE
3545	hidnplayr	248
5050	hidnplayr	249	io_addr dd ?
		250	pci_bus dd ?
		251	pci_dev dd ?
		252	irq_line db ?
		253	rb 3 ; align 4
		254	pcfg dd ?
		255	mcfg dd ?
5498	hidnplayr	256
5050	hidnplayr	257	cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
		258	cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
5498	hidnplayr	259	last_tx dd ?
5494	hidnplayr	260	mac_version dd ?
3545	hidnplayr	261
5050	hidnplayr	262	rb 0x100-($ and 0xff) ; align 256
		263	tx_ring rb NUM_TX_DESC * sizeof.tx_desc * 2
3545	hidnplayr	264
5050	hidnplayr	265	rb 0x100-($ and 0xff) ; align 256
		266	rx_ring rb NUM_RX_DESC * sizeof.rx_desc * 2
3545	hidnplayr	267
5050	hidnplayr	268	ends
3545	hidnplayr	269
		270	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
		271	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
		272
		273
		274	macro udelay msec {
		275
4803	hidnplayr	276	push esi ecx
3545	hidnplayr	277	mov esi, msec
5050	hidnplayr	278	invoke Sleep
4803	hidnplayr	279	pop ecx esi
3545	hidnplayr	280
		281	}
		282
		283	macro WRITE_GMII_REG RegAddr, value {
		284
5050	hidnplayr	285	set_io [ebx + device.io_addr], REG_PHYAR
3545	hidnplayr	286	if value eq ax
		287	and eax, 0x0000ffff
		288	or eax, 0x80000000 + (RegAddr shl 16)
		289	else
		290	mov eax, 0x80000000 + (RegAddr shl 16) + value
		291	end if
		292	out dx, eax
		293
		294	call PHY_WAIT_WRITE
		295	}
		296
		297	macro READ_GMII_REG RegAddr {
		298
		299	local .error, .done
		300
5050	hidnplayr	301	set_io [ebx + device.io_addr], REG_PHYAR
3545	hidnplayr	302	mov eax, RegAddr shl 16
		303	out dx, eax
		304
		305	call PHY_WAIT_READ
		306	jz .error
		307
		308	in eax, dx
		309	and eax, 0xFFFF
		310	jmp .done
		311
		312	.error:
		313	or eax, -1
		314	.done:
		315	}
		316
		317	align 4
		318	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR
		319
		320	udelay 1 ;;;1000
		321
		322	push ecx
		323	mov ecx, 2000
		324	; Check if the RTL8169 has completed writing/reading to the specified MII register
		325	@@:
		326	in eax, dx
		327	test eax, 0x80000000
		328	jnz .exit
		329	udelay 1 ;;;100
		330	loop @b
		331	.exit:
		332	pop ecx
		333	ret
		334
		335	align 4
		336	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR
		337
		338	udelay 1 ;;;1000
		339
		340	push ecx
		341	mov ecx, 2000
		342	; Check if the RTL8169 has completed writing/reading to the specified MII register
		343	@@:
		344	in eax, dx
		345	test eax, 0x80000000
		346	jz .exit
		347	udelay 1 ;;;100
		348	loop @b
		349	.exit:
		350	pop ecx
		351	ret
		352
		353
		354
		355	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		356	;; ;;
		357	;; proc START ;;
		358	;; ;;
		359	;; (standard driver proc) ;;
		360	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		361
5050	hidnplayr	362	proc START c, reason:dword, cmdline:dword
3545	hidnplayr	363
5050	hidnplayr	364	cmp [reason], DRV_ENTRY
		365	jne .fail
3545	hidnplayr	366
5050	hidnplayr	367	DEBUGF 2,"Loading driver\n"
		368	invoke RegService, my_service, service_proc
3545	hidnplayr	369	ret
		370
		371	.fail:
5050	hidnplayr	372	xor eax, eax
3545	hidnplayr	373	ret
		374
		375	endp
		376
		377
		378	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		379	;; ;;
		380	;; proc SERVICE_PROC ;;
		381	;; ;;
		382	;; (standard driver proc) ;;
		383	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		384
		385	proc service_proc stdcall, ioctl:dword
		386
		387	mov edx, [ioctl]
4470	hidnplayr	388	mov eax, [edx + IOCTL.io_code]
3545	hidnplayr	389
		390	;------------------------------------------------------
		391
		392	cmp eax, 0 ;SRV_GETVERSION
		393	jne @F
		394
4470	hidnplayr	395	cmp [edx + IOCTL.out_size], 4
3545	hidnplayr	396	jb .fail
4470	hidnplayr	397	mov eax, [edx + IOCTL.output]
3545	hidnplayr	398	mov [eax], dword API_VERSION
		399
		400	xor eax, eax
		401	ret
		402
		403	;------------------------------------------------------
		404	@@:
		405	cmp eax, 1 ;SRV_HOOK
		406	jne .fail
		407
4470	hidnplayr	408	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
3545	hidnplayr	409	jb .fail
		410
4470	hidnplayr	411	mov eax, [edx + IOCTL.input]
3545	hidnplayr	412	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
		413	jne .fail ; other types arent supported for this card yet
		414
		415	; check if the device is already listed
		416
		417	mov esi, device_list
		418	mov ecx, [devices]
		419	test ecx, ecx
		420	jz .firstdevice
		421
4470	hidnplayr	422	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
		423	mov ax, [eax+1] ;
3545	hidnplayr	424	.nextdevice:
		425	mov ebx, [esi]
5050	hidnplayr	426	cmp al, byte[ebx + device.pci_bus]
3545	hidnplayr	427	jne @f
5050	hidnplayr	428	cmp ah, byte[ebx + device.pci_dev]
3545	hidnplayr	429	je .find_devicenum ; Device is already loaded, let's find it's device number
		430	@@:
		431	add esi, 4
		432	loop .nextdevice
		433
		434
		435	; This device doesnt have its own eth_device structure yet, lets create one
		436	.firstdevice:
		437	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
		438	jae .fail
		439
5050	hidnplayr	440	allocate_and_clear ebx, sizeof.device, .fail ; Allocate memory to put the device structure in
3545	hidnplayr	441
		442	; Fill in the direct call addresses into the struct
		443
5050	hidnplayr	444	mov [ebx + device.reset], reset
		445	mov [ebx + device.transmit], transmit
		446	mov [ebx + device.unload], unload
		447	mov [ebx + device.name], my_service
3545	hidnplayr	448
		449	; save the pci bus and device numbers
		450
4470	hidnplayr	451	mov eax, [edx + IOCTL.input]
3545	hidnplayr	452	movzx ecx, byte[eax+1]
5050	hidnplayr	453	mov [ebx + device.pci_bus], ecx
3545	hidnplayr	454	movzx ecx, byte[eax+2]
5050	hidnplayr	455	mov [ebx + device.pci_dev], ecx
3545	hidnplayr	456
		457	; Now, it's time to find the base io addres of the PCI device
		458
5050	hidnplayr	459	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
		460	mov [ebx + device.io_addr], eax
3545	hidnplayr	461
		462	; We've found the io address, find IRQ now
		463
5050	hidnplayr	464	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
		465	mov [ebx + device.irq_line], al
3545	hidnplayr	466
		467	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
5050	hidnplayr	468	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8
3545	hidnplayr	469
		470	; Ok, the eth_device structure is ready, let's probe the device
		471	; Because initialization fires IRQ, IRQ handler must be aware of this device
		472	mov eax, [devices] ; Add the device structure to our device list
		473	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)
		474	inc [devices] ;
		475
		476	call probe ; this function will output in eax
		477	test eax, eax
		478	jnz .err2 ; If an error occured, exit
		479
5050	hidnplayr	480	mov [ebx + device.type], NET_TYPE_ETH
		481	invoke NetRegDev
3545	hidnplayr	482
		483	cmp eax, -1
		484	je .destroy
		485
		486	ret
		487
		488	; If the device was already loaded, find the device number and return it in eax
		489
		490	.find_devicenum:
		491	DEBUGF 2,"Trying to find device number of already registered device\n"
5050	hidnplayr	492	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
3545	hidnplayr	493	; into a device number in edi
		494	mov eax, edi ; Application wants it in eax instead
		495	DEBUGF 2,"Kernel says: %u\n", eax
		496	ret
		497
		498	; If an error occured, remove all allocated data and exit (returning -1 in eax)
		499
		500	.destroy:
		501	; todo: reset device into virgin state
		502
		503	.err2:
		504	dec [devices]
		505	.err:
		506	DEBUGF 2,"removing device structure\n"
5050	hidnplayr	507	invoke KernelFree, ebx
3545	hidnplayr	508	.fail:
		509	or eax, -1
		510	ret
		511
		512	;------------------------------------------------------
		513	endp
		514
		515
		516	align 4
		517	unload:
		518
		519	ret
		520
		521
		522	align 4
		523	init_board:
		524
		525	DEBUGF 1,"init_board\n"
		526
5050	hidnplayr	527	; Make the device a bus master
		528	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
7299	hidnplayr	529	or al, PCI_CMD_MASTER or PCI_CMD_PIO
5050	hidnplayr	530	invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
3545	hidnplayr	531
		532	; Soft reset the chip
5050	hidnplayr	533	set_io [ebx + device.io_addr], 0
		534	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	535	mov al, CMD_Reset
		536	out dx, al
		537
		538	; Check that the chip has finished the reset
		539	mov ecx, 1000
5050	hidnplayr	540	set_io [ebx + device.io_addr], REG_ChipCmd
5494	hidnplayr	541	@@:
		542	in al, dx
3545	hidnplayr	543	test al, CMD_Reset
		544	jz @f
		545	udelay 10
		546	loop @b
7299	hidnplayr	547	DEBUGF 2,"chip reset timeout\n"
		548	or eax, -1
		549	ret
5494	hidnplayr	550	@@:
3545	hidnplayr	551
		552
5050	hidnplayr	553	set_io [ebx + device.io_addr], REG_TxConfig
3545	hidnplayr	554	in eax, dx
5494	hidnplayr	555	mov esi, MAC_VERSION_LIST
		556	@@:
		557	mov ecx, eax
		558	and ecx, dword[esi]
		559	cmp ecx, dword[esi+4]
		560	je @f
		561	add esi, 4*4
		562	jmp @r
		563	@@:
3545	hidnplayr	564
6119	hidnplayr	565	mov ecx, [esi+8]
		566	mov [ebx + device.mac_version], ecx
		567	mov ecx, [esi+12]
		568	mov [ebx + device.name], ecx
		569	DEBUGF 2, "Detected chip: %s\n", ecx
		570	cmp dword[esi], 0
		571	jne @f
7299	hidnplayr	572	DEBUGF 1, "TxConfig = 0x%x\n", eax
6119	hidnplayr	573	@@:
3545	hidnplayr	574
		575	xor eax, eax
		576	ret
		577
		578
		579
		580	;***************************************************************************
		581	; Function
		582	; probe
		583	; Description
		584	; Searches for an ethernet card, enables it and clears the rx buffer
		585	; If a card was found, it enables the ethernet -> TCPIP link
		586	; Destroyed registers
		587	; eax, ebx, ecx, edx
		588	;
		589	;***************************************************************************
		590	align 4
		591	probe:
		592
		593	DEBUGF 1,"probe\n"
		594
		595	call init_board
		596	call read_mac
		597	call PHY_config
		598
4334	hidnplayr	599	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
5050	hidnplayr	600	set_io [ebx + device.io_addr], 0
		601	set_io [ebx + device.io_addr], 0x82
3545	hidnplayr	602	mov al, 0x01
		603	out dx, al
5050	hidnplayr	604	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	605	jae @f
4334	hidnplayr	606	DEBUGF 1,"Set PCI Latency=0x40\n"
5050	hidnplayr	607	; Adjust PCI latency to be at least 64
		608	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency
		609	cmp al, 64
		610	jae @f
		611	mov al, 64
		612	invoke PciWrite8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency, eax
		613	@@:
		614	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	615	jne @f
4334	hidnplayr	616	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
5050	hidnplayr	617	set_io [ebx + device.io_addr], 0
		618	set_io [ebx + device.io_addr], 0x82
3545	hidnplayr	619	mov al, 0x01
		620	out dx, al
4334	hidnplayr	621	DEBUGF 1,"Set PHY Reg 0x0bh = 0x00h\n"
3545	hidnplayr	622	WRITE_GMII_REG 0x0b, 0x0000 ; w 0x0b 15 0 0
		623	@@:
		624	; if TBI is not enabled
5050	hidnplayr	625	set_io [ebx + device.io_addr], 0
		626	set_io [ebx + device.io_addr], REG_PHYstatus
3545	hidnplayr	627	in al, dx
		628	test al, PHYS_TBI_Enable
		629	jz .tbi_dis
		630	READ_GMII_REG PHY_AUTO_NEGO_REG
		631
		632	; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
		633	and eax, 0x0C1F
		634	or eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
		635	WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
		636
		637	; enable 1000 Full Mode
		638	WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
		639
		640	; Enable auto-negotiation and restart auto-nigotiation
		641	WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
		642
4803	hidnplayr	643	udelay 1 ; 100
		644	mov ecx, 200 ; 10000
		645	DEBUGF 1, "Waiting for auto-negotiation to complete\n"
3545	hidnplayr	646	; wait for auto-negotiation process
		647	@@: dec ecx
		648	jz @f
5050	hidnplayr	649	set_io [ebx + device.io_addr], 0
3545	hidnplayr	650	READ_GMII_REG PHY_STAT_REG
4803	hidnplayr	651	udelay 1 ; 100
3545	hidnplayr	652	test eax, PHY_Auto_Neco_Comp
		653	jz @b
5050	hidnplayr	654	set_io [ebx + device.io_addr], REG_PHYstatus
3545	hidnplayr	655	in al, dx
		656	jmp @f
		657	.tbi_dis:
4803	hidnplayr	658	udelay 1 ; 100
3545	hidnplayr	659	@@:
4803	hidnplayr	660	DEBUGF 1, "auto-negotiation complete\n"
3545	hidnplayr	661
		662	;***************************************************************************
		663	; Function
		664	; rt8169_reset
		665	; Description
		666	; Place the chip (ie, the ethernet card) into a virgin state
		667	; Destroyed registers
		668	; eax, ebx, ecx, edx
		669	;
		670	;***************************************************************************
		671	align 4
		672	reset:
		673
4803	hidnplayr	674	DEBUGF 1,"resetting\n"
3545	hidnplayr	675
		676	call init_ring
5522	hidnplayr	677	test eax, eax
		678	jnz .err
		679
3545	hidnplayr	680	call hw_start
		681
		682	; clear packet/byte counters
		683
		684	xor eax, eax
5050	hidnplayr	685	lea edi, [ebx + device.bytes_tx]
3545	hidnplayr	686	mov ecx, 6
		687	rep stosd
		688
5050	hidnplayr	689	mov [ebx + device.mtu], 1500
5498	hidnplayr	690	call detect_link
3545	hidnplayr	691
4803	hidnplayr	692	DEBUGF 2,"init OK!\n"
3545	hidnplayr	693	xor eax, eax
		694	ret
		695
5522	hidnplayr	696	.err:
7299	hidnplayr	697	DEBUGF 2,"reset failed!\n"
5522	hidnplayr	698	or eax, -1
		699	ret
3545	hidnplayr	700
		701
		702
		703	align 4
		704	PHY_config:
		705
5050	hidnplayr	706	DEBUGF 1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n", [ebx + device.mcfg], [ebx + device.pcfg]
3545	hidnplayr	707
5050	hidnplayr	708	cmp [ebx + device.mcfg], MCFG_METHOD_04
3545	hidnplayr	709	jne .not_4
5050	hidnplayr	710	set_io [ebx + device.io_addr], 0
3545	hidnplayr	711	; WRITE_GMII_REG 0x1F, 0x0001
		712	; WRITE_GMII_REG 0x1b, 0x841e
		713	; WRITE_GMII_REG 0x0e, 0x7bfb
		714	; WRITE_GMII_REG 0x09, 0x273a
		715	WRITE_GMII_REG 0x1F, 0x0002
		716	WRITE_GMII_REG 0x01, 0x90D0
		717	WRITE_GMII_REG 0x1F, 0x0000
		718	jmp .exit
		719	.not_4:
5050	hidnplayr	720	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	721	je @f
5050	hidnplayr	722	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	723	jne .not_2_or_3
		724	@@:
5050	hidnplayr	725	set_io [ebx + device.io_addr], 0
3545	hidnplayr	726	WRITE_GMII_REG 0x1F, 0x0001
		727	WRITE_GMII_REG 0x15, 0x1000
		728	WRITE_GMII_REG 0x18, 0x65C7
		729	WRITE_GMII_REG 0x04, 0x0000
		730	WRITE_GMII_REG 0x03, 0x00A1
		731	WRITE_GMII_REG 0x02, 0x0008
		732	WRITE_GMII_REG 0x01, 0x1020
		733	WRITE_GMII_REG 0x00, 0x1000
		734	WRITE_GMII_REG 0x04, 0x0800
		735	WRITE_GMII_REG 0x04, 0x0000
		736	WRITE_GMII_REG 0x04, 0x7000
		737	WRITE_GMII_REG 0x03, 0xFF41
		738	WRITE_GMII_REG 0x02, 0xDE60
		739	WRITE_GMII_REG 0x01, 0x0140
		740	WRITE_GMII_REG 0x00, 0x0077
		741	WRITE_GMII_REG 0x04, 0x7800
		742	WRITE_GMII_REG 0x04, 0x7000
		743	WRITE_GMII_REG 0x04, 0xA000
		744	WRITE_GMII_REG 0x03, 0xDF01
		745	WRITE_GMII_REG 0x02, 0xDF20
		746	WRITE_GMII_REG 0x01, 0xFF95
		747	WRITE_GMII_REG 0x00, 0xFA00
		748	WRITE_GMII_REG 0x04, 0xA800
		749	WRITE_GMII_REG 0x04, 0xA000
		750	WRITE_GMII_REG 0x04, 0xB000
		751	WRITE_GMII_REG 0x03, 0xFF41
		752	WRITE_GMII_REG 0x02, 0xDE20
		753	WRITE_GMII_REG 0x01, 0x0140
		754	WRITE_GMII_REG 0x00, 0x00BB
		755	WRITE_GMII_REG 0x04, 0xB800
		756	WRITE_GMII_REG 0x04, 0xB000
		757	WRITE_GMII_REG 0x04, 0xF000
		758	WRITE_GMII_REG 0x03, 0xDF01
		759	WRITE_GMII_REG 0x02, 0xDF20
		760	WRITE_GMII_REG 0x01, 0xFF95
		761	WRITE_GMII_REG 0x00, 0xBF00
		762	WRITE_GMII_REG 0x04, 0xF800
		763	WRITE_GMII_REG 0x04, 0xF000
		764	WRITE_GMII_REG 0x04, 0x0000
		765	WRITE_GMII_REG 0x1F, 0x0000
		766	WRITE_GMII_REG 0x0B, 0x0000
		767	jmp .exit
		768	.not_2_or_3:
5050	hidnplayr	769	DEBUGF 1,"mcfg=%d, discard hw PHY config\n", [ebx + device.mcfg]
3545	hidnplayr	770	.exit:
		771	ret
		772
		773
		774
		775	align 4
		776	set_rx_mode:
		777
		778	DEBUGF 1,"set_rx_mode\n"
		779
		780	; IFF_ALLMULTI
		781	; Too many to filter perfectly -- accept all multicasts
5050	hidnplayr	782	set_io [ebx + device.io_addr], 0
		783	set_io [ebx + device.io_addr], REG_RxConfig
3545	hidnplayr	784	in eax, dx
5494	hidnplayr	785	and eax, 0xff7e1880
3545	hidnplayr	786	or eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
		787	out dx, eax
		788
		789	; Multicast hash filter
5050	hidnplayr	790	set_io [ebx + device.io_addr], REG_MAR0 + 0
3545	hidnplayr	791	or eax, -1
		792	out dx, eax
5050	hidnplayr	793	set_io [ebx + device.io_addr], REG_MAR0 + 4
3545	hidnplayr	794	out dx, eax
		795
		796	ret
		797
		798
		799	align 4
		800	init_ring:
		801
		802	DEBUGF 1,"init_ring\n"
		803
		804	xor eax, eax
5050	hidnplayr	805	mov [ebx + device.cur_rx], eax
		806	mov [ebx + device.cur_tx], eax
5498	hidnplayr	807	mov [ebx + device.last_tx], eax
3545	hidnplayr	808
5050	hidnplayr	809	lea edi, [ebx + device.tx_ring]
5498	hidnplayr	810	mov ecx, (NUM_TX_DESC * sizeof.tx_desc) / 4 * 2
3545	hidnplayr	811	rep stosd
		812
5050	hidnplayr	813	lea edi, [ebx + device.rx_ring]
		814	mov ecx, (NUM_RX_DESC * sizeof.rx_desc) / 4
3545	hidnplayr	815	rep stosd
		816
5498	hidnplayr	817	lea edi, [ebx + device.rx_ring]
3545	hidnplayr	818	mov ecx, NUM_RX_DESC
		819	.loop:
		820	push ecx
5522	hidnplayr	821	invoke NetAlloc, RX_BUF_SIZE+NET_BUFF.data
		822	test eax, eax
		823	jz .err
5050	hidnplayr	824	mov dword [edi + rx_desc.buf_soft_addr], eax
5498	hidnplayr	825	invoke GetPhysAddr
5522	hidnplayr	826	add eax, NET_BUFF.data
3545	hidnplayr	827	mov dword [edi + rx_desc.buf_addr], eax
		828	mov [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
5050	hidnplayr	829	add edi, sizeof.rx_desc
3545	hidnplayr	830	pop ecx
5050	hidnplayr	831	dec ecx
		832	jnz .loop
		833	or [edi - sizeof.rx_desc + rx_desc.status], DSB_EORbit
3545	hidnplayr	834
5522	hidnplayr	835	xor eax, eax
3545	hidnplayr	836	ret
		837
5522	hidnplayr	838	.err:
		839	pop eax
		840	or eax, -1
		841	ret
3545	hidnplayr	842
		843	align 4
		844	hw_start:
		845
		846	DEBUGF 1,"hw_start\n"
		847
		848	; attach int handler
5050	hidnplayr	849	movzx eax, [ebx + device.irq_line]
3545	hidnplayr	850	DEBUGF 1,"Attaching int handler to irq %x\n", eax:1
5050	hidnplayr	851	invoke AttachIntHandler, eax, int_handler, ebx
		852	test eax, eax
		853	jnz @f
		854	DEBUGF 2,"Could not attach int handler!\n"
		855	or eax, -1
		856	ret
		857	@@:
3545	hidnplayr	858
		859	; Soft reset the chip
5050	hidnplayr	860	set_io [ebx + device.io_addr], 0
		861	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	862	mov al, CMD_Reset
		863	out dx, al
		864
		865	DEBUGF 1,"Waiting for chip to reset... "
		866	; Check that the chip has finished the reset
		867	mov ecx, 1000
5050	hidnplayr	868	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	869	@@: in al, dx
		870	test al, CMD_Reset
		871	jz @f
		872	udelay 10
		873	loop @b
		874	@@:
		875	DEBUGF 1,"done!\n"
		876
5050	hidnplayr	877	set_io [ebx + device.io_addr], REG_Cfg9346
3545	hidnplayr	878	mov al, CFG_9346_Unlock
		879	out dx, al
		880
5050	hidnplayr	881	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	882	mov al, CMD_TxEnb or CMD_RxEnb
		883	out dx, al
		884
5050	hidnplayr	885	set_io [ebx + device.io_addr], REG_ETThReg
3545	hidnplayr	886	mov al, ETTh
		887	out dx, al
		888
		889	; For gigabit rtl8169
5050	hidnplayr	890	set_io [ebx + device.io_addr], REG_RxMaxSize
3545	hidnplayr	891	mov ax, RxPacketMaxSize
		892	out dx, ax
		893
		894	; Set Rx Config register
5050	hidnplayr	895	set_io [ebx + device.io_addr], REG_RxConfig
3545	hidnplayr	896	in ax, dx
5494	hidnplayr	897	and eax, 0xff7e1880
3545	hidnplayr	898	or eax, rx_config
		899	out dx, eax
		900
		901	; Set DMA burst size and Interframe Gap Time
5050	hidnplayr	902	set_io [ebx + device.io_addr], REG_TxConfig
3545	hidnplayr	903	mov eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
		904	out dx, eax
		905
5050	hidnplayr	906	set_io [ebx + device.io_addr], REG_CPlusCmd
3545	hidnplayr	907	in ax, dx
		908	out dx, ax
		909
		910	in ax, dx
		911	or ax, 1 shl 3
5050	hidnplayr	912	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	913	jne @f
5050	hidnplayr	914	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	915	jne @f
		916	or ax,1 shl 14
		917	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
		918	jmp .set
		919	@@:
		920	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n"
		921	.set:
5050	hidnplayr	922	set_io [ebx + device.io_addr], REG_CPlusCmd
3545	hidnplayr	923	out dx, ax
		924
5050	hidnplayr	925	set_io [ebx + device.io_addr], 0xE2
3545	hidnplayr	926	; mov ax, 0x1517
		927	; out dx, ax
		928	; mov ax, 0x152a
		929	; out dx, ax
		930	; mov ax, 0x282a
		931	; out dx, ax
		932	xor ax, ax
		933	out dx, ax
		934
		935	xor eax, eax
5050	hidnplayr	936	mov [ebx + device.cur_rx], eax
		937	lea eax, [ebx + device.tx_ring]
		938	invoke GetPhysAddr
		939	set_io [ebx + device.io_addr], REG_TxDescStartAddr
3545	hidnplayr	940	out dx, eax
5050	hidnplayr	941	set_io [ebx + device.io_addr], REG_TxDescStartAddr + 4
4301	clevermous	942	xor eax, eax
		943	out dx, eax
3545	hidnplayr	944
5050	hidnplayr	945	lea eax, [ebx + device.rx_ring]
		946	invoke GetPhysAddr
		947	set_io [ebx + device.io_addr], REG_RxDescStartAddr
3545	hidnplayr	948	out dx, eax
4301	clevermous	949	xor eax, eax
5050	hidnplayr	950	set_io [ebx + device.io_addr], REG_RxDescStartAddr + 4
4301	clevermous	951	out dx, eax
3545	hidnplayr	952
5050	hidnplayr	953	set_io [ebx + device.io_addr], REG_Cfg9346
3545	hidnplayr	954	mov al, CFG_9346_Lock
		955	out dx, al
		956
		957	udelay 10
		958
		959	xor eax, eax
5050	hidnplayr	960	set_io [ebx + device.io_addr], REG_RxMissed
3545	hidnplayr	961	out dx, eax
		962
		963	call set_rx_mode
		964
5050	hidnplayr	965	set_io [ebx + device.io_addr], 0
3545	hidnplayr	966	; no early-rx interrupts
5050	hidnplayr	967	set_io [ebx + device.io_addr], REG_MultiIntr
3545	hidnplayr	968	in ax, dx
		969	and ax, 0xF000
		970	out dx, ax
		971
		972	; set interrupt mask
5050	hidnplayr	973	set_io [ebx + device.io_addr], REG_IntrMask
3545	hidnplayr	974	mov ax, intr_mask
		975	out dx, ax
		976
		977	xor eax, eax
		978	ret
		979
		980
		981	align 4
		982	read_mac:
		983
5050	hidnplayr	984	set_io [ebx + device.io_addr], 0
		985	set_io [ebx + device.io_addr], REG_MAC0
3545	hidnplayr	986	xor ecx, ecx
5050	hidnplayr	987	lea edi, [ebx + device.mac]
3545	hidnplayr	988	mov ecx, 6
		989
		990	; Get MAC address. FIXME: read EEPROM
5498	hidnplayr	991	@@:
		992	in al, dx
3545	hidnplayr	993	stosb
		994	inc edx
		995	loop @r
		996
		997	DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\
5050	hidnplayr	998	[ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,[ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
3545	hidnplayr	999
		1000	ret
		1001
		1002	align 4
		1003	write_mac:
		1004
		1005	ret 6
		1006
		1007
		1008	;***************************************************************************
		1009	; Function
		1010	; transmit
		1011	; Description
		1012	; Transmits a packet of data via the ethernet card
		1013	;
		1014	; Destroyed registers
		1015	; eax, edx, esi, edi
		1016	;
		1017	;***************************************************************************
		1018
5522	hidnplayr	1019	proc transmit stdcall bufferptr
5050	hidnplayr	1020
		1021	pushf
		1022	cli
		1023
5522	hidnplayr	1024	mov esi, [bufferptr]
		1025	DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [esi + NET_BUFF.length]
		1026	lea eax, [esi + NET_BUFF.data]
3545	hidnplayr	1027	DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
		1028	[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
		1029	[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
		1030	[eax+13]:2,[eax+12]:2
		1031
5522	hidnplayr	1032	cmp [esi + NET_BUFF.length], 1514
3545	hidnplayr	1033	ja .fail
5522	hidnplayr	1034	cmp [esi + NET_BUFF.length], 60
5050	hidnplayr	1035	jb .fail
3545	hidnplayr	1036
		1037	;----------------------------------
		1038	; Find currentTX descriptor address
		1039
5050	hidnplayr	1040	mov eax, sizeof.tx_desc
		1041	mul [ebx + device.cur_tx]
		1042	lea esi, [ebx + device.tx_ring + eax]
3545	hidnplayr	1043
		1044	DEBUGF 1,"Using TX desc: %x\n", esi
		1045
5498	hidnplayr	1046	;----------------------------------
		1047	; Check if the descriptor is in use
		1048
		1049	test [esi + tx_desc.status], DSB_OWNbit
		1050	jnz .desc
		1051
3545	hidnplayr	1052	;---------------------------
		1053	; Program the packet pointer
		1054
5050	hidnplayr	1055	mov eax, [bufferptr]
5522	hidnplayr	1056	mov ecx, [eax + NET_BUFF.length]
3545	hidnplayr	1057	mov [esi + tx_desc.buf_soft_addr], eax
5522	hidnplayr	1058	add eax, [eax + NET_BUFF.offset]
5050	hidnplayr	1059	invoke GetPhysAddr
3545	hidnplayr	1060	mov dword [esi + tx_desc.buf_addr], eax
		1061
		1062	;------------------------
		1063	; Program the packet size
		1064
5522	hidnplayr	1065	mov eax, ecx
5498	hidnplayr	1066	or eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
5050	hidnplayr	1067	cmp [ebx + device.cur_tx], NUM_TX_DESC - 1
3545	hidnplayr	1068	jne @f
		1069	or eax, DSB_EORbit
5498	hidnplayr	1070	@@:
		1071	mov [esi + tx_desc.status], eax
3545	hidnplayr	1072
		1073	;-----------------------------------------
		1074	; Set the polling bit (start transmission)
		1075
5050	hidnplayr	1076	set_io [ebx + device.io_addr], 0
		1077	set_io [ebx + device.io_addr], REG_TxPoll
3545	hidnplayr	1078	mov al, 0x40 ; set polling bit
		1079	out dx, al
		1080
		1081	;-----------------------
		1082	; Update TX descriptor
		1083
5050	hidnplayr	1084	inc [ebx + device.cur_tx]
		1085	and [ebx + device.cur_tx], NUM_TX_DESC - 1
3545	hidnplayr	1086
		1087	;-------------
		1088	; Update stats
		1089
5050	hidnplayr	1090	inc [ebx + device.packets_tx]
5522	hidnplayr	1091	add dword [ebx + device.bytes_tx], ecx
5050	hidnplayr	1092	adc dword [ebx + device.bytes_tx + 4], 0
3545	hidnplayr	1093
5126	hidnplayr	1094	popf
3545	hidnplayr	1095	xor eax, eax
5050	hidnplayr	1096	ret
3545	hidnplayr	1097
5498	hidnplayr	1098	.desc:
		1099	DEBUGF 2,"Descriptor is still in use!\n"
3545	hidnplayr	1100	.fail:
5050	hidnplayr	1101	DEBUGF 2,"Transmit failed\n"
5522	hidnplayr	1102	invoke NetFree, [bufferptr]
5050	hidnplayr	1103	popf
3545	hidnplayr	1104	or eax, -1
5050	hidnplayr	1105	ret
3545	hidnplayr	1106
5050	hidnplayr	1107	endp
3545	hidnplayr	1108
5050	hidnplayr	1109
3545	hidnplayr	1110
		1111	;;;;;;;;;;;;;;;;;;;;;;;
		1112	;; ;;
		1113	;; Interrupt handler ;;
		1114	;; ;;
		1115	;;;;;;;;;;;;;;;;;;;;;;;
		1116
		1117	align 4
		1118	int_handler:
		1119
		1120	push ebx esi edi
		1121
4334	hidnplayr	1122	DEBUGF 1,"INT\n"
3545	hidnplayr	1123
		1124	; find pointer of device wich made IRQ occur
		1125
		1126	mov ecx, [devices]
		1127	test ecx, ecx
		1128	jz .nothing
		1129	mov esi, device_list
		1130	.nextdevice:
		1131	mov ebx, [esi]
		1132
5050	hidnplayr	1133	set_io [ebx + device.io_addr], 0
		1134	set_io [ebx + device.io_addr], REG_IntrStatus
3545	hidnplayr	1135	in ax, dx
5498	hidnplayr	1136	out dx, ax ; ACK all interrupts
		1137	cmp ax, 0xffff ; if so, hardware is no longer present
		1138	je .nothing
3545	hidnplayr	1139	test ax, ax
		1140	jnz .got_it
		1141	.continue:
		1142	add esi, 4
		1143	dec ecx
		1144	jnz .nextdevice
		1145	.nothing:
		1146	pop edi esi ebx
		1147	xor eax, eax
		1148
		1149	ret ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
		1150
		1151	.got_it:
5050	hidnplayr	1152	DEBUGF 1,"Device: %x Status: %x\n", ebx, ax
3545	hidnplayr	1153
		1154	;--------
		1155	; Receive
		1156	test ax, ISB_RxOK
		1157	jz .no_rx
		1158
		1159	push ax
		1160	push ebx
		1161
5567	hidnplayr	1162	.rx_loop:
3545	hidnplayr	1163	pop ebx
5050	hidnplayr	1164	mov eax, sizeof.rx_desc
		1165	mul [ebx + device.cur_rx]
		1166	lea esi, [ebx + device.rx_ring + eax]
3545	hidnplayr	1167
		1168	DEBUGF 1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
5522	hidnplayr	1169	mov ecx, [esi + rx_desc.status]
5567	hidnplayr	1170	test ecx, DSB_OWNbit
5522	hidnplayr	1171	jnz .rx_return
3545	hidnplayr	1172
5050	hidnplayr	1173	DEBUGF 1,"cur_rx = %u\n", [ebx + device.cur_rx]
5522	hidnplayr	1174	test ecx, SD_RxRES
5567	hidnplayr	1175	jnz .rx_reuse
3545	hidnplayr	1176
		1177	push ebx
5567	hidnplayr	1178	push .rx_loop
5522	hidnplayr	1179	and ecx, 0x00001FFF
		1180	add ecx, -4 ; we dont need CRC
		1181	DEBUGF 1,"data length = %u\n", ecx
		1182	mov eax, [esi + rx_desc.buf_soft_addr]
3545	hidnplayr	1183	push eax
5522	hidnplayr	1184	mov [eax + NET_BUFF.length], ecx
		1185	mov [eax + NET_BUFF.device], ebx
		1186	mov [eax + NET_BUFF.offset], NET_BUFF.data
3545	hidnplayr	1187
5522	hidnplayr	1188	;-------------
		1189	; Update stats
3545	hidnplayr	1190
6480	hidnplayr	1191	add dword [ebx + device.bytes_rx], ecx
5050	hidnplayr	1192	adc dword [ebx + device.bytes_rx + 4], 0
		1193	inc [ebx + device.packets_rx]
3545	hidnplayr	1194
5522	hidnplayr	1195	;----------------------
		1196	; Allocate a new buffer
3545	hidnplayr	1197
5567	hidnplayr	1198	mov [esi + rx_desc.status], 0
5522	hidnplayr	1199	invoke NetAlloc, RX_BUF_SIZE+NET_BUFF.data
5567	hidnplayr	1200	test eax, eax
		1201	jz .no_more_buffers
3545	hidnplayr	1202	mov [esi + rx_desc.buf_soft_addr], eax
5050	hidnplayr	1203	invoke GetPhysAddr
5522	hidnplayr	1204	add eax, NET_BUFF.data
3545	hidnplayr	1205	mov dword [esi + rx_desc.buf_addr], eax
		1206
5522	hidnplayr	1207	;---------------
		1208	; re set OWN bit
3545	hidnplayr	1209
		1210	mov eax, DSB_OWNbit or RX_BUF_SIZE
5050	hidnplayr	1211	cmp [ebx + device.cur_rx], NUM_RX_DESC - 1
3545	hidnplayr	1212	jne @f
		1213	or eax, DSB_EORbit
5050	hidnplayr	1214	@@:
		1215	mov [esi + rx_desc.status], eax
3545	hidnplayr	1216
5567	hidnplayr	1217	.no_more_buffers:
5522	hidnplayr	1218	;--------------
		1219	; Update rx ptr
3545	hidnplayr	1220
5050	hidnplayr	1221	inc [ebx + device.cur_rx]
		1222	and [ebx + device.cur_rx], NUM_RX_DESC - 1
3545	hidnplayr	1223
5522	hidnplayr	1224	jmp [EthInput]
5567	hidnplayr	1225
		1226	.rx_reuse:
		1227	mov eax, DSB_OWNbit or RX_BUF_SIZE
		1228	cmp [ebx + device.cur_rx], NUM_RX_DESC - 1
		1229	jne @f
		1230	or eax, DSB_EORbit
		1231	@@:
		1232	mov [esi + rx_desc.status], eax
		1233	push ebx
		1234	jmp .rx_loop
		1235
3545	hidnplayr	1236	.rx_return:
		1237	pop ax
		1238	.no_rx:
		1239
5498	hidnplayr	1240	;-----------------
		1241	; Transmit cleanup
3545	hidnplayr	1242
5498	hidnplayr	1243	test ax, ISB_TxOK or ISB_TxErr or ISB_TxDescUnavail
3545	hidnplayr	1244	jz .no_tx
5522	hidnplayr	1245	push ax
3545	hidnplayr	1246
5498	hidnplayr	1247	DEBUGF 1,"TX done!\n"
5522	hidnplayr	1248
		1249	mov ecx, NUM_TX_DESC
		1250	lea esi, [ebx + device.tx_ring]
5498	hidnplayr	1251	.txloop:
5050	hidnplayr	1252	cmp dword [esi + tx_desc.buf_soft_addr], 0
5522	hidnplayr	1253	jz .maybenext
3545	hidnplayr	1254
		1255	test [esi + tx_desc.status], DSB_OWNbit
5522	hidnplayr	1256	jnz .maybenext
3545	hidnplayr	1257
5522	hidnplayr	1258	push ecx
		1259	DEBUGF 1,"Freeing up TX desc: %x\n", esi
		1260	invoke NetFree, [esi + tx_desc.buf_soft_addr]
		1261	pop ecx
5050	hidnplayr	1262	and dword [esi + tx_desc.buf_soft_addr], 0
3545	hidnplayr	1263
5522	hidnplayr	1264	.maybenext:
		1265	add esi, sizeof.tx_desc
		1266	dec ecx
		1267	jnz .txloop
		1268
		1269	pop ax
3545	hidnplayr	1270	.no_tx:
		1271
5498	hidnplayr	1272	test ax, ISB_LinkChg
		1273	jz .no_linkchange
		1274	DEBUGF 2, "Link change detected\n"
		1275	call detect_link
		1276	.no_linkchange:
3545	hidnplayr	1277
		1278	pop edi esi ebx
		1279	xor eax, eax
		1280	inc eax
		1281
		1282	ret
		1283
		1284
		1285
5498	hidnplayr	1286	align 4
		1287	detect_link:
		1288
		1289	set_io [ebx + device.io_addr], 0
		1290
		1291	; set_io [ebx + device.io_addr], REG_TBICSR
		1292	; in eax, dx
		1293	; test eax, TBI_LinkOK
		1294	; jz .down
		1295
		1296	; mov [ebx + device.state], ETH_LINK_UNKNOWN
		1297	; invoke NetLinkChanged
		1298	; ret
		1299
		1300	set_io [ebx + device.io_addr], REG_PHYstatus
		1301	in al, dx
		1302	test al, PHYS_LinkStatus
		1303	jz .down
		1304	DEBUGF 2, "Link is up, phystatus=0x%x\n", al
		1305	xor ecx, ecx
		1306	test al, PHYS_10bps
		1307	jz @f
		1308	or cl, ETH_LINK_10M
		1309	@@:
		1310	test al, PHYS_100bps
		1311	jz @f
		1312	or cl, ETH_LINK_100M
		1313	@@:
		1314	test al, PHYS_1000bpsF
		1315	jz @f
		1316	or cl, ETH_LINK_1G ;or ETH_LINK_FD
		1317	@@:
		1318	test al, PHYS_FullDup
		1319	jz @f
		1320	or cl, ETH_LINK_FD
		1321	@@:
		1322	mov [ebx + device.state], ecx
		1323	invoke NetLinkChanged
		1324	ret
		1325
		1326	.down:
		1327	DEBUGF 2, "Link is down\n"
		1328	mov [ebx + device.state], ETH_LINK_DOWN
		1329	invoke NetLinkChanged
		1330	ret
		1331
		1332
		1333
5050	hidnplayr	1334	; End of code
3545	hidnplayr	1335
5050	hidnplayr	1336	data fixups
		1337	end data
3545	hidnplayr	1338
5050	hidnplayr	1339	include '../peimport.inc'
3545	hidnplayr	1340
		1341	my_service db 'RTL8169',0 ; max 16 chars include zero
		1342
		1343	include_debug_strings ; All data wich FDO uses will be included here
		1344
5494	hidnplayr	1345	MAC_VERSION_LIST:
3545	hidnplayr	1346
7299	hidnplayr	1347	; 8168E+ family
		1348	dd 0x7cf00000, 0x50200000, 51, sz_rtl8168ep
		1349	dd 0x7cf00000, 0x50100000, 50, sz_rtl8168ep
		1350	dd 0x7cf00000, 0x50000000, 49, sz_rtl8168ep
3545	hidnplayr	1351
7299	hidnplayr	1352	; 8168H family
		1353	dd 0x7cf00000, 0x54100000, 46, sz_rtl8168h
		1354	dd 0x7cf00000, 0x54000000, 45, sz_rtl8168h
3545	hidnplayr	1355
7299	hidnplayr	1356	; 8168G family
		1357	dd 0x7cf00000, 0x5c800000, 44, sz_rtl8411
		1358	dd 0x7cf00000, 0x50900000, 42, sz_rtl8168g
		1359	dd 0x7cf00000, 0x4c100000, 41, sz_rtl8168g
		1360	dd 0x7cf00000, 0x4c000000, 40, sz_rtl8168g
5494	hidnplayr	1361
7299	hidnplayr	1362	; 8168F family
		1363	dd 0x7c800000, 0x48800000, 38, sz_rtl8411
		1364	dd 0x7cf00000, 0x48100000, 36, sz_rtl8168f
		1365	dd 0x7cf00000, 0x48000000, 35, sz_rtl8168f
5494	hidnplayr	1366
7299	hidnplayr	1367	; 8168E family
		1368	dd 0x7c800000, 0x2c800000, 34, sz_rtl8168evl
		1369	dd 0x7cf00000, 0x2c200000, 33, sz_rtl8168e
		1370	dd 0x7cf00000, 0x2c100000, 32, sz_rtl8168e
		1371	dd 0x7c800000, 0x2c000000, 33, sz_rtl8168e
5494	hidnplayr	1372
7299	hidnplayr	1373	; 8168D family
		1374	dd 0x7cf00000, 0x28300000, 26, sz_rtl8168d
		1375	dd 0x7cf00000, 0x28100000, 25, sz_rtl8168d
		1376	dd 0x7c800000, 0x28000000, 26, sz_rtl8168d
5494	hidnplayr	1377
7299	hidnplayr	1378	; 8168D+ family
		1379	dd 0x7cf00000, 0x28800000, 27, sz_rtl8168dp
		1380	dd 0x7cf00000, 0x28a00000, 28, sz_rtl8168dp
5494	hidnplayr	1381
7299	hidnplayr	1382	; 8168C family
		1383	dd 0x7cf00000, 0x3cb00000, 24, sz_rtl8168p
		1384	dd 0x7cf00000, 0x3c900000, 23, sz_rtl8168p
		1385	dd 0x7cf00000, 0x3c800000, 18, sz_rtl8168p
		1386	dd 0x7c800000, 0x3c800000, 24, sz_rtl8168p
		1387	dd 0x7cf00000, 0x3c000000, 19, sz_rtl8168c
		1388	dd 0x7cf00000, 0x3c200000, 20, sz_rtl8168c
		1389	dd 0x7cf00000, 0x3c300000, 21, sz_rtl8168c
		1390	dd 0x7cf00000, 0x3c400000, 22, sz_rtl8168c
		1391	dd 0x7c800000, 0x3c000000, 22, sz_rtl8168c
5494	hidnplayr	1392
7299	hidnplayr	1393	; 8168B family
		1394	dd 0x7cf00000, 0x38000000, 12, sz_rtl8168b
		1395	dd 0x7cf00000, 0x38500000, 17, sz_rtl8101e
		1396	dd 0x7c800000, 0x38000000, 17, sz_rtl8101e
		1397	dd 0x7c800000, 0x30000000, 11, sz_rtl8168b
5494	hidnplayr	1398
7299	hidnplayr	1399	; 8101 family
		1400	dd 0x7cf00000, 0x44900000, 39, sz_rtl8106e
		1401	dd 0x7c800000, 0x44800000, 39, sz_rtl8106e
		1402	dd 0x7c800000, 0x44000000, 37, sz_rtl8402
		1403	dd 0x7cf00000, 0x40b00000, 30, sz_rtl8105e
		1404	dd 0x7cf00000, 0x40a00000, 30, sz_rtl8105e
		1405	dd 0x7cf00000, 0x40900000, 29, sz_rtl8105e
		1406	dd 0x7c800000, 0x40800000, 30, sz_rtl8105e
		1407	dd 0x7cf00000, 0x34a00000, 09, sz_rtl8102e
		1408	dd 0x7cf00000, 0x24a00000, 09, sz_rtl8102e
		1409	dd 0x7cf00000, 0x34900000, 08, sz_rtl8102e
		1410	dd 0x7cf00000, 0x24900000, 08, sz_rtl8102e
		1411	dd 0x7cf00000, 0x34800000, 07, sz_rtl8102e
		1412	dd 0x7cf00000, 0x24800000, 07, sz_rtl8102e
		1413	dd 0x7cf00000, 0x34000000, 13, sz_rtl8101e
		1414	dd 0x7cf00000, 0x34300000, 10, sz_rtl8101e
		1415	dd 0x7cf00000, 0x34200000, 16, sz_rtl8168b
		1416	dd 0x7c800000, 0x34800000, 09, sz_rtl8102e
		1417	dd 0x7c800000, 0x24800000, 09, sz_rtl8102e
		1418	dd 0x7c800000, 0x34000000, 16, sz_rtl8168b
		1419	dd 0xfc800000, 0x38800000, 15, sz_rtl8100e
		1420	dd 0xfc800000, 0x30800000, 14, sz_rtl8100e
5494	hidnplayr	1421
7299	hidnplayr	1422	; 8110 family
		1423	dd 0xfc800000, 0x98000000, 06, sz_rtl8169sc
		1424	dd 0xfc800000, 0x18000000, 05, sz_rtl8169sc
		1425	dd 0xfc800000, 0x10000000, 04, sz_rtl8169sb
		1426	dd 0xfc800000, 0x04000000, 03, sz_rtl8110s
		1427	dd 0xfc800000, 0x00800000, 02, sz_rtl8169s
		1428	dd 0xfc800000, 0x00000000, 01, sz_rtl8169
5494	hidnplayr	1429
		1430	; Catch-all
7299	hidnplayr	1431	dd 0x00000000, 0x00000000, 0, sz_unknown
5494	hidnplayr	1432
7299	hidnplayr	1433	sz_rtl8169 db "Realtek 8169",0
		1434	sz_rtl8169s db "Realtek 8169s",0
		1435	sz_rtl8110s db "Realtek 8110s",0
		1436	sz_rtl8169sb db "Realtek 8169sb/8110sb",0
		1437	sz_rtl8169sc db "Realtek 8169sc/8110sc",0
		1438	sz_rtl8102e db "Realtek 8102e",0
		1439	sz_rtl8101e db "Realtek 8101e",0
		1440	sz_rtl8168b db "Realtek 8168b/8111b",0
		1441	sz_rtl8100e db "Realtek 8100e",0
		1442	sz_rtl8168p db "Realtek 8168c+/8111c+",0
		1443	sz_rtl8168c db "Realtek 8168c/8111c",0
		1444	sz_rtl8168d db "Realtek 8168d/8111d",0
		1445	sz_rtl8168dp db "Realtek 8168d+/8111d+",0
		1446	sz_rtl8105e db "Realtek 8105e",0
		1447	sz_rtl8168e db "Realtek 8168e/8111e",0
		1448	sz_rtl8168evl db "Realtek 8168evl/8111evl",0
		1449	sz_rtl8168f db "Realtek 8168f/8111f",0
		1450	sz_rtl8402 db "Realtek 8402",0
		1451	sz_rtl8411 db "Realtek 8411",0
		1452	sz_rtl8106e db "Realtek 8106e",0
		1453	sz_rtl8168ep db "Realtek 8168e+",0
		1454	sz_rtl8168g db "Realtek 8168g/8111g",0
		1455	sz_rtl8168h db "Realtek 8168h/8111h",0
		1456	sz_unknown db "unknown RTL8169 rev",0
5494	hidnplayr	1457
5050	hidnplayr	1458	align 4
		1459	devices dd 0
3545	hidnplayr	1460	device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling
		1461

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(root)/drivers/ethernet/RTL8169.asm – Rev 7299