WebSVN – Kolibri OS – Blame – /drivers/ethernet/RTL8169.asm

Rev	Author	Line No.	Line
3545	hidnplayr	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
5363	yogev_ezra	3	;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;
3545	hidnplayr	4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;; RTL8169 driver for KolibriOS ;;
		7	;; ;;
		8	;; Copyright 2007 mike.dld, ;;
		9	;; mike.dld@gmail.com ;;
		10	;; ;;
		11	;; port to net branch by hidnplayr ;;
		12	;; ;;
		13	;; References: ;;
		14	;; r8169.c - linux driver (etherboot project) ;;
		15	;; ;;
		16	;; GNU GENERAL PUBLIC LICENSE ;;
		17	;; Version 2, June 1991 ;;
		18	;; ;;
		19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		20
5050	hidnplayr	21	format PE DLL native
		22	entry START
3545	hidnplayr	23
5050	hidnplayr	24	CURRENT_API = 0x0200
		25	COMPATIBLE_API = 0x0100
		26	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
3545	hidnplayr	27
		28	MAX_DEVICES = 16
		29
		30	__DEBUG__ = 1
5050	hidnplayr	31	__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only
3545	hidnplayr	32
		33	NUM_TX_DESC = 4
		34	NUM_RX_DESC = 4
		35
5050	hidnplayr	36	section '.flat' readable writable executable
		37
		38	include '../proc32.inc'
4467	hidnplayr	39	include '../struct.inc'
		40	include '../macros.inc'
3545	hidnplayr	41	include '../fdo.inc'
5074	hidnplayr	42	include '../netdrv.inc'
3545	hidnplayr	43
		44	REG_MAC0 = 0x0 ; Ethernet hardware address
		45	REG_MAR0 = 0x8 ; Multicast filter
		46	REG_TxDescStartAddr = 0x20
		47	REG_TxHDescStartAddr = 0x28
		48	REG_FLASH = 0x30
		49	REG_ERSR = 0x36
		50	REG_ChipCmd = 0x37
		51	REG_TxPoll = 0x38
		52	REG_IntrMask = 0x3C
		53	REG_IntrStatus = 0x3E
		54	REG_TxConfig = 0x40
		55	REG_RxConfig = 0x44
		56	REG_RxMissed = 0x4C
		57	REG_Cfg9346 = 0x50
		58	REG_Config0 = 0x51
		59	REG_Config1 = 0x52
		60	REG_Config2 = 0x53
		61	REG_Config3 = 0x54
		62	REG_Config4 = 0x55
		63	REG_Config5 = 0x56
		64	REG_MultiIntr = 0x5C
		65	REG_PHYAR = 0x60
		66	REG_TBICSR = 0x64
		67	REG_TBI_ANAR = 0x68
		68	REG_TBI_LPAR = 0x6A
		69	REG_PHYstatus = 0x6C
		70	REG_RxMaxSize = 0xDA
		71	REG_CPlusCmd = 0xE0
		72	REG_RxDescStartAddr = 0xE4
		73	REG_ETThReg = 0xEC
		74	REG_FuncEvent = 0xF0
		75	REG_FuncEventMask = 0xF4
		76	REG_FuncPresetState = 0xF8
		77	REG_FuncForceEvent = 0xFC
		78
		79	; InterruptStatusBits
		80	ISB_SYSErr = 0x8000
		81	ISB_PCSTimeout = 0x4000
		82	ISB_SWInt = 0x0100
		83	ISB_TxDescUnavail = 0x80
		84	ISB_RxFIFOOver = 0x40
		85	ISB_LinkChg = 0x20
		86	ISB_RxOverflow = 0x10
		87	ISB_TxErr = 0x08
		88	ISB_TxOK = 0x04
		89	ISB_RxErr = 0x02
		90	ISB_RxOK = 0x01
		91
		92	; RxStatusDesc
		93	SD_RxRES = 0x00200000
		94	SD_RxCRC = 0x00080000
		95	SD_RxRUNT = 0x00100000
		96	SD_RxRWT = 0x00400000
		97
		98	; ChipCmdBits
		99	CMD_Reset = 0x10
		100	CMD_RxEnb = 0x08
		101	CMD_TxEnb = 0x04
		102	CMD_RxBufEmpty = 0x01
		103
		104	; Cfg9346Bits
		105	CFG_9346_Lock = 0x00
		106	CFG_9346_Unlock = 0xC0
		107
		108	; rx_mode_bits
		109	RXM_AcceptErr = 0x20
		110	RXM_AcceptRunt = 0x10
		111	RXM_AcceptBroadcast = 0x08
		112	RXM_AcceptMulticast = 0x04
		113	RXM_AcceptMyPhys = 0x02
		114	RXM_AcceptAllPhys = 0x01
		115
		116	; RxConfigBits
		117	RXC_FIFOShift = 13
		118	RXC_DMAShift = 8
		119
		120	; TxConfigBits
		121	TXC_InterFrameGapShift = 24
		122	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
		123
		124	; PHYstatus
		125	PHYS_TBI_Enable = 0x80
		126	PHYS_TxFlowCtrl = 0x40
		127	PHYS_RxFlowCtrl = 0x20
		128	PHYS_1000bpsF = 0x10
		129	PHYS_100bps = 0x08
		130	PHYS_10bps = 0x04
		131	PHYS_LinkStatus = 0x02
		132	PHYS_FullDup = 0x01
		133
		134	; GIGABIT_PHY_registers
		135	PHY_CTRL_REG = 0
		136	PHY_STAT_REG = 1
		137	PHY_AUTO_NEGO_REG = 4
		138	PHY_1000_CTRL_REG = 9
		139
		140	; GIGABIT_PHY_REG_BIT
		141	PHY_Restart_Auto_Nego = 0x0200
		142	PHY_Enable_Auto_Nego = 0x1000
		143
		144	; PHY_STAT_REG = 1
		145	PHY_Auto_Neco_Comp = 0x0020
		146
		147	; PHY_AUTO_NEGO_REG = 4
		148	PHY_Cap_10_Half = 0x0020
		149	PHY_Cap_10_Full = 0x0040
		150	PHY_Cap_100_Half = 0x0080
		151	PHY_Cap_100_Full = 0x0100
		152
		153	; PHY_1000_CTRL_REG = 9
		154	PHY_Cap_1000_Full = 0x0200
		155	PHY_Cap_1000_Half = 0x0100
		156
		157	PHY_Cap_PAUSE = 0x0400
		158	PHY_Cap_ASYM_PAUSE = 0x0800
		159
		160	PHY_Cap_Null = 0x0
		161
		162	; _MediaType
		163	MT_10_Half = 0x01
		164	MT_10_Full = 0x02
		165	MT_100_Half = 0x04
		166	MT_100_Full = 0x08
		167	MT_1000_Full = 0x10
		168
		169	; _TBICSRBit
		170	TBI_LinkOK = 0x02000000
		171
		172	; _DescStatusBit
		173	DSB_OWNbit = 0x80000000
		174	DSB_EORbit = 0x40000000
		175	DSB_FSbit = 0x20000000
		176	DSB_LSbit = 0x10000000
		177
		178	RX_BUF_SIZE = 1536 ; Rx Buffer size
		179
		180	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
		181	MAX_ETH_FRAME_SIZE = 1536
		182
		183	TX_FIFO_THRESH = 256 ; In bytes
		184
		185	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
		186	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		187	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		188	ETTh = 0x3F ; 0x3F means NO threshold
		189
		190	EarlyTxThld = 0x3F ; 0x3F means NO early transmit
		191	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
		192	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
		193
		194	HZ = 1000
		195
		196	RTL_MIN_IO_SIZE = 0x80
		197	TX_TIMEOUT = (6*HZ)
		198
		199	TIMER_EXPIRE_TIME = 100
		200
		201	ETH_HDR_LEN = 14
		202	DEFAULT_MTU = 1500
		203	DEFAULT_RX_BUF_LEN = 1536
		204
		205
		206	;ifdef JUMBO_FRAME_SUPPORT
		207	; MAX_JUMBO_FRAME_MTU = 10000
		208	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
		209	;else
		210	MAX_RX_SKBDATA_SIZE = 1600
		211	;end if
		212
		213	MCFG_METHOD_01 = 0x01
		214	MCFG_METHOD_02 = 0x02
		215	MCFG_METHOD_03 = 0x03
		216	MCFG_METHOD_04 = 0x04
		217	MCFG_METHOD_05 = 0x05
		218	MCFG_METHOD_11 = 0x0b
		219	MCFG_METHOD_12 = 0x0c
		220	MCFG_METHOD_13 = 0x0d
		221	MCFG_METHOD_14 = 0x0e
		222	MCFG_METHOD_15 = 0x0f
		223
		224	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
		225	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
		226	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
		227
5050	hidnplayr	228	struct tx_desc
		229	status dd ?
		230	vlan_tag dd ?
		231	buf_addr dq ?
		232	ends
		233	tx_desc.buf_soft_addr = NUM_TX_DESC*sizeof.tx_desc
3545	hidnplayr	234
5050	hidnplayr	235	struct rx_desc
		236	status dd ?
		237	vlan_tag dd ?
		238	buf_addr dq ?
		239	ends
		240	rx_desc.buf_soft_addr = NUM_RX_DESC*sizeof.rx_desc
3545	hidnplayr	241
5050	hidnplayr	242	struct device ETH_DEVICE
3545	hidnplayr	243
5050	hidnplayr	244	io_addr dd ?
		245	pci_bus dd ?
		246	pci_dev dd ?
		247	irq_line db ?
		248	rb 3 ; align 4
		249	mmio_addr dd ? ; memory map physical address
		250	pcfg dd ?
		251	mcfg dd ?
5498	hidnplayr	252
5050	hidnplayr	253	cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
		254	cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
5498	hidnplayr	255	last_tx dd ?
5494	hidnplayr	256	mac_version dd ?
3545	hidnplayr	257
5050	hidnplayr	258	rb 0x100-($ and 0xff) ; align 256
		259	tx_ring rb NUM_TX_DESC * sizeof.tx_desc * 2
3545	hidnplayr	260
5050	hidnplayr	261	rb 0x100-($ and 0xff) ; align 256
		262	rx_ring rb NUM_RX_DESC * sizeof.rx_desc * 2
3545	hidnplayr	263
5050	hidnplayr	264	ends
3545	hidnplayr	265
		266	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
		267	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
		268
		269
		270	macro udelay msec {
		271
4803	hidnplayr	272	push esi ecx
3545	hidnplayr	273	mov esi, msec
5050	hidnplayr	274	invoke Sleep
4803	hidnplayr	275	pop ecx esi
3545	hidnplayr	276
		277	}
		278
		279	macro WRITE_GMII_REG RegAddr, value {
		280
5050	hidnplayr	281	set_io [ebx + device.io_addr], REG_PHYAR
3545	hidnplayr	282	if value eq ax
		283	and eax, 0x0000ffff
		284	or eax, 0x80000000 + (RegAddr shl 16)
		285	else
		286	mov eax, 0x80000000 + (RegAddr shl 16) + value
		287	end if
		288	out dx, eax
		289
		290	call PHY_WAIT_WRITE
		291	}
		292
		293	macro READ_GMII_REG RegAddr {
		294
		295	local .error, .done
		296
5050	hidnplayr	297	set_io [ebx + device.io_addr], REG_PHYAR
3545	hidnplayr	298	mov eax, RegAddr shl 16
		299	out dx, eax
		300
		301	call PHY_WAIT_READ
		302	jz .error
		303
		304	in eax, dx
		305	and eax, 0xFFFF
		306	jmp .done
		307
		308	.error:
		309	or eax, -1
		310	.done:
		311	}
		312
		313	align 4
		314	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR
		315
		316	udelay 1 ;;;1000
		317
		318	push ecx
		319	mov ecx, 2000
		320	; Check if the RTL8169 has completed writing/reading to the specified MII register
		321	@@:
		322	in eax, dx
		323	test eax, 0x80000000
		324	jnz .exit
		325	udelay 1 ;;;100
		326	loop @b
		327	.exit:
		328	pop ecx
		329	ret
		330
		331	align 4
		332	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR
		333
		334	udelay 1 ;;;1000
		335
		336	push ecx
		337	mov ecx, 2000
		338	; Check if the RTL8169 has completed writing/reading to the specified MII register
		339	@@:
		340	in eax, dx
		341	test eax, 0x80000000
		342	jz .exit
		343	udelay 1 ;;;100
		344	loop @b
		345	.exit:
		346	pop ecx
		347	ret
		348
		349
		350
		351	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		352	;; ;;
		353	;; proc START ;;
		354	;; ;;
		355	;; (standard driver proc) ;;
		356	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		357
5050	hidnplayr	358	proc START c, reason:dword, cmdline:dword
3545	hidnplayr	359
5050	hidnplayr	360	cmp [reason], DRV_ENTRY
		361	jne .fail
3545	hidnplayr	362
5050	hidnplayr	363	DEBUGF 2,"Loading driver\n"
		364	invoke RegService, my_service, service_proc
3545	hidnplayr	365	ret
		366
		367	.fail:
5050	hidnplayr	368	xor eax, eax
3545	hidnplayr	369	ret
		370
		371	endp
		372
		373
		374	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		375	;; ;;
		376	;; proc SERVICE_PROC ;;
		377	;; ;;
		378	;; (standard driver proc) ;;
		379	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		380
		381	proc service_proc stdcall, ioctl:dword
		382
		383	mov edx, [ioctl]
4470	hidnplayr	384	mov eax, [edx + IOCTL.io_code]
3545	hidnplayr	385
		386	;------------------------------------------------------
		387
		388	cmp eax, 0 ;SRV_GETVERSION
		389	jne @F
		390
4470	hidnplayr	391	cmp [edx + IOCTL.out_size], 4
3545	hidnplayr	392	jb .fail
4470	hidnplayr	393	mov eax, [edx + IOCTL.output]
3545	hidnplayr	394	mov [eax], dword API_VERSION
		395
		396	xor eax, eax
		397	ret
		398
		399	;------------------------------------------------------
		400	@@:
		401	cmp eax, 1 ;SRV_HOOK
		402	jne .fail
		403
4470	hidnplayr	404	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
3545	hidnplayr	405	jb .fail
		406
4470	hidnplayr	407	mov eax, [edx + IOCTL.input]
3545	hidnplayr	408	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
		409	jne .fail ; other types arent supported for this card yet
		410
		411	; check if the device is already listed
		412
		413	mov esi, device_list
		414	mov ecx, [devices]
		415	test ecx, ecx
		416	jz .firstdevice
		417
4470	hidnplayr	418	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
		419	mov ax, [eax+1] ;
3545	hidnplayr	420	.nextdevice:
		421	mov ebx, [esi]
5050	hidnplayr	422	cmp al, byte[ebx + device.pci_bus]
3545	hidnplayr	423	jne @f
5050	hidnplayr	424	cmp ah, byte[ebx + device.pci_dev]
3545	hidnplayr	425	je .find_devicenum ; Device is already loaded, let's find it's device number
		426	@@:
		427	add esi, 4
		428	loop .nextdevice
		429
		430
		431	; This device doesnt have its own eth_device structure yet, lets create one
		432	.firstdevice:
		433	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
		434	jae .fail
		435
5050	hidnplayr	436	allocate_and_clear ebx, sizeof.device, .fail ; Allocate memory to put the device structure in
3545	hidnplayr	437
		438	; Fill in the direct call addresses into the struct
		439
5050	hidnplayr	440	mov [ebx + device.reset], reset
		441	mov [ebx + device.transmit], transmit
		442	mov [ebx + device.unload], unload
		443	mov [ebx + device.name], my_service
3545	hidnplayr	444
		445	; save the pci bus and device numbers
		446
4470	hidnplayr	447	mov eax, [edx + IOCTL.input]
3545	hidnplayr	448	movzx ecx, byte[eax+1]
5050	hidnplayr	449	mov [ebx + device.pci_bus], ecx
3545	hidnplayr	450	movzx ecx, byte[eax+2]
5050	hidnplayr	451	mov [ebx + device.pci_dev], ecx
3545	hidnplayr	452
		453	; Now, it's time to find the base io addres of the PCI device
		454
5050	hidnplayr	455	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
		456	mov [ebx + device.io_addr], eax
3545	hidnplayr	457
		458	; We've found the io address, find IRQ now
		459
5050	hidnplayr	460	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
		461	mov [ebx + device.irq_line], al
3545	hidnplayr	462
		463	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
5050	hidnplayr	464	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8
3545	hidnplayr	465
		466	; Ok, the eth_device structure is ready, let's probe the device
		467	; Because initialization fires IRQ, IRQ handler must be aware of this device
		468	mov eax, [devices] ; Add the device structure to our device list
		469	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)
		470	inc [devices] ;
		471
		472	call probe ; this function will output in eax
		473	test eax, eax
		474	jnz .err2 ; If an error occured, exit
		475
5050	hidnplayr	476	mov [ebx + device.type], NET_TYPE_ETH
		477	invoke NetRegDev
3545	hidnplayr	478
		479	cmp eax, -1
		480	je .destroy
		481
		482	ret
		483
		484	; If the device was already loaded, find the device number and return it in eax
		485
		486	.find_devicenum:
		487	DEBUGF 2,"Trying to find device number of already registered device\n"
5050	hidnplayr	488	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
3545	hidnplayr	489	; into a device number in edi
		490	mov eax, edi ; Application wants it in eax instead
		491	DEBUGF 2,"Kernel says: %u\n", eax
		492	ret
		493
		494	; If an error occured, remove all allocated data and exit (returning -1 in eax)
		495
		496	.destroy:
		497	; todo: reset device into virgin state
		498
		499	.err2:
		500	dec [devices]
		501	.err:
		502	DEBUGF 2,"removing device structure\n"
5050	hidnplayr	503	invoke KernelFree, ebx
3545	hidnplayr	504	.fail:
		505	or eax, -1
		506	ret
		507
		508	;------------------------------------------------------
		509	endp
		510
		511
		512	align 4
		513	unload:
		514
		515	ret
		516
		517
		518	align 4
		519	init_board:
		520
		521	DEBUGF 1,"init_board\n"
		522
5050	hidnplayr	523	; Make the device a bus master
		524	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
		525	or al, PCI_CMD_MASTER
		526	invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
3545	hidnplayr	527
		528	; Soft reset the chip
5050	hidnplayr	529	set_io [ebx + device.io_addr], 0
		530	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	531	mov al, CMD_Reset
		532	out dx, al
		533
		534	; Check that the chip has finished the reset
		535	mov ecx, 1000
5050	hidnplayr	536	set_io [ebx + device.io_addr], REG_ChipCmd
5494	hidnplayr	537	@@:
		538	in al, dx
3545	hidnplayr	539	test al, CMD_Reset
		540	jz @f
		541	udelay 10
		542	loop @b
5494	hidnplayr	543	@@:
3545	hidnplayr	544
		545
5050	hidnplayr	546	set_io [ebx + device.io_addr], REG_TxConfig
3545	hidnplayr	547	in eax, dx
5494	hidnplayr	548	mov esi, MAC_VERSION_LIST
		549	@@:
		550	mov ecx, eax
		551	and ecx, dword[esi]
		552	cmp ecx, dword[esi+4]
		553	je @f
		554	add esi, 4*4
		555	jmp @r
		556	@@:
3545	hidnplayr	557
5494	hidnplayr	558	mov eax, [esi+8]
		559	mov [ebx + device.mac_version], eax
		560	mov eax, [esi+12]
		561	mov [ebx + device.name], eax
3545	hidnplayr	562
		563	xor eax, eax
		564	ret
		565
		566
		567
		568	;***************************************************************************
		569	; Function
		570	; probe
		571	; Description
		572	; Searches for an ethernet card, enables it and clears the rx buffer
		573	; If a card was found, it enables the ethernet -> TCPIP link
		574	; Destroyed registers
		575	; eax, ebx, ecx, edx
		576	;
		577	;***************************************************************************
		578	align 4
		579	probe:
		580
		581	DEBUGF 1,"probe\n"
		582
		583	call init_board
		584	call read_mac
		585	call PHY_config
		586
4334	hidnplayr	587	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
5050	hidnplayr	588	set_io [ebx + device.io_addr], 0
		589	set_io [ebx + device.io_addr], 0x82
3545	hidnplayr	590	mov al, 0x01
		591	out dx, al
5050	hidnplayr	592	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	593	jae @f
4334	hidnplayr	594	DEBUGF 1,"Set PCI Latency=0x40\n"
5050	hidnplayr	595	; Adjust PCI latency to be at least 64
		596	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency
		597	cmp al, 64
		598	jae @f
		599	mov al, 64
		600	invoke PciWrite8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency, eax
		601	@@:
		602	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	603	jne @f
4334	hidnplayr	604	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
5050	hidnplayr	605	set_io [ebx + device.io_addr], 0
		606	set_io [ebx + device.io_addr], 0x82
3545	hidnplayr	607	mov al, 0x01
		608	out dx, al
4334	hidnplayr	609	DEBUGF 1,"Set PHY Reg 0x0bh = 0x00h\n"
3545	hidnplayr	610	WRITE_GMII_REG 0x0b, 0x0000 ; w 0x0b 15 0 0
		611	@@:
		612	; if TBI is not enabled
5050	hidnplayr	613	set_io [ebx + device.io_addr], 0
		614	set_io [ebx + device.io_addr], REG_PHYstatus
3545	hidnplayr	615	in al, dx
		616	test al, PHYS_TBI_Enable
		617	jz .tbi_dis
		618	READ_GMII_REG PHY_AUTO_NEGO_REG
		619
		620	; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
		621	and eax, 0x0C1F
		622	or eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
		623	WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
		624
		625	; enable 1000 Full Mode
		626	WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
		627
		628	; Enable auto-negotiation and restart auto-nigotiation
		629	WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
		630
4803	hidnplayr	631	udelay 1 ; 100
		632	mov ecx, 200 ; 10000
		633	DEBUGF 1, "Waiting for auto-negotiation to complete\n"
3545	hidnplayr	634	; wait for auto-negotiation process
		635	@@: dec ecx
		636	jz @f
5050	hidnplayr	637	set_io [ebx + device.io_addr], 0
3545	hidnplayr	638	READ_GMII_REG PHY_STAT_REG
4803	hidnplayr	639	udelay 1 ; 100
3545	hidnplayr	640	test eax, PHY_Auto_Neco_Comp
		641	jz @b
5050	hidnplayr	642	set_io [ebx + device.io_addr], REG_PHYstatus
3545	hidnplayr	643	in al, dx
		644	jmp @f
		645	.tbi_dis:
4803	hidnplayr	646	udelay 1 ; 100
3545	hidnplayr	647	@@:
4803	hidnplayr	648	DEBUGF 1, "auto-negotiation complete\n"
3545	hidnplayr	649
		650	;***************************************************************************
		651	; Function
		652	; rt8169_reset
		653	; Description
		654	; Place the chip (ie, the ethernet card) into a virgin state
		655	; Destroyed registers
		656	; eax, ebx, ecx, edx
		657	;
		658	;***************************************************************************
		659	align 4
		660	reset:
		661
4803	hidnplayr	662	DEBUGF 1,"resetting\n"
3545	hidnplayr	663
		664	call init_ring
		665	call hw_start
		666
		667	; clear packet/byte counters
		668
		669	xor eax, eax
5050	hidnplayr	670	lea edi, [ebx + device.bytes_tx]
3545	hidnplayr	671	mov ecx, 6
		672	rep stosd
		673
5050	hidnplayr	674	mov [ebx + device.mtu], 1500
5498	hidnplayr	675	call detect_link
3545	hidnplayr	676
4803	hidnplayr	677	DEBUGF 2,"init OK!\n"
3545	hidnplayr	678	xor eax, eax
		679	ret
		680
		681
		682
		683
		684
		685	align 4
		686	PHY_config:
		687
5050	hidnplayr	688	DEBUGF 1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n", [ebx + device.mcfg], [ebx + device.pcfg]
3545	hidnplayr	689
5050	hidnplayr	690	cmp [ebx + device.mcfg], MCFG_METHOD_04
3545	hidnplayr	691	jne .not_4
5050	hidnplayr	692	set_io [ebx + device.io_addr], 0
3545	hidnplayr	693	; WRITE_GMII_REG 0x1F, 0x0001
		694	; WRITE_GMII_REG 0x1b, 0x841e
		695	; WRITE_GMII_REG 0x0e, 0x7bfb
		696	; WRITE_GMII_REG 0x09, 0x273a
		697	WRITE_GMII_REG 0x1F, 0x0002
		698	WRITE_GMII_REG 0x01, 0x90D0
		699	WRITE_GMII_REG 0x1F, 0x0000
		700	jmp .exit
		701	.not_4:
5050	hidnplayr	702	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	703	je @f
5050	hidnplayr	704	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	705	jne .not_2_or_3
		706	@@:
5050	hidnplayr	707	set_io [ebx + device.io_addr], 0
3545	hidnplayr	708	WRITE_GMII_REG 0x1F, 0x0001
		709	WRITE_GMII_REG 0x15, 0x1000
		710	WRITE_GMII_REG 0x18, 0x65C7
		711	WRITE_GMII_REG 0x04, 0x0000
		712	WRITE_GMII_REG 0x03, 0x00A1
		713	WRITE_GMII_REG 0x02, 0x0008
		714	WRITE_GMII_REG 0x01, 0x1020
		715	WRITE_GMII_REG 0x00, 0x1000
		716	WRITE_GMII_REG 0x04, 0x0800
		717	WRITE_GMII_REG 0x04, 0x0000
		718	WRITE_GMII_REG 0x04, 0x7000
		719	WRITE_GMII_REG 0x03, 0xFF41
		720	WRITE_GMII_REG 0x02, 0xDE60
		721	WRITE_GMII_REG 0x01, 0x0140
		722	WRITE_GMII_REG 0x00, 0x0077
		723	WRITE_GMII_REG 0x04, 0x7800
		724	WRITE_GMII_REG 0x04, 0x7000
		725	WRITE_GMII_REG 0x04, 0xA000
		726	WRITE_GMII_REG 0x03, 0xDF01
		727	WRITE_GMII_REG 0x02, 0xDF20
		728	WRITE_GMII_REG 0x01, 0xFF95
		729	WRITE_GMII_REG 0x00, 0xFA00
		730	WRITE_GMII_REG 0x04, 0xA800
		731	WRITE_GMII_REG 0x04, 0xA000
		732	WRITE_GMII_REG 0x04, 0xB000
		733	WRITE_GMII_REG 0x03, 0xFF41
		734	WRITE_GMII_REG 0x02, 0xDE20
		735	WRITE_GMII_REG 0x01, 0x0140
		736	WRITE_GMII_REG 0x00, 0x00BB
		737	WRITE_GMII_REG 0x04, 0xB800
		738	WRITE_GMII_REG 0x04, 0xB000
		739	WRITE_GMII_REG 0x04, 0xF000
		740	WRITE_GMII_REG 0x03, 0xDF01
		741	WRITE_GMII_REG 0x02, 0xDF20
		742	WRITE_GMII_REG 0x01, 0xFF95
		743	WRITE_GMII_REG 0x00, 0xBF00
		744	WRITE_GMII_REG 0x04, 0xF800
		745	WRITE_GMII_REG 0x04, 0xF000
		746	WRITE_GMII_REG 0x04, 0x0000
		747	WRITE_GMII_REG 0x1F, 0x0000
		748	WRITE_GMII_REG 0x0B, 0x0000
		749	jmp .exit
		750	.not_2_or_3:
5050	hidnplayr	751	DEBUGF 1,"mcfg=%d, discard hw PHY config\n", [ebx + device.mcfg]
3545	hidnplayr	752	.exit:
		753	ret
		754
		755
		756
		757	align 4
		758	set_rx_mode:
		759
		760	DEBUGF 1,"set_rx_mode\n"
		761
		762	; IFF_ALLMULTI
		763	; Too many to filter perfectly -- accept all multicasts
5050	hidnplayr	764	set_io [ebx + device.io_addr], 0
		765	set_io [ebx + device.io_addr], REG_RxConfig
3545	hidnplayr	766	in eax, dx
5494	hidnplayr	767	and eax, 0xff7e1880
3545	hidnplayr	768	or eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
		769	out dx, eax
		770
		771	; Multicast hash filter
5050	hidnplayr	772	set_io [ebx + device.io_addr], REG_MAR0 + 0
3545	hidnplayr	773	or eax, -1
		774	out dx, eax
5050	hidnplayr	775	set_io [ebx + device.io_addr], REG_MAR0 + 4
3545	hidnplayr	776	out dx, eax
		777
		778	ret
		779
		780
		781	align 4
		782	init_ring:
		783
		784	DEBUGF 1,"init_ring\n"
		785
		786	xor eax, eax
5050	hidnplayr	787	mov [ebx + device.cur_rx], eax
		788	mov [ebx + device.cur_tx], eax
5498	hidnplayr	789	mov [ebx + device.last_tx], eax
3545	hidnplayr	790
5050	hidnplayr	791	lea edi, [ebx + device.tx_ring]
5498	hidnplayr	792	mov ecx, (NUM_TX_DESC * sizeof.tx_desc) / 4 * 2
3545	hidnplayr	793	rep stosd
		794
5050	hidnplayr	795	lea edi, [ebx + device.rx_ring]
		796	mov ecx, (NUM_RX_DESC * sizeof.rx_desc) / 4
3545	hidnplayr	797	rep stosd
		798
5498	hidnplayr	799	lea edi, [ebx + device.rx_ring]
3545	hidnplayr	800	mov ecx, NUM_RX_DESC
		801	.loop:
		802	push ecx
5050	hidnplayr	803	invoke KernelAlloc, RX_BUF_SIZE
		804	mov dword [edi + rx_desc.buf_soft_addr], eax
5498	hidnplayr	805	invoke GetPhysAddr
3545	hidnplayr	806	mov dword [edi + rx_desc.buf_addr], eax
		807	mov [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
5050	hidnplayr	808	add edi, sizeof.rx_desc
3545	hidnplayr	809	pop ecx
5050	hidnplayr	810	dec ecx
		811	jnz .loop
		812	or [edi - sizeof.rx_desc + rx_desc.status], DSB_EORbit
3545	hidnplayr	813
		814	ret
		815
		816
		817	align 4
		818	hw_start:
		819
		820	DEBUGF 1,"hw_start\n"
		821
		822	; attach int handler
5050	hidnplayr	823	movzx eax, [ebx + device.irq_line]
3545	hidnplayr	824	DEBUGF 1,"Attaching int handler to irq %x\n", eax:1
5050	hidnplayr	825	invoke AttachIntHandler, eax, int_handler, ebx
		826	test eax, eax
		827	jnz @f
		828	DEBUGF 2,"Could not attach int handler!\n"
		829	or eax, -1
		830	ret
		831	@@:
3545	hidnplayr	832
		833	; Soft reset the chip
5050	hidnplayr	834	set_io [ebx + device.io_addr], 0
		835	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	836	mov al, CMD_Reset
		837	out dx, al
		838
		839	DEBUGF 1,"Waiting for chip to reset... "
		840	; Check that the chip has finished the reset
		841	mov ecx, 1000
5050	hidnplayr	842	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	843	@@: in al, dx
		844	test al, CMD_Reset
		845	jz @f
		846	udelay 10
		847	loop @b
		848	@@:
		849	DEBUGF 1,"done!\n"
		850
5050	hidnplayr	851	set_io [ebx + device.io_addr], REG_Cfg9346
3545	hidnplayr	852	mov al, CFG_9346_Unlock
		853	out dx, al
		854
5050	hidnplayr	855	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	856	mov al, CMD_TxEnb or CMD_RxEnb
		857	out dx, al
		858
5050	hidnplayr	859	set_io [ebx + device.io_addr], REG_ETThReg
3545	hidnplayr	860	mov al, ETTh
		861	out dx, al
		862
		863	; For gigabit rtl8169
5050	hidnplayr	864	set_io [ebx + device.io_addr], REG_RxMaxSize
3545	hidnplayr	865	mov ax, RxPacketMaxSize
		866	out dx, ax
		867
		868	; Set Rx Config register
5050	hidnplayr	869	set_io [ebx + device.io_addr], REG_RxConfig
3545	hidnplayr	870	in ax, dx
5494	hidnplayr	871	and eax, 0xff7e1880
3545	hidnplayr	872	or eax, rx_config
		873	out dx, eax
		874
		875	; Set DMA burst size and Interframe Gap Time
5050	hidnplayr	876	set_io [ebx + device.io_addr], REG_TxConfig
3545	hidnplayr	877	mov eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
		878	out dx, eax
		879
5050	hidnplayr	880	set_io [ebx + device.io_addr], REG_CPlusCmd
3545	hidnplayr	881	in ax, dx
		882	out dx, ax
		883
		884	in ax, dx
		885	or ax, 1 shl 3
5050	hidnplayr	886	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	887	jne @f
5050	hidnplayr	888	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	889	jne @f
		890	or ax,1 shl 14
		891	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
		892	jmp .set
		893	@@:
		894	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n"
		895	.set:
5050	hidnplayr	896	set_io [ebx + device.io_addr], REG_CPlusCmd
3545	hidnplayr	897	out dx, ax
		898
5050	hidnplayr	899	set_io [ebx + device.io_addr], 0xE2
3545	hidnplayr	900	; mov ax, 0x1517
		901	; out dx, ax
		902	; mov ax, 0x152a
		903	; out dx, ax
		904	; mov ax, 0x282a
		905	; out dx, ax
		906	xor ax, ax
		907	out dx, ax
		908
		909	xor eax, eax
5050	hidnplayr	910	mov [ebx + device.cur_rx], eax
		911	lea eax, [ebx + device.tx_ring]
		912	invoke GetPhysAddr
		913	set_io [ebx + device.io_addr], REG_TxDescStartAddr
3545	hidnplayr	914	out dx, eax
5050	hidnplayr	915	set_io [ebx + device.io_addr], REG_TxDescStartAddr + 4
4301	clevermous	916	xor eax, eax
		917	out dx, eax
3545	hidnplayr	918
5050	hidnplayr	919	lea eax, [ebx + device.rx_ring]
		920	invoke GetPhysAddr
		921	set_io [ebx + device.io_addr], REG_RxDescStartAddr
3545	hidnplayr	922	out dx, eax
4301	clevermous	923	xor eax, eax
5050	hidnplayr	924	set_io [ebx + device.io_addr], REG_RxDescStartAddr + 4
4301	clevermous	925	out dx, eax
3545	hidnplayr	926
5050	hidnplayr	927	set_io [ebx + device.io_addr], REG_Cfg9346
3545	hidnplayr	928	mov al, CFG_9346_Lock
		929	out dx, al
		930
		931	udelay 10
		932
		933	xor eax, eax
5050	hidnplayr	934	set_io [ebx + device.io_addr], REG_RxMissed
3545	hidnplayr	935	out dx, eax
		936
		937	call set_rx_mode
		938
5050	hidnplayr	939	set_io [ebx + device.io_addr], 0
3545	hidnplayr	940	; no early-rx interrupts
5050	hidnplayr	941	set_io [ebx + device.io_addr], REG_MultiIntr
3545	hidnplayr	942	in ax, dx
		943	and ax, 0xF000
		944	out dx, ax
		945
		946	; set interrupt mask
5050	hidnplayr	947	set_io [ebx + device.io_addr], REG_IntrMask
3545	hidnplayr	948	mov ax, intr_mask
		949	out dx, ax
		950
		951	xor eax, eax
		952	ret
		953
		954
		955	align 4
		956	read_mac:
		957
5050	hidnplayr	958	set_io [ebx + device.io_addr], 0
		959	set_io [ebx + device.io_addr], REG_MAC0
3545	hidnplayr	960	xor ecx, ecx
5050	hidnplayr	961	lea edi, [ebx + device.mac]
3545	hidnplayr	962	mov ecx, 6
		963
		964	; Get MAC address. FIXME: read EEPROM
5498	hidnplayr	965	@@:
		966	in al, dx
3545	hidnplayr	967	stosb
		968	inc edx
		969	loop @r
		970
		971	DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\
5050	hidnplayr	972	[ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,[ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
3545	hidnplayr	973
		974	ret
		975
		976	align 4
		977	write_mac:
		978
		979	ret 6
		980
		981
		982	;***************************************************************************
		983	; Function
		984	; transmit
		985	; Description
		986	; Transmits a packet of data via the ethernet card
		987	;
		988	; Destroyed registers
		989	; eax, edx, esi, edi
		990	;
		991	;***************************************************************************
		992
5050	hidnplayr	993	proc transmit stdcall bufferptr, buffersize
		994
		995	pushf
		996	cli
		997
		998	DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [buffersize]
		999	mov eax, [bufferptr]
3545	hidnplayr	1000	DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
		1001	[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
		1002	[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
		1003	[eax+13]:2,[eax+12]:2
		1004
5050	hidnplayr	1005	cmp [buffersize], 1514
3545	hidnplayr	1006	ja .fail
5050	hidnplayr	1007	cmp [buffersize], 60
		1008	jb .fail
3545	hidnplayr	1009
		1010	;----------------------------------
		1011	; Find currentTX descriptor address
		1012
5050	hidnplayr	1013	mov eax, sizeof.tx_desc
		1014	mul [ebx + device.cur_tx]
		1015	lea esi, [ebx + device.tx_ring + eax]
3545	hidnplayr	1016
		1017	DEBUGF 1,"Using TX desc: %x\n", esi
		1018
5498	hidnplayr	1019	;----------------------------------
		1020	; Check if the descriptor is in use
		1021
		1022	test [esi + tx_desc.status], DSB_OWNbit
		1023	jnz .desc
		1024
3545	hidnplayr	1025	;---------------------------
		1026	; Program the packet pointer
		1027
5050	hidnplayr	1028	mov eax, [bufferptr]
3545	hidnplayr	1029	mov [esi + tx_desc.buf_soft_addr], eax
5050	hidnplayr	1030	invoke GetPhysAddr
3545	hidnplayr	1031	mov dword [esi + tx_desc.buf_addr], eax
		1032
		1033	;------------------------
		1034	; Program the packet size
		1035
5050	hidnplayr	1036	mov eax, [buffersize]
5498	hidnplayr	1037	@@:
		1038	or eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
5050	hidnplayr	1039	cmp [ebx + device.cur_tx], NUM_TX_DESC - 1
3545	hidnplayr	1040	jne @f
		1041	or eax, DSB_EORbit
5498	hidnplayr	1042	@@:
		1043	mov [esi + tx_desc.status], eax
3545	hidnplayr	1044
		1045	;-----------------------------------------
		1046	; Set the polling bit (start transmission)
		1047
5050	hidnplayr	1048	set_io [ebx + device.io_addr], 0
		1049	set_io [ebx + device.io_addr], REG_TxPoll
3545	hidnplayr	1050	mov al, 0x40 ; set polling bit
		1051	out dx, al
		1052
		1053	;-----------------------
		1054	; Update TX descriptor
		1055
5050	hidnplayr	1056	inc [ebx + device.cur_tx]
		1057	and [ebx + device.cur_tx], NUM_TX_DESC - 1
3545	hidnplayr	1058
		1059	;-------------
		1060	; Update stats
		1061
5050	hidnplayr	1062	inc [ebx + device.packets_tx]
		1063	mov eax, [buffersize]
		1064	add dword [ebx + device.bytes_tx], eax
		1065	adc dword [ebx + device.bytes_tx + 4], 0
3545	hidnplayr	1066
5126	hidnplayr	1067	popf
3545	hidnplayr	1068	xor eax, eax
5050	hidnplayr	1069	ret
3545	hidnplayr	1070
5498	hidnplayr	1071	.desc:
		1072	DEBUGF 2,"Descriptor is still in use!\n"
3545	hidnplayr	1073	.fail:
5050	hidnplayr	1074	DEBUGF 2,"Transmit failed\n"
		1075	invoke KernelFree, [bufferptr]
		1076	popf
3545	hidnplayr	1077	or eax, -1
5050	hidnplayr	1078	ret
3545	hidnplayr	1079
5050	hidnplayr	1080	endp
3545	hidnplayr	1081
5050	hidnplayr	1082
3545	hidnplayr	1083
		1084	;;;;;;;;;;;;;;;;;;;;;;;
		1085	;; ;;
		1086	;; Interrupt handler ;;
		1087	;; ;;
		1088	;;;;;;;;;;;;;;;;;;;;;;;
		1089
		1090	align 4
		1091	int_handler:
		1092
		1093	push ebx esi edi
		1094
4334	hidnplayr	1095	DEBUGF 1,"INT\n"
3545	hidnplayr	1096
		1097	; find pointer of device wich made IRQ occur
		1098
		1099	mov ecx, [devices]
		1100	test ecx, ecx
		1101	jz .nothing
		1102	mov esi, device_list
		1103	.nextdevice:
		1104	mov ebx, [esi]
		1105
5050	hidnplayr	1106	set_io [ebx + device.io_addr], 0
		1107	set_io [ebx + device.io_addr], REG_IntrStatus
3545	hidnplayr	1108	in ax, dx
5498	hidnplayr	1109	out dx, ax ; ACK all interrupts
		1110	cmp ax, 0xffff ; if so, hardware is no longer present
		1111	je .nothing
3545	hidnplayr	1112	test ax, ax
		1113	jnz .got_it
		1114	.continue:
		1115	add esi, 4
		1116	dec ecx
		1117	jnz .nextdevice
		1118	.nothing:
		1119	pop edi esi ebx
		1120	xor eax, eax
		1121
		1122	ret ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
		1123
		1124	.got_it:
5050	hidnplayr	1125	DEBUGF 1,"Device: %x Status: %x\n", ebx, ax
3545	hidnplayr	1126
		1127	;--------
		1128	; Receive
		1129	test ax, ISB_RxOK
		1130	jz .no_rx
		1131
		1132	push ax
		1133	push ebx
		1134
		1135	.check_more:
		1136	pop ebx
5050	hidnplayr	1137	mov eax, sizeof.rx_desc
		1138	mul [ebx + device.cur_rx]
		1139	lea esi, [ebx + device.rx_ring + eax]
3545	hidnplayr	1140
		1141	DEBUGF 1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
		1142	mov eax, [esi + rx_desc.status]
		1143	test eax, DSB_OWNbit ;;;
5498	hidnplayr	1144	jnz .no_own
3545	hidnplayr	1145
5050	hidnplayr	1146	DEBUGF 1,"cur_rx = %u\n", [ebx + device.cur_rx]
3545	hidnplayr	1147
		1148	test eax, SD_RxRES
		1149	jnz .rx_return ;;;;; RX error!
		1150
		1151	push ebx
		1152	push .check_more
		1153	and eax, 0x00001FFF
		1154	add eax, -4 ; we dont need CRC
		1155	push eax
		1156	DEBUGF 1,"data length = %u\n", ax
		1157
5498	hidnplayr	1158	; Update stats
3545	hidnplayr	1159
5050	hidnplayr	1160	add dword [ebx + device.bytes_rx], eax
		1161	adc dword [ebx + device.bytes_rx + 4], 0
		1162	inc [ebx + device.packets_rx]
3545	hidnplayr	1163
5050	hidnplayr	1164	pushd [esi + rx_desc.buf_soft_addr]
3545	hidnplayr	1165
5498	hidnplayr	1166	; Allocate a new buffer
3545	hidnplayr	1167
5050	hidnplayr	1168	invoke KernelAlloc, RX_BUF_SIZE
3545	hidnplayr	1169	mov [esi + rx_desc.buf_soft_addr], eax
5050	hidnplayr	1170	invoke GetPhysAddr
3545	hidnplayr	1171	mov dword [esi + rx_desc.buf_addr], eax
		1172
5498	hidnplayr	1173	; reset OWN bit
3545	hidnplayr	1174
		1175	mov eax, DSB_OWNbit or RX_BUF_SIZE
5050	hidnplayr	1176	cmp [ebx + device.cur_rx], NUM_RX_DESC - 1
3545	hidnplayr	1177	jne @f
		1178	or eax, DSB_EORbit
5050	hidnplayr	1179	@@:
		1180	mov [esi + rx_desc.status], eax
3545	hidnplayr	1181
5498	hidnplayr	1182	; Update rx ptr
3545	hidnplayr	1183
5050	hidnplayr	1184	inc [ebx + device.cur_rx]
		1185	and [ebx + device.cur_rx], NUM_RX_DESC - 1
3545	hidnplayr	1186
5050	hidnplayr	1187	jmp [Eth_input]
3545	hidnplayr	1188	.rx_return:
5498	hidnplayr	1189	DEBUGF 1,"RX error!\n"
		1190	.no_own:
3545	hidnplayr	1191	pop ax
		1192	.no_rx:
		1193
5498	hidnplayr	1194	;-----------------
		1195	; Transmit cleanup
3545	hidnplayr	1196
5498	hidnplayr	1197	test ax, ISB_TxOK or ISB_TxErr or ISB_TxDescUnavail
3545	hidnplayr	1198	jz .no_tx
		1199
5498	hidnplayr	1200	DEBUGF 1,"TX done!\n"
		1201	.txloop:
		1202	mov esi, [ebx + device.last_tx]
		1203	imul esi, sizeof.tx_desc
		1204	lea esi, [ebx + device.tx_ring + esi]
3545	hidnplayr	1205
5050	hidnplayr	1206	cmp dword [esi + tx_desc.buf_soft_addr], 0
5498	hidnplayr	1207	je .no_tx
3545	hidnplayr	1208
		1209	test [esi + tx_desc.status], DSB_OWNbit
5498	hidnplayr	1210	jnz .no_tx
3545	hidnplayr	1211
5498	hidnplayr	1212	DEBUGF 1,"Freeing up TX desc: 0x%x\n", esi
		1213	DEBUGF 1,"buff: 0x%x\n", [esi + tx_desc.buf_soft_addr]
		1214	push eax
		1215	push dword [esi + tx_desc.buf_soft_addr]
5050	hidnplayr	1216	and dword [esi + tx_desc.buf_soft_addr], 0
5498	hidnplayr	1217	invoke KernelFree
		1218	pop eax
3545	hidnplayr	1219
5498	hidnplayr	1220	inc [ebx + device.last_tx]
		1221	and [ebx + device.last_tx], NUM_TX_DESC-1
		1222	jmp .txloop
3545	hidnplayr	1223	.no_tx:
		1224
5498	hidnplayr	1225	test ax, ISB_LinkChg
		1226	jz .no_linkchange
		1227	DEBUGF 2, "Link change detected\n"
		1228	call detect_link
		1229	.no_linkchange:
3545	hidnplayr	1230
		1231	pop edi esi ebx
		1232	xor eax, eax
		1233	inc eax
		1234
		1235	ret
		1236
		1237
		1238
5498	hidnplayr	1239	align 4
		1240	detect_link:
		1241
		1242	set_io [ebx + device.io_addr], 0
		1243
		1244	; set_io [ebx + device.io_addr], REG_TBICSR
		1245	; in eax, dx
		1246	; test eax, TBI_LinkOK
		1247	; jz .down
		1248
		1249	; mov [ebx + device.state], ETH_LINK_UNKNOWN
		1250	; invoke NetLinkChanged
		1251	; ret
		1252
		1253	set_io [ebx + device.io_addr], REG_PHYstatus
		1254	in al, dx
		1255	test al, PHYS_LinkStatus
		1256	jz .down
		1257	DEBUGF 2, "Link is up, phystatus=0x%x\n", al
		1258	xor ecx, ecx
		1259	test al, PHYS_10bps
		1260	jz @f
		1261	or cl, ETH_LINK_10M
		1262	@@:
		1263	test al, PHYS_100bps
		1264	jz @f
		1265	or cl, ETH_LINK_100M
		1266	@@:
		1267	test al, PHYS_1000bpsF
		1268	jz @f
		1269	or cl, ETH_LINK_1G ;or ETH_LINK_FD
		1270	@@:
		1271	test al, PHYS_FullDup
		1272	jz @f
		1273	or cl, ETH_LINK_FD
		1274	@@:
		1275	mov [ebx + device.state], ecx
		1276	invoke NetLinkChanged
		1277	ret
		1278
		1279	.down:
		1280	DEBUGF 2, "Link is down\n"
		1281	mov [ebx + device.state], ETH_LINK_DOWN
		1282	invoke NetLinkChanged
		1283	ret
		1284
		1285
		1286
5050	hidnplayr	1287	; End of code
3545	hidnplayr	1288
5050	hidnplayr	1289	data fixups
		1290	end data
3545	hidnplayr	1291
5050	hidnplayr	1292	include '../peimport.inc'
3545	hidnplayr	1293
		1294	my_service db 'RTL8169',0 ; max 16 chars include zero
		1295
		1296	include_debug_strings ; All data wich FDO uses will be included here
		1297
5494	hidnplayr	1298	MAC_VERSION_LIST:
3545	hidnplayr	1299
5494	hidnplayr	1300	; 8168EP family.
		1301	dd 0x7cf00000, 0x50200000, 51, name_49
		1302	dd 0x7cf00000, 0x50100000, 50, name_49
		1303	dd 0x7cf00000, 0x50000000, 49, name_49
3545	hidnplayr	1304
5494	hidnplayr	1305	; 8168H family.
		1306	dd 0x7cf00000, 0x54100000, 46, name_45
		1307	dd 0x7cf00000, 0x54000000, 45, name_45
3545	hidnplayr	1308
5494	hidnplayr	1309	; 8168G family.
		1310	dd 0x7cf00000, 0x5c800000, 44, name_44
		1311	dd 0x7cf00000, 0x50900000, 42, name_40
		1312	dd 0x7cf00000, 0x4c100000, 41, name_40
		1313	dd 0x7cf00000, 0x4c000000, 40, name_40
		1314
		1315	; 8168F family.
		1316	dd 0x7c800000, 0x48800000, 38, name_38
		1317	dd 0x7cf00000, 0x48100000, 36, name_35
		1318	dd 0x7cf00000, 0x48000000, 35, name_35
		1319
		1320	; 8168E family.
		1321	dd 0x7c800000, 0x2c800000, 34, name_34
		1322	dd 0x7cf00000, 0x2c200000, 33, name_32
		1323	dd 0x7cf00000, 0x2c100000, 32, name_32
		1324	dd 0x7c800000, 0x2c000000, 33, name_32
		1325
		1326	; 8168D family.
		1327	dd 0x7cf00000, 0x28300000, 26, name_25
		1328	dd 0x7cf00000, 0x28100000, 25, name_25
		1329	dd 0x7c800000, 0x28000000, 26, name_25
		1330
		1331	; 8168DP family.
		1332	dd 0x7cf00000, 0x28800000, 27, name_27
		1333	dd 0x7cf00000, 0x28a00000, 28, name_27
		1334
		1335	; 8168C family.
		1336	dd 0x7cf00000, 0x3cb00000, 24, name_23
		1337	dd 0x7cf00000, 0x3c900000, 23, name_23
		1338	dd 0x7cf00000, 0x3c800000, 18, name_18
		1339	dd 0x7c800000, 0x3c800000, 24, name_23
		1340	dd 0x7cf00000, 0x3c000000, 19, name_19
		1341	dd 0x7cf00000, 0x3c200000, 20, name_19
		1342	dd 0x7cf00000, 0x3c300000, 21, name_19
		1343	dd 0x7cf00000, 0x3c400000, 22, name_19
		1344	dd 0x7c800000, 0x3c000000, 22, name_19
		1345
		1346	; 8168B family.
		1347	dd 0x7cf00000, 0x38000000, 12, name_11
		1348	dd 0x7cf00000, 0x38500000, 17, name_10
		1349	dd 0x7c800000, 0x38000000, 17, name_10
		1350	dd 0x7c800000, 0x30000000, 11, name_11
		1351
		1352	; 8101 family.
		1353	dd 0x7cf00000, 0x34a00000, 09, name_07
		1354	dd 0x7cf00000, 0x24a00000, 09, name_07
		1355	dd 0x7cf00000, 0x34900000, 08, name_07
		1356	dd 0x7cf00000, 0x24900000, 08, name_07
		1357	dd 0x7cf00000, 0x34800000, 07, name_07
		1358	dd 0x7cf00000, 0x24800000, 07, name_07
		1359	dd 0x7cf00000, 0x34000000, 13, name_10
		1360	dd 0x7cf00000, 0x34300000, 10, name_10
		1361	dd 0x7cf00000, 0x34200000, 16, name_11
		1362	dd 0x7c800000, 0x34800000, 09, name_07
		1363	dd 0x7c800000, 0x24800000, 09, name_07
		1364	dd 0x7c800000, 0x34000000, 16, name_11
		1365	dd 0xfc800000, 0x38800000, 15, name_14
		1366	dd 0xfc800000, 0x30800000, 14, name_14
		1367
		1368	; 8110 family.
		1369	dd 0xfc800000, 0x98000000, 06, name_05
		1370	dd 0xfc800000, 0x18000000, 05, name_05
		1371	dd 0xfc800000, 0x10000000, 04, name_04
		1372	dd 0xfc800000, 0x04000000, 03, name_03
		1373	dd 0xfc800000, 0x00800000, 02, name_02
		1374	dd 0xfc800000, 0x00000000, 01, name_01
		1375
		1376	; Catch-all
		1377	dd 0x00000000, 0x00000000, 0, name_unknown
		1378
		1379	; PCI-devices
		1380	name_01 db "RTL8169",0
		1381	name_02 db "RTL8169s",0
		1382	name_03 db "RTL8110s",0
		1383	name_04 db "RTL8169sb/8110sb",0
		1384	name_05 db "RTL8169sc/8110sc",0
		1385	;name_06 db "RTL8169sc/8110sc",0
		1386
		1387	; PCI-E devices
		1388	name_07 db "RTL8102e",0
		1389	;name_08 db "RTL8102e",0
		1390	;name_09 db "RTL8102e",0
		1391	name_10 db "RTL8101e",0
		1392	name_11 db "RTL8168b/8111b",0
		1393	;name_12 db "RTL8168b/8111b",0
		1394	;name_13 db "RTL8101e",0
		1395	name_14 db "RTL8100e",0
		1396	;name_15 db "RTL8100e",0
		1397	;name_16 db "RTL8168b/8111b",0
		1398	;name_17 db "RTL8101e",0
		1399	name_18 db "RTL8168cp/8111cp",0
		1400	name_19 db "RTL8168c/8111c",0
		1401	;name_20 db "RTL8168c/8111c",0
		1402	;name_21 db "RTL8168c/8111c",0
		1403	;name_22 db "RTL8168c/8111c",0
		1404	name_23 db "RTL8168cp/8111cp",0
		1405	;name_24 db "RTL8168cp/8111cp",0
		1406	name_25 db "RTL8168d/8111d",0
		1407	;name_26 db "RTL8168d/8111d",0
		1408	name_27 db "RTL8168dp/8111dp",0
		1409	;name_28 db "RTL8168dp/8111dp",0
		1410	name_29 db "RTL8105e",0
		1411	;name_30 db "RTL8105e",0
		1412	;name_31 db "RTL8168dp/8111dp",0
		1413	name_32 db "RTL8168e/8111e",0
		1414	;name_33 db "RTL8168e/8111e",0
		1415	name_34 db "RTL8168evl/8111evl",0
		1416	name_35 db "RTL8168f/8111f",0
		1417	;name_36 db "RTL8168f/8111f",0
		1418	name_37 db "RTL8402",0
		1419	name_38 db "RTL8411",0
		1420	name_39 db "RTL8106e",0
		1421	name_40 db "RTL8168g/8111g",0
		1422	;name_41 db "RTL8168g/8111g",0
		1423	;name_42 db "RTL8168g/8111g",0
		1424	;name_43 db "RTL8106e",0
		1425	name_44 db "RTL8411",0
		1426	name_45 db "RTL8168h/8111h",0
		1427	;name_46 db "RTL8168h/8111h",0
		1428	name_47 db "RTL8107e",0
		1429	;name_48 db "RTL8107e",0
		1430	name_49 db "RTL8168ep/8111ep",0
		1431	;name_50 db "RTL8168ep/8111ep",0
		1432	;name_51 db "RTL8168ep/8111ep",0
		1433
		1434	name_unknown db "unknown RTL8169 clone",0
		1435
5050	hidnplayr	1436	align 4
		1437	devices dd 0
3545	hidnplayr	1438	device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling
		1439

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(root)/drivers/ethernet/RTL8169.asm @ 6124 – Rev 5498