WebSVN – Kolibri OS – Blame – /drivers/ethernet/RTL8169.asm

Rev	Author	Line No.	Line
3545	hidnplayr	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
4467	hidnplayr	3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
3545	hidnplayr	4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;; RTL8169 driver for KolibriOS ;;
		7	;; ;;
		8	;; Copyright 2007 mike.dld, ;;
		9	;; mike.dld@gmail.com ;;
		10	;; ;;
		11	;; port to net branch by hidnplayr ;;
		12	;; ;;
		13	;; References: ;;
		14	;; r8169.c - linux driver (etherboot project) ;;
		15	;; ;;
		16	;; GNU GENERAL PUBLIC LICENSE ;;
		17	;; Version 2, June 1991 ;;
		18	;; ;;
		19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		20
		21	format MS COFF
		22
		23	API_VERSION = 0x01000100
		24	DRIVER_VERSION = 5
		25
		26	MAX_DEVICES = 16
		27
		28	DEBUG = 1
		29	__DEBUG__ = 1
		30	__DEBUG_LEVEL__ = 2
		31
		32	NUM_TX_DESC = 4
		33	NUM_RX_DESC = 4
		34
4467	hidnplayr	35	include '../struct.inc'
		36	include '../macros.inc'
3545	hidnplayr	37	include '../proc32.inc'
		38	include '../imports.inc'
		39	include '../fdo.inc'
		40	include '../netdrv.inc'
		41
		42	public START
		43	public service_proc
		44	public version
		45
		46
		47	REG_MAC0 = 0x0 ; Ethernet hardware address
		48	REG_MAR0 = 0x8 ; Multicast filter
		49	REG_TxDescStartAddr = 0x20
		50	REG_TxHDescStartAddr = 0x28
		51	REG_FLASH = 0x30
		52	REG_ERSR = 0x36
		53	REG_ChipCmd = 0x37
		54	REG_TxPoll = 0x38
		55	REG_IntrMask = 0x3C
		56	REG_IntrStatus = 0x3E
		57	REG_TxConfig = 0x40
		58	REG_RxConfig = 0x44
		59	REG_RxMissed = 0x4C
		60	REG_Cfg9346 = 0x50
		61	REG_Config0 = 0x51
		62	REG_Config1 = 0x52
		63	REG_Config2 = 0x53
		64	REG_Config3 = 0x54
		65	REG_Config4 = 0x55
		66	REG_Config5 = 0x56
		67	REG_MultiIntr = 0x5C
		68	REG_PHYAR = 0x60
		69	REG_TBICSR = 0x64
		70	REG_TBI_ANAR = 0x68
		71	REG_TBI_LPAR = 0x6A
		72	REG_PHYstatus = 0x6C
		73	REG_RxMaxSize = 0xDA
		74	REG_CPlusCmd = 0xE0
		75	REG_RxDescStartAddr = 0xE4
		76	REG_ETThReg = 0xEC
		77	REG_FuncEvent = 0xF0
		78	REG_FuncEventMask = 0xF4
		79	REG_FuncPresetState = 0xF8
		80	REG_FuncForceEvent = 0xFC
		81
		82	; InterruptStatusBits
		83	ISB_SYSErr = 0x8000
		84	ISB_PCSTimeout = 0x4000
		85	ISB_SWInt = 0x0100
		86	ISB_TxDescUnavail = 0x80
		87	ISB_RxFIFOOver = 0x40
		88	ISB_LinkChg = 0x20
		89	ISB_RxOverflow = 0x10
		90	ISB_TxErr = 0x08
		91	ISB_TxOK = 0x04
		92	ISB_RxErr = 0x02
		93	ISB_RxOK = 0x01
		94
		95	; RxStatusDesc
		96	SD_RxRES = 0x00200000
		97	SD_RxCRC = 0x00080000
		98	SD_RxRUNT = 0x00100000
		99	SD_RxRWT = 0x00400000
		100
		101	; ChipCmdBits
		102	CMD_Reset = 0x10
		103	CMD_RxEnb = 0x08
		104	CMD_TxEnb = 0x04
		105	CMD_RxBufEmpty = 0x01
		106
		107	; Cfg9346Bits
		108	CFG_9346_Lock = 0x00
		109	CFG_9346_Unlock = 0xC0
		110
		111	; rx_mode_bits
		112	RXM_AcceptErr = 0x20
		113	RXM_AcceptRunt = 0x10
		114	RXM_AcceptBroadcast = 0x08
		115	RXM_AcceptMulticast = 0x04
		116	RXM_AcceptMyPhys = 0x02
		117	RXM_AcceptAllPhys = 0x01
		118
		119	; RxConfigBits
		120	RXC_FIFOShift = 13
		121	RXC_DMAShift = 8
		122
		123	; TxConfigBits
		124	TXC_InterFrameGapShift = 24
		125	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
		126
		127	; PHYstatus
		128	PHYS_TBI_Enable = 0x80
		129	PHYS_TxFlowCtrl = 0x40
		130	PHYS_RxFlowCtrl = 0x20
		131	PHYS_1000bpsF = 0x10
		132	PHYS_100bps = 0x08
		133	PHYS_10bps = 0x04
		134	PHYS_LinkStatus = 0x02
		135	PHYS_FullDup = 0x01
		136
		137	; GIGABIT_PHY_registers
		138	PHY_CTRL_REG = 0
		139	PHY_STAT_REG = 1
		140	PHY_AUTO_NEGO_REG = 4
		141	PHY_1000_CTRL_REG = 9
		142
		143	; GIGABIT_PHY_REG_BIT
		144	PHY_Restart_Auto_Nego = 0x0200
		145	PHY_Enable_Auto_Nego = 0x1000
		146
		147	; PHY_STAT_REG = 1
		148	PHY_Auto_Neco_Comp = 0x0020
		149
		150	; PHY_AUTO_NEGO_REG = 4
		151	PHY_Cap_10_Half = 0x0020
		152	PHY_Cap_10_Full = 0x0040
		153	PHY_Cap_100_Half = 0x0080
		154	PHY_Cap_100_Full = 0x0100
		155
		156	; PHY_1000_CTRL_REG = 9
		157	PHY_Cap_1000_Full = 0x0200
		158	PHY_Cap_1000_Half = 0x0100
		159
		160	PHY_Cap_PAUSE = 0x0400
		161	PHY_Cap_ASYM_PAUSE = 0x0800
		162
		163	PHY_Cap_Null = 0x0
		164
		165	; _MediaType
		166	MT_10_Half = 0x01
		167	MT_10_Full = 0x02
		168	MT_100_Half = 0x04
		169	MT_100_Full = 0x08
		170	MT_1000_Full = 0x10
		171
		172	; _TBICSRBit
		173	TBI_LinkOK = 0x02000000
		174
		175	; _DescStatusBit
		176	DSB_OWNbit = 0x80000000
		177	DSB_EORbit = 0x40000000
		178	DSB_FSbit = 0x20000000
		179	DSB_LSbit = 0x10000000
		180
		181	RX_BUF_SIZE = 1536 ; Rx Buffer size
		182
		183	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
		184	MAX_ETH_FRAME_SIZE = 1536
		185
		186	TX_FIFO_THRESH = 256 ; In bytes
		187
		188	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
		189	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		190	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		191	ETTh = 0x3F ; 0x3F means NO threshold
		192
		193	EarlyTxThld = 0x3F ; 0x3F means NO early transmit
		194	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
		195	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
		196
		197	HZ = 1000
		198
		199	RTL_MIN_IO_SIZE = 0x80
		200	TX_TIMEOUT = (6*HZ)
		201
		202	TIMER_EXPIRE_TIME = 100
		203
		204	ETH_HDR_LEN = 14
		205	DEFAULT_MTU = 1500
		206	DEFAULT_RX_BUF_LEN = 1536
		207
		208
		209	;ifdef JUMBO_FRAME_SUPPORT
		210	; MAX_JUMBO_FRAME_MTU = 10000
		211	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
		212	;else
		213	MAX_RX_SKBDATA_SIZE = 1600
		214	;end if
		215
		216	MCFG_METHOD_01 = 0x01
		217	MCFG_METHOD_02 = 0x02
		218	MCFG_METHOD_03 = 0x03
		219	MCFG_METHOD_04 = 0x04
		220	MCFG_METHOD_05 = 0x05
		221	MCFG_METHOD_11 = 0x0b
		222	MCFG_METHOD_12 = 0x0c
		223	MCFG_METHOD_13 = 0x0d
		224	MCFG_METHOD_14 = 0x0e
		225	MCFG_METHOD_15 = 0x0f
		226
		227	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
		228	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
		229	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
		230
		231	virtual at 0
		232	tx_desc:
		233	.status dd ?
		234	.vlan_tag dd ?
		235	.buf_addr dq ?
		236	.size = $
		237	rb (NUM_TX_DESC-1)*tx_desc.size
		238	.buf_soft_addr dd ?
		239	end virtual
		240
		241	virtual at 0
		242	rx_desc:
		243	.status dd ?
		244	.vlan_tag dd ?
		245	.buf_addr dq ?
		246	.size = $
		247	rb (NUM_RX_DESC-1)*rx_desc.size
		248	.buf_soft_addr dd ?
		249	end virtual
		250
		251	virtual at ebx
		252
		253	device:
		254
		255	ETH_DEVICE
		256
		257	.io_addr dd ?
		258	.pci_bus dd ?
		259	.pci_dev dd ?
		260	.irq_line db ?
		261
		262	rb 256-(($ - device) and 255) ; align 256
		263	.tx_ring rb NUM_TX_DESC * tx_desc.size * 2
		264
		265	rb 256-(($ - device) and 255) ; align 256
		266	.rx_ring rb NUM_RX_DESC * rx_desc.size * 2
		267
		268	tpc:
		269	.mmio_addr dd ? ; memory map physical address
		270	.chipset dd ?
		271	.pcfg dd ?
		272	.mcfg dd ?
		273	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
		274	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
		275	.TxDescArrays dd ? ; Index of Tx Descriptor buffer
		276	.RxDescArrays dd ? ; Index of Rx Descriptor buffer
		277	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer
		278	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer
		279
		280	device_size = $ - device
		281
		282	end virtual
		283
		284	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
		285	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
		286
		287
		288	macro udelay msec {
		289
4803	hidnplayr	290	push esi ecx
3545	hidnplayr	291	mov esi, msec
		292	call Sleep
4803	hidnplayr	293	pop ecx esi
3545	hidnplayr	294
		295	}
		296
		297	macro WRITE_GMII_REG RegAddr, value {
		298
		299	set_io REG_PHYAR
		300	if value eq ax
		301	and eax, 0x0000ffff
		302	or eax, 0x80000000 + (RegAddr shl 16)
		303	else
		304	mov eax, 0x80000000 + (RegAddr shl 16) + value
		305	end if
		306	out dx, eax
		307
		308	call PHY_WAIT_WRITE
		309	}
		310
		311	macro READ_GMII_REG RegAddr {
		312
		313	local .error, .done
		314
		315	set_io REG_PHYAR
		316	mov eax, RegAddr shl 16
		317	out dx, eax
		318
		319	call PHY_WAIT_READ
		320	jz .error
		321
		322	in eax, dx
		323	and eax, 0xFFFF
		324	jmp .done
		325
		326	.error:
		327	or eax, -1
		328	.done:
		329	}
		330
		331	align 4
		332	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR
		333
		334	udelay 1 ;;;1000
		335
		336	push ecx
		337	mov ecx, 2000
		338	; Check if the RTL8169 has completed writing/reading to the specified MII register
		339	@@:
		340	in eax, dx
		341	test eax, 0x80000000
		342	jnz .exit
		343	udelay 1 ;;;100
		344	loop @b
		345	.exit:
		346	pop ecx
		347	ret
		348
		349	align 4
		350	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR
		351
		352	udelay 1 ;;;1000
		353
		354	push ecx
		355	mov ecx, 2000
		356	; Check if the RTL8169 has completed writing/reading to the specified MII register
		357	@@:
		358	in eax, dx
		359	test eax, 0x80000000
		360	jz .exit
		361	udelay 1 ;;;100
		362	loop @b
		363	.exit:
		364	pop ecx
		365	ret
		366
		367
		368
		369	section '.flat' code readable align 16
		370
		371	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		372	;; ;;
		373	;; proc START ;;
		374	;; ;;
		375	;; (standard driver proc) ;;
		376	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		377
		378	align 4
		379	proc START stdcall, state:dword
		380
		381	cmp [state], 1
		382	jne .exit
		383
		384	.entry:
		385
		386	DEBUGF 2,"Loading %s driver\n", my_service
		387	stdcall RegService, my_service, service_proc
		388	ret
		389
		390	.fail:
		391	.exit:
		392	xor eax, eax
		393	ret
		394
		395	endp
		396
		397
		398	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		399	;; ;;
		400	;; proc SERVICE_PROC ;;
		401	;; ;;
		402	;; (standard driver proc) ;;
		403	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		404
		405	align 4
		406	proc service_proc stdcall, ioctl:dword
		407
		408	mov edx, [ioctl]
4470	hidnplayr	409	mov eax, [edx + IOCTL.io_code]
3545	hidnplayr	410
		411	;------------------------------------------------------
		412
		413	cmp eax, 0 ;SRV_GETVERSION
		414	jne @F
		415
4470	hidnplayr	416	cmp [edx + IOCTL.out_size], 4
3545	hidnplayr	417	jb .fail
4470	hidnplayr	418	mov eax, [edx + IOCTL.output]
3545	hidnplayr	419	mov [eax], dword API_VERSION
		420
		421	xor eax, eax
		422	ret
		423
		424	;------------------------------------------------------
		425	@@:
		426	cmp eax, 1 ;SRV_HOOK
		427	jne .fail
		428
4470	hidnplayr	429	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
3545	hidnplayr	430	jb .fail
		431
4470	hidnplayr	432	mov eax, [edx + IOCTL.input]
3545	hidnplayr	433	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
		434	jne .fail ; other types arent supported for this card yet
		435
		436	; check if the device is already listed
		437
		438	mov esi, device_list
		439	mov ecx, [devices]
		440	test ecx, ecx
		441	jz .firstdevice
		442
4470	hidnplayr	443	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
		444	mov ax, [eax+1] ;
3545	hidnplayr	445	.nextdevice:
		446	mov ebx, [esi]
		447	cmp al, byte[device.pci_bus]
		448	jne @f
		449	cmp ah, byte[device.pci_dev]
		450	je .find_devicenum ; Device is already loaded, let's find it's device number
		451	@@:
		452	add esi, 4
		453	loop .nextdevice
		454
		455
		456	; This device doesnt have its own eth_device structure yet, lets create one
		457	.firstdevice:
		458	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
		459	jae .fail
		460
		461	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in
		462
		463	; Fill in the direct call addresses into the struct
		464
		465	mov [device.reset], reset
		466	mov [device.transmit], transmit
		467	mov [device.unload], unload
		468	mov [device.name], my_service
		469
		470	; save the pci bus and device numbers
		471
4470	hidnplayr	472	mov eax, [edx + IOCTL.input]
3545	hidnplayr	473	movzx ecx, byte[eax+1]
		474	mov [device.pci_bus], ecx
		475	movzx ecx, byte[eax+2]
		476	mov [device.pci_dev], ecx
		477
		478	; Now, it's time to find the base io addres of the PCI device
		479
		480	PCI_find_io
		481	mov [tpc.mmio_addr], eax ; CHECKME
		482
		483	; We've found the io address, find IRQ now
		484
		485	PCI_find_irq
		486
		487	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
		488	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
		489
		490	; Ok, the eth_device structure is ready, let's probe the device
		491	; Because initialization fires IRQ, IRQ handler must be aware of this device
		492	mov eax, [devices] ; Add the device structure to our device list
		493	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)
		494	inc [devices] ;
		495
		496	call probe ; this function will output in eax
		497	test eax, eax
		498	jnz .err2 ; If an error occured, exit
		499
		500	mov [device.type], NET_TYPE_ETH
		501	call NetRegDev
		502
		503	cmp eax, -1
		504	je .destroy
		505
		506	ret
		507
		508	; If the device was already loaded, find the device number and return it in eax
		509
		510	.find_devicenum:
		511	DEBUGF 2,"Trying to find device number of already registered device\n"
		512	call NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
		513	; into a device number in edi
		514	mov eax, edi ; Application wants it in eax instead
		515	DEBUGF 2,"Kernel says: %u\n", eax
		516	ret
		517
		518	; If an error occured, remove all allocated data and exit (returning -1 in eax)
		519
		520	.destroy:
		521	; todo: reset device into virgin state
		522
		523	.err2:
		524	dec [devices]
		525	.err:
		526	DEBUGF 2,"removing device structure\n"
		527	stdcall KernelFree, ebx
		528	.fail:
		529	or eax, -1
		530	ret
		531
		532	;------------------------------------------------------
		533	endp
		534
		535
		536	align 4
		537	unload:
		538
		539	ret
		540
		541
		542	align 4
		543	init_board:
		544
		545	DEBUGF 1,"init_board\n"
		546
		547	PCI_make_bus_master
		548
		549	; Soft reset the chip
		550	set_io 0
		551	set_io REG_ChipCmd
		552	mov al, CMD_Reset
		553	out dx, al
		554
		555	; Check that the chip has finished the reset
		556	mov ecx, 1000
		557	set_io REG_ChipCmd
		558	@@: in al, dx
		559	test al, CMD_Reset
		560	jz @f
		561	udelay 10
		562	loop @b
		563	@@:
		564	; identify config method
		565	set_io REG_TxConfig
		566	in eax, dx
		567	and eax, 0x7c800000
		568	DEBUGF 1,"init_board: TxConfig & 0x7c800000 = 0x%x\n", eax
		569	mov esi, mac_info-8
		570	@@: add esi, 8
		571	mov ecx, eax
		572	and ecx, [esi]
		573	cmp ecx, [esi]
		574	jne @b
		575	mov eax, [esi+4]
		576	mov [tpc.mcfg], eax
		577
		578	mov [tpc.pcfg], PCFG_METHOD_3
		579	READ_GMII_REG 3
		580	and al, 0x0f
		581	or al, al
		582	jnz @f
		583	mov [tpc.pcfg], PCFG_METHOD_1
		584	jmp .pconf
		585	@@: dec al
		586	jnz .pconf
		587	mov [tpc.pcfg], PCFG_METHOD_2
		588	.pconf:
		589
		590	; identify chip attached to board
		591	mov ecx, 10
		592	mov eax, [tpc.mcfg]
		593	@@: dec ecx
		594	js @f
		595	cmp eax, [rtl_chip_info + ecx*8]
		596	jne @b
		597	mov [tpc.chipset], ecx
		598	jmp .match
		599	@@:
		600	; if unknown chip, assume array element #0, original RTL-8169 in this case
		601	DEBUGF 1,"init_board: PCI device: unknown chip version, assuming RTL-8169\n"
		602	set_io REG_TxConfig
		603	in eax, dx
		604	DEBUGF 1,"init_board: PCI device: TxConfig = 0x%x\n", eax
		605
		606	mov [tpc.chipset], 0
		607
		608	xor eax, eax
		609	inc eax
		610	ret
		611
		612	.match:
		613	DEBUGF 1,"init_board: chipset=%u\n", ecx
		614	xor eax,eax
		615	ret
		616
		617
		618
		619	;***************************************************************************
		620	; Function
		621	; probe
		622	; Description
		623	; Searches for an ethernet card, enables it and clears the rx buffer
		624	; If a card was found, it enables the ethernet -> TCPIP link
		625	; Destroyed registers
		626	; eax, ebx, ecx, edx
		627	;
		628	;***************************************************************************
		629	align 4
		630	probe:
		631
		632	DEBUGF 1,"probe\n"
		633
		634	call init_board
		635	call read_mac
		636	call PHY_config
		637
4334	hidnplayr	638	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
3545	hidnplayr	639	set_io 0
		640	set_io 0x82
		641	mov al, 0x01
		642	out dx, al
		643	cmp [tpc.mcfg], MCFG_METHOD_03
		644	jae @f
4334	hidnplayr	645	DEBUGF 1,"Set PCI Latency=0x40\n"
		646	PCI_adjust_latency 0x40
3545	hidnplayr	647	@@:
		648	cmp [tpc.mcfg], MCFG_METHOD_02
		649	jne @f
4334	hidnplayr	650	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
4803	hidnplayr	651	set_io 0
3545	hidnplayr	652	set_io 0x82
		653	mov al, 0x01
		654	out dx, al
4334	hidnplayr	655	DEBUGF 1,"Set PHY Reg 0x0bh = 0x00h\n"
3545	hidnplayr	656	WRITE_GMII_REG 0x0b, 0x0000 ; w 0x0b 15 0 0
		657	@@:
		658	; if TBI is not enabled
		659	set_io 0
		660	set_io REG_PHYstatus
		661	in al, dx
		662	test al, PHYS_TBI_Enable
		663	jz .tbi_dis
		664	READ_GMII_REG PHY_AUTO_NEGO_REG
		665
		666	; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
		667	and eax, 0x0C1F
		668	or eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
		669	WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
		670
		671	; enable 1000 Full Mode
		672	WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
		673
		674	; Enable auto-negotiation and restart auto-nigotiation
		675	WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
		676
4803	hidnplayr	677	udelay 1 ; 100
		678	mov ecx, 200 ; 10000
		679	DEBUGF 1, "Waiting for auto-negotiation to complete\n"
3545	hidnplayr	680	; wait for auto-negotiation process
		681	@@: dec ecx
		682	jz @f
		683	set_io 0
		684	READ_GMII_REG PHY_STAT_REG
4803	hidnplayr	685	udelay 1 ; 100
3545	hidnplayr	686	test eax, PHY_Auto_Neco_Comp
		687	jz @b
		688	set_io REG_PHYstatus
		689	in al, dx
		690	jmp @f
		691	.tbi_dis:
4803	hidnplayr	692	udelay 1 ; 100
3545	hidnplayr	693	@@:
4803	hidnplayr	694	DEBUGF 1, "auto-negotiation complete\n"
3545	hidnplayr	695
		696	;***************************************************************************
		697	; Function
		698	; rt8169_reset
		699	; Description
		700	; Place the chip (ie, the ethernet card) into a virgin state
		701	; Destroyed registers
		702	; eax, ebx, ecx, edx
		703	;
		704	;***************************************************************************
		705	align 4
		706	reset:
		707
4803	hidnplayr	708	DEBUGF 1,"resetting\n"
3545	hidnplayr	709
		710	lea eax, [device.tx_ring]
		711	mov [tpc.TxDescArrays], eax
		712	mov [tpc.TxDescArray], eax
		713
		714	lea eax, [device.rx_ring]
		715	mov [tpc.RxDescArrays], eax
		716	mov [tpc.RxDescArray], eax
		717
		718	call init_ring
		719	call hw_start
		720
		721	; clear packet/byte counters
		722
		723	xor eax, eax
		724	lea edi, [device.bytes_tx]
		725	mov ecx, 6
		726	rep stosd
		727
		728	mov [device.mtu], 1500
		729
		730	; Set link state to unknown
		731	mov [device.state], ETH_LINK_UNKOWN
		732
4803	hidnplayr	733	DEBUGF 2,"init OK!\n"
3545	hidnplayr	734	xor eax, eax
		735	ret
		736
		737
		738
		739
		740
		741	align 4
		742	PHY_config:
		743
4334	hidnplayr	744	DEBUGF 1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n", [tpc.mcfg], [tpc.pcfg]
3545	hidnplayr	745
		746	cmp [tpc.mcfg], MCFG_METHOD_04
		747	jne .not_4
		748	set_io 0
		749	; WRITE_GMII_REG 0x1F, 0x0001
		750	; WRITE_GMII_REG 0x1b, 0x841e
		751	; WRITE_GMII_REG 0x0e, 0x7bfb
		752	; WRITE_GMII_REG 0x09, 0x273a
		753	WRITE_GMII_REG 0x1F, 0x0002
		754	WRITE_GMII_REG 0x01, 0x90D0
		755	WRITE_GMII_REG 0x1F, 0x0000
		756	jmp .exit
		757	.not_4:
		758	cmp [tpc.mcfg], MCFG_METHOD_02
		759	je @f
		760	cmp [tpc.mcfg], MCFG_METHOD_03
		761	jne .not_2_or_3
		762	@@:
		763	set_io 0
		764	WRITE_GMII_REG 0x1F, 0x0001
		765	WRITE_GMII_REG 0x15, 0x1000
		766	WRITE_GMII_REG 0x18, 0x65C7
		767	WRITE_GMII_REG 0x04, 0x0000
		768	WRITE_GMII_REG 0x03, 0x00A1
		769	WRITE_GMII_REG 0x02, 0x0008
		770	WRITE_GMII_REG 0x01, 0x1020
		771	WRITE_GMII_REG 0x00, 0x1000
		772	WRITE_GMII_REG 0x04, 0x0800
		773	WRITE_GMII_REG 0x04, 0x0000
		774	WRITE_GMII_REG 0x04, 0x7000
		775	WRITE_GMII_REG 0x03, 0xFF41
		776	WRITE_GMII_REG 0x02, 0xDE60
		777	WRITE_GMII_REG 0x01, 0x0140
		778	WRITE_GMII_REG 0x00, 0x0077
		779	WRITE_GMII_REG 0x04, 0x7800
		780	WRITE_GMII_REG 0x04, 0x7000
		781	WRITE_GMII_REG 0x04, 0xA000
		782	WRITE_GMII_REG 0x03, 0xDF01
		783	WRITE_GMII_REG 0x02, 0xDF20
		784	WRITE_GMII_REG 0x01, 0xFF95
		785	WRITE_GMII_REG 0x00, 0xFA00
		786	WRITE_GMII_REG 0x04, 0xA800
		787	WRITE_GMII_REG 0x04, 0xA000
		788	WRITE_GMII_REG 0x04, 0xB000
		789	WRITE_GMII_REG 0x03, 0xFF41
		790	WRITE_GMII_REG 0x02, 0xDE20
		791	WRITE_GMII_REG 0x01, 0x0140
		792	WRITE_GMII_REG 0x00, 0x00BB
		793	WRITE_GMII_REG 0x04, 0xB800
		794	WRITE_GMII_REG 0x04, 0xB000
		795	WRITE_GMII_REG 0x04, 0xF000
		796	WRITE_GMII_REG 0x03, 0xDF01
		797	WRITE_GMII_REG 0x02, 0xDF20
		798	WRITE_GMII_REG 0x01, 0xFF95
		799	WRITE_GMII_REG 0x00, 0xBF00
		800	WRITE_GMII_REG 0x04, 0xF800
		801	WRITE_GMII_REG 0x04, 0xF000
		802	WRITE_GMII_REG 0x04, 0x0000
		803	WRITE_GMII_REG 0x1F, 0x0000
		804	WRITE_GMII_REG 0x0B, 0x0000
		805	jmp .exit
		806	.not_2_or_3:
		807	DEBUGF 1,"tpc.mcfg=%d, discard hw PHY config\n", [tpc.mcfg]
		808	.exit:
		809	ret
		810
		811
		812
		813	align 4
		814	set_rx_mode:
		815
		816	DEBUGF 1,"set_rx_mode\n"
		817
		818	; IFF_ALLMULTI
		819	; Too many to filter perfectly -- accept all multicasts
		820	set_io 0
		821	set_io REG_RxConfig
		822	in eax, dx
		823	mov ecx, [tpc.chipset]
		824	and eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
		825	or eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
		826	out dx, eax
		827
		828	; Multicast hash filter
		829	set_io REG_MAR0 + 0
		830	or eax, -1
		831	out dx, eax
		832	set_io REG_MAR0 + 4
		833	out dx, eax
		834
		835	ret
		836
		837
		838	align 4
		839	init_ring:
		840
		841	DEBUGF 1,"init_ring\n"
		842
		843	xor eax, eax
		844	mov [tpc.cur_rx], eax
		845	mov [tpc.cur_tx], eax
		846
		847	lea edi, [device.tx_ring]
		848	mov ecx, (NUM_TX_DESC * tx_desc.size) / 4
		849	rep stosd
		850
		851	lea edi, [device.rx_ring]
		852	mov ecx, (NUM_RX_DESC * rx_desc.size) / 4
		853	rep stosd
		854
		855	mov edi, [tpc.RxDescArray]
		856	mov ecx, NUM_RX_DESC
		857	.loop:
		858	push ecx
		859	stdcall KernelAlloc, RX_BUF_SIZE
		860	mov [edi + rx_desc.buf_soft_addr], eax
		861	call GetPgAddr
		862	mov dword [edi + rx_desc.buf_addr], eax
		863	mov [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
		864	add edi, rx_desc.size
		865	pop ecx
		866	loop .loop
		867	or [edi - rx_desc.size + rx_desc.status], DSB_EORbit
		868
		869	ret
		870
		871
		872	align 4
		873	hw_start:
		874
		875	DEBUGF 1,"hw_start\n"
		876
		877	; attach int handler
		878	movzx eax, [device.irq_line]
		879	DEBUGF 1,"Attaching int handler to irq %x\n", eax:1
		880	stdcall AttachIntHandler, eax, int_handler, dword 0
		881
		882	; Soft reset the chip
		883	set_io 0
		884	set_io REG_ChipCmd
		885	mov al, CMD_Reset
		886	out dx, al
		887
		888	DEBUGF 1,"Waiting for chip to reset... "
		889	; Check that the chip has finished the reset
		890	mov ecx, 1000
		891	set_io REG_ChipCmd
		892	@@: in al, dx
		893	test al, CMD_Reset
		894	jz @f
		895	udelay 10
		896	loop @b
		897	@@:
		898	DEBUGF 1,"done!\n"
		899
		900	set_io REG_Cfg9346
		901	mov al, CFG_9346_Unlock
		902	out dx, al
		903
		904	set_io REG_ChipCmd
		905	mov al, CMD_TxEnb or CMD_RxEnb
		906	out dx, al
		907
		908	set_io REG_ETThReg
		909	mov al, ETTh
		910	out dx, al
		911
		912	; For gigabit rtl8169
		913	set_io REG_RxMaxSize
		914	mov ax, RxPacketMaxSize
		915	out dx, ax
		916
		917	; Set Rx Config register
		918	set_io REG_RxConfig
		919	in ax, dx
		920	mov ecx, [tpc.chipset]
		921	and eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
		922	or eax, rx_config
		923	out dx, eax
		924
		925	; Set DMA burst size and Interframe Gap Time
		926	set_io REG_TxConfig
		927	mov eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
		928	out dx, eax
		929
		930	set_io REG_CPlusCmd
		931	in ax, dx
		932	out dx, ax
		933
		934	in ax, dx
		935	or ax, 1 shl 3
		936	cmp [tpc.mcfg], MCFG_METHOD_02
		937	jne @f
		938	cmp [tpc.mcfg], MCFG_METHOD_03
		939	jne @f
		940	or ax,1 shl 14
		941	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
		942	jmp .set
		943	@@:
		944	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n"
		945	.set:
		946	set_io REG_CPlusCmd
		947	out dx, ax
		948
		949	set_io 0xE2
		950	; mov ax, 0x1517
		951	; out dx, ax
		952	; mov ax, 0x152a
		953	; out dx, ax
		954	; mov ax, 0x282a
		955	; out dx, ax
		956	xor ax, ax
		957	out dx, ax
		958
		959	xor eax, eax
		960	mov [tpc.cur_rx], eax
		961	lea eax, [device.tx_ring]
		962	GetRealAddr
		963	set_io REG_TxDescStartAddr
		964	out dx, eax
4301	clevermous	965	set_io REG_TxDescStartAddr + 4
		966	xor eax, eax
		967	out dx, eax
3545	hidnplayr	968
		969	lea eax, [device.rx_ring]
		970	GetRealAddr
		971	set_io REG_RxDescStartAddr
		972	out dx, eax
4301	clevermous	973	xor eax, eax
		974	set_io REG_RxDescStartAddr + 4
		975	out dx, eax
3545	hidnplayr	976
		977	set_io REG_Cfg9346
		978	mov al, CFG_9346_Lock
		979	out dx, al
		980
		981	udelay 10
		982
		983	xor eax, eax
		984	set_io REG_RxMissed
		985	out dx, eax
		986
		987	call set_rx_mode
		988
		989	set_io 0
		990	; no early-rx interrupts
		991	set_io REG_MultiIntr
		992	in ax, dx
		993	and ax, 0xF000
		994	out dx, ax
		995
		996	; set interrupt mask
		997	set_io REG_IntrMask
		998	mov ax, intr_mask
		999	out dx, ax
		1000
		1001	xor eax, eax
		1002	ret
		1003
		1004
		1005	align 4
		1006	read_mac:
		1007
		1008	set_io 0
		1009	set_io REG_MAC0
		1010	xor ecx, ecx
		1011	lea edi, [device.mac]
		1012	mov ecx, 6
		1013
		1014	; Get MAC address. FIXME: read EEPROM
		1015	@@: in al, dx
		1016	stosb
		1017	inc edx
		1018	loop @r
		1019
		1020	DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\
		1021	[device.mac+0]:2,[device.mac+1]:2,[device.mac+2]:2,[device.mac+3]:2,[device.mac+4]:2,[device.mac+5]:2
		1022
		1023	ret
		1024
		1025	align 4
		1026	write_mac:
		1027
		1028	ret 6
		1029
		1030
		1031
		1032
		1033
		1034	;***************************************************************************
		1035	; Function
		1036	; transmit
		1037	; Description
		1038	; Transmits a packet of data via the ethernet card
		1039	;
		1040	; Destroyed registers
		1041	; eax, edx, esi, edi
		1042	;
		1043	;***************************************************************************
		1044	align 4
		1045	transmit:
		1046
		1047	DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8]
		1048	mov eax, [esp+4]
		1049	DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
		1050	[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
		1051	[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
		1052	[eax+13]:2,[eax+12]:2
		1053
		1054	cmp dword [esp+8], MAX_ETH_FRAME_SIZE
		1055	ja .fail
		1056
		1057	;----------------------------------
		1058	; Find currentTX descriptor address
		1059
		1060	mov eax, tx_desc.size
		1061	mul [tpc.cur_tx]
		1062	lea esi, [eax + device.tx_ring]
		1063
		1064	DEBUGF 1,"Using TX desc: %x\n", esi
		1065
		1066	;---------------------------
		1067	; Program the packet pointer
		1068
		1069	mov eax, [esp + 4]
		1070	mov [esi + tx_desc.buf_soft_addr], eax
		1071	GetRealAddr
		1072	mov dword [esi + tx_desc.buf_addr], eax
		1073
		1074	;------------------------
		1075	; Program the packet size
		1076
		1077	mov eax, [esp + 8]
		1078	@@: or eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
		1079	cmp [tpc.cur_tx], NUM_TX_DESC - 1
		1080	jne @f
		1081	or eax, DSB_EORbit
		1082	@@: mov [esi + tx_desc.status], eax
		1083
		1084	;-----------------------------------------
		1085	; Set the polling bit (start transmission)
		1086
		1087	set_io 0
		1088	set_io REG_TxPoll
		1089	mov al, 0x40 ; set polling bit
		1090	out dx, al
		1091
		1092	;-----------------------
		1093	; Update TX descriptor
		1094
		1095	inc [tpc.cur_tx]
		1096	and [tpc.cur_tx], NUM_TX_DESC - 1
		1097
		1098	;-------------
		1099	; Update stats
		1100
		1101	inc [device.packets_tx]
		1102	mov eax, [esp + 8]
		1103	add dword [device.bytes_tx], eax
		1104	adc dword [device.bytes_tx + 4], 0
		1105
		1106	xor eax, eax
		1107	ret 8
		1108
		1109	.fail:
		1110	DEBUGF 1,"transmit failed\n"
4334	hidnplayr	1111	stdcall KernelFree, [esp+4]
3545	hidnplayr	1112	or eax, -1
		1113	ret 8
		1114
		1115
		1116	;;;DSB_OWNbit
		1117
		1118
		1119	;;;;;;;;;;;;;;;;;;;;;;;
		1120	;; ;;
		1121	;; Interrupt handler ;;
		1122	;; ;;
		1123	;;;;;;;;;;;;;;;;;;;;;;;
		1124
		1125	align 4
		1126	int_handler:
		1127
		1128	push ebx esi edi
		1129
4334	hidnplayr	1130	DEBUGF 1,"INT\n"
3545	hidnplayr	1131
		1132	; find pointer of device wich made IRQ occur
		1133
		1134	mov ecx, [devices]
		1135	test ecx, ecx
		1136	jz .nothing
		1137	mov esi, device_list
		1138	.nextdevice:
		1139	mov ebx, [esi]
		1140
		1141	set_io 0
		1142	set_io REG_IntrStatus
		1143	in ax, dx
		1144	test ax, ax
		1145	jnz .got_it
		1146	.continue:
		1147	add esi, 4
		1148	dec ecx
		1149	jnz .nextdevice
		1150	.nothing:
		1151	pop edi esi ebx
		1152	xor eax, eax
		1153
		1154	ret ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
		1155
		1156	.got_it:
		1157
		1158	DEBUGF 1,"Device: %x Status: %x ", ebx, ax
		1159
		1160	cmp ax, 0xFFFF ; if so, hardware is no longer present
		1161	je .fail
		1162
		1163	;--------
		1164	; Receive
		1165
		1166	test ax, ISB_RxOK
		1167	jz .no_rx
		1168
		1169	push ax
		1170	push ebx
		1171
		1172	.check_more:
		1173	pop ebx
		1174	DEBUGF 1,"ebx = 0x%x\n", ebx
		1175	mov eax, rx_desc.size
		1176	mul [tpc.cur_rx]
		1177	lea esi, [eax + device.rx_ring]
		1178
		1179	DEBUGF 1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
		1180
		1181	mov eax, [esi + rx_desc.status]
		1182	test eax, DSB_OWNbit ;;;
		1183	jnz .rx_return
		1184
		1185	DEBUGF 1,"tpc.cur_rx = %u\n", [tpc.cur_rx]
		1186
		1187	test eax, SD_RxRES
		1188	jnz .rx_return ;;;;; RX error!
		1189
		1190	push ebx
		1191	push .check_more
		1192	and eax, 0x00001FFF
		1193	add eax, -4 ; we dont need CRC
		1194	push eax
		1195	DEBUGF 1,"data length = %u\n", ax
		1196
		1197	;-------------
		1198	; Update stats
		1199
		1200	add dword [device.bytes_rx], eax
		1201	adc dword [device.bytes_rx + 4], 0
		1202	inc dword [device.packets_rx]
		1203
		1204	push [esi + rx_desc.buf_soft_addr]
		1205
		1206	;----------------------
		1207	; Allocate a new buffer
		1208
		1209	stdcall KernelAlloc, RX_BUF_SIZE
		1210	mov [esi + rx_desc.buf_soft_addr], eax
		1211	GetRealAddr
		1212	mov dword [esi + rx_desc.buf_addr], eax
		1213
		1214	;---------------
		1215	; re set OWN bit
		1216
		1217	mov eax, DSB_OWNbit or RX_BUF_SIZE
		1218	cmp [tpc.cur_rx], NUM_RX_DESC - 1
		1219	jne @f
		1220	or eax, DSB_EORbit
		1221	@@: mov [esi + rx_desc.status], eax
		1222
		1223	;--------------
		1224	; Update rx ptr
		1225
		1226	inc [tpc.cur_rx]
		1227	and [tpc.cur_rx], NUM_RX_DESC - 1
		1228
		1229	jmp Eth_input
		1230	.rx_return:
		1231
		1232	pop ax
		1233	.no_rx:
		1234
		1235	;---------
		1236	; Transmit
		1237
		1238	test ax, ISB_TxOK
		1239	jz .no_tx
		1240	push ax
		1241
		1242	DEBUGF 1,"TX ok!\n"
		1243
		1244	mov ecx, NUM_TX_DESC
		1245	lea esi, [device.tx_ring]
		1246	.txloop:
		1247	cmp [esi + tx_desc.buf_soft_addr], 0
		1248	jz .maybenext
		1249
		1250	test [esi + tx_desc.status], DSB_OWNbit
		1251	jnz .maybenext
		1252
		1253	push ecx
		1254	DEBUGF 1,"Freeing up TX desc: %x\n", esi
		1255	stdcall KernelFree, [esi + tx_desc.buf_soft_addr]
		1256	pop ecx
		1257	and [esi + tx_desc.buf_soft_addr], 0
		1258
		1259	.maybenext:
		1260	add esi, tx_desc.size
		1261	dec ecx
		1262	jnz .txloop
		1263
		1264	pop ax
		1265	.no_tx:
		1266
		1267	;-------
		1268	; Finish
		1269
		1270	set_io 0
		1271	set_io REG_IntrStatus
		1272	out dx, ax ; ACK all interrupts
		1273
		1274	.fail:
		1275	pop edi esi ebx
		1276	xor eax, eax
		1277	inc eax
		1278
		1279	ret
		1280
		1281
		1282
		1283
		1284
		1285
		1286
		1287
		1288
		1289	; End of code
		1290	align 4 ; Place all initialised data here
		1291
		1292	devices dd 0
		1293	version dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF)
		1294	my_service db 'RTL8169',0 ; max 16 chars include zero
		1295
		1296	include_debug_strings ; All data wich FDO uses will be included here
		1297
		1298	rtl_chip_info dd \
		1299	MCFG_METHOD_01, 0xff7e1880, \ ; RTL8169
		1300	MCFG_METHOD_02, 0xff7e1880, \ ; RTL8169s/8110s
		1301	MCFG_METHOD_03, 0xff7e1880, \ ; RTL8169s/8110s
		1302	MCFG_METHOD_04, 0xff7e1880, \ ; RTL8169sb/8110sb
		1303	MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc
		1304	MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E
		1305	MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E
		1306	MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e // PCI-E 8139
		1307	MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e // PCI-E 8139
		1308	MCFG_METHOD_15, 0xff7e1880 ; RTL8100e // PCI-E 8139
		1309
		1310	mac_info dd \
		1311	0x38800000, MCFG_METHOD_15, \
		1312	0x38000000, MCFG_METHOD_12, \
		1313	0x34000000, MCFG_METHOD_13, \
		1314	0x30800000, MCFG_METHOD_14, \
		1315	0x30000000, MCFG_METHOD_11, \
		1316	0x18000000, MCFG_METHOD_05, \
		1317	0x10000000, MCFG_METHOD_04, \
		1318	0x04000000, MCFG_METHOD_03, \
		1319	0x00800000, MCFG_METHOD_02, \
		1320	0x00000000, MCFG_METHOD_01 ; catch-all
		1321
		1322	name_01 db "RTL8169", 0
		1323	name_02_03 db "RTL8169s/8110s", 0
		1324	name_04 db "RTL8169sb/8110sb", 0
		1325	name_05 db "RTL8169sc/8110sc", 0
		1326	name_11_12 db "RTL8168b/8111b", 0 ; PCI-E
		1327	name_13 db "RTL8101e", 0 ; PCI-E 8139
		1328	name_14_15 db "RTL8100e", 0 ; PCI-E 8139
		1329
		1330
		1331	section '.data' data readable writable align 16 ; place all uninitialized data place here
		1332
		1333	device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling
		1334

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(root)/drivers/ethernet/RTL8169.asm – Rev 4803