WebSVN – Kolibri OS – Blame – /drivers/devman/acpinfo/acpi.h

Rev	Author	Line No.	Line
2293	Serge	1
		2	#define ACPI_OEM_ID_SIZE 6
		3	#define ACPI_OEM_TABLE_ID_SIZE 8
		4
		5
		6	{
		7	u8_t type;
		8	u8_t len;
		9	}acpi_madt_hdr_t;
		10
		11
		12	{
		13	acpi_madt_hdr_t header;
		14
		15
		16	u8_t id;
		17	struct {
		18	u32_t enabled : 1;
		19	u32_t : 31;
		20	} flags;
		21	}acpi_madt_lapic_t;
		22
		23
		24	{
		25	acpi_madt_hdr_t header;
		26
		27
		28	u8_t _rsvd_3;
		29
		30
		31	u32_t irq_base; /* global irq number base */
		32	}acpi_madt_ioapic_t;
		33
		34
		35	conform_polarity = 0,
		36	active_high = 1,
		37	reserved_polarity = 2,
		38	active_low = 3
		39	}polarity_t ;
		40
		41
		42	conform_trigger = 0,
		43	edge = 1,
		44	reserved_trigger = 2,
		45	level = 3
		46	}trigger_mode_t;
		47
		48
		49	{
		50	acpi_madt_hdr_t header;
		51
		52
		53	u8_t src_irq; /* source bus irq */
		54	u32_t dest; /* global irq number */
		55	union {
		56	u16_t flags; /* irq flags */
		57	struct {
		58	u16_t polarity : 2;
		59	u16_t trigger_mode : 2;
		60	u16_t reserved : 12;
		61	} x;
		62	};
		63	}acpi_madt_irq_t;
		64
		65
		66	{ return (polarity_t) irq->x.polarity; }
		67
		68
		69	{ return (trigger_mode_t) irq->x.trigger_mode; }
		70
		71
		72
		73	{
		74	acpi_madt_hdr_t header;
		75
		76
		77	u16_t flags;
		78	struct {
		79	u16_t polarity : 2;
		80	u16_t trigger_mode : 2;
		81	u16_t reserved : 12;
		82	} x;
		83	};
		84	u32_t irq;
		85
		86
		87
		88
		89	{ return (polarity_t) nmi->x.polarity; }
		90
		91
		92	{ return (trigger_mode_t) nmi->x.trigger_mode; }
		93
		94
		95	{
		96	acpi_madt_hdr_t header;
		97
		98
		99
		100
		101	u16_t flags;
		102	struct {
		103	u16_t polarity : 2;
		104	u16_t trigger_mode : 2;
		105	u16_t reserved : 12;
		106	} x;
		107	};
		108	u8_t lint;
		109
		110
		111
		112
		113	{ return (polarity_t) nmi->x.polarity; }
		114
		115
		116	{ return (trigger_mode_t) nmi->x.trigger_mode; }
		117
		118
		119
		120	{
		121	u32_t sig;
		122	u32_t len;
		123	u8_t rev;
		124	u8_t csum;
		125	char oem_id[ACPI_OEM_ID_SIZE];
		126	char oem_tid[ACPI_OEM_TABLE_ID_SIZE];
		127	u32_t oem_rev;
		128	u32_t creator_id;
		129	u32_t creator_rev;
		130	}acpi_thead_t;
		131
		132
		133
		134	{
		135	acpi_thead_t header;
		136	u32_t local_apic_addr;
		137	u32_t apic_flags;
		138	u8_t data[0];
		139	} acpi_madt_t;
		140
		141
		142	{
		143	acpi_thead_t header;
		144	u32_t ptrs[0];
		145	}acpi_rsdt_t;
		146
		147
		148	{
		149	acpi_thead_t header;
		150	u64_t ptrs[0];
		151	}acpi_xsdt_t;
		152
		153
		154	{
		155	u32_t sig[2];
		156	u8_t csum;
		157	char oemid[6];
		158	u8_t rev;
		159	u32_t rsdt_ptr;
		160	u32_t rsdt_len;
		161	u64_t xsdt_ptr;
		162	u8_t xcsum;
		163	u8_t _rsvd_33[3];
		164	}acpi_rsdp_t;
		165
		166
		167	{
		168	u8_t SpaceId; /* Address space where struct or register exists */
		169	u8_t BitWidth; /* Size in bits of given register */
		170	u8_t BitOffset; /* Bit offset within the register */
		171	u8_t AccessWidth; /* Minimum Access size (ACPI 3.0) */
		172	u64_t Address; /* 64-bit address of struct or register */
		173
		174
		175
		176
		177	{
		178	acpi_thead_t Header; /* Common ACPI table header */
		179	u32_t Facs; /* 32-bit physical address of FACS */
		180	u32_t Dsdt; /* 32-bit physical address of DSDT */
		181	u8_t Model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
		182	u8_t PreferredProfile; /* Conveys preferred power management profile to OSPM. */
		183	u16_t SciInterrupt; /* System vector of SCI interrupt */
		184	u32_t SmiCommand; /* 32-bit Port address of SMI command port */
		185	u8_t AcpiEnable; /* Value to write to smi_cmd to enable ACPI */
		186	u8_t AcpiDisable; /* Value to write to smi_cmd to disable ACPI */
		187	u8_t S4BiosRequest; /* Value to write to SMI CMD to enter S4BIOS state */
		188	u8_t PstateControl; /* Processor performance state control*/
		189	u32_t Pm1aEventBlock; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */
		190	u32_t Pm1bEventBlock; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */
		191	u32_t Pm1aControlBlock; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */
		192	u32_t Pm1bControlBlock; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */
		193	u32_t Pm2ControlBlock; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */
		194	u32_t PmTimerBlock; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */
		195	u32_t Gpe0Block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */
		196	u32_t Gpe1Block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */
		197	u8_t Pm1EventLength; /* Byte Length of ports at Pm1xEventBlock */
		198	u8_t Pm1ControlLength; /* Byte Length of ports at Pm1xControlBlock */
		199	u8_t Pm2ControlLength; /* Byte Length of ports at Pm2ControlBlock */
		200	u8_t PmTimerLength; /* Byte Length of ports at PmTimerBlock */
		201	u8_t Gpe0BlockLength; /* Byte Length of ports at Gpe0Block */
		202	u8_t Gpe1BlockLength; /* Byte Length of ports at Gpe1Block */
		203	u8_t Gpe1Base; /* Offset in GPE number space where GPE1 events start */
		204	u8_t CstControl; /* Support for the _CST object and C States change notification */
		205	u16_t C2Latency; /* Worst case HW latency to enter/exit C2 state */
		206	u16_t C3Latency; /* Worst case HW latency to enter/exit C3 state */
		207	u16_t FlushSize; /* Processor's memory cache line width, in bytes */
		208	u16_t FlushStride; /* Number of flush strides that need to be read */
		209	u8_t DutyOffset; /* Processor duty cycle index in processor's P_CNT reg*/
		210	u8_t DutyWidth; /* Processor duty cycle value bit width in P_CNT register.*/
		211	u8_t DayAlarm; /* Index to day-of-month alarm in RTC CMOS RAM */
		212	u8_t MonthAlarm; /* Index to month-of-year alarm in RTC CMOS RAM */
		213	u8_t Century; /* Index to century in RTC CMOS RAM */
		214	u16_t BootFlags; /* IA-PC Boot Architecture Flags. See Table 5-10 for description */
		215	u8_t Reserved; /* Reserved, must be zero */
		216	u32_t Flags; /* Miscellaneous flag bits (see below for individual flags) */
		217	acpi_address_t ResetRegister; /* 64-bit address of the Reset register */
		218	u8_t ResetValue; /* Value to write to the ResetRegister port to reset the system */
		219	u8_t Reserved4[3]; /* Reserved, must be zero */
		220	u64_t XFacs; /* 64-bit physical address of FACS */
		221	u64_t XDsdt; /* 64-bit physical address of DSDT */
		222	acpi_address_t XPm1aEventBlock; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
		223	acpi_address_t XPm1bEventBlock; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
		224	acpi_address_t XPm1aControlBlock; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
		225	acpi_address_t XPm1bControlBlock; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
		226	acpi_address_t XPm2ControlBlock; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
		227	acpi_address_t XPmTimerBlock; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
		228	acpi_address_t XGpe0Block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
		229	acpi_address_t XGpe1Block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
		230	} acpi_fadt_t;
		231
		232
		233
		234
		235
		236	#define ACPI_HI_RSDP_WINDOW_END (OS_BASE+0x00100000)
		237	#define ACPI_RSDP_CHECKSUM_LENGTH 20
		238	#define ACPI_RSDP_XCHECKSUM_LENGTH 36
		239
		240
		241
		242
		243	(addr_t)((addr_t)(addr) + (addr_t)(off))
		244
		245
		246	(addr_t)((addr_t)(x)+OS_BASE)
		247
		248
		249

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(root)/drivers/devman/acpinfo/acpi.h – Rev 2293