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1498 | serge | 1 | |
2 | * |
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3 | * Module Name: hwregs - Read/write access functions for the various ACPI |
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4 | * control and status registers. |
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5 | * |
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6 | ******************************************************************************/ |
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7 | |||
8 | |||
9 | * |
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10 | * 1. Copyright Notice |
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11 | * |
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12 | * Some or all of this work - Copyright (c) 1999 - 2011, Intel Corp. |
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2216 | Serge | 13 | * All rights reserved. |
1498 | serge | 14 | * |
15 | * 2. License |
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16 | * |
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17 | * 2.1. This is your license from Intel Corp. under its intellectual property |
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18 | * rights. You may have additional license terms from the party that provided |
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19 | * you this software, covering your right to use that party's intellectual |
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20 | * property rights. |
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21 | * |
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22 | * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a |
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23 | * copy of the source code appearing in this file ("Covered Code") an |
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24 | * irrevocable, perpetual, worldwide license under Intel's copyrights in the |
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25 | * base code distributed originally by Intel ("Original Intel Code") to copy, |
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26 | * make derivatives, distribute, use and display any portion of the Covered |
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27 | * Code in any form, with the right to sublicense such rights; and |
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28 | * |
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29 | * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent |
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30 | * license (with the right to sublicense), under only those claims of Intel |
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31 | * patents that are infringed by the Original Intel Code, to make, use, sell, |
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32 | * offer to sell, and import the Covered Code and derivative works thereof |
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33 | * solely to the minimum extent necessary to exercise the above copyright |
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34 | * license, and in no event shall the patent license extend to any additions |
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35 | * to or modifications of the Original Intel Code. No other license or right |
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36 | * is granted directly or by implication, estoppel or otherwise; |
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37 | * |
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38 | * The above copyright and patent license is granted only if the following |
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39 | * conditions are met: |
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40 | * |
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41 | * 3. Conditions |
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42 | * |
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43 | * 3.1. Redistribution of Source with Rights to Further Distribute Source. |
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44 | * Redistribution of source code of any substantial portion of the Covered |
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45 | * Code or modification with rights to further distribute source must include |
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46 | * the above Copyright Notice, the above License, this list of Conditions, |
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47 | * and the following Disclaimer and Export Compliance provision. In addition, |
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48 | * Licensee must cause all Covered Code to which Licensee contributes to |
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49 | * contain a file documenting the changes Licensee made to create that Covered |
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50 | * Code and the date of any change. Licensee must include in that file the |
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51 | * documentation of any changes made by any predecessor Licensee. Licensee |
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52 | * must include a prominent statement that the modification is derived, |
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53 | * directly or indirectly, from Original Intel Code. |
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54 | * |
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55 | * 3.2. Redistribution of Source with no Rights to Further Distribute Source. |
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56 | * Redistribution of source code of any substantial portion of the Covered |
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57 | * Code or modification without rights to further distribute source must |
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58 | * include the following Disclaimer and Export Compliance provision in the |
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59 | * documentation and/or other materials provided with distribution. In |
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60 | * addition, Licensee may not authorize further sublicense of source of any |
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61 | * portion of the Covered Code, and must include terms to the effect that the |
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62 | * license from Licensee to its licensee is limited to the intellectual |
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63 | * property embodied in the software Licensee provides to its licensee, and |
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64 | * not to intellectual property embodied in modifications its licensee may |
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65 | * make. |
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66 | * |
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67 | * 3.3. Redistribution of Executable. Redistribution in executable form of any |
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68 | * substantial portion of the Covered Code or modification must reproduce the |
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69 | * above Copyright Notice, and the following Disclaimer and Export Compliance |
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70 | * provision in the documentation and/or other materials provided with the |
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71 | * distribution. |
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72 | * |
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73 | * 3.4. Intel retains all right, title, and interest in and to the Original |
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74 | * Intel Code. |
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75 | * |
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76 | * 3.5. Neither the name Intel nor any other trademark owned or controlled by |
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77 | * Intel shall be used in advertising or otherwise to promote the sale, use or |
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78 | * other dealings in products derived from or relating to the Covered Code |
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79 | * without prior written authorization from Intel. |
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80 | * |
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81 | * 4. Disclaimer and Export Compliance |
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82 | * |
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83 | * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED |
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84 | * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE |
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85 | * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, |
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86 | * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY |
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87 | * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY |
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88 | * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A |
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89 | * PARTICULAR PURPOSE. |
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90 | * |
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91 | * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES |
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92 | * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR |
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93 | * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, |
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94 | * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY |
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95 | * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL |
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96 | * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS |
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97 | * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY |
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98 | * LIMITED REMEDY. |
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99 | * |
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100 | * 4.3. Licensee shall not export, either directly or indirectly, any of this |
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101 | * software or system incorporating such software without first obtaining any |
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102 | * required license or other approval from the U. S. Department of Commerce or |
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103 | * any other agency or department of the United States Government. In the |
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104 | * event Licensee exports any such software from the United States or |
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105 | * re-exports any such software from a foreign destination, Licensee shall |
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106 | * ensure that the distribution and export/re-export of the software is in |
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107 | * compliance with all laws, regulations, orders, or other restrictions of the |
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108 | * U.S. Export Administration Regulations. Licensee agrees that neither it nor |
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109 | * any of its subsidiaries will export/re-export any technical data, process, |
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110 | * software, or service, directly or indirectly, to any country for which the |
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111 | * United States government or any agency thereof requires an export license, |
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112 | * other governmental approval, or letter of assurance, without first obtaining |
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113 | * such license, approval or letter. |
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114 | * |
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115 | *****************************************************************************/ |
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116 | |||
117 | |||
118 | |||
119 | |||
120 | #include "accommon.h" |
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121 | #include "acevents.h" |
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122 | |||
123 | |||
124 | ACPI_MODULE_NAME ("hwregs") |
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125 | |||
126 | |||
127 | |||
128 | |||
129 | |||
130 | AcpiHwReadMultiple ( |
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131 | UINT32 *Value, |
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132 | ACPI_GENERIC_ADDRESS *RegisterA, |
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133 | ACPI_GENERIC_ADDRESS *RegisterB); |
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134 | |||
135 | |||
136 | AcpiHwWriteMultiple ( |
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137 | UINT32 Value, |
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138 | ACPI_GENERIC_ADDRESS *RegisterA, |
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139 | ACPI_GENERIC_ADDRESS *RegisterB); |
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140 | |||
141 | |||
142 | |||
143 | * |
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144 | * FUNCTION: AcpiHwValidateRegister |
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145 | * |
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146 | * PARAMETERS: Reg - GAS register structure |
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147 | * MaxBitWidth - Max BitWidth supported (32 or 64) |
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148 | * Address - Pointer to where the gas->address |
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149 | * is returned |
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150 | * |
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151 | * RETURN: Status |
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152 | * |
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153 | * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS |
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154 | * pointer, Address, SpaceId, BitWidth, and BitOffset. |
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155 | * |
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156 | ******************************************************************************/ |
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157 | |||
158 | |||
159 | AcpiHwValidateRegister ( |
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160 | ACPI_GENERIC_ADDRESS *Reg, |
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161 | UINT8 MaxBitWidth, |
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162 | UINT64 *Address) |
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163 | { |
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164 | |||
165 | |||
166 | |||
167 | |||
168 | { |
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169 | return (AE_BAD_PARAMETER); |
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170 | } |
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171 | |||
172 | |||
173 | * Copy the target address. This handles possible alignment issues. |
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174 | * Address must not be null. A null address also indicates an optional |
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175 | * ACPI register that is not supported, so no error message. |
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176 | */ |
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177 | ACPI_MOVE_64_TO_64 (Address, &Reg->Address); |
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178 | if (!(*Address)) |
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179 | { |
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180 | return (AE_BAD_ADDRESS); |
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181 | } |
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182 | |||
183 | |||
184 | |||
185 | |||
186 | (Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_IO)) |
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187 | { |
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188 | ACPI_ERROR ((AE_INFO, |
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189 | "Unsupported address space: 0x%X", Reg->SpaceId)); |
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190 | return (AE_SUPPORT); |
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191 | } |
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192 | |||
193 | |||
194 | |||
195 | |||
196 | (Reg->BitWidth != 16) && |
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197 | (Reg->BitWidth != 32) && |
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198 | (Reg->BitWidth != MaxBitWidth)) |
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199 | { |
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200 | ACPI_ERROR ((AE_INFO, |
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201 | "Unsupported register bit width: 0x%X", Reg->BitWidth)); |
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202 | return (AE_SUPPORT); |
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203 | } |
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204 | |||
205 | |||
206 | |||
207 | |||
208 | { |
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209 | ACPI_WARNING ((AE_INFO, |
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210 | "Unsupported register bit offset: 0x%X", Reg->BitOffset)); |
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211 | } |
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212 | |||
213 | |||
214 | } |
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215 | |||
216 | |||
217 | |||
218 | * |
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219 | * FUNCTION: AcpiHwRead |
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220 | * |
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221 | * PARAMETERS: Value - Where the value is returned |
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222 | * Reg - GAS register structure |
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223 | * |
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224 | * RETURN: Status |
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225 | * |
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226 | * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max |
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227 | * version of AcpiRead, used internally since the overhead of |
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228 | * 64-bit values is not needed. |
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229 | * |
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230 | * LIMITATIONS: |
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231 | * BitWidth must be exactly 8, 16, or 32. |
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232 | * SpaceID must be SystemMemory or SystemIO. |
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233 | * BitOffset and AccessWidth are currently ignored, as there has |
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234 | * not been a need to implement these. |
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235 | * |
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236 | ******************************************************************************/ |
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237 | |||
238 | |||
239 | AcpiHwRead ( |
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240 | UINT32 *Value, |
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241 | ACPI_GENERIC_ADDRESS *Reg) |
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242 | { |
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243 | UINT64 Address; |
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244 | ACPI_STATUS Status; |
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245 | |||
246 | |||
247 | |||
248 | |||
249 | |||
250 | |||
251 | |||
252 | |||
253 | if (ACPI_FAILURE (Status)) |
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254 | { |
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255 | return (Status); |
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256 | } |
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257 | |||
258 | |||
259 | |||
260 | |||
261 | |||
262 | |||
263 | * Two address spaces supported: Memory or IO. PCI_Config is |
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264 | * not supported here because the GAS structure is insufficient |
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265 | */ |
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266 | if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
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267 | { |
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268 | Status = AcpiOsReadMemory ((ACPI_PHYSICAL_ADDRESS) |
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269 | Address, Value, Reg->BitWidth); |
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270 | } |
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271 | else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ |
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272 | { |
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273 | Status = AcpiHwReadPort ((ACPI_IO_ADDRESS) |
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274 | Address, Value, Reg->BitWidth); |
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275 | } |
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276 | |||
277 | |||
278 | "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", |
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279 | *Value, Reg->BitWidth, ACPI_FORMAT_UINT64 (Address), |
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280 | AcpiUtGetRegionName (Reg->SpaceId))); |
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281 | |||
282 | |||
283 | } |
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284 | |||
285 | |||
286 | |||
287 | * |
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288 | * FUNCTION: AcpiHwWrite |
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289 | * |
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290 | * PARAMETERS: Value - Value to be written |
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291 | * Reg - GAS register structure |
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292 | * |
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293 | * RETURN: Status |
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294 | * |
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295 | * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max |
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296 | * version of AcpiWrite, used internally since the overhead of |
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297 | * 64-bit values is not needed. |
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298 | * |
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299 | ******************************************************************************/ |
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300 | |||
301 | |||
302 | AcpiHwWrite ( |
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303 | UINT32 Value, |
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304 | ACPI_GENERIC_ADDRESS *Reg) |
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305 | { |
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306 | UINT64 Address; |
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307 | ACPI_STATUS Status; |
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308 | |||
309 | |||
310 | |||
311 | |||
312 | |||
313 | |||
314 | |||
315 | |||
316 | if (ACPI_FAILURE (Status)) |
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317 | { |
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318 | return (Status); |
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319 | } |
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320 | |||
321 | |||
322 | * Two address spaces supported: Memory or IO. PCI_Config is |
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323 | * not supported here because the GAS structure is insufficient |
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324 | */ |
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325 | if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
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326 | { |
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327 | Status = AcpiOsWriteMemory ((ACPI_PHYSICAL_ADDRESS) |
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328 | Address, Value, Reg->BitWidth); |
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329 | } |
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330 | else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ |
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331 | { |
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332 | Status = AcpiHwWritePort ((ACPI_IO_ADDRESS) |
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333 | Address, Value, Reg->BitWidth); |
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334 | } |
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335 | |||
336 | |||
337 | "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", |
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338 | Value, Reg->BitWidth, ACPI_FORMAT_UINT64 (Address), |
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339 | AcpiUtGetRegionName (Reg->SpaceId))); |
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340 | |||
341 | |||
342 | } |
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343 | |||
344 | |||
345 | |||
346 | * |
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347 | * FUNCTION: AcpiHwClearAcpiStatus |
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348 | * |
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349 | * PARAMETERS: None |
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350 | * |
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351 | * RETURN: Status |
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352 | * |
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353 | * DESCRIPTION: Clears all fixed and general purpose status bits |
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354 | * |
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355 | ******************************************************************************/ |
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356 | |||
357 | |||
358 | AcpiHwClearAcpiStatus ( |
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359 | void) |
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360 | { |
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361 | ACPI_STATUS Status; |
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362 | ACPI_CPU_FLAGS LockFlags = 0; |
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363 | |||
364 | |||
365 | |||
366 | |||
367 | |||
368 | |||
369 | ACPI_BITMASK_ALL_FIXED_STATUS, |
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370 | ACPI_FORMAT_UINT64 (AcpiGbl_XPm1aStatus.Address))); |
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371 | |||
372 | |||
373 | |||
374 | |||
375 | |||
376 | |||
377 | ACPI_BITMASK_ALL_FIXED_STATUS); |
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378 | if (ACPI_FAILURE (Status)) |
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379 | { |
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380 | goto UnlockAndExit; |
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381 | } |
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382 | |||
383 | |||
384 | |||
385 | |||
386 | |||
387 | |||
388 | AcpiOsReleaseLock (AcpiGbl_HardwareLock, LockFlags); |
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389 | return_ACPI_STATUS (Status); |
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390 | } |
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391 | |||
392 | |||
393 | |||
394 | * |
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395 | * FUNCTION: AcpiHwGetRegisterBitMask |
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396 | * |
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397 | * PARAMETERS: RegisterId - Index of ACPI Register to access |
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398 | * |
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399 | * RETURN: The bitmask to be used when accessing the register |
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400 | * |
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401 | * DESCRIPTION: Map RegisterId into a register bitmask. |
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402 | * |
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403 | ******************************************************************************/ |
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404 | |||
405 | |||
406 | AcpiHwGetBitRegisterInfo ( |
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407 | UINT32 RegisterId) |
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408 | { |
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409 | ACPI_FUNCTION_ENTRY (); |
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410 | |||
411 | |||
412 | |||
413 | { |
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414 | ACPI_ERROR ((AE_INFO, "Invalid BitRegister ID: 0x%X", RegisterId)); |
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415 | return (NULL); |
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416 | } |
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417 | |||
418 | |||
419 | } |
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420 | |||
421 | |||
422 | |||
423 | * |
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424 | * FUNCTION: AcpiHwWritePm1Control |
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425 | * |
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426 | * PARAMETERS: Pm1aControl - Value to be written to PM1A control |
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427 | * Pm1bControl - Value to be written to PM1B control |
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428 | * |
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429 | * RETURN: Status |
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430 | * |
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431 | * DESCRIPTION: Write the PM1 A/B control registers. These registers are |
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432 | * different than than the PM1 A/B status and enable registers |
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433 | * in that different values can be written to the A/B registers. |
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434 | * Most notably, the SLP_TYP bits can be different, as per the |
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435 | * values returned from the _Sx predefined methods. |
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436 | * |
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437 | ******************************************************************************/ |
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438 | |||
439 | |||
440 | AcpiHwWritePm1Control ( |
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441 | UINT32 Pm1aControl, |
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442 | UINT32 Pm1bControl) |
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443 | { |
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444 | ACPI_STATUS Status; |
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445 | |||
446 | |||
447 | |||
448 | |||
449 | |||
450 | |||
451 | if (ACPI_FAILURE (Status)) |
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452 | { |
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453 | return_ACPI_STATUS (Status); |
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454 | } |
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455 | |||
456 | |||
457 | { |
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458 | Status = AcpiHwWrite (Pm1bControl, &AcpiGbl_FADT.XPm1bControlBlock); |
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459 | } |
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460 | return_ACPI_STATUS (Status); |
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461 | } |
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462 | |||
463 | |||
464 | |||
465 | * |
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466 | * FUNCTION: AcpiHwRegisterRead |
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467 | * |
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468 | * PARAMETERS: RegisterId - ACPI Register ID |
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469 | * ReturnValue - Where the register value is returned |
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470 | * |
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471 | * RETURN: Status and the value read. |
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472 | * |
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473 | * DESCRIPTION: Read from the specified ACPI register |
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474 | * |
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475 | ******************************************************************************/ |
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476 | |||
477 | |||
478 | AcpiHwRegisterRead ( |
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479 | UINT32 RegisterId, |
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480 | UINT32 *ReturnValue) |
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481 | { |
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482 | UINT32 Value = 0; |
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483 | ACPI_STATUS Status; |
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484 | |||
485 | |||
486 | |||
487 | |||
488 | |||
489 | |||
490 | { |
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491 | case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ |
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492 | |||
493 | |||
494 | &AcpiGbl_XPm1aStatus, |
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495 | &AcpiGbl_XPm1bStatus); |
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496 | break; |
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497 | |||
498 | |||
499 | |||
500 | |||
501 | |||
502 | &AcpiGbl_XPm1aEnable, |
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503 | &AcpiGbl_XPm1bEnable); |
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504 | break; |
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505 | |||
506 | |||
507 | |||
508 | |||
509 | |||
510 | &AcpiGbl_FADT.XPm1aControlBlock, |
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511 | &AcpiGbl_FADT.XPm1bControlBlock); |
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512 | |||
513 | |||
514 | * Zero the write-only bits. From the ACPI specification, "Hardware |
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515 | * Write-Only Bits": "Upon reads to registers with write-only bits, |
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516 | * software masks out all write-only bits." |
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517 | */ |
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518 | Value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS; |
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519 | break; |
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520 | |||
521 | |||
522 | |||
523 | |||
524 | |||
525 | break; |
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526 | |||
527 | |||
528 | |||
529 | |||
530 | |||
531 | break; |
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532 | |||
533 | |||
534 | |||
535 | |||
536 | |||
537 | break; |
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538 | |||
539 | |||
540 | |||
541 | ACPI_ERROR ((AE_INFO, "Unknown Register ID: 0x%X", |
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542 | RegisterId)); |
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543 | Status = AE_BAD_PARAMETER; |
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544 | break; |
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545 | } |
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546 | |||
547 | |||
548 | { |
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549 | *ReturnValue = Value; |
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550 | } |
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551 | |||
552 | |||
553 | } |
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554 | |||
555 | |||
556 | |||
557 | * |
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558 | * FUNCTION: AcpiHwRegisterWrite |
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559 | * |
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560 | * PARAMETERS: RegisterId - ACPI Register ID |
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561 | * Value - The value to write |
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562 | * |
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563 | * RETURN: Status |
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564 | * |
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565 | * DESCRIPTION: Write to the specified ACPI register |
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566 | * |
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567 | * NOTE: In accordance with the ACPI specification, this function automatically |
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568 | * preserves the value of the following bits, meaning that these bits cannot be |
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569 | * changed via this interface: |
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570 | * |
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571 | * PM1_CONTROL[0] = SCI_EN |
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572 | * PM1_CONTROL[9] |
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573 | * PM1_STATUS[11] |
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574 | * |
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575 | * ACPI References: |
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576 | * 1) Hardware Ignored Bits: When software writes to a register with ignored |
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577 | * bit fields, it preserves the ignored bit fields |
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578 | * 2) SCI_EN: OSPM always preserves this bit position |
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579 | * |
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580 | ******************************************************************************/ |
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581 | |||
582 | |||
583 | AcpiHwRegisterWrite ( |
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584 | UINT32 RegisterId, |
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585 | UINT32 Value) |
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586 | { |
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587 | ACPI_STATUS Status; |
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588 | UINT32 ReadValue; |
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589 | |||
590 | |||
591 | |||
592 | |||
593 | |||
594 | |||
595 | { |
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596 | case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ |
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597 | /* |
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598 | * Handle the "ignored" bit in PM1 Status. According to the ACPI |
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599 | * specification, ignored bits are to be preserved when writing. |
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600 | * Normally, this would mean a read/modify/write sequence. However, |
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601 | * preserving a bit in the status register is different. Writing a |
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602 | * one clears the status, and writing a zero preserves the status. |
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603 | * Therefore, we must always write zero to the ignored bit. |
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604 | * |
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605 | * This behavior is clarified in the ACPI 4.0 specification. |
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606 | */ |
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607 | Value &= ~ACPI_PM1_STATUS_PRESERVED_BITS; |
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608 | |||
609 | |||
610 | &AcpiGbl_XPm1aStatus, |
||
611 | &AcpiGbl_XPm1bStatus); |
||
612 | break; |
||
613 | |||
614 | |||
615 | |||
616 | |||
617 | |||
618 | &AcpiGbl_XPm1aEnable, |
||
619 | &AcpiGbl_XPm1bEnable); |
||
620 | break; |
||
621 | |||
622 | |||
623 | |||
624 | |||
625 | |||
626 | * Perform a read first to preserve certain bits (per ACPI spec) |
||
627 | * Note: This includes SCI_EN, we never want to change this bit |
||
628 | */ |
||
629 | Status = AcpiHwReadMultiple (&ReadValue, |
||
630 | &AcpiGbl_FADT.XPm1aControlBlock, |
||
631 | &AcpiGbl_FADT.XPm1bControlBlock); |
||
632 | if (ACPI_FAILURE (Status)) |
||
633 | { |
||
634 | goto Exit; |
||
635 | } |
||
636 | |||
637 | |||
638 | |||
639 | |||
640 | |||
641 | |||
642 | |||
643 | |||
644 | &AcpiGbl_FADT.XPm1aControlBlock, |
||
645 | &AcpiGbl_FADT.XPm1bControlBlock); |
||
646 | break; |
||
647 | |||
648 | |||
649 | |||
650 | |||
651 | |||
652 | * For control registers, all reserved bits must be preserved, |
||
653 | * as per the ACPI spec. |
||
654 | */ |
||
655 | Status = AcpiHwRead (&ReadValue, &AcpiGbl_FADT.XPm2ControlBlock); |
||
656 | if (ACPI_FAILURE (Status)) |
||
657 | { |
||
658 | goto Exit; |
||
659 | } |
||
660 | |||
661 | |||
662 | |||
663 | |||
664 | |||
665 | |||
666 | break; |
||
667 | |||
668 | |||
669 | |||
670 | |||
671 | |||
672 | break; |
||
673 | |||
674 | |||
675 | |||
676 | |||
677 | |||
678 | |||
679 | |||
680 | break; |
||
681 | |||
682 | |||
683 | |||
684 | ACPI_ERROR ((AE_INFO, "Unknown Register ID: 0x%X", |
||
685 | RegisterId)); |
||
686 | Status = AE_BAD_PARAMETER; |
||
687 | break; |
||
688 | } |
||
689 | |||
690 | |||
691 | return_ACPI_STATUS (Status); |
||
692 | } |
||
693 | |||
694 | |||
695 | |||
696 | * |
||
697 | * FUNCTION: AcpiHwReadMultiple |
||
698 | * |
||
699 | * PARAMETERS: Value - Where the register value is returned |
||
700 | * RegisterA - First ACPI register (required) |
||
701 | * RegisterB - Second ACPI register (optional) |
||
702 | * |
||
703 | * RETURN: Status |
||
704 | * |
||
705 | * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B) |
||
706 | * |
||
707 | ******************************************************************************/ |
||
708 | |||
709 | |||
710 | AcpiHwReadMultiple ( |
||
711 | UINT32 *Value, |
||
712 | ACPI_GENERIC_ADDRESS *RegisterA, |
||
713 | ACPI_GENERIC_ADDRESS *RegisterB) |
||
714 | { |
||
715 | UINT32 ValueA = 0; |
||
716 | UINT32 ValueB = 0; |
||
717 | ACPI_STATUS Status; |
||
718 | |||
719 | |||
720 | |||
721 | |||
722 | |||
723 | if (ACPI_FAILURE (Status)) |
||
724 | { |
||
725 | return (Status); |
||
726 | } |
||
727 | |||
728 | |||
729 | |||
730 | |||
731 | { |
||
732 | Status = AcpiHwRead (&ValueB, RegisterB); |
||
733 | if (ACPI_FAILURE (Status)) |
||
734 | { |
||
735 | return (Status); |
||
736 | } |
||
737 | } |
||
738 | |||
739 | |||
740 | * OR the two return values together. No shifting or masking is necessary, |
||
741 | * because of how the PM1 registers are defined in the ACPI specification: |
||
742 | * |
||
743 | * "Although the bits can be split between the two register blocks (each |
||
744 | * register block has a unique pointer within the FADT), the bit positions |
||
745 | * are maintained. The register block with unimplemented bits (that is, |
||
746 | * those implemented in the other register block) always returns zeros, |
||
747 | * and writes have no side effects" |
||
748 | */ |
||
749 | *Value = (ValueA | ValueB); |
||
750 | return (AE_OK); |
||
751 | } |
||
752 | |||
753 | |||
754 | |||
755 | * |
||
756 | * FUNCTION: AcpiHwWriteMultiple |
||
757 | * |
||
758 | * PARAMETERS: Value - The value to write |
||
759 | * RegisterA - First ACPI register (required) |
||
760 | * RegisterB - Second ACPI register (optional) |
||
761 | * |
||
762 | * RETURN: Status |
||
763 | * |
||
764 | * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B) |
||
765 | * |
||
766 | ******************************************************************************/ |
||
767 | |||
768 | |||
769 | AcpiHwWriteMultiple ( |
||
770 | UINT32 Value, |
||
771 | ACPI_GENERIC_ADDRESS *RegisterA, |
||
772 | ACPI_GENERIC_ADDRESS *RegisterB) |
||
773 | { |
||
774 | ACPI_STATUS Status; |
||
775 | |||
776 | |||
777 | |||
778 | |||
779 | |||
780 | if (ACPI_FAILURE (Status)) |
||
781 | { |
||
782 | return (Status); |
||
783 | } |
||
784 | |||
785 | |||
786 | * Second register is optional |
||
787 | * |
||
788 | * No bit shifting or clearing is necessary, because of how the PM1 |
||
789 | * registers are defined in the ACPI specification: |
||
790 | * |
||
791 | * "Although the bits can be split between the two register blocks (each |
||
792 | * register block has a unique pointer within the FADT), the bit positions |
||
793 | * are maintained. The register block with unimplemented bits (that is, |
||
794 | * those implemented in the other register block) always returns zeros, |
||
795 | * and writes have no side effects" |
||
796 | */ |
||
797 | if (RegisterB->Address) |
||
798 | { |
||
799 | Status = AcpiHwWrite (Value, RegisterB); |
||
800 | } |
||
801 | |||
802 | |||
803 | } |
||
804 |