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5221 | serge | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
6324 | serge | 2 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
5221 | serge | 3 | |
4 | This file is part of the GNU opcodes library. |
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5 | |||
6 | This library is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 3, or (at your option) |
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9 | any later version. |
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10 | |||
11 | It is distributed in the hope that it will be useful, but WITHOUT |
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12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
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13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
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14 | License for more details. |
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15 | |||
16 | You should have received a copy of the GNU General Public License |
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17 | along with this program; if not, write to the Free Software |
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18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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19 | MA 02110-1301, USA. */ |
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20 | |||
21 | |||
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) |
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23 | July 1988 |
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24 | modified by John Hassey (hassey@dg-rtp.dg.com) |
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25 | x86-64 support added by Jan Hubicka (jh@suse.cz) |
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26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ |
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27 | |||
28 | /* The main tables describing the instructions is essentially a copy |
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29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 |
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30 | Programmers Manual. Usually, there is a capital letter, followed |
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31 | by a small letter. The capital letter tell the addressing mode, |
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32 | and the small letter tells about the operand size. Refer to |
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33 | the Intel manual for details. */ |
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34 | |||
35 | #include "sysdep.h" |
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36 | #include "dis-asm.h" |
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37 | #include "opintl.h" |
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38 | #include "opcode/i386.h" |
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39 | #include "libiberty.h" |
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40 | |||
41 | #include |
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42 | |||
43 | static int print_insn (bfd_vma, disassemble_info *); |
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44 | static void dofloat (int); |
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45 | static void OP_ST (int, int); |
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46 | static void OP_STi (int, int); |
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47 | static int putop (const char *, int); |
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48 | static void oappend (const char *); |
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49 | static void append_seg (void); |
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50 | static void OP_indirE (int, int); |
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51 | static void print_operand_value (char *, int, bfd_vma); |
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52 | static void OP_E_register (int, int); |
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53 | static void OP_E_memory (int, int); |
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54 | static void print_displacement (char *, bfd_vma); |
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55 | static void OP_E (int, int); |
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56 | static void OP_G (int, int); |
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57 | static bfd_vma get64 (void); |
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58 | static bfd_signed_vma get32 (void); |
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59 | static bfd_signed_vma get32s (void); |
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60 | static int get16 (void); |
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61 | static void set_op (bfd_vma, int); |
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62 | static void OP_Skip_MODRM (int, int); |
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63 | static void OP_REG (int, int); |
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64 | static void OP_IMREG (int, int); |
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65 | static void OP_I (int, int); |
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66 | static void OP_I64 (int, int); |
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67 | static void OP_sI (int, int); |
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68 | static void OP_J (int, int); |
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69 | static void OP_SEG (int, int); |
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70 | static void OP_DIR (int, int); |
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71 | static void OP_OFF (int, int); |
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72 | static void OP_OFF64 (int, int); |
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73 | static void ptr_reg (int, int); |
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74 | static void OP_ESreg (int, int); |
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75 | static void OP_DSreg (int, int); |
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76 | static void OP_C (int, int); |
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77 | static void OP_D (int, int); |
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78 | static void OP_T (int, int); |
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79 | static void OP_R (int, int); |
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80 | static void OP_MMX (int, int); |
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81 | static void OP_XMM (int, int); |
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82 | static void OP_EM (int, int); |
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83 | static void OP_EX (int, int); |
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84 | static void OP_EMC (int,int); |
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85 | static void OP_MXC (int,int); |
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86 | static void OP_MS (int, int); |
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87 | static void OP_XS (int, int); |
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88 | static void OP_M (int, int); |
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89 | static void OP_VEX (int, int); |
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90 | static void OP_EX_Vex (int, int); |
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91 | static void OP_EX_VexW (int, int); |
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92 | static void OP_EX_VexImmW (int, int); |
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93 | static void OP_XMM_Vex (int, int); |
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94 | static void OP_XMM_VexW (int, int); |
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95 | static void OP_Rounding (int, int); |
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96 | static void OP_REG_VexI4 (int, int); |
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97 | static void PCLMUL_Fixup (int, int); |
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98 | static void VEXI4_Fixup (int, int); |
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99 | static void VZERO_Fixup (int, int); |
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100 | static void VCMP_Fixup (int, int); |
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101 | static void VPCMP_Fixup (int, int); |
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102 | static void OP_0f07 (int, int); |
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103 | static void OP_Monitor (int, int); |
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104 | static void OP_Mwait (int, int); |
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6324 | serge | 105 | static void OP_Mwaitx (int, int); |
5221 | serge | 106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); |
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108 | static void OP_3DNowSuffix (int, int); |
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109 | static void CMP_Fixup (int, int); |
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110 | static void BadOp (void); |
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111 | static void REP_Fixup (int, int); |
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112 | static void BND_Fixup (int, int); |
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113 | static void HLE_Fixup1 (int, int); |
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114 | static void HLE_Fixup2 (int, int); |
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115 | static void HLE_Fixup3 (int, int); |
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116 | static void CMPXCHG8B_Fixup (int, int); |
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117 | static void XMM_Fixup (int, int); |
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118 | static void CRC32_Fixup (int, int); |
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119 | static void FXSAVE_Fixup (int, int); |
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120 | static void OP_LWPCB_E (int, int); |
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121 | static void OP_LWP_E (int, int); |
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122 | static void OP_Vex_2src_1 (int, int); |
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123 | static void OP_Vex_2src_2 (int, int); |
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124 | |||
125 | static void MOVBE_Fixup (int, int); |
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126 | |||
127 | static void OP_Mask (int, int); |
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128 | |||
129 | struct dis_private { |
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130 | /* Points to first byte not fetched. */ |
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131 | bfd_byte *max_fetched; |
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132 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
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133 | bfd_vma insn_start; |
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134 | int orig_sizeflag; |
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6324 | serge | 135 | OPCODES_SIGJMP_BUF bailout; |
5221 | serge | 136 | }; |
137 | |||
138 | enum address_mode |
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139 | { |
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140 | mode_16bit, |
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141 | mode_32bit, |
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142 | mode_64bit |
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143 | }; |
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144 | |||
145 | enum address_mode address_mode; |
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146 | |||
147 | /* Flags for the prefixes for the current instruction. See below. */ |
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148 | static int prefixes; |
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149 | |||
150 | /* REX prefix the current instruction. See below. */ |
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151 | static int rex; |
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152 | /* Bits of REX we've already used. */ |
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153 | static int rex_used; |
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154 | /* REX bits in original REX prefix ignored. */ |
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155 | static int rex_ignored; |
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156 | /* Mark parts used in the REX prefix. When we are testing for |
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157 | empty prefix (for 8bit register REX extension), just mask it |
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158 | out. Otherwise test for REX bit is excuse for existence of REX |
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159 | only in case value is nonzero. */ |
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160 | #define USED_REX(value) \ |
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161 | { \ |
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162 | if (value) \ |
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163 | { \ |
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164 | if ((rex & value)) \ |
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165 | rex_used |= (value) | REX_OPCODE; \ |
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166 | } \ |
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167 | else \ |
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168 | rex_used |= REX_OPCODE; \ |
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169 | } |
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170 | |||
171 | /* Flags for prefixes which we somehow handled when printing the |
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172 | current instruction. */ |
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173 | static int used_prefixes; |
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174 | |||
175 | /* Flags stored in PREFIXES. */ |
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176 | #define PREFIX_REPZ 1 |
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177 | #define PREFIX_REPNZ 2 |
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178 | #define PREFIX_LOCK 4 |
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179 | #define PREFIX_CS 8 |
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180 | #define PREFIX_SS 0x10 |
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181 | #define PREFIX_DS 0x20 |
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182 | #define PREFIX_ES 0x40 |
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183 | #define PREFIX_FS 0x80 |
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184 | #define PREFIX_GS 0x100 |
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185 | #define PREFIX_DATA 0x200 |
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186 | #define PREFIX_ADDR 0x400 |
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187 | #define PREFIX_FWAIT 0x800 |
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188 | |||
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
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190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps |
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191 | on error. */ |
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192 | #define FETCH_DATA(info, addr) \ |
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193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
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194 | ? 1 : fetch_data ((info), (addr))) |
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195 | |||
196 | static int |
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197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
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198 | { |
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199 | int status; |
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200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
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201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
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202 | |||
203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
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204 | status = (*info->read_memory_func) (start, |
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205 | priv->max_fetched, |
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206 | addr - priv->max_fetched, |
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207 | info); |
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208 | else |
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209 | status = -1; |
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210 | if (status != 0) |
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211 | { |
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212 | /* If we did manage to read at least one byte, then |
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213 | print_insn_i386 will do something sensible. Otherwise, print |
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214 | an error. We do that here because this is where we know |
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215 | STATUS. */ |
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216 | if (priv->max_fetched == priv->the_buffer) |
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217 | (*info->memory_error_func) (status, start, info); |
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6324 | serge | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
5221 | serge | 219 | } |
220 | else |
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221 | priv->max_fetched = addr; |
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222 | return 1; |
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223 | } |
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224 | |||
6324 | serge | 225 | /* Possible values for prefix requirement. */ |
226 | #define PREFIX_IGNORED_SHIFT 16 |
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227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) |
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228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) |
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229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) |
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230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) |
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231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) |
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232 | |||
233 | /* Opcode prefixes. */ |
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234 | #define PREFIX_OPCODE (PREFIX_REPZ \ |
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235 | | PREFIX_REPNZ \ |
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236 | | PREFIX_DATA) |
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237 | |||
238 | /* Prefixes ignored. */ |
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239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ |
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240 | | PREFIX_IGNORED_REPNZ \ |
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241 | | PREFIX_IGNORED_DATA) |
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242 | |||
5221 | serge | 243 | #define XX { NULL, 0 } |
6324 | serge | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
5221 | serge | 245 | |
246 | #define Eb { OP_E, b_mode } |
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247 | #define Ebnd { OP_E, bnd_mode } |
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248 | #define EbS { OP_E, b_swap_mode } |
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249 | #define Ev { OP_E, v_mode } |
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250 | #define Ev_bnd { OP_E, v_bnd_mode } |
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251 | #define EvS { OP_E, v_swap_mode } |
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252 | #define Ed { OP_E, d_mode } |
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253 | #define Edq { OP_E, dq_mode } |
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254 | #define Edqw { OP_E, dqw_mode } |
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6324 | serge | 255 | #define EdqwS { OP_E, dqw_swap_mode } |
5221 | serge | 256 | #define Edqb { OP_E, dqb_mode } |
6324 | serge | 257 | #define Edb { OP_E, db_mode } |
258 | #define Edw { OP_E, dw_mode } |
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5221 | serge | 259 | #define Edqd { OP_E, dqd_mode } |
260 | #define Eq { OP_E, q_mode } |
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261 | #define indirEv { OP_indirE, stack_v_mode } |
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262 | #define indirEp { OP_indirE, f_mode } |
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263 | #define stackEv { OP_E, stack_v_mode } |
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264 | #define Em { OP_E, m_mode } |
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265 | #define Ew { OP_E, w_mode } |
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266 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ |
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267 | #define Ma { OP_M, a_mode } |
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268 | #define Mb { OP_M, b_mode } |
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269 | #define Md { OP_M, d_mode } |
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270 | #define Mo { OP_M, o_mode } |
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271 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
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272 | #define Mq { OP_M, q_mode } |
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273 | #define Mx { OP_M, x_mode } |
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274 | #define Mxmm { OP_M, xmm_mode } |
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275 | #define Gb { OP_G, b_mode } |
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276 | #define Gbnd { OP_G, bnd_mode } |
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277 | #define Gv { OP_G, v_mode } |
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278 | #define Gd { OP_G, d_mode } |
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279 | #define Gdq { OP_G, dq_mode } |
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280 | #define Gm { OP_G, m_mode } |
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281 | #define Gw { OP_G, w_mode } |
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282 | #define Rd { OP_R, d_mode } |
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283 | #define Rdq { OP_R, dq_mode } |
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284 | #define Rm { OP_R, m_mode } |
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285 | #define Ib { OP_I, b_mode } |
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286 | #define sIb { OP_sI, b_mode } /* sign extened byte */ |
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287 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
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288 | #define Iv { OP_I, v_mode } |
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289 | #define sIv { OP_sI, v_mode } |
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290 | #define Iq { OP_I, q_mode } |
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291 | #define Iv64 { OP_I64, v_mode } |
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292 | #define Iw { OP_I, w_mode } |
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293 | #define I1 { OP_I, const_1_mode } |
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294 | #define Jb { OP_J, b_mode } |
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295 | #define Jv { OP_J, v_mode } |
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296 | #define Cm { OP_C, m_mode } |
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297 | #define Dm { OP_D, m_mode } |
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298 | #define Td { OP_T, d_mode } |
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299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
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300 | |||
301 | #define RMeAX { OP_REG, eAX_reg } |
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302 | #define RMeBX { OP_REG, eBX_reg } |
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303 | #define RMeCX { OP_REG, eCX_reg } |
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304 | #define RMeDX { OP_REG, eDX_reg } |
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305 | #define RMeSP { OP_REG, eSP_reg } |
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306 | #define RMeBP { OP_REG, eBP_reg } |
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307 | #define RMeSI { OP_REG, eSI_reg } |
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308 | #define RMeDI { OP_REG, eDI_reg } |
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309 | #define RMrAX { OP_REG, rAX_reg } |
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310 | #define RMrBX { OP_REG, rBX_reg } |
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311 | #define RMrCX { OP_REG, rCX_reg } |
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312 | #define RMrDX { OP_REG, rDX_reg } |
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313 | #define RMrSP { OP_REG, rSP_reg } |
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314 | #define RMrBP { OP_REG, rBP_reg } |
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315 | #define RMrSI { OP_REG, rSI_reg } |
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316 | #define RMrDI { OP_REG, rDI_reg } |
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317 | #define RMAL { OP_REG, al_reg } |
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318 | #define RMCL { OP_REG, cl_reg } |
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319 | #define RMDL { OP_REG, dl_reg } |
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320 | #define RMBL { OP_REG, bl_reg } |
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321 | #define RMAH { OP_REG, ah_reg } |
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322 | #define RMCH { OP_REG, ch_reg } |
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323 | #define RMDH { OP_REG, dh_reg } |
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324 | #define RMBH { OP_REG, bh_reg } |
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325 | #define RMAX { OP_REG, ax_reg } |
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326 | #define RMDX { OP_REG, dx_reg } |
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327 | |||
328 | #define eAX { OP_IMREG, eAX_reg } |
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329 | #define eBX { OP_IMREG, eBX_reg } |
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330 | #define eCX { OP_IMREG, eCX_reg } |
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331 | #define eDX { OP_IMREG, eDX_reg } |
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332 | #define eSP { OP_IMREG, eSP_reg } |
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333 | #define eBP { OP_IMREG, eBP_reg } |
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334 | #define eSI { OP_IMREG, eSI_reg } |
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335 | #define eDI { OP_IMREG, eDI_reg } |
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336 | #define AL { OP_IMREG, al_reg } |
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337 | #define CL { OP_IMREG, cl_reg } |
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338 | #define DL { OP_IMREG, dl_reg } |
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339 | #define BL { OP_IMREG, bl_reg } |
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340 | #define AH { OP_IMREG, ah_reg } |
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341 | #define CH { OP_IMREG, ch_reg } |
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342 | #define DH { OP_IMREG, dh_reg } |
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343 | #define BH { OP_IMREG, bh_reg } |
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344 | #define AX { OP_IMREG, ax_reg } |
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345 | #define DX { OP_IMREG, dx_reg } |
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346 | #define zAX { OP_IMREG, z_mode_ax_reg } |
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347 | #define indirDX { OP_IMREG, indir_dx_reg } |
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348 | |||
349 | #define Sw { OP_SEG, w_mode } |
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350 | #define Sv { OP_SEG, v_mode } |
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351 | #define Ap { OP_DIR, 0 } |
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352 | #define Ob { OP_OFF64, b_mode } |
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353 | #define Ov { OP_OFF64, v_mode } |
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354 | #define Xb { OP_DSreg, eSI_reg } |
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355 | #define Xv { OP_DSreg, eSI_reg } |
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356 | #define Xz { OP_DSreg, eSI_reg } |
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357 | #define Yb { OP_ESreg, eDI_reg } |
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358 | #define Yv { OP_ESreg, eDI_reg } |
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359 | #define DSBX { OP_DSreg, eBX_reg } |
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360 | |||
361 | #define es { OP_REG, es_reg } |
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362 | #define ss { OP_REG, ss_reg } |
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363 | #define cs { OP_REG, cs_reg } |
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364 | #define ds { OP_REG, ds_reg } |
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365 | #define fs { OP_REG, fs_reg } |
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366 | #define gs { OP_REG, gs_reg } |
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367 | |||
368 | #define MX { OP_MMX, 0 } |
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369 | #define XM { OP_XMM, 0 } |
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370 | #define XMScalar { OP_XMM, scalar_mode } |
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371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
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372 | #define XMM { OP_XMM, xmm_mode } |
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373 | #define XMxmmq { OP_XMM, xmmq_mode } |
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374 | #define EM { OP_EM, v_mode } |
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375 | #define EMS { OP_EM, v_swap_mode } |
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376 | #define EMd { OP_EM, d_mode } |
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377 | #define EMx { OP_EM, x_mode } |
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378 | #define EXw { OP_EX, w_mode } |
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379 | #define EXd { OP_EX, d_mode } |
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380 | #define EXdScalar { OP_EX, d_scalar_mode } |
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381 | #define EXdS { OP_EX, d_swap_mode } |
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382 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
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383 | #define EXq { OP_EX, q_mode } |
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384 | #define EXqScalar { OP_EX, q_scalar_mode } |
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385 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } |
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386 | #define EXqS { OP_EX, q_swap_mode } |
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387 | #define EXx { OP_EX, x_mode } |
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388 | #define EXxS { OP_EX, x_swap_mode } |
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389 | #define EXxmm { OP_EX, xmm_mode } |
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390 | #define EXymm { OP_EX, ymm_mode } |
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391 | #define EXxmmq { OP_EX, xmmq_mode } |
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392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
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393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
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394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } |
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395 | #define EXxmm_md { OP_EX, xmm_md_mode } |
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396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } |
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397 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
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398 | #define EXxmmdw { OP_EX, xmmdw_mode } |
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399 | #define EXxmmqd { OP_EX, xmmqd_mode } |
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400 | #define EXymmq { OP_EX, ymmq_mode } |
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401 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
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402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
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403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
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404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } |
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405 | #define MS { OP_MS, v_mode } |
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406 | #define XS { OP_XS, v_mode } |
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407 | #define EMCq { OP_EMC, q_mode } |
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408 | #define MXC { OP_MXC, 0 } |
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409 | #define OPSUF { OP_3DNowSuffix, 0 } |
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410 | #define CMP { CMP_Fixup, 0 } |
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411 | #define XMM0 { XMM_Fixup, 0 } |
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412 | #define FXSAVE { FXSAVE_Fixup, 0 } |
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413 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
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414 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } |
||
415 | |||
416 | #define Vex { OP_VEX, vex_mode } |
||
417 | #define VexScalar { OP_VEX, vex_scalar_mode } |
||
418 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
||
419 | #define Vex128 { OP_VEX, vex128_mode } |
||
420 | #define Vex256 { OP_VEX, vex256_mode } |
||
421 | #define VexGdq { OP_VEX, dq_mode } |
||
422 | #define VexI4 { VEXI4_Fixup, 0} |
||
423 | #define EXdVex { OP_EX_Vex, d_mode } |
||
424 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
||
425 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
||
426 | #define EXqVex { OP_EX_Vex, q_mode } |
||
427 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
||
428 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
||
429 | #define EXVexW { OP_EX_VexW, x_mode } |
||
430 | #define EXdVexW { OP_EX_VexW, d_mode } |
||
431 | #define EXqVexW { OP_EX_VexW, q_mode } |
||
432 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
||
433 | #define XMVex { OP_XMM_Vex, 0 } |
||
434 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
||
435 | #define XMVexW { OP_XMM_VexW, 0 } |
||
436 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
||
437 | #define PCLMUL { PCLMUL_Fixup, 0 } |
||
438 | #define VZERO { VZERO_Fixup, 0 } |
||
439 | #define VCMP { VCMP_Fixup, 0 } |
||
440 | #define VPCMP { VPCMP_Fixup, 0 } |
||
441 | |||
442 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } |
||
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
||
444 | |||
445 | #define XMask { OP_Mask, mask_mode } |
||
446 | #define MaskG { OP_G, mask_mode } |
||
447 | #define MaskE { OP_E, mask_mode } |
||
6324 | serge | 448 | #define MaskBDE { OP_E, mask_bd_mode } |
5221 | serge | 449 | #define MaskR { OP_R, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } |
||
451 | |||
452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
||
6324 | serge | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
5221 | serge | 454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
6324 | serge | 455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
5221 | serge | 456 | |
457 | /* Used handle "rep" prefix for string instructions. */ |
||
458 | #define Xbr { REP_Fixup, eSI_reg } |
||
459 | #define Xvr { REP_Fixup, eSI_reg } |
||
460 | #define Ybr { REP_Fixup, eDI_reg } |
||
461 | #define Yvr { REP_Fixup, eDI_reg } |
||
462 | #define Yzr { REP_Fixup, eDI_reg } |
||
463 | #define indirDXr { REP_Fixup, indir_dx_reg } |
||
464 | #define ALr { REP_Fixup, al_reg } |
||
465 | #define eAXr { REP_Fixup, eAX_reg } |
||
466 | |||
467 | /* Used handle HLE prefix for lockable instructions. */ |
||
468 | #define Ebh1 { HLE_Fixup1, b_mode } |
||
469 | #define Evh1 { HLE_Fixup1, v_mode } |
||
470 | #define Ebh2 { HLE_Fixup2, b_mode } |
||
471 | #define Evh2 { HLE_Fixup2, v_mode } |
||
472 | #define Ebh3 { HLE_Fixup3, b_mode } |
||
473 | #define Evh3 { HLE_Fixup3, v_mode } |
||
474 | |||
475 | #define BND { BND_Fixup, 0 } |
||
476 | |||
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
||
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } |
||
479 | |||
480 | /* bits in sizeflag */ |
||
481 | #define SUFFIX_ALWAYS 4 |
||
482 | #define AFLAG 2 |
||
483 | #define DFLAG 1 |
||
484 | |||
485 | enum |
||
486 | { |
||
487 | /* byte operand */ |
||
488 | b_mode = 1, |
||
489 | /* byte operand with operand swapped */ |
||
490 | b_swap_mode, |
||
491 | /* byte operand, sign extend like 'T' suffix */ |
||
492 | b_T_mode, |
||
493 | /* operand size depends on prefixes */ |
||
494 | v_mode, |
||
495 | /* operand size depends on prefixes with operand swapped */ |
||
496 | v_swap_mode, |
||
497 | /* word operand */ |
||
498 | w_mode, |
||
499 | /* double word operand */ |
||
500 | d_mode, |
||
501 | /* double word operand with operand swapped */ |
||
502 | d_swap_mode, |
||
503 | /* quad word operand */ |
||
504 | q_mode, |
||
505 | /* quad word operand with operand swapped */ |
||
506 | q_swap_mode, |
||
507 | /* ten-byte operand */ |
||
508 | t_mode, |
||
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
||
510 | broadcast enabled. */ |
||
511 | x_mode, |
||
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
||
513 | evex_x_gscat_mode, |
||
514 | /* Similar to x_mode, but with disabled broadcast. */ |
||
515 | evex_x_nobcst_mode, |
||
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast |
||
517 | in EVEX. */ |
||
518 | x_swap_mode, |
||
519 | /* 16-byte XMM operand */ |
||
520 | xmm_mode, |
||
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
||
522 | memory operand (depending on vector length). Broadcast isn't |
||
523 | allowed. */ |
||
524 | xmmq_mode, |
||
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
||
526 | evex_half_bcst_xmmq_mode, |
||
527 | /* XMM register or byte memory operand */ |
||
528 | xmm_mb_mode, |
||
529 | /* XMM register or word memory operand */ |
||
530 | xmm_mw_mode, |
||
531 | /* XMM register or double word memory operand */ |
||
532 | xmm_md_mode, |
||
533 | /* XMM register or quad word memory operand */ |
||
534 | xmm_mq_mode, |
||
535 | /* XMM register or double/quad word memory operand, depending on |
||
536 | VEX.W. */ |
||
537 | xmm_mdq_mode, |
||
538 | /* 16-byte XMM, word, double word or quad word operand. */ |
||
539 | xmmdw_mode, |
||
540 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
||
541 | xmmqd_mode, |
||
542 | /* 32-byte YMM operand */ |
||
543 | ymm_mode, |
||
544 | /* quad word, ymmword or zmmword memory operand. */ |
||
545 | ymmq_mode, |
||
546 | /* 32-byte YMM or 16-byte word operand */ |
||
547 | ymmxmm_mode, |
||
548 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
||
549 | m_mode, |
||
550 | /* pair of v_mode operands */ |
||
551 | a_mode, |
||
552 | cond_jump_mode, |
||
553 | loop_jcxz_mode, |
||
554 | v_bnd_mode, |
||
555 | /* operand size depends on REX prefixes. */ |
||
556 | dq_mode, |
||
557 | /* registers like dq_mode, memory like w_mode. */ |
||
558 | dqw_mode, |
||
6324 | serge | 559 | dqw_swap_mode, |
5221 | serge | 560 | bnd_mode, |
561 | /* 4- or 6-byte pointer operand */ |
||
562 | f_mode, |
||
563 | const_1_mode, |
||
564 | /* v_mode for stack-related opcodes. */ |
||
565 | stack_v_mode, |
||
566 | /* non-quad operand size depends on prefixes */ |
||
567 | z_mode, |
||
568 | /* 16-byte operand */ |
||
569 | o_mode, |
||
570 | /* registers like dq_mode, memory like b_mode. */ |
||
571 | dqb_mode, |
||
6324 | serge | 572 | /* registers like d_mode, memory like b_mode. */ |
573 | db_mode, |
||
574 | /* registers like d_mode, memory like w_mode. */ |
||
575 | dw_mode, |
||
5221 | serge | 576 | /* registers like dq_mode, memory like d_mode. */ |
577 | dqd_mode, |
||
578 | /* normal vex mode */ |
||
579 | vex_mode, |
||
580 | /* 128bit vex mode */ |
||
581 | vex128_mode, |
||
582 | /* 256bit vex mode */ |
||
583 | vex256_mode, |
||
584 | /* operand size depends on the VEX.W bit. */ |
||
585 | vex_w_dq_mode, |
||
586 | |||
587 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
||
588 | vex_vsib_d_w_dq_mode, |
||
6324 | serge | 589 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
590 | vex_vsib_d_w_d_mode, |
||
5221 | serge | 591 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
592 | vex_vsib_q_w_dq_mode, |
||
6324 | serge | 593 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
594 | vex_vsib_q_w_d_mode, |
||
5221 | serge | 595 | |
596 | /* scalar, ignore vector length. */ |
||
597 | scalar_mode, |
||
598 | /* like d_mode, ignore vector length. */ |
||
599 | d_scalar_mode, |
||
600 | /* like d_swap_mode, ignore vector length. */ |
||
601 | d_scalar_swap_mode, |
||
602 | /* like q_mode, ignore vector length. */ |
||
603 | q_scalar_mode, |
||
604 | /* like q_swap_mode, ignore vector length. */ |
||
605 | q_scalar_swap_mode, |
||
606 | /* like vex_mode, ignore vector length. */ |
||
607 | vex_scalar_mode, |
||
608 | /* like vex_w_dq_mode, ignore vector length. */ |
||
609 | vex_scalar_w_dq_mode, |
||
610 | |||
611 | /* Static rounding. */ |
||
612 | evex_rounding_mode, |
||
613 | /* Supress all exceptions. */ |
||
614 | evex_sae_mode, |
||
615 | |||
616 | /* Mask register operand. */ |
||
617 | mask_mode, |
||
6324 | serge | 618 | /* Mask register operand. */ |
619 | mask_bd_mode, |
||
5221 | serge | 620 | |
621 | es_reg, |
||
622 | cs_reg, |
||
623 | ss_reg, |
||
624 | ds_reg, |
||
625 | fs_reg, |
||
626 | gs_reg, |
||
627 | |||
628 | eAX_reg, |
||
629 | eCX_reg, |
||
630 | eDX_reg, |
||
631 | eBX_reg, |
||
632 | eSP_reg, |
||
633 | eBP_reg, |
||
634 | eSI_reg, |
||
635 | eDI_reg, |
||
636 | |||
637 | al_reg, |
||
638 | cl_reg, |
||
639 | dl_reg, |
||
640 | bl_reg, |
||
641 | ah_reg, |
||
642 | ch_reg, |
||
643 | dh_reg, |
||
644 | bh_reg, |
||
645 | |||
646 | ax_reg, |
||
647 | cx_reg, |
||
648 | dx_reg, |
||
649 | bx_reg, |
||
650 | sp_reg, |
||
651 | bp_reg, |
||
652 | si_reg, |
||
653 | di_reg, |
||
654 | |||
655 | rAX_reg, |
||
656 | rCX_reg, |
||
657 | rDX_reg, |
||
658 | rBX_reg, |
||
659 | rSP_reg, |
||
660 | rBP_reg, |
||
661 | rSI_reg, |
||
662 | rDI_reg, |
||
663 | |||
664 | z_mode_ax_reg, |
||
665 | indir_dx_reg |
||
666 | }; |
||
667 | |||
668 | enum |
||
669 | { |
||
670 | FLOATCODE = 1, |
||
671 | USE_REG_TABLE, |
||
672 | USE_MOD_TABLE, |
||
673 | USE_RM_TABLE, |
||
674 | USE_PREFIX_TABLE, |
||
675 | USE_X86_64_TABLE, |
||
676 | USE_3BYTE_TABLE, |
||
677 | USE_XOP_8F_TABLE, |
||
678 | USE_VEX_C4_TABLE, |
||
679 | USE_VEX_C5_TABLE, |
||
680 | USE_VEX_LEN_TABLE, |
||
681 | USE_VEX_W_TABLE, |
||
682 | USE_EVEX_TABLE |
||
683 | }; |
||
684 | |||
6324 | serge | 685 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
5221 | serge | 686 | |
6324 | serge | 687 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
688 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P |
||
5221 | serge | 689 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
690 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
||
691 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
||
692 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
||
693 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
||
694 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
||
6324 | serge | 695 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
5221 | serge | 696 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
697 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
||
698 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
||
699 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) |
||
700 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
||
701 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
||
702 | |||
703 | enum |
||
704 | { |
||
705 | REG_80 = 0, |
||
706 | REG_81, |
||
707 | REG_82, |
||
708 | REG_8F, |
||
709 | REG_C0, |
||
710 | REG_C1, |
||
711 | REG_C6, |
||
712 | REG_C7, |
||
713 | REG_D0, |
||
714 | REG_D1, |
||
715 | REG_D2, |
||
716 | REG_D3, |
||
717 | REG_F6, |
||
718 | REG_F7, |
||
719 | REG_FE, |
||
720 | REG_FF, |
||
721 | REG_0F00, |
||
722 | REG_0F01, |
||
723 | REG_0F0D, |
||
724 | REG_0F18, |
||
725 | REG_0F71, |
||
726 | REG_0F72, |
||
727 | REG_0F73, |
||
728 | REG_0FA6, |
||
729 | REG_0FA7, |
||
730 | REG_0FAE, |
||
731 | REG_0FBA, |
||
732 | REG_0FC7, |
||
733 | REG_VEX_0F71, |
||
734 | REG_VEX_0F72, |
||
735 | REG_VEX_0F73, |
||
736 | REG_VEX_0FAE, |
||
737 | REG_VEX_0F38F3, |
||
738 | REG_XOP_LWPCB, |
||
739 | REG_XOP_LWP, |
||
740 | REG_XOP_TBM_01, |
||
741 | REG_XOP_TBM_02, |
||
742 | |||
6324 | serge | 743 | REG_EVEX_0F71, |
5221 | serge | 744 | REG_EVEX_0F72, |
745 | REG_EVEX_0F73, |
||
746 | REG_EVEX_0F38C6, |
||
747 | REG_EVEX_0F38C7 |
||
748 | }; |
||
749 | |||
750 | enum |
||
751 | { |
||
752 | MOD_8D = 0, |
||
753 | MOD_C6_REG_7, |
||
754 | MOD_C7_REG_7, |
||
6324 | serge | 755 | MOD_FF_REG_3, |
756 | MOD_FF_REG_5, |
||
5221 | serge | 757 | MOD_0F01_REG_0, |
758 | MOD_0F01_REG_1, |
||
759 | MOD_0F01_REG_2, |
||
760 | MOD_0F01_REG_3, |
||
6324 | serge | 761 | MOD_0F01_REG_5, |
5221 | serge | 762 | MOD_0F01_REG_7, |
763 | MOD_0F12_PREFIX_0, |
||
764 | MOD_0F13, |
||
765 | MOD_0F16_PREFIX_0, |
||
766 | MOD_0F17, |
||
767 | MOD_0F18_REG_0, |
||
768 | MOD_0F18_REG_1, |
||
769 | MOD_0F18_REG_2, |
||
770 | MOD_0F18_REG_3, |
||
771 | MOD_0F18_REG_4, |
||
772 | MOD_0F18_REG_5, |
||
773 | MOD_0F18_REG_6, |
||
774 | MOD_0F18_REG_7, |
||
775 | MOD_0F1A_PREFIX_0, |
||
776 | MOD_0F1B_PREFIX_0, |
||
777 | MOD_0F1B_PREFIX_1, |
||
778 | MOD_0F24, |
||
779 | MOD_0F26, |
||
780 | MOD_0F2B_PREFIX_0, |
||
781 | MOD_0F2B_PREFIX_1, |
||
782 | MOD_0F2B_PREFIX_2, |
||
783 | MOD_0F2B_PREFIX_3, |
||
784 | MOD_0F51, |
||
785 | MOD_0F71_REG_2, |
||
786 | MOD_0F71_REG_4, |
||
787 | MOD_0F71_REG_6, |
||
788 | MOD_0F72_REG_2, |
||
789 | MOD_0F72_REG_4, |
||
790 | MOD_0F72_REG_6, |
||
791 | MOD_0F73_REG_2, |
||
792 | MOD_0F73_REG_3, |
||
793 | MOD_0F73_REG_6, |
||
794 | MOD_0F73_REG_7, |
||
795 | MOD_0FAE_REG_0, |
||
796 | MOD_0FAE_REG_1, |
||
797 | MOD_0FAE_REG_2, |
||
798 | MOD_0FAE_REG_3, |
||
799 | MOD_0FAE_REG_4, |
||
800 | MOD_0FAE_REG_5, |
||
801 | MOD_0FAE_REG_6, |
||
802 | MOD_0FAE_REG_7, |
||
803 | MOD_0FB2, |
||
804 | MOD_0FB4, |
||
805 | MOD_0FB5, |
||
6324 | serge | 806 | MOD_0FC3, |
807 | MOD_0FC7_REG_3, |
||
808 | MOD_0FC7_REG_4, |
||
809 | MOD_0FC7_REG_5, |
||
5221 | serge | 810 | MOD_0FC7_REG_6, |
811 | MOD_0FC7_REG_7, |
||
812 | MOD_0FD7, |
||
813 | MOD_0FE7_PREFIX_2, |
||
814 | MOD_0FF0_PREFIX_3, |
||
815 | MOD_0F382A_PREFIX_2, |
||
816 | MOD_62_32BIT, |
||
817 | MOD_C4_32BIT, |
||
818 | MOD_C5_32BIT, |
||
819 | MOD_VEX_0F12_PREFIX_0, |
||
820 | MOD_VEX_0F13, |
||
821 | MOD_VEX_0F16_PREFIX_0, |
||
822 | MOD_VEX_0F17, |
||
823 | MOD_VEX_0F2B, |
||
6324 | serge | 824 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
825 | MOD_VEX_W_1_0F41_P_0_LEN_1, |
||
826 | MOD_VEX_W_0_0F41_P_2_LEN_1, |
||
827 | MOD_VEX_W_1_0F41_P_2_LEN_1, |
||
828 | MOD_VEX_W_0_0F42_P_0_LEN_1, |
||
829 | MOD_VEX_W_1_0F42_P_0_LEN_1, |
||
830 | MOD_VEX_W_0_0F42_P_2_LEN_1, |
||
831 | MOD_VEX_W_1_0F42_P_2_LEN_1, |
||
832 | MOD_VEX_W_0_0F44_P_0_LEN_1, |
||
833 | MOD_VEX_W_1_0F44_P_0_LEN_1, |
||
834 | MOD_VEX_W_0_0F44_P_2_LEN_1, |
||
835 | MOD_VEX_W_1_0F44_P_2_LEN_1, |
||
836 | MOD_VEX_W_0_0F45_P_0_LEN_1, |
||
837 | MOD_VEX_W_1_0F45_P_0_LEN_1, |
||
838 | MOD_VEX_W_0_0F45_P_2_LEN_1, |
||
839 | MOD_VEX_W_1_0F45_P_2_LEN_1, |
||
840 | MOD_VEX_W_0_0F46_P_0_LEN_1, |
||
841 | MOD_VEX_W_1_0F46_P_0_LEN_1, |
||
842 | MOD_VEX_W_0_0F46_P_2_LEN_1, |
||
843 | MOD_VEX_W_1_0F46_P_2_LEN_1, |
||
844 | MOD_VEX_W_0_0F47_P_0_LEN_1, |
||
845 | MOD_VEX_W_1_0F47_P_0_LEN_1, |
||
846 | MOD_VEX_W_0_0F47_P_2_LEN_1, |
||
847 | MOD_VEX_W_1_0F47_P_2_LEN_1, |
||
848 | MOD_VEX_W_0_0F4A_P_0_LEN_1, |
||
849 | MOD_VEX_W_1_0F4A_P_0_LEN_1, |
||
850 | MOD_VEX_W_0_0F4A_P_2_LEN_1, |
||
851 | MOD_VEX_W_1_0F4A_P_2_LEN_1, |
||
852 | MOD_VEX_W_0_0F4B_P_0_LEN_1, |
||
853 | MOD_VEX_W_1_0F4B_P_0_LEN_1, |
||
854 | MOD_VEX_W_0_0F4B_P_2_LEN_1, |
||
5221 | serge | 855 | MOD_VEX_0F50, |
856 | MOD_VEX_0F71_REG_2, |
||
857 | MOD_VEX_0F71_REG_4, |
||
858 | MOD_VEX_0F71_REG_6, |
||
859 | MOD_VEX_0F72_REG_2, |
||
860 | MOD_VEX_0F72_REG_4, |
||
861 | MOD_VEX_0F72_REG_6, |
||
862 | MOD_VEX_0F73_REG_2, |
||
863 | MOD_VEX_0F73_REG_3, |
||
864 | MOD_VEX_0F73_REG_6, |
||
865 | MOD_VEX_0F73_REG_7, |
||
6324 | serge | 866 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
867 | MOD_VEX_W_1_0F91_P_0_LEN_0, |
||
868 | MOD_VEX_W_0_0F91_P_2_LEN_0, |
||
869 | MOD_VEX_W_1_0F91_P_2_LEN_0, |
||
870 | MOD_VEX_W_0_0F92_P_0_LEN_0, |
||
871 | MOD_VEX_W_0_0F92_P_2_LEN_0, |
||
872 | MOD_VEX_W_0_0F92_P_3_LEN_0, |
||
873 | MOD_VEX_W_1_0F92_P_3_LEN_0, |
||
874 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
||
875 | MOD_VEX_W_0_0F93_P_2_LEN_0, |
||
876 | MOD_VEX_W_0_0F93_P_3_LEN_0, |
||
877 | MOD_VEX_W_1_0F93_P_3_LEN_0, |
||
878 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
||
879 | MOD_VEX_W_1_0F98_P_0_LEN_0, |
||
880 | MOD_VEX_W_0_0F98_P_2_LEN_0, |
||
881 | MOD_VEX_W_1_0F98_P_2_LEN_0, |
||
882 | MOD_VEX_W_0_0F99_P_0_LEN_0, |
||
883 | MOD_VEX_W_1_0F99_P_0_LEN_0, |
||
884 | MOD_VEX_W_0_0F99_P_2_LEN_0, |
||
885 | MOD_VEX_W_1_0F99_P_2_LEN_0, |
||
5221 | serge | 886 | MOD_VEX_0FAE_REG_2, |
887 | MOD_VEX_0FAE_REG_3, |
||
888 | MOD_VEX_0FD7_PREFIX_2, |
||
889 | MOD_VEX_0FE7_PREFIX_2, |
||
890 | MOD_VEX_0FF0_PREFIX_3, |
||
891 | MOD_VEX_0F381A_PREFIX_2, |
||
892 | MOD_VEX_0F382A_PREFIX_2, |
||
893 | MOD_VEX_0F382C_PREFIX_2, |
||
894 | MOD_VEX_0F382D_PREFIX_2, |
||
895 | MOD_VEX_0F382E_PREFIX_2, |
||
896 | MOD_VEX_0F382F_PREFIX_2, |
||
897 | MOD_VEX_0F385A_PREFIX_2, |
||
898 | MOD_VEX_0F388C_PREFIX_2, |
||
899 | MOD_VEX_0F388E_PREFIX_2, |
||
6324 | serge | 900 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
901 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, |
||
902 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, |
||
903 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, |
||
904 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, |
||
905 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, |
||
906 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, |
||
907 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, |
||
5221 | serge | 908 | |
909 | MOD_EVEX_0F10_PREFIX_1, |
||
910 | MOD_EVEX_0F10_PREFIX_3, |
||
911 | MOD_EVEX_0F11_PREFIX_1, |
||
912 | MOD_EVEX_0F11_PREFIX_3, |
||
913 | MOD_EVEX_0F12_PREFIX_0, |
||
914 | MOD_EVEX_0F16_PREFIX_0, |
||
915 | MOD_EVEX_0F38C6_REG_1, |
||
916 | MOD_EVEX_0F38C6_REG_2, |
||
917 | MOD_EVEX_0F38C6_REG_5, |
||
918 | MOD_EVEX_0F38C6_REG_6, |
||
919 | MOD_EVEX_0F38C7_REG_1, |
||
920 | MOD_EVEX_0F38C7_REG_2, |
||
921 | MOD_EVEX_0F38C7_REG_5, |
||
922 | MOD_EVEX_0F38C7_REG_6 |
||
923 | }; |
||
924 | |||
925 | enum |
||
926 | { |
||
927 | RM_C6_REG_7 = 0, |
||
928 | RM_C7_REG_7, |
||
929 | RM_0F01_REG_0, |
||
930 | RM_0F01_REG_1, |
||
931 | RM_0F01_REG_2, |
||
932 | RM_0F01_REG_3, |
||
6324 | serge | 933 | RM_0F01_REG_5, |
5221 | serge | 934 | RM_0F01_REG_7, |
935 | RM_0FAE_REG_5, |
||
936 | RM_0FAE_REG_6, |
||
937 | RM_0FAE_REG_7 |
||
938 | }; |
||
939 | |||
940 | enum |
||
941 | { |
||
942 | PREFIX_90 = 0, |
||
943 | PREFIX_0F10, |
||
944 | PREFIX_0F11, |
||
945 | PREFIX_0F12, |
||
946 | PREFIX_0F16, |
||
947 | PREFIX_0F1A, |
||
948 | PREFIX_0F1B, |
||
949 | PREFIX_0F2A, |
||
950 | PREFIX_0F2B, |
||
951 | PREFIX_0F2C, |
||
952 | PREFIX_0F2D, |
||
953 | PREFIX_0F2E, |
||
954 | PREFIX_0F2F, |
||
955 | PREFIX_0F51, |
||
956 | PREFIX_0F52, |
||
957 | PREFIX_0F53, |
||
958 | PREFIX_0F58, |
||
959 | PREFIX_0F59, |
||
960 | PREFIX_0F5A, |
||
961 | PREFIX_0F5B, |
||
962 | PREFIX_0F5C, |
||
963 | PREFIX_0F5D, |
||
964 | PREFIX_0F5E, |
||
965 | PREFIX_0F5F, |
||
966 | PREFIX_0F60, |
||
967 | PREFIX_0F61, |
||
968 | PREFIX_0F62, |
||
969 | PREFIX_0F6C, |
||
970 | PREFIX_0F6D, |
||
971 | PREFIX_0F6F, |
||
972 | PREFIX_0F70, |
||
973 | PREFIX_0F73_REG_3, |
||
974 | PREFIX_0F73_REG_7, |
||
975 | PREFIX_0F78, |
||
976 | PREFIX_0F79, |
||
977 | PREFIX_0F7C, |
||
978 | PREFIX_0F7D, |
||
979 | PREFIX_0F7E, |
||
980 | PREFIX_0F7F, |
||
981 | PREFIX_0FAE_REG_0, |
||
982 | PREFIX_0FAE_REG_1, |
||
983 | PREFIX_0FAE_REG_2, |
||
984 | PREFIX_0FAE_REG_3, |
||
6324 | serge | 985 | PREFIX_0FAE_REG_6, |
986 | PREFIX_0FAE_REG_7, |
||
987 | PREFIX_RM_0_0FAE_REG_7, |
||
5221 | serge | 988 | PREFIX_0FB8, |
989 | PREFIX_0FBC, |
||
990 | PREFIX_0FBD, |
||
991 | PREFIX_0FC2, |
||
6324 | serge | 992 | PREFIX_MOD_0_0FC3, |
993 | PREFIX_MOD_0_0FC7_REG_6, |
||
994 | PREFIX_MOD_3_0FC7_REG_6, |
||
995 | PREFIX_MOD_3_0FC7_REG_7, |
||
5221 | serge | 996 | PREFIX_0FD0, |
997 | PREFIX_0FD6, |
||
998 | PREFIX_0FE6, |
||
999 | PREFIX_0FE7, |
||
1000 | PREFIX_0FF0, |
||
1001 | PREFIX_0FF7, |
||
1002 | PREFIX_0F3810, |
||
1003 | PREFIX_0F3814, |
||
1004 | PREFIX_0F3815, |
||
1005 | PREFIX_0F3817, |
||
1006 | PREFIX_0F3820, |
||
1007 | PREFIX_0F3821, |
||
1008 | PREFIX_0F3822, |
||
1009 | PREFIX_0F3823, |
||
1010 | PREFIX_0F3824, |
||
1011 | PREFIX_0F3825, |
||
1012 | PREFIX_0F3828, |
||
1013 | PREFIX_0F3829, |
||
1014 | PREFIX_0F382A, |
||
1015 | PREFIX_0F382B, |
||
1016 | PREFIX_0F3830, |
||
1017 | PREFIX_0F3831, |
||
1018 | PREFIX_0F3832, |
||
1019 | PREFIX_0F3833, |
||
1020 | PREFIX_0F3834, |
||
1021 | PREFIX_0F3835, |
||
1022 | PREFIX_0F3837, |
||
1023 | PREFIX_0F3838, |
||
1024 | PREFIX_0F3839, |
||
1025 | PREFIX_0F383A, |
||
1026 | PREFIX_0F383B, |
||
1027 | PREFIX_0F383C, |
||
1028 | PREFIX_0F383D, |
||
1029 | PREFIX_0F383E, |
||
1030 | PREFIX_0F383F, |
||
1031 | PREFIX_0F3840, |
||
1032 | PREFIX_0F3841, |
||
1033 | PREFIX_0F3880, |
||
1034 | PREFIX_0F3881, |
||
1035 | PREFIX_0F3882, |
||
1036 | PREFIX_0F38C8, |
||
1037 | PREFIX_0F38C9, |
||
1038 | PREFIX_0F38CA, |
||
1039 | PREFIX_0F38CB, |
||
1040 | PREFIX_0F38CC, |
||
1041 | PREFIX_0F38CD, |
||
1042 | PREFIX_0F38DB, |
||
1043 | PREFIX_0F38DC, |
||
1044 | PREFIX_0F38DD, |
||
1045 | PREFIX_0F38DE, |
||
1046 | PREFIX_0F38DF, |
||
1047 | PREFIX_0F38F0, |
||
1048 | PREFIX_0F38F1, |
||
1049 | PREFIX_0F38F6, |
||
1050 | PREFIX_0F3A08, |
||
1051 | PREFIX_0F3A09, |
||
1052 | PREFIX_0F3A0A, |
||
1053 | PREFIX_0F3A0B, |
||
1054 | PREFIX_0F3A0C, |
||
1055 | PREFIX_0F3A0D, |
||
1056 | PREFIX_0F3A0E, |
||
1057 | PREFIX_0F3A14, |
||
1058 | PREFIX_0F3A15, |
||
1059 | PREFIX_0F3A16, |
||
1060 | PREFIX_0F3A17, |
||
1061 | PREFIX_0F3A20, |
||
1062 | PREFIX_0F3A21, |
||
1063 | PREFIX_0F3A22, |
||
1064 | PREFIX_0F3A40, |
||
1065 | PREFIX_0F3A41, |
||
1066 | PREFIX_0F3A42, |
||
1067 | PREFIX_0F3A44, |
||
1068 | PREFIX_0F3A60, |
||
1069 | PREFIX_0F3A61, |
||
1070 | PREFIX_0F3A62, |
||
1071 | PREFIX_0F3A63, |
||
1072 | PREFIX_0F3ACC, |
||
1073 | PREFIX_0F3ADF, |
||
1074 | PREFIX_VEX_0F10, |
||
1075 | PREFIX_VEX_0F11, |
||
1076 | PREFIX_VEX_0F12, |
||
1077 | PREFIX_VEX_0F16, |
||
1078 | PREFIX_VEX_0F2A, |
||
1079 | PREFIX_VEX_0F2C, |
||
1080 | PREFIX_VEX_0F2D, |
||
1081 | PREFIX_VEX_0F2E, |
||
1082 | PREFIX_VEX_0F2F, |
||
1083 | PREFIX_VEX_0F41, |
||
1084 | PREFIX_VEX_0F42, |
||
1085 | PREFIX_VEX_0F44, |
||
1086 | PREFIX_VEX_0F45, |
||
1087 | PREFIX_VEX_0F46, |
||
1088 | PREFIX_VEX_0F47, |
||
6324 | serge | 1089 | PREFIX_VEX_0F4A, |
5221 | serge | 1090 | PREFIX_VEX_0F4B, |
1091 | PREFIX_VEX_0F51, |
||
1092 | PREFIX_VEX_0F52, |
||
1093 | PREFIX_VEX_0F53, |
||
1094 | PREFIX_VEX_0F58, |
||
1095 | PREFIX_VEX_0F59, |
||
1096 | PREFIX_VEX_0F5A, |
||
1097 | PREFIX_VEX_0F5B, |
||
1098 | PREFIX_VEX_0F5C, |
||
1099 | PREFIX_VEX_0F5D, |
||
1100 | PREFIX_VEX_0F5E, |
||
1101 | PREFIX_VEX_0F5F, |
||
1102 | PREFIX_VEX_0F60, |
||
1103 | PREFIX_VEX_0F61, |
||
1104 | PREFIX_VEX_0F62, |
||
1105 | PREFIX_VEX_0F63, |
||
1106 | PREFIX_VEX_0F64, |
||
1107 | PREFIX_VEX_0F65, |
||
1108 | PREFIX_VEX_0F66, |
||
1109 | PREFIX_VEX_0F67, |
||
1110 | PREFIX_VEX_0F68, |
||
1111 | PREFIX_VEX_0F69, |
||
1112 | PREFIX_VEX_0F6A, |
||
1113 | PREFIX_VEX_0F6B, |
||
1114 | PREFIX_VEX_0F6C, |
||
1115 | PREFIX_VEX_0F6D, |
||
1116 | PREFIX_VEX_0F6E, |
||
1117 | PREFIX_VEX_0F6F, |
||
1118 | PREFIX_VEX_0F70, |
||
1119 | PREFIX_VEX_0F71_REG_2, |
||
1120 | PREFIX_VEX_0F71_REG_4, |
||
1121 | PREFIX_VEX_0F71_REG_6, |
||
1122 | PREFIX_VEX_0F72_REG_2, |
||
1123 | PREFIX_VEX_0F72_REG_4, |
||
1124 | PREFIX_VEX_0F72_REG_6, |
||
1125 | PREFIX_VEX_0F73_REG_2, |
||
1126 | PREFIX_VEX_0F73_REG_3, |
||
1127 | PREFIX_VEX_0F73_REG_6, |
||
1128 | PREFIX_VEX_0F73_REG_7, |
||
1129 | PREFIX_VEX_0F74, |
||
1130 | PREFIX_VEX_0F75, |
||
1131 | PREFIX_VEX_0F76, |
||
1132 | PREFIX_VEX_0F77, |
||
1133 | PREFIX_VEX_0F7C, |
||
1134 | PREFIX_VEX_0F7D, |
||
1135 | PREFIX_VEX_0F7E, |
||
1136 | PREFIX_VEX_0F7F, |
||
1137 | PREFIX_VEX_0F90, |
||
1138 | PREFIX_VEX_0F91, |
||
1139 | PREFIX_VEX_0F92, |
||
1140 | PREFIX_VEX_0F93, |
||
1141 | PREFIX_VEX_0F98, |
||
6324 | serge | 1142 | PREFIX_VEX_0F99, |
5221 | serge | 1143 | PREFIX_VEX_0FC2, |
1144 | PREFIX_VEX_0FC4, |
||
1145 | PREFIX_VEX_0FC5, |
||
1146 | PREFIX_VEX_0FD0, |
||
1147 | PREFIX_VEX_0FD1, |
||
1148 | PREFIX_VEX_0FD2, |
||
1149 | PREFIX_VEX_0FD3, |
||
1150 | PREFIX_VEX_0FD4, |
||
1151 | PREFIX_VEX_0FD5, |
||
1152 | PREFIX_VEX_0FD6, |
||
1153 | PREFIX_VEX_0FD7, |
||
1154 | PREFIX_VEX_0FD8, |
||
1155 | PREFIX_VEX_0FD9, |
||
1156 | PREFIX_VEX_0FDA, |
||
1157 | PREFIX_VEX_0FDB, |
||
1158 | PREFIX_VEX_0FDC, |
||
1159 | PREFIX_VEX_0FDD, |
||
1160 | PREFIX_VEX_0FDE, |
||
1161 | PREFIX_VEX_0FDF, |
||
1162 | PREFIX_VEX_0FE0, |
||
1163 | PREFIX_VEX_0FE1, |
||
1164 | PREFIX_VEX_0FE2, |
||
1165 | PREFIX_VEX_0FE3, |
||
1166 | PREFIX_VEX_0FE4, |
||
1167 | PREFIX_VEX_0FE5, |
||
1168 | PREFIX_VEX_0FE6, |
||
1169 | PREFIX_VEX_0FE7, |
||
1170 | PREFIX_VEX_0FE8, |
||
1171 | PREFIX_VEX_0FE9, |
||
1172 | PREFIX_VEX_0FEA, |
||
1173 | PREFIX_VEX_0FEB, |
||
1174 | PREFIX_VEX_0FEC, |
||
1175 | PREFIX_VEX_0FED, |
||
1176 | PREFIX_VEX_0FEE, |
||
1177 | PREFIX_VEX_0FEF, |
||
1178 | PREFIX_VEX_0FF0, |
||
1179 | PREFIX_VEX_0FF1, |
||
1180 | PREFIX_VEX_0FF2, |
||
1181 | PREFIX_VEX_0FF3, |
||
1182 | PREFIX_VEX_0FF4, |
||
1183 | PREFIX_VEX_0FF5, |
||
1184 | PREFIX_VEX_0FF6, |
||
1185 | PREFIX_VEX_0FF7, |
||
1186 | PREFIX_VEX_0FF8, |
||
1187 | PREFIX_VEX_0FF9, |
||
1188 | PREFIX_VEX_0FFA, |
||
1189 | PREFIX_VEX_0FFB, |
||
1190 | PREFIX_VEX_0FFC, |
||
1191 | PREFIX_VEX_0FFD, |
||
1192 | PREFIX_VEX_0FFE, |
||
1193 | PREFIX_VEX_0F3800, |
||
1194 | PREFIX_VEX_0F3801, |
||
1195 | PREFIX_VEX_0F3802, |
||
1196 | PREFIX_VEX_0F3803, |
||
1197 | PREFIX_VEX_0F3804, |
||
1198 | PREFIX_VEX_0F3805, |
||
1199 | PREFIX_VEX_0F3806, |
||
1200 | PREFIX_VEX_0F3807, |
||
1201 | PREFIX_VEX_0F3808, |
||
1202 | PREFIX_VEX_0F3809, |
||
1203 | PREFIX_VEX_0F380A, |
||
1204 | PREFIX_VEX_0F380B, |
||
1205 | PREFIX_VEX_0F380C, |
||
1206 | PREFIX_VEX_0F380D, |
||
1207 | PREFIX_VEX_0F380E, |
||
1208 | PREFIX_VEX_0F380F, |
||
1209 | PREFIX_VEX_0F3813, |
||
1210 | PREFIX_VEX_0F3816, |
||
1211 | PREFIX_VEX_0F3817, |
||
1212 | PREFIX_VEX_0F3818, |
||
1213 | PREFIX_VEX_0F3819, |
||
1214 | PREFIX_VEX_0F381A, |
||
1215 | PREFIX_VEX_0F381C, |
||
1216 | PREFIX_VEX_0F381D, |
||
1217 | PREFIX_VEX_0F381E, |
||
1218 | PREFIX_VEX_0F3820, |
||
1219 | PREFIX_VEX_0F3821, |
||
1220 | PREFIX_VEX_0F3822, |
||
1221 | PREFIX_VEX_0F3823, |
||
1222 | PREFIX_VEX_0F3824, |
||
1223 | PREFIX_VEX_0F3825, |
||
1224 | PREFIX_VEX_0F3828, |
||
1225 | PREFIX_VEX_0F3829, |
||
1226 | PREFIX_VEX_0F382A, |
||
1227 | PREFIX_VEX_0F382B, |
||
1228 | PREFIX_VEX_0F382C, |
||
1229 | PREFIX_VEX_0F382D, |
||
1230 | PREFIX_VEX_0F382E, |
||
1231 | PREFIX_VEX_0F382F, |
||
1232 | PREFIX_VEX_0F3830, |
||
1233 | PREFIX_VEX_0F3831, |
||
1234 | PREFIX_VEX_0F3832, |
||
1235 | PREFIX_VEX_0F3833, |
||
1236 | PREFIX_VEX_0F3834, |
||
1237 | PREFIX_VEX_0F3835, |
||
1238 | PREFIX_VEX_0F3836, |
||
1239 | PREFIX_VEX_0F3837, |
||
1240 | PREFIX_VEX_0F3838, |
||
1241 | PREFIX_VEX_0F3839, |
||
1242 | PREFIX_VEX_0F383A, |
||
1243 | PREFIX_VEX_0F383B, |
||
1244 | PREFIX_VEX_0F383C, |
||
1245 | PREFIX_VEX_0F383D, |
||
1246 | PREFIX_VEX_0F383E, |
||
1247 | PREFIX_VEX_0F383F, |
||
1248 | PREFIX_VEX_0F3840, |
||
1249 | PREFIX_VEX_0F3841, |
||
1250 | PREFIX_VEX_0F3845, |
||
1251 | PREFIX_VEX_0F3846, |
||
1252 | PREFIX_VEX_0F3847, |
||
1253 | PREFIX_VEX_0F3858, |
||
1254 | PREFIX_VEX_0F3859, |
||
1255 | PREFIX_VEX_0F385A, |
||
1256 | PREFIX_VEX_0F3878, |
||
1257 | PREFIX_VEX_0F3879, |
||
1258 | PREFIX_VEX_0F388C, |
||
1259 | PREFIX_VEX_0F388E, |
||
1260 | PREFIX_VEX_0F3890, |
||
1261 | PREFIX_VEX_0F3891, |
||
1262 | PREFIX_VEX_0F3892, |
||
1263 | PREFIX_VEX_0F3893, |
||
1264 | PREFIX_VEX_0F3896, |
||
1265 | PREFIX_VEX_0F3897, |
||
1266 | PREFIX_VEX_0F3898, |
||
1267 | PREFIX_VEX_0F3899, |
||
1268 | PREFIX_VEX_0F389A, |
||
1269 | PREFIX_VEX_0F389B, |
||
1270 | PREFIX_VEX_0F389C, |
||
1271 | PREFIX_VEX_0F389D, |
||
1272 | PREFIX_VEX_0F389E, |
||
1273 | PREFIX_VEX_0F389F, |
||
1274 | PREFIX_VEX_0F38A6, |
||
1275 | PREFIX_VEX_0F38A7, |
||
1276 | PREFIX_VEX_0F38A8, |
||
1277 | PREFIX_VEX_0F38A9, |
||
1278 | PREFIX_VEX_0F38AA, |
||
1279 | PREFIX_VEX_0F38AB, |
||
1280 | PREFIX_VEX_0F38AC, |
||
1281 | PREFIX_VEX_0F38AD, |
||
1282 | PREFIX_VEX_0F38AE, |
||
1283 | PREFIX_VEX_0F38AF, |
||
1284 | PREFIX_VEX_0F38B6, |
||
1285 | PREFIX_VEX_0F38B7, |
||
1286 | PREFIX_VEX_0F38B8, |
||
1287 | PREFIX_VEX_0F38B9, |
||
1288 | PREFIX_VEX_0F38BA, |
||
1289 | PREFIX_VEX_0F38BB, |
||
1290 | PREFIX_VEX_0F38BC, |
||
1291 | PREFIX_VEX_0F38BD, |
||
1292 | PREFIX_VEX_0F38BE, |
||
1293 | PREFIX_VEX_0F38BF, |
||
1294 | PREFIX_VEX_0F38DB, |
||
1295 | PREFIX_VEX_0F38DC, |
||
1296 | PREFIX_VEX_0F38DD, |
||
1297 | PREFIX_VEX_0F38DE, |
||
1298 | PREFIX_VEX_0F38DF, |
||
1299 | PREFIX_VEX_0F38F2, |
||
1300 | PREFIX_VEX_0F38F3_REG_1, |
||
1301 | PREFIX_VEX_0F38F3_REG_2, |
||
1302 | PREFIX_VEX_0F38F3_REG_3, |
||
1303 | PREFIX_VEX_0F38F5, |
||
1304 | PREFIX_VEX_0F38F6, |
||
1305 | PREFIX_VEX_0F38F7, |
||
1306 | PREFIX_VEX_0F3A00, |
||
1307 | PREFIX_VEX_0F3A01, |
||
1308 | PREFIX_VEX_0F3A02, |
||
1309 | PREFIX_VEX_0F3A04, |
||
1310 | PREFIX_VEX_0F3A05, |
||
1311 | PREFIX_VEX_0F3A06, |
||
1312 | PREFIX_VEX_0F3A08, |
||
1313 | PREFIX_VEX_0F3A09, |
||
1314 | PREFIX_VEX_0F3A0A, |
||
1315 | PREFIX_VEX_0F3A0B, |
||
1316 | PREFIX_VEX_0F3A0C, |
||
1317 | PREFIX_VEX_0F3A0D, |
||
1318 | PREFIX_VEX_0F3A0E, |
||
1319 | PREFIX_VEX_0F3A0F, |
||
1320 | PREFIX_VEX_0F3A14, |
||
1321 | PREFIX_VEX_0F3A15, |
||
1322 | PREFIX_VEX_0F3A16, |
||
1323 | PREFIX_VEX_0F3A17, |
||
1324 | PREFIX_VEX_0F3A18, |
||
1325 | PREFIX_VEX_0F3A19, |
||
1326 | PREFIX_VEX_0F3A1D, |
||
1327 | PREFIX_VEX_0F3A20, |
||
1328 | PREFIX_VEX_0F3A21, |
||
1329 | PREFIX_VEX_0F3A22, |
||
1330 | PREFIX_VEX_0F3A30, |
||
6324 | serge | 1331 | PREFIX_VEX_0F3A31, |
5221 | serge | 1332 | PREFIX_VEX_0F3A32, |
6324 | serge | 1333 | PREFIX_VEX_0F3A33, |
5221 | serge | 1334 | PREFIX_VEX_0F3A38, |
1335 | PREFIX_VEX_0F3A39, |
||
1336 | PREFIX_VEX_0F3A40, |
||
1337 | PREFIX_VEX_0F3A41, |
||
1338 | PREFIX_VEX_0F3A42, |
||
1339 | PREFIX_VEX_0F3A44, |
||
1340 | PREFIX_VEX_0F3A46, |
||
1341 | PREFIX_VEX_0F3A48, |
||
1342 | PREFIX_VEX_0F3A49, |
||
1343 | PREFIX_VEX_0F3A4A, |
||
1344 | PREFIX_VEX_0F3A4B, |
||
1345 | PREFIX_VEX_0F3A4C, |
||
1346 | PREFIX_VEX_0F3A5C, |
||
1347 | PREFIX_VEX_0F3A5D, |
||
1348 | PREFIX_VEX_0F3A5E, |
||
1349 | PREFIX_VEX_0F3A5F, |
||
1350 | PREFIX_VEX_0F3A60, |
||
1351 | PREFIX_VEX_0F3A61, |
||
1352 | PREFIX_VEX_0F3A62, |
||
1353 | PREFIX_VEX_0F3A63, |
||
1354 | PREFIX_VEX_0F3A68, |
||
1355 | PREFIX_VEX_0F3A69, |
||
1356 | PREFIX_VEX_0F3A6A, |
||
1357 | PREFIX_VEX_0F3A6B, |
||
1358 | PREFIX_VEX_0F3A6C, |
||
1359 | PREFIX_VEX_0F3A6D, |
||
1360 | PREFIX_VEX_0F3A6E, |
||
1361 | PREFIX_VEX_0F3A6F, |
||
1362 | PREFIX_VEX_0F3A78, |
||
1363 | PREFIX_VEX_0F3A79, |
||
1364 | PREFIX_VEX_0F3A7A, |
||
1365 | PREFIX_VEX_0F3A7B, |
||
1366 | PREFIX_VEX_0F3A7C, |
||
1367 | PREFIX_VEX_0F3A7D, |
||
1368 | PREFIX_VEX_0F3A7E, |
||
1369 | PREFIX_VEX_0F3A7F, |
||
1370 | PREFIX_VEX_0F3ADF, |
||
1371 | PREFIX_VEX_0F3AF0, |
||
1372 | |||
1373 | PREFIX_EVEX_0F10, |
||
1374 | PREFIX_EVEX_0F11, |
||
1375 | PREFIX_EVEX_0F12, |
||
1376 | PREFIX_EVEX_0F13, |
||
1377 | PREFIX_EVEX_0F14, |
||
1378 | PREFIX_EVEX_0F15, |
||
1379 | PREFIX_EVEX_0F16, |
||
1380 | PREFIX_EVEX_0F17, |
||
1381 | PREFIX_EVEX_0F28, |
||
1382 | PREFIX_EVEX_0F29, |
||
1383 | PREFIX_EVEX_0F2A, |
||
1384 | PREFIX_EVEX_0F2B, |
||
1385 | PREFIX_EVEX_0F2C, |
||
1386 | PREFIX_EVEX_0F2D, |
||
1387 | PREFIX_EVEX_0F2E, |
||
1388 | PREFIX_EVEX_0F2F, |
||
1389 | PREFIX_EVEX_0F51, |
||
6324 | serge | 1390 | PREFIX_EVEX_0F54, |
1391 | PREFIX_EVEX_0F55, |
||
1392 | PREFIX_EVEX_0F56, |
||
1393 | PREFIX_EVEX_0F57, |
||
5221 | serge | 1394 | PREFIX_EVEX_0F58, |
1395 | PREFIX_EVEX_0F59, |
||
1396 | PREFIX_EVEX_0F5A, |
||
1397 | PREFIX_EVEX_0F5B, |
||
1398 | PREFIX_EVEX_0F5C, |
||
1399 | PREFIX_EVEX_0F5D, |
||
1400 | PREFIX_EVEX_0F5E, |
||
1401 | PREFIX_EVEX_0F5F, |
||
6324 | serge | 1402 | PREFIX_EVEX_0F60, |
1403 | PREFIX_EVEX_0F61, |
||
5221 | serge | 1404 | PREFIX_EVEX_0F62, |
6324 | serge | 1405 | PREFIX_EVEX_0F63, |
1406 | PREFIX_EVEX_0F64, |
||
1407 | PREFIX_EVEX_0F65, |
||
5221 | serge | 1408 | PREFIX_EVEX_0F66, |
6324 | serge | 1409 | PREFIX_EVEX_0F67, |
1410 | PREFIX_EVEX_0F68, |
||
1411 | PREFIX_EVEX_0F69, |
||
5221 | serge | 1412 | PREFIX_EVEX_0F6A, |
6324 | serge | 1413 | PREFIX_EVEX_0F6B, |
5221 | serge | 1414 | PREFIX_EVEX_0F6C, |
1415 | PREFIX_EVEX_0F6D, |
||
1416 | PREFIX_EVEX_0F6E, |
||
1417 | PREFIX_EVEX_0F6F, |
||
1418 | PREFIX_EVEX_0F70, |
||
6324 | serge | 1419 | PREFIX_EVEX_0F71_REG_2, |
1420 | PREFIX_EVEX_0F71_REG_4, |
||
1421 | PREFIX_EVEX_0F71_REG_6, |
||
5221 | serge | 1422 | PREFIX_EVEX_0F72_REG_0, |
1423 | PREFIX_EVEX_0F72_REG_1, |
||
1424 | PREFIX_EVEX_0F72_REG_2, |
||
1425 | PREFIX_EVEX_0F72_REG_4, |
||
1426 | PREFIX_EVEX_0F72_REG_6, |
||
1427 | PREFIX_EVEX_0F73_REG_2, |
||
6324 | serge | 1428 | PREFIX_EVEX_0F73_REG_3, |
5221 | serge | 1429 | PREFIX_EVEX_0F73_REG_6, |
6324 | serge | 1430 | PREFIX_EVEX_0F73_REG_7, |
1431 | PREFIX_EVEX_0F74, |
||
1432 | PREFIX_EVEX_0F75, |
||
5221 | serge | 1433 | PREFIX_EVEX_0F76, |
1434 | PREFIX_EVEX_0F78, |
||
1435 | PREFIX_EVEX_0F79, |
||
1436 | PREFIX_EVEX_0F7A, |
||
1437 | PREFIX_EVEX_0F7B, |
||
1438 | PREFIX_EVEX_0F7E, |
||
1439 | PREFIX_EVEX_0F7F, |
||
1440 | PREFIX_EVEX_0FC2, |
||
6324 | serge | 1441 | PREFIX_EVEX_0FC4, |
1442 | PREFIX_EVEX_0FC5, |
||
5221 | serge | 1443 | PREFIX_EVEX_0FC6, |
6324 | serge | 1444 | PREFIX_EVEX_0FD1, |
5221 | serge | 1445 | PREFIX_EVEX_0FD2, |
1446 | PREFIX_EVEX_0FD3, |
||
1447 | PREFIX_EVEX_0FD4, |
||
6324 | serge | 1448 | PREFIX_EVEX_0FD5, |
5221 | serge | 1449 | PREFIX_EVEX_0FD6, |
6324 | serge | 1450 | PREFIX_EVEX_0FD8, |
1451 | PREFIX_EVEX_0FD9, |
||
1452 | PREFIX_EVEX_0FDA, |
||
5221 | serge | 1453 | PREFIX_EVEX_0FDB, |
6324 | serge | 1454 | PREFIX_EVEX_0FDC, |
1455 | PREFIX_EVEX_0FDD, |
||
1456 | PREFIX_EVEX_0FDE, |
||
5221 | serge | 1457 | PREFIX_EVEX_0FDF, |
6324 | serge | 1458 | PREFIX_EVEX_0FE0, |
1459 | PREFIX_EVEX_0FE1, |
||
5221 | serge | 1460 | PREFIX_EVEX_0FE2, |
6324 | serge | 1461 | PREFIX_EVEX_0FE3, |
1462 | PREFIX_EVEX_0FE4, |
||
1463 | PREFIX_EVEX_0FE5, |
||
5221 | serge | 1464 | PREFIX_EVEX_0FE6, |
1465 | PREFIX_EVEX_0FE7, |
||
6324 | serge | 1466 | PREFIX_EVEX_0FE8, |
1467 | PREFIX_EVEX_0FE9, |
||
1468 | PREFIX_EVEX_0FEA, |
||
5221 | serge | 1469 | PREFIX_EVEX_0FEB, |
6324 | serge | 1470 | PREFIX_EVEX_0FEC, |
1471 | PREFIX_EVEX_0FED, |
||
1472 | PREFIX_EVEX_0FEE, |
||
5221 | serge | 1473 | PREFIX_EVEX_0FEF, |
6324 | serge | 1474 | PREFIX_EVEX_0FF1, |
5221 | serge | 1475 | PREFIX_EVEX_0FF2, |
1476 | PREFIX_EVEX_0FF3, |
||
1477 | PREFIX_EVEX_0FF4, |
||
6324 | serge | 1478 | PREFIX_EVEX_0FF5, |
1479 | PREFIX_EVEX_0FF6, |
||
1480 | PREFIX_EVEX_0FF8, |
||
1481 | PREFIX_EVEX_0FF9, |
||
5221 | serge | 1482 | PREFIX_EVEX_0FFA, |
1483 | PREFIX_EVEX_0FFB, |
||
6324 | serge | 1484 | PREFIX_EVEX_0FFC, |
1485 | PREFIX_EVEX_0FFD, |
||
5221 | serge | 1486 | PREFIX_EVEX_0FFE, |
6324 | serge | 1487 | PREFIX_EVEX_0F3800, |
1488 | PREFIX_EVEX_0F3804, |
||
1489 | PREFIX_EVEX_0F380B, |
||
5221 | serge | 1490 | PREFIX_EVEX_0F380C, |
1491 | PREFIX_EVEX_0F380D, |
||
6324 | serge | 1492 | PREFIX_EVEX_0F3810, |
5221 | serge | 1493 | PREFIX_EVEX_0F3811, |
1494 | PREFIX_EVEX_0F3812, |
||
1495 | PREFIX_EVEX_0F3813, |
||
1496 | PREFIX_EVEX_0F3814, |
||
1497 | PREFIX_EVEX_0F3815, |
||
1498 | PREFIX_EVEX_0F3816, |
||
1499 | PREFIX_EVEX_0F3818, |
||
1500 | PREFIX_EVEX_0F3819, |
||
1501 | PREFIX_EVEX_0F381A, |
||
1502 | PREFIX_EVEX_0F381B, |
||
6324 | serge | 1503 | PREFIX_EVEX_0F381C, |
1504 | PREFIX_EVEX_0F381D, |
||
5221 | serge | 1505 | PREFIX_EVEX_0F381E, |
1506 | PREFIX_EVEX_0F381F, |
||
6324 | serge | 1507 | PREFIX_EVEX_0F3820, |
5221 | serge | 1508 | PREFIX_EVEX_0F3821, |
1509 | PREFIX_EVEX_0F3822, |
||
1510 | PREFIX_EVEX_0F3823, |
||
1511 | PREFIX_EVEX_0F3824, |
||
1512 | PREFIX_EVEX_0F3825, |
||
6324 | serge | 1513 | PREFIX_EVEX_0F3826, |
5221 | serge | 1514 | PREFIX_EVEX_0F3827, |
1515 | PREFIX_EVEX_0F3828, |
||
1516 | PREFIX_EVEX_0F3829, |
||
1517 | PREFIX_EVEX_0F382A, |
||
6324 | serge | 1518 | PREFIX_EVEX_0F382B, |
5221 | serge | 1519 | PREFIX_EVEX_0F382C, |
1520 | PREFIX_EVEX_0F382D, |
||
6324 | serge | 1521 | PREFIX_EVEX_0F3830, |
5221 | serge | 1522 | PREFIX_EVEX_0F3831, |
1523 | PREFIX_EVEX_0F3832, |
||
1524 | PREFIX_EVEX_0F3833, |
||
1525 | PREFIX_EVEX_0F3834, |
||
1526 | PREFIX_EVEX_0F3835, |
||
1527 | PREFIX_EVEX_0F3836, |
||
1528 | PREFIX_EVEX_0F3837, |
||
6324 | serge | 1529 | PREFIX_EVEX_0F3838, |
5221 | serge | 1530 | PREFIX_EVEX_0F3839, |
1531 | PREFIX_EVEX_0F383A, |
||
1532 | PREFIX_EVEX_0F383B, |
||
6324 | serge | 1533 | PREFIX_EVEX_0F383C, |
5221 | serge | 1534 | PREFIX_EVEX_0F383D, |
6324 | serge | 1535 | PREFIX_EVEX_0F383E, |
5221 | serge | 1536 | PREFIX_EVEX_0F383F, |
1537 | PREFIX_EVEX_0F3840, |
||
1538 | PREFIX_EVEX_0F3842, |
||
1539 | PREFIX_EVEX_0F3843, |
||
1540 | PREFIX_EVEX_0F3844, |
||
1541 | PREFIX_EVEX_0F3845, |
||
1542 | PREFIX_EVEX_0F3846, |
||
1543 | PREFIX_EVEX_0F3847, |
||
1544 | PREFIX_EVEX_0F384C, |
||
1545 | PREFIX_EVEX_0F384D, |
||
1546 | PREFIX_EVEX_0F384E, |
||
1547 | PREFIX_EVEX_0F384F, |
||
1548 | PREFIX_EVEX_0F3858, |
||
1549 | PREFIX_EVEX_0F3859, |
||
1550 | PREFIX_EVEX_0F385A, |
||
1551 | PREFIX_EVEX_0F385B, |
||
1552 | PREFIX_EVEX_0F3864, |
||
1553 | PREFIX_EVEX_0F3865, |
||
6324 | serge | 1554 | PREFIX_EVEX_0F3866, |
1555 | PREFIX_EVEX_0F3875, |
||
5221 | serge | 1556 | PREFIX_EVEX_0F3876, |
1557 | PREFIX_EVEX_0F3877, |
||
6324 | serge | 1558 | PREFIX_EVEX_0F3878, |
1559 | PREFIX_EVEX_0F3879, |
||
1560 | PREFIX_EVEX_0F387A, |
||
1561 | PREFIX_EVEX_0F387B, |
||
5221 | serge | 1562 | PREFIX_EVEX_0F387C, |
6324 | serge | 1563 | PREFIX_EVEX_0F387D, |
5221 | serge | 1564 | PREFIX_EVEX_0F387E, |
1565 | PREFIX_EVEX_0F387F, |
||
6324 | serge | 1566 | PREFIX_EVEX_0F3883, |
5221 | serge | 1567 | PREFIX_EVEX_0F3888, |
1568 | PREFIX_EVEX_0F3889, |
||
1569 | PREFIX_EVEX_0F388A, |
||
1570 | PREFIX_EVEX_0F388B, |
||
6324 | serge | 1571 | PREFIX_EVEX_0F388D, |
5221 | serge | 1572 | PREFIX_EVEX_0F3890, |
1573 | PREFIX_EVEX_0F3891, |
||
1574 | PREFIX_EVEX_0F3892, |
||
1575 | PREFIX_EVEX_0F3893, |
||
1576 | PREFIX_EVEX_0F3896, |
||
1577 | PREFIX_EVEX_0F3897, |
||
1578 | PREFIX_EVEX_0F3898, |
||
1579 | PREFIX_EVEX_0F3899, |
||
1580 | PREFIX_EVEX_0F389A, |
||
1581 | PREFIX_EVEX_0F389B, |
||
1582 | PREFIX_EVEX_0F389C, |
||
1583 | PREFIX_EVEX_0F389D, |
||
1584 | PREFIX_EVEX_0F389E, |
||
1585 | PREFIX_EVEX_0F389F, |
||
1586 | PREFIX_EVEX_0F38A0, |
||
1587 | PREFIX_EVEX_0F38A1, |
||
1588 | PREFIX_EVEX_0F38A2, |
||
1589 | PREFIX_EVEX_0F38A3, |
||
1590 | PREFIX_EVEX_0F38A6, |
||
1591 | PREFIX_EVEX_0F38A7, |
||
1592 | PREFIX_EVEX_0F38A8, |
||
1593 | PREFIX_EVEX_0F38A9, |
||
1594 | PREFIX_EVEX_0F38AA, |
||
1595 | PREFIX_EVEX_0F38AB, |
||
1596 | PREFIX_EVEX_0F38AC, |
||
1597 | PREFIX_EVEX_0F38AD, |
||
1598 | PREFIX_EVEX_0F38AE, |
||
1599 | PREFIX_EVEX_0F38AF, |
||
6324 | serge | 1600 | PREFIX_EVEX_0F38B4, |
1601 | PREFIX_EVEX_0F38B5, |
||
5221 | serge | 1602 | PREFIX_EVEX_0F38B6, |
1603 | PREFIX_EVEX_0F38B7, |
||
1604 | PREFIX_EVEX_0F38B8, |
||
1605 | PREFIX_EVEX_0F38B9, |
||
1606 | PREFIX_EVEX_0F38BA, |
||
1607 | PREFIX_EVEX_0F38BB, |
||
1608 | PREFIX_EVEX_0F38BC, |
||
1609 | PREFIX_EVEX_0F38BD, |
||
1610 | PREFIX_EVEX_0F38BE, |
||
1611 | PREFIX_EVEX_0F38BF, |
||
1612 | PREFIX_EVEX_0F38C4, |
||
1613 | PREFIX_EVEX_0F38C6_REG_1, |
||
1614 | PREFIX_EVEX_0F38C6_REG_2, |
||
1615 | PREFIX_EVEX_0F38C6_REG_5, |
||
1616 | PREFIX_EVEX_0F38C6_REG_6, |
||
1617 | PREFIX_EVEX_0F38C7_REG_1, |
||
1618 | PREFIX_EVEX_0F38C7_REG_2, |
||
1619 | PREFIX_EVEX_0F38C7_REG_5, |
||
1620 | PREFIX_EVEX_0F38C7_REG_6, |
||
1621 | PREFIX_EVEX_0F38C8, |
||
1622 | PREFIX_EVEX_0F38CA, |
||
1623 | PREFIX_EVEX_0F38CB, |
||
1624 | PREFIX_EVEX_0F38CC, |
||
1625 | PREFIX_EVEX_0F38CD, |
||
1626 | |||
1627 | PREFIX_EVEX_0F3A00, |
||
1628 | PREFIX_EVEX_0F3A01, |
||
1629 | PREFIX_EVEX_0F3A03, |
||
1630 | PREFIX_EVEX_0F3A04, |
||
1631 | PREFIX_EVEX_0F3A05, |
||
1632 | PREFIX_EVEX_0F3A08, |
||
1633 | PREFIX_EVEX_0F3A09, |
||
1634 | PREFIX_EVEX_0F3A0A, |
||
1635 | PREFIX_EVEX_0F3A0B, |
||
6324 | serge | 1636 | PREFIX_EVEX_0F3A0F, |
1637 | PREFIX_EVEX_0F3A14, |
||
1638 | PREFIX_EVEX_0F3A15, |
||
1639 | PREFIX_EVEX_0F3A16, |
||
5221 | serge | 1640 | PREFIX_EVEX_0F3A17, |
1641 | PREFIX_EVEX_0F3A18, |
||
1642 | PREFIX_EVEX_0F3A19, |
||
1643 | PREFIX_EVEX_0F3A1A, |
||
1644 | PREFIX_EVEX_0F3A1B, |
||
1645 | PREFIX_EVEX_0F3A1D, |
||
1646 | PREFIX_EVEX_0F3A1E, |
||
1647 | PREFIX_EVEX_0F3A1F, |
||
6324 | serge | 1648 | PREFIX_EVEX_0F3A20, |
5221 | serge | 1649 | PREFIX_EVEX_0F3A21, |
6324 | serge | 1650 | PREFIX_EVEX_0F3A22, |
5221 | serge | 1651 | PREFIX_EVEX_0F3A23, |
1652 | PREFIX_EVEX_0F3A25, |
||
1653 | PREFIX_EVEX_0F3A26, |
||
1654 | PREFIX_EVEX_0F3A27, |
||
1655 | PREFIX_EVEX_0F3A38, |
||
1656 | PREFIX_EVEX_0F3A39, |
||
1657 | PREFIX_EVEX_0F3A3A, |
||
1658 | PREFIX_EVEX_0F3A3B, |
||
6324 | serge | 1659 | PREFIX_EVEX_0F3A3E, |
1660 | PREFIX_EVEX_0F3A3F, |
||
1661 | PREFIX_EVEX_0F3A42, |
||
5221 | serge | 1662 | PREFIX_EVEX_0F3A43, |
6324 | serge | 1663 | PREFIX_EVEX_0F3A50, |
1664 | PREFIX_EVEX_0F3A51, |
||
5221 | serge | 1665 | PREFIX_EVEX_0F3A54, |
1666 | PREFIX_EVEX_0F3A55, |
||
6324 | serge | 1667 | PREFIX_EVEX_0F3A56, |
1668 | PREFIX_EVEX_0F3A57, |
||
1669 | PREFIX_EVEX_0F3A66, |
||
1670 | PREFIX_EVEX_0F3A67 |
||
5221 | serge | 1671 | }; |
1672 | |||
1673 | enum |
||
1674 | { |
||
1675 | X86_64_06 = 0, |
||
1676 | X86_64_07, |
||
1677 | X86_64_0D, |
||
1678 | X86_64_16, |
||
1679 | X86_64_17, |
||
1680 | X86_64_1E, |
||
1681 | X86_64_1F, |
||
1682 | X86_64_27, |
||
1683 | X86_64_2F, |
||
1684 | X86_64_37, |
||
1685 | X86_64_3F, |
||
1686 | X86_64_60, |
||
1687 | X86_64_61, |
||
1688 | X86_64_62, |
||
1689 | X86_64_63, |
||
1690 | X86_64_6D, |
||
1691 | X86_64_6F, |
||
1692 | X86_64_9A, |
||
1693 | X86_64_C4, |
||
1694 | X86_64_C5, |
||
1695 | X86_64_CE, |
||
1696 | X86_64_D4, |
||
1697 | X86_64_D5, |
||
6324 | serge | 1698 | X86_64_E8, |
1699 | X86_64_E9, |
||
5221 | serge | 1700 | X86_64_EA, |
1701 | X86_64_0F01_REG_0, |
||
1702 | X86_64_0F01_REG_1, |
||
1703 | X86_64_0F01_REG_2, |
||
1704 | X86_64_0F01_REG_3 |
||
1705 | }; |
||
1706 | |||
1707 | enum |
||
1708 | { |
||
1709 | THREE_BYTE_0F38 = 0, |
||
1710 | THREE_BYTE_0F3A, |
||
1711 | THREE_BYTE_0F7A |
||
1712 | }; |
||
1713 | |||
1714 | enum |
||
1715 | { |
||
1716 | XOP_08 = 0, |
||
1717 | XOP_09, |
||
1718 | XOP_0A |
||
1719 | }; |
||
1720 | |||
1721 | enum |
||
1722 | { |
||
1723 | VEX_0F = 0, |
||
1724 | VEX_0F38, |
||
1725 | VEX_0F3A |
||
1726 | }; |
||
1727 | |||
1728 | enum |
||
1729 | { |
||
1730 | EVEX_0F = 0, |
||
1731 | EVEX_0F38, |
||
1732 | EVEX_0F3A |
||
1733 | }; |
||
1734 | |||
1735 | enum |
||
1736 | { |
||
1737 | VEX_LEN_0F10_P_1 = 0, |
||
1738 | VEX_LEN_0F10_P_3, |
||
1739 | VEX_LEN_0F11_P_1, |
||
1740 | VEX_LEN_0F11_P_3, |
||
1741 | VEX_LEN_0F12_P_0_M_0, |
||
1742 | VEX_LEN_0F12_P_0_M_1, |
||
1743 | VEX_LEN_0F12_P_2, |
||
1744 | VEX_LEN_0F13_M_0, |
||
1745 | VEX_LEN_0F16_P_0_M_0, |
||
1746 | VEX_LEN_0F16_P_0_M_1, |
||
1747 | VEX_LEN_0F16_P_2, |
||
1748 | VEX_LEN_0F17_M_0, |
||
1749 | VEX_LEN_0F2A_P_1, |
||
1750 | VEX_LEN_0F2A_P_3, |
||
1751 | VEX_LEN_0F2C_P_1, |
||
1752 | VEX_LEN_0F2C_P_3, |
||
1753 | VEX_LEN_0F2D_P_1, |
||
1754 | VEX_LEN_0F2D_P_3, |
||
1755 | VEX_LEN_0F2E_P_0, |
||
1756 | VEX_LEN_0F2E_P_2, |
||
1757 | VEX_LEN_0F2F_P_0, |
||
1758 | VEX_LEN_0F2F_P_2, |
||
1759 | VEX_LEN_0F41_P_0, |
||
6324 | serge | 1760 | VEX_LEN_0F41_P_2, |
5221 | serge | 1761 | VEX_LEN_0F42_P_0, |
6324 | serge | 1762 | VEX_LEN_0F42_P_2, |
5221 | serge | 1763 | VEX_LEN_0F44_P_0, |
6324 | serge | 1764 | VEX_LEN_0F44_P_2, |
5221 | serge | 1765 | VEX_LEN_0F45_P_0, |
6324 | serge | 1766 | VEX_LEN_0F45_P_2, |
5221 | serge | 1767 | VEX_LEN_0F46_P_0, |
6324 | serge | 1768 | VEX_LEN_0F46_P_2, |
5221 | serge | 1769 | VEX_LEN_0F47_P_0, |
6324 | serge | 1770 | VEX_LEN_0F47_P_2, |
1771 | VEX_LEN_0F4A_P_0, |
||
1772 | VEX_LEN_0F4A_P_2, |
||
1773 | VEX_LEN_0F4B_P_0, |
||
5221 | serge | 1774 | VEX_LEN_0F4B_P_2, |
1775 | VEX_LEN_0F51_P_1, |
||
1776 | VEX_LEN_0F51_P_3, |
||
1777 | VEX_LEN_0F52_P_1, |
||
1778 | VEX_LEN_0F53_P_1, |
||
1779 | VEX_LEN_0F58_P_1, |
||
1780 | VEX_LEN_0F58_P_3, |
||
1781 | VEX_LEN_0F59_P_1, |
||
1782 | VEX_LEN_0F59_P_3, |
||
1783 | VEX_LEN_0F5A_P_1, |
||
1784 | VEX_LEN_0F5A_P_3, |
||
1785 | VEX_LEN_0F5C_P_1, |
||
1786 | VEX_LEN_0F5C_P_3, |
||
1787 | VEX_LEN_0F5D_P_1, |
||
1788 | VEX_LEN_0F5D_P_3, |
||
1789 | VEX_LEN_0F5E_P_1, |
||
1790 | VEX_LEN_0F5E_P_3, |
||
1791 | VEX_LEN_0F5F_P_1, |
||
1792 | VEX_LEN_0F5F_P_3, |
||
1793 | VEX_LEN_0F6E_P_2, |
||
1794 | VEX_LEN_0F7E_P_1, |
||
1795 | VEX_LEN_0F7E_P_2, |
||
1796 | VEX_LEN_0F90_P_0, |
||
6324 | serge | 1797 | VEX_LEN_0F90_P_2, |
5221 | serge | 1798 | VEX_LEN_0F91_P_0, |
6324 | serge | 1799 | VEX_LEN_0F91_P_2, |
5221 | serge | 1800 | VEX_LEN_0F92_P_0, |
6324 | serge | 1801 | VEX_LEN_0F92_P_2, |
1802 | VEX_LEN_0F92_P_3, |
||
5221 | serge | 1803 | VEX_LEN_0F93_P_0, |
6324 | serge | 1804 | VEX_LEN_0F93_P_2, |
1805 | VEX_LEN_0F93_P_3, |
||
5221 | serge | 1806 | VEX_LEN_0F98_P_0, |
6324 | serge | 1807 | VEX_LEN_0F98_P_2, |
1808 | VEX_LEN_0F99_P_0, |
||
1809 | VEX_LEN_0F99_P_2, |
||
5221 | serge | 1810 | VEX_LEN_0FAE_R_2_M_0, |
1811 | VEX_LEN_0FAE_R_3_M_0, |
||
1812 | VEX_LEN_0FC2_P_1, |
||
1813 | VEX_LEN_0FC2_P_3, |
||
1814 | VEX_LEN_0FC4_P_2, |
||
1815 | VEX_LEN_0FC5_P_2, |
||
1816 | VEX_LEN_0FD6_P_2, |
||
1817 | VEX_LEN_0FF7_P_2, |
||
1818 | VEX_LEN_0F3816_P_2, |
||
1819 | VEX_LEN_0F3819_P_2, |
||
1820 | VEX_LEN_0F381A_P_2_M_0, |
||
1821 | VEX_LEN_0F3836_P_2, |
||
1822 | VEX_LEN_0F3841_P_2, |
||
1823 | VEX_LEN_0F385A_P_2_M_0, |
||
1824 | VEX_LEN_0F38DB_P_2, |
||
1825 | VEX_LEN_0F38DC_P_2, |
||
1826 | VEX_LEN_0F38DD_P_2, |
||
1827 | VEX_LEN_0F38DE_P_2, |
||
1828 | VEX_LEN_0F38DF_P_2, |
||
1829 | VEX_LEN_0F38F2_P_0, |
||
1830 | VEX_LEN_0F38F3_R_1_P_0, |
||
1831 | VEX_LEN_0F38F3_R_2_P_0, |
||
1832 | VEX_LEN_0F38F3_R_3_P_0, |
||
1833 | VEX_LEN_0F38F5_P_0, |
||
1834 | VEX_LEN_0F38F5_P_1, |
||
1835 | VEX_LEN_0F38F5_P_3, |
||
1836 | VEX_LEN_0F38F6_P_3, |
||
1837 | VEX_LEN_0F38F7_P_0, |
||
1838 | VEX_LEN_0F38F7_P_1, |
||
1839 | VEX_LEN_0F38F7_P_2, |
||
1840 | VEX_LEN_0F38F7_P_3, |
||
1841 | VEX_LEN_0F3A00_P_2, |
||
1842 | VEX_LEN_0F3A01_P_2, |
||
1843 | VEX_LEN_0F3A06_P_2, |
||
1844 | VEX_LEN_0F3A0A_P_2, |
||
1845 | VEX_LEN_0F3A0B_P_2, |
||
1846 | VEX_LEN_0F3A14_P_2, |
||
1847 | VEX_LEN_0F3A15_P_2, |
||
1848 | VEX_LEN_0F3A16_P_2, |
||
1849 | VEX_LEN_0F3A17_P_2, |
||
1850 | VEX_LEN_0F3A18_P_2, |
||
1851 | VEX_LEN_0F3A19_P_2, |
||
1852 | VEX_LEN_0F3A20_P_2, |
||
1853 | VEX_LEN_0F3A21_P_2, |
||
1854 | VEX_LEN_0F3A22_P_2, |
||
1855 | VEX_LEN_0F3A30_P_2, |
||
6324 | serge | 1856 | VEX_LEN_0F3A31_P_2, |
5221 | serge | 1857 | VEX_LEN_0F3A32_P_2, |
6324 | serge | 1858 | VEX_LEN_0F3A33_P_2, |
5221 | serge | 1859 | VEX_LEN_0F3A38_P_2, |
1860 | VEX_LEN_0F3A39_P_2, |
||
1861 | VEX_LEN_0F3A41_P_2, |
||
1862 | VEX_LEN_0F3A44_P_2, |
||
1863 | VEX_LEN_0F3A46_P_2, |
||
1864 | VEX_LEN_0F3A60_P_2, |
||
1865 | VEX_LEN_0F3A61_P_2, |
||
1866 | VEX_LEN_0F3A62_P_2, |
||
1867 | VEX_LEN_0F3A63_P_2, |
||
1868 | VEX_LEN_0F3A6A_P_2, |
||
1869 | VEX_LEN_0F3A6B_P_2, |
||
1870 | VEX_LEN_0F3A6E_P_2, |
||
1871 | VEX_LEN_0F3A6F_P_2, |
||
1872 | VEX_LEN_0F3A7A_P_2, |
||
1873 | VEX_LEN_0F3A7B_P_2, |
||
1874 | VEX_LEN_0F3A7E_P_2, |
||
1875 | VEX_LEN_0F3A7F_P_2, |
||
1876 | VEX_LEN_0F3ADF_P_2, |
||
1877 | VEX_LEN_0F3AF0_P_3, |
||
1878 | VEX_LEN_0FXOP_08_CC, |
||
1879 | VEX_LEN_0FXOP_08_CD, |
||
1880 | VEX_LEN_0FXOP_08_CE, |
||
1881 | VEX_LEN_0FXOP_08_CF, |
||
1882 | VEX_LEN_0FXOP_08_EC, |
||
1883 | VEX_LEN_0FXOP_08_ED, |
||
1884 | VEX_LEN_0FXOP_08_EE, |
||
1885 | VEX_LEN_0FXOP_08_EF, |
||
1886 | VEX_LEN_0FXOP_09_80, |
||
1887 | VEX_LEN_0FXOP_09_81 |
||
1888 | }; |
||
1889 | |||
1890 | enum |
||
1891 | { |
||
1892 | VEX_W_0F10_P_0 = 0, |
||
1893 | VEX_W_0F10_P_1, |
||
1894 | VEX_W_0F10_P_2, |
||
1895 | VEX_W_0F10_P_3, |
||
1896 | VEX_W_0F11_P_0, |
||
1897 | VEX_W_0F11_P_1, |
||
1898 | VEX_W_0F11_P_2, |
||
1899 | VEX_W_0F11_P_3, |
||
1900 | VEX_W_0F12_P_0_M_0, |
||
1901 | VEX_W_0F12_P_0_M_1, |
||
1902 | VEX_W_0F12_P_1, |
||
1903 | VEX_W_0F12_P_2, |
||
1904 | VEX_W_0F12_P_3, |
||
1905 | VEX_W_0F13_M_0, |
||
1906 | VEX_W_0F14, |
||
1907 | VEX_W_0F15, |
||
1908 | VEX_W_0F16_P_0_M_0, |
||
1909 | VEX_W_0F16_P_0_M_1, |
||
1910 | VEX_W_0F16_P_1, |
||
1911 | VEX_W_0F16_P_2, |
||
1912 | VEX_W_0F17_M_0, |
||
1913 | VEX_W_0F28, |
||
1914 | VEX_W_0F29, |
||
1915 | VEX_W_0F2B_M_0, |
||
1916 | VEX_W_0F2E_P_0, |
||
1917 | VEX_W_0F2E_P_2, |
||
1918 | VEX_W_0F2F_P_0, |
||
1919 | VEX_W_0F2F_P_2, |
||
1920 | VEX_W_0F41_P_0_LEN_1, |
||
6324 | serge | 1921 | VEX_W_0F41_P_2_LEN_1, |
5221 | serge | 1922 | VEX_W_0F42_P_0_LEN_1, |
6324 | serge | 1923 | VEX_W_0F42_P_2_LEN_1, |
5221 | serge | 1924 | VEX_W_0F44_P_0_LEN_0, |
6324 | serge | 1925 | VEX_W_0F44_P_2_LEN_0, |
5221 | serge | 1926 | VEX_W_0F45_P_0_LEN_1, |
6324 | serge | 1927 | VEX_W_0F45_P_2_LEN_1, |
5221 | serge | 1928 | VEX_W_0F46_P_0_LEN_1, |
6324 | serge | 1929 | VEX_W_0F46_P_2_LEN_1, |
5221 | serge | 1930 | VEX_W_0F47_P_0_LEN_1, |
6324 | serge | 1931 | VEX_W_0F47_P_2_LEN_1, |
1932 | VEX_W_0F4A_P_0_LEN_1, |
||
1933 | VEX_W_0F4A_P_2_LEN_1, |
||
1934 | VEX_W_0F4B_P_0_LEN_1, |
||
5221 | serge | 1935 | VEX_W_0F4B_P_2_LEN_1, |
1936 | VEX_W_0F50_M_0, |
||
1937 | VEX_W_0F51_P_0, |
||
1938 | VEX_W_0F51_P_1, |
||
1939 | VEX_W_0F51_P_2, |
||
1940 | VEX_W_0F51_P_3, |
||
1941 | VEX_W_0F52_P_0, |
||
1942 | VEX_W_0F52_P_1, |
||
1943 | VEX_W_0F53_P_0, |
||
1944 | VEX_W_0F53_P_1, |
||
1945 | VEX_W_0F58_P_0, |
||
1946 | VEX_W_0F58_P_1, |
||
1947 | VEX_W_0F58_P_2, |
||
1948 | VEX_W_0F58_P_3, |
||
1949 | VEX_W_0F59_P_0, |
||
1950 | VEX_W_0F59_P_1, |
||
1951 | VEX_W_0F59_P_2, |
||
1952 | VEX_W_0F59_P_3, |
||
1953 | VEX_W_0F5A_P_0, |
||
1954 | VEX_W_0F5A_P_1, |
||
1955 | VEX_W_0F5A_P_3, |
||
1956 | VEX_W_0F5B_P_0, |
||
1957 | VEX_W_0F5B_P_1, |
||
1958 | VEX_W_0F5B_P_2, |
||
1959 | VEX_W_0F5C_P_0, |
||
1960 | VEX_W_0F5C_P_1, |
||
1961 | VEX_W_0F5C_P_2, |
||
1962 | VEX_W_0F5C_P_3, |
||
1963 | VEX_W_0F5D_P_0, |
||
1964 | VEX_W_0F5D_P_1, |
||
1965 | VEX_W_0F5D_P_2, |
||
1966 | VEX_W_0F5D_P_3, |
||
1967 | VEX_W_0F5E_P_0, |
||
1968 | VEX_W_0F5E_P_1, |
||
1969 | VEX_W_0F5E_P_2, |
||
1970 | VEX_W_0F5E_P_3, |
||
1971 | VEX_W_0F5F_P_0, |
||
1972 | VEX_W_0F5F_P_1, |
||
1973 | VEX_W_0F5F_P_2, |
||
1974 | VEX_W_0F5F_P_3, |
||
1975 | VEX_W_0F60_P_2, |
||
1976 | VEX_W_0F61_P_2, |
||
1977 | VEX_W_0F62_P_2, |
||
1978 | VEX_W_0F63_P_2, |
||
1979 | VEX_W_0F64_P_2, |
||
1980 | VEX_W_0F65_P_2, |
||
1981 | VEX_W_0F66_P_2, |
||
1982 | VEX_W_0F67_P_2, |
||
1983 | VEX_W_0F68_P_2, |
||
1984 | VEX_W_0F69_P_2, |
||
1985 | VEX_W_0F6A_P_2, |
||
1986 | VEX_W_0F6B_P_2, |
||
1987 | VEX_W_0F6C_P_2, |
||
1988 | VEX_W_0F6D_P_2, |
||
1989 | VEX_W_0F6F_P_1, |
||
1990 | VEX_W_0F6F_P_2, |
||
1991 | VEX_W_0F70_P_1, |
||
1992 | VEX_W_0F70_P_2, |
||
1993 | VEX_W_0F70_P_3, |
||
1994 | VEX_W_0F71_R_2_P_2, |
||
1995 | VEX_W_0F71_R_4_P_2, |
||
1996 | VEX_W_0F71_R_6_P_2, |
||
1997 | VEX_W_0F72_R_2_P_2, |
||
1998 | VEX_W_0F72_R_4_P_2, |
||
1999 | VEX_W_0F72_R_6_P_2, |
||
2000 | VEX_W_0F73_R_2_P_2, |
||
2001 | VEX_W_0F73_R_3_P_2, |
||
2002 | VEX_W_0F73_R_6_P_2, |
||
2003 | VEX_W_0F73_R_7_P_2, |
||
2004 | VEX_W_0F74_P_2, |
||
2005 | VEX_W_0F75_P_2, |
||
2006 | VEX_W_0F76_P_2, |
||
2007 | VEX_W_0F77_P_0, |
||
2008 | VEX_W_0F7C_P_2, |
||
2009 | VEX_W_0F7C_P_3, |
||
2010 | VEX_W_0F7D_P_2, |
||
2011 | VEX_W_0F7D_P_3, |
||
2012 | VEX_W_0F7E_P_1, |
||
2013 | VEX_W_0F7F_P_1, |
||
2014 | VEX_W_0F7F_P_2, |
||
2015 | VEX_W_0F90_P_0_LEN_0, |
||
6324 | serge | 2016 | VEX_W_0F90_P_2_LEN_0, |
5221 | serge | 2017 | VEX_W_0F91_P_0_LEN_0, |
6324 | serge | 2018 | VEX_W_0F91_P_2_LEN_0, |
5221 | serge | 2019 | VEX_W_0F92_P_0_LEN_0, |
6324 | serge | 2020 | VEX_W_0F92_P_2_LEN_0, |
2021 | VEX_W_0F92_P_3_LEN_0, |
||
5221 | serge | 2022 | VEX_W_0F93_P_0_LEN_0, |
6324 | serge | 2023 | VEX_W_0F93_P_2_LEN_0, |
2024 | VEX_W_0F93_P_3_LEN_0, |
||
5221 | serge | 2025 | VEX_W_0F98_P_0_LEN_0, |
6324 | serge | 2026 | VEX_W_0F98_P_2_LEN_0, |
2027 | VEX_W_0F99_P_0_LEN_0, |
||
2028 | VEX_W_0F99_P_2_LEN_0, |
||
5221 | serge | 2029 | VEX_W_0FAE_R_2_M_0, |
2030 | VEX_W_0FAE_R_3_M_0, |
||
2031 | VEX_W_0FC2_P_0, |
||
2032 | VEX_W_0FC2_P_1, |
||
2033 | VEX_W_0FC2_P_2, |
||
2034 | VEX_W_0FC2_P_3, |
||
2035 | VEX_W_0FC4_P_2, |
||
2036 | VEX_W_0FC5_P_2, |
||
2037 | VEX_W_0FD0_P_2, |
||
2038 | VEX_W_0FD0_P_3, |
||
2039 | VEX_W_0FD1_P_2, |
||
2040 | VEX_W_0FD2_P_2, |
||
2041 | VEX_W_0FD3_P_2, |
||
2042 | VEX_W_0FD4_P_2, |
||
2043 | VEX_W_0FD5_P_2, |
||
2044 | VEX_W_0FD6_P_2, |
||
2045 | VEX_W_0FD7_P_2_M_1, |
||
2046 | VEX_W_0FD8_P_2, |
||
2047 | VEX_W_0FD9_P_2, |
||
2048 | VEX_W_0FDA_P_2, |
||
2049 | VEX_W_0FDB_P_2, |
||
2050 | VEX_W_0FDC_P_2, |
||
2051 | VEX_W_0FDD_P_2, |
||
2052 | VEX_W_0FDE_P_2, |
||
2053 | VEX_W_0FDF_P_2, |
||
2054 | VEX_W_0FE0_P_2, |
||
2055 | VEX_W_0FE1_P_2, |
||
2056 | VEX_W_0FE2_P_2, |
||
2057 | VEX_W_0FE3_P_2, |
||
2058 | VEX_W_0FE4_P_2, |
||
2059 | VEX_W_0FE5_P_2, |
||
2060 | VEX_W_0FE6_P_1, |
||
2061 | VEX_W_0FE6_P_2, |
||
2062 | VEX_W_0FE6_P_3, |
||
2063 | VEX_W_0FE7_P_2_M_0, |
||
2064 | VEX_W_0FE8_P_2, |
||
2065 | VEX_W_0FE9_P_2, |
||
2066 | VEX_W_0FEA_P_2, |
||
2067 | VEX_W_0FEB_P_2, |
||
2068 | VEX_W_0FEC_P_2, |
||
2069 | VEX_W_0FED_P_2, |
||
2070 | VEX_W_0FEE_P_2, |
||
2071 | VEX_W_0FEF_P_2, |
||
2072 | VEX_W_0FF0_P_3_M_0, |
||
2073 | VEX_W_0FF1_P_2, |
||
2074 | VEX_W_0FF2_P_2, |
||
2075 | VEX_W_0FF3_P_2, |
||
2076 | VEX_W_0FF4_P_2, |
||
2077 | VEX_W_0FF5_P_2, |
||
2078 | VEX_W_0FF6_P_2, |
||
2079 | VEX_W_0FF7_P_2, |
||
2080 | VEX_W_0FF8_P_2, |
||
2081 | VEX_W_0FF9_P_2, |
||
2082 | VEX_W_0FFA_P_2, |
||
2083 | VEX_W_0FFB_P_2, |
||
2084 | VEX_W_0FFC_P_2, |
||
2085 | VEX_W_0FFD_P_2, |
||
2086 | VEX_W_0FFE_P_2, |
||
2087 | VEX_W_0F3800_P_2, |
||
2088 | VEX_W_0F3801_P_2, |
||
2089 | VEX_W_0F3802_P_2, |
||
2090 | VEX_W_0F3803_P_2, |
||
2091 | VEX_W_0F3804_P_2, |
||
2092 | VEX_W_0F3805_P_2, |
||
2093 | VEX_W_0F3806_P_2, |
||
2094 | VEX_W_0F3807_P_2, |
||
2095 | VEX_W_0F3808_P_2, |
||
2096 | VEX_W_0F3809_P_2, |
||
2097 | VEX_W_0F380A_P_2, |
||
2098 | VEX_W_0F380B_P_2, |
||
2099 | VEX_W_0F380C_P_2, |
||
2100 | VEX_W_0F380D_P_2, |
||
2101 | VEX_W_0F380E_P_2, |
||
2102 | VEX_W_0F380F_P_2, |
||
2103 | VEX_W_0F3816_P_2, |
||
2104 | VEX_W_0F3817_P_2, |
||
2105 | VEX_W_0F3818_P_2, |
||
2106 | VEX_W_0F3819_P_2, |
||
2107 | VEX_W_0F381A_P_2_M_0, |
||
2108 | VEX_W_0F381C_P_2, |
||
2109 | VEX_W_0F381D_P_2, |
||
2110 | VEX_W_0F381E_P_2, |
||
2111 | VEX_W_0F3820_P_2, |
||
2112 | VEX_W_0F3821_P_2, |
||
2113 | VEX_W_0F3822_P_2, |
||
2114 | VEX_W_0F3823_P_2, |
||
2115 | VEX_W_0F3824_P_2, |
||
2116 | VEX_W_0F3825_P_2, |
||
2117 | VEX_W_0F3828_P_2, |
||
2118 | VEX_W_0F3829_P_2, |
||
2119 | VEX_W_0F382A_P_2_M_0, |
||
2120 | VEX_W_0F382B_P_2, |
||
2121 | VEX_W_0F382C_P_2_M_0, |
||
2122 | VEX_W_0F382D_P_2_M_0, |
||
2123 | VEX_W_0F382E_P_2_M_0, |
||
2124 | VEX_W_0F382F_P_2_M_0, |
||
2125 | VEX_W_0F3830_P_2, |
||
2126 | VEX_W_0F3831_P_2, |
||
2127 | VEX_W_0F3832_P_2, |
||
2128 | VEX_W_0F3833_P_2, |
||
2129 | VEX_W_0F3834_P_2, |
||
2130 | VEX_W_0F3835_P_2, |
||
2131 | VEX_W_0F3836_P_2, |
||
2132 | VEX_W_0F3837_P_2, |
||
2133 | VEX_W_0F3838_P_2, |
||
2134 | VEX_W_0F3839_P_2, |
||
2135 | VEX_W_0F383A_P_2, |
||
2136 | VEX_W_0F383B_P_2, |
||
2137 | VEX_W_0F383C_P_2, |
||
2138 | VEX_W_0F383D_P_2, |
||
2139 | VEX_W_0F383E_P_2, |
||
2140 | VEX_W_0F383F_P_2, |
||
2141 | VEX_W_0F3840_P_2, |
||
2142 | VEX_W_0F3841_P_2, |
||
2143 | VEX_W_0F3846_P_2, |
||
2144 | VEX_W_0F3858_P_2, |
||
2145 | VEX_W_0F3859_P_2, |
||
2146 | VEX_W_0F385A_P_2_M_0, |
||
2147 | VEX_W_0F3878_P_2, |
||
2148 | VEX_W_0F3879_P_2, |
||
2149 | VEX_W_0F38DB_P_2, |
||
2150 | VEX_W_0F38DC_P_2, |
||
2151 | VEX_W_0F38DD_P_2, |
||
2152 | VEX_W_0F38DE_P_2, |
||
2153 | VEX_W_0F38DF_P_2, |
||
2154 | VEX_W_0F3A00_P_2, |
||
2155 | VEX_W_0F3A01_P_2, |
||
2156 | VEX_W_0F3A02_P_2, |
||
2157 | VEX_W_0F3A04_P_2, |
||
2158 | VEX_W_0F3A05_P_2, |
||
2159 | VEX_W_0F3A06_P_2, |
||
2160 | VEX_W_0F3A08_P_2, |
||
2161 | VEX_W_0F3A09_P_2, |
||
2162 | VEX_W_0F3A0A_P_2, |
||
2163 | VEX_W_0F3A0B_P_2, |
||
2164 | VEX_W_0F3A0C_P_2, |
||
2165 | VEX_W_0F3A0D_P_2, |
||
2166 | VEX_W_0F3A0E_P_2, |
||
2167 | VEX_W_0F3A0F_P_2, |
||
2168 | VEX_W_0F3A14_P_2, |
||
2169 | VEX_W_0F3A15_P_2, |
||
2170 | VEX_W_0F3A18_P_2, |
||
2171 | VEX_W_0F3A19_P_2, |
||
2172 | VEX_W_0F3A20_P_2, |
||
2173 | VEX_W_0F3A21_P_2, |
||
2174 | VEX_W_0F3A30_P_2_LEN_0, |
||
6324 | serge | 2175 | VEX_W_0F3A31_P_2_LEN_0, |
5221 | serge | 2176 | VEX_W_0F3A32_P_2_LEN_0, |
6324 | serge | 2177 | VEX_W_0F3A33_P_2_LEN_0, |
5221 | serge | 2178 | VEX_W_0F3A38_P_2, |
2179 | VEX_W_0F3A39_P_2, |
||
2180 | VEX_W_0F3A40_P_2, |
||
2181 | VEX_W_0F3A41_P_2, |
||
2182 | VEX_W_0F3A42_P_2, |
||
2183 | VEX_W_0F3A44_P_2, |
||
2184 | VEX_W_0F3A46_P_2, |
||
2185 | VEX_W_0F3A48_P_2, |
||
2186 | VEX_W_0F3A49_P_2, |
||
2187 | VEX_W_0F3A4A_P_2, |
||
2188 | VEX_W_0F3A4B_P_2, |
||
2189 | VEX_W_0F3A4C_P_2, |
||
2190 | VEX_W_0F3A60_P_2, |
||
2191 | VEX_W_0F3A61_P_2, |
||
2192 | VEX_W_0F3A62_P_2, |
||
2193 | VEX_W_0F3A63_P_2, |
||
2194 | VEX_W_0F3ADF_P_2, |
||
2195 | |||
2196 | EVEX_W_0F10_P_0, |
||
2197 | EVEX_W_0F10_P_1_M_0, |
||
2198 | EVEX_W_0F10_P_1_M_1, |
||
2199 | EVEX_W_0F10_P_2, |
||
2200 | EVEX_W_0F10_P_3_M_0, |
||
2201 | EVEX_W_0F10_P_3_M_1, |
||
2202 | EVEX_W_0F11_P_0, |
||
2203 | EVEX_W_0F11_P_1_M_0, |
||
2204 | EVEX_W_0F11_P_1_M_1, |
||
2205 | EVEX_W_0F11_P_2, |
||
2206 | EVEX_W_0F11_P_3_M_0, |
||
2207 | EVEX_W_0F11_P_3_M_1, |
||
2208 | EVEX_W_0F12_P_0_M_0, |
||
2209 | EVEX_W_0F12_P_0_M_1, |
||
2210 | EVEX_W_0F12_P_1, |
||
2211 | EVEX_W_0F12_P_2, |
||
2212 | EVEX_W_0F12_P_3, |
||
2213 | EVEX_W_0F13_P_0, |
||
2214 | EVEX_W_0F13_P_2, |
||
2215 | EVEX_W_0F14_P_0, |
||
2216 | EVEX_W_0F14_P_2, |
||
2217 | EVEX_W_0F15_P_0, |
||
2218 | EVEX_W_0F15_P_2, |
||
2219 | EVEX_W_0F16_P_0_M_0, |
||
2220 | EVEX_W_0F16_P_0_M_1, |
||
2221 | EVEX_W_0F16_P_1, |
||
2222 | EVEX_W_0F16_P_2, |
||
2223 | EVEX_W_0F17_P_0, |
||
2224 | EVEX_W_0F17_P_2, |
||
2225 | EVEX_W_0F28_P_0, |
||
2226 | EVEX_W_0F28_P_2, |
||
2227 | EVEX_W_0F29_P_0, |
||
2228 | EVEX_W_0F29_P_2, |
||
2229 | EVEX_W_0F2A_P_1, |
||
2230 | EVEX_W_0F2A_P_3, |
||
2231 | EVEX_W_0F2B_P_0, |
||
2232 | EVEX_W_0F2B_P_2, |
||
2233 | EVEX_W_0F2E_P_0, |
||
2234 | EVEX_W_0F2E_P_2, |
||
2235 | EVEX_W_0F2F_P_0, |
||
2236 | EVEX_W_0F2F_P_2, |
||
2237 | EVEX_W_0F51_P_0, |
||
2238 | EVEX_W_0F51_P_1, |
||
2239 | EVEX_W_0F51_P_2, |
||
2240 | EVEX_W_0F51_P_3, |
||
6324 | serge | 2241 | EVEX_W_0F54_P_0, |
2242 | EVEX_W_0F54_P_2, |
||
2243 | EVEX_W_0F55_P_0, |
||
2244 | EVEX_W_0F55_P_2, |
||
2245 | EVEX_W_0F56_P_0, |
||
2246 | EVEX_W_0F56_P_2, |
||
2247 | EVEX_W_0F57_P_0, |
||
2248 | EVEX_W_0F57_P_2, |
||
5221 | serge | 2249 | EVEX_W_0F58_P_0, |
2250 | EVEX_W_0F58_P_1, |
||
2251 | EVEX_W_0F58_P_2, |
||
2252 | EVEX_W_0F58_P_3, |
||
2253 | EVEX_W_0F59_P_0, |
||
2254 | EVEX_W_0F59_P_1, |
||
2255 | EVEX_W_0F59_P_2, |
||
2256 | EVEX_W_0F59_P_3, |
||
2257 | EVEX_W_0F5A_P_0, |
||
2258 | EVEX_W_0F5A_P_1, |
||
2259 | EVEX_W_0F5A_P_2, |
||
2260 | EVEX_W_0F5A_P_3, |
||
2261 | EVEX_W_0F5B_P_0, |
||
2262 | EVEX_W_0F5B_P_1, |
||
2263 | EVEX_W_0F5B_P_2, |
||
2264 | EVEX_W_0F5C_P_0, |
||
2265 | EVEX_W_0F5C_P_1, |
||
2266 | EVEX_W_0F5C_P_2, |
||
2267 | EVEX_W_0F5C_P_3, |
||
2268 | EVEX_W_0F5D_P_0, |
||
2269 | EVEX_W_0F5D_P_1, |
||
2270 | EVEX_W_0F5D_P_2, |
||
2271 | EVEX_W_0F5D_P_3, |
||
2272 | EVEX_W_0F5E_P_0, |
||
2273 | EVEX_W_0F5E_P_1, |
||
2274 | EVEX_W_0F5E_P_2, |
||
2275 | EVEX_W_0F5E_P_3, |
||
2276 | EVEX_W_0F5F_P_0, |
||
2277 | EVEX_W_0F5F_P_1, |
||
2278 | EVEX_W_0F5F_P_2, |
||
2279 | EVEX_W_0F5F_P_3, |
||
2280 | EVEX_W_0F62_P_2, |
||
2281 | EVEX_W_0F66_P_2, |
||
2282 | EVEX_W_0F6A_P_2, |
||
6324 | serge | 2283 | EVEX_W_0F6B_P_2, |
5221 | serge | 2284 | EVEX_W_0F6C_P_2, |
2285 | EVEX_W_0F6D_P_2, |
||
2286 | EVEX_W_0F6E_P_2, |
||
2287 | EVEX_W_0F6F_P_1, |
||
2288 | EVEX_W_0F6F_P_2, |
||
6324 | serge | 2289 | EVEX_W_0F6F_P_3, |
5221 | serge | 2290 | EVEX_W_0F70_P_2, |
2291 | EVEX_W_0F72_R_2_P_2, |
||
2292 | EVEX_W_0F72_R_6_P_2, |
||
2293 | EVEX_W_0F73_R_2_P_2, |
||
2294 | EVEX_W_0F73_R_6_P_2, |
||
2295 | EVEX_W_0F76_P_2, |
||
2296 | EVEX_W_0F78_P_0, |
||
6324 | serge | 2297 | EVEX_W_0F78_P_2, |
5221 | serge | 2298 | EVEX_W_0F79_P_0, |
6324 | serge | 2299 | EVEX_W_0F79_P_2, |
5221 | serge | 2300 | EVEX_W_0F7A_P_1, |
6324 | serge | 2301 | EVEX_W_0F7A_P_2, |
5221 | serge | 2302 | EVEX_W_0F7A_P_3, |
2303 | EVEX_W_0F7B_P_1, |
||
6324 | serge | 2304 | EVEX_W_0F7B_P_2, |
5221 | serge | 2305 | EVEX_W_0F7B_P_3, |
2306 | EVEX_W_0F7E_P_1, |
||
2307 | EVEX_W_0F7E_P_2, |
||
2308 | EVEX_W_0F7F_P_1, |
||
2309 | EVEX_W_0F7F_P_2, |
||
6324 | serge | 2310 | EVEX_W_0F7F_P_3, |
5221 | serge | 2311 | EVEX_W_0FC2_P_0, |
2312 | EVEX_W_0FC2_P_1, |
||
2313 | EVEX_W_0FC2_P_2, |
||
2314 | EVEX_W_0FC2_P_3, |
||
2315 | EVEX_W_0FC6_P_0, |
||
2316 | EVEX_W_0FC6_P_2, |
||
2317 | EVEX_W_0FD2_P_2, |
||
2318 | EVEX_W_0FD3_P_2, |
||
2319 | EVEX_W_0FD4_P_2, |
||
2320 | EVEX_W_0FD6_P_2, |
||
2321 | EVEX_W_0FE6_P_1, |
||
2322 | EVEX_W_0FE6_P_2, |
||
2323 | EVEX_W_0FE6_P_3, |
||
2324 | EVEX_W_0FE7_P_2, |
||
2325 | EVEX_W_0FF2_P_2, |
||
2326 | EVEX_W_0FF3_P_2, |
||
2327 | EVEX_W_0FF4_P_2, |
||
2328 | EVEX_W_0FFA_P_2, |
||
2329 | EVEX_W_0FFB_P_2, |
||
2330 | EVEX_W_0FFE_P_2, |
||
2331 | EVEX_W_0F380C_P_2, |
||
2332 | EVEX_W_0F380D_P_2, |
||
6324 | serge | 2333 | EVEX_W_0F3810_P_1, |
2334 | EVEX_W_0F3810_P_2, |
||
5221 | serge | 2335 | EVEX_W_0F3811_P_1, |
6324 | serge | 2336 | EVEX_W_0F3811_P_2, |
5221 | serge | 2337 | EVEX_W_0F3812_P_1, |
6324 | serge | 2338 | EVEX_W_0F3812_P_2, |
5221 | serge | 2339 | EVEX_W_0F3813_P_1, |
2340 | EVEX_W_0F3813_P_2, |
||
2341 | EVEX_W_0F3814_P_1, |
||
2342 | EVEX_W_0F3815_P_1, |
||
2343 | EVEX_W_0F3818_P_2, |
||
2344 | EVEX_W_0F3819_P_2, |
||
2345 | EVEX_W_0F381A_P_2, |
||
2346 | EVEX_W_0F381B_P_2, |
||
2347 | EVEX_W_0F381E_P_2, |
||
2348 | EVEX_W_0F381F_P_2, |
||
6324 | serge | 2349 | EVEX_W_0F3820_P_1, |
5221 | serge | 2350 | EVEX_W_0F3821_P_1, |
2351 | EVEX_W_0F3822_P_1, |
||
2352 | EVEX_W_0F3823_P_1, |
||
2353 | EVEX_W_0F3824_P_1, |
||
2354 | EVEX_W_0F3825_P_1, |
||
2355 | EVEX_W_0F3825_P_2, |
||
6324 | serge | 2356 | EVEX_W_0F3826_P_1, |
2357 | EVEX_W_0F3826_P_2, |
||
2358 | EVEX_W_0F3828_P_1, |
||
5221 | serge | 2359 | EVEX_W_0F3828_P_2, |
6324 | serge | 2360 | EVEX_W_0F3829_P_1, |
5221 | serge | 2361 | EVEX_W_0F3829_P_2, |
2362 | EVEX_W_0F382A_P_1, |
||
2363 | EVEX_W_0F382A_P_2, |
||
6324 | serge | 2364 | EVEX_W_0F382B_P_2, |
2365 | EVEX_W_0F3830_P_1, |
||
5221 | serge | 2366 | EVEX_W_0F3831_P_1, |
2367 | EVEX_W_0F3832_P_1, |
||
2368 | EVEX_W_0F3833_P_1, |
||
2369 | EVEX_W_0F3834_P_1, |
||
2370 | EVEX_W_0F3835_P_1, |
||
2371 | EVEX_W_0F3835_P_2, |
||
2372 | EVEX_W_0F3837_P_2, |
||
6324 | serge | 2373 | EVEX_W_0F3838_P_1, |
2374 | EVEX_W_0F3839_P_1, |
||
5221 | serge | 2375 | EVEX_W_0F383A_P_1, |
2376 | EVEX_W_0F3840_P_2, |
||
2377 | EVEX_W_0F3858_P_2, |
||
2378 | EVEX_W_0F3859_P_2, |
||
2379 | EVEX_W_0F385A_P_2, |
||
2380 | EVEX_W_0F385B_P_2, |
||
6324 | serge | 2381 | EVEX_W_0F3866_P_2, |
2382 | EVEX_W_0F3875_P_2, |
||
2383 | EVEX_W_0F3878_P_2, |
||
2384 | EVEX_W_0F3879_P_2, |
||
2385 | EVEX_W_0F387A_P_2, |
||
2386 | EVEX_W_0F387B_P_2, |
||
2387 | EVEX_W_0F387D_P_2, |
||
2388 | EVEX_W_0F3883_P_2, |
||
2389 | EVEX_W_0F388D_P_2, |
||
5221 | serge | 2390 | EVEX_W_0F3891_P_2, |
2391 | EVEX_W_0F3893_P_2, |
||
2392 | EVEX_W_0F38A1_P_2, |
||
2393 | EVEX_W_0F38A3_P_2, |
||
2394 | EVEX_W_0F38C7_R_1_P_2, |
||
2395 | EVEX_W_0F38C7_R_2_P_2, |
||
2396 | EVEX_W_0F38C7_R_5_P_2, |
||
2397 | EVEX_W_0F38C7_R_6_P_2, |
||
2398 | |||
2399 | EVEX_W_0F3A00_P_2, |
||
2400 | EVEX_W_0F3A01_P_2, |
||
2401 | EVEX_W_0F3A04_P_2, |
||
2402 | EVEX_W_0F3A05_P_2, |
||
2403 | EVEX_W_0F3A08_P_2, |
||
2404 | EVEX_W_0F3A09_P_2, |
||
2405 | EVEX_W_0F3A0A_P_2, |
||
2406 | EVEX_W_0F3A0B_P_2, |
||
6324 | serge | 2407 | EVEX_W_0F3A16_P_2, |
5221 | serge | 2408 | EVEX_W_0F3A18_P_2, |
2409 | EVEX_W_0F3A19_P_2, |
||
2410 | EVEX_W_0F3A1A_P_2, |
||
2411 | EVEX_W_0F3A1B_P_2, |
||
2412 | EVEX_W_0F3A1D_P_2, |
||
2413 | EVEX_W_0F3A21_P_2, |
||
6324 | serge | 2414 | EVEX_W_0F3A22_P_2, |
5221 | serge | 2415 | EVEX_W_0F3A23_P_2, |
2416 | EVEX_W_0F3A38_P_2, |
||
2417 | EVEX_W_0F3A39_P_2, |
||
2418 | EVEX_W_0F3A3A_P_2, |
||
2419 | EVEX_W_0F3A3B_P_2, |
||
6324 | serge | 2420 | EVEX_W_0F3A3E_P_2, |
2421 | EVEX_W_0F3A3F_P_2, |
||
2422 | EVEX_W_0F3A42_P_2, |
||
5221 | serge | 2423 | EVEX_W_0F3A43_P_2, |
6324 | serge | 2424 | EVEX_W_0F3A50_P_2, |
2425 | EVEX_W_0F3A51_P_2, |
||
2426 | EVEX_W_0F3A56_P_2, |
||
2427 | EVEX_W_0F3A57_P_2, |
||
2428 | EVEX_W_0F3A66_P_2, |
||
2429 | EVEX_W_0F3A67_P_2 |
||
5221 | serge | 2430 | }; |
2431 | |||
2432 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
||
2433 | |||
2434 | struct dis386 { |
||
2435 | const char *name; |
||
2436 | struct |
||
2437 | { |
||
2438 | op_rtn rtn; |
||
2439 | int bytemode; |
||
2440 | } op[MAX_OPERANDS]; |
||
6324 | serge | 2441 | unsigned int prefix_requirement; |
5221 | serge | 2442 | }; |
2443 | |||
2444 | /* Upper case letters in the instruction names here are macros. |
||
2445 | 'A' => print 'b' if no register operands or suffix_always is true |
||
2446 | 'B' => print 'b' if suffix_always is true |
||
2447 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
||
2448 | size prefix |
||
2449 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
||
2450 | suffix_always is true |
||
2451 | 'E' => print 'e' if 32-bit form of jcxz |
||
2452 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
||
2453 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
||
2454 | 'H' => print ",pt" or ",pn" branch hint |
||
2455 | 'I' => honor following macro letter even in Intel mode (implemented only |
||
2456 | for some of the macro letters) |
||
2457 | 'J' => print 'l' |
||
2458 | 'K' => print 'd' or 'q' if rex prefix is present. |
||
2459 | 'L' => print 'l' if suffix_always is true |
||
2460 | 'M' => print 'r' if intel_mnemonic is false. |
||
2461 | 'N' => print 'n' if instruction has no wait "prefix" |
||
2462 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
||
2463 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
||
2464 | or suffix_always is true. print 'q' if rex prefix is present. |
||
2465 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
||
2466 | is true |
||
2467 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
||
2468 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
||
6324 | serge | 2469 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2470 | prefix and behave as 'P' otherwise |
||
2471 | 'U' => print 'q' in 64bit mode if instruction has no operand size |
||
2472 | prefix and behave as 'Q' otherwise |
||
2473 | 'V' => print 'q' in 64bit mode if instruction has no operand size |
||
2474 | prefix and behave as 'S' otherwise |
||
5221 | serge | 2475 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
2476 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
||
2477 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
||
2478 | suffix_always is true. |
||
2479 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
||
2480 | '!' => change condition from true to false or from false to true. |
||
2481 | '%' => add 1 upper case letter to the macro. |
||
6324 | serge | 2482 | '^' => print 'w' or 'l' depending on operand size prefix or |
2483 | suffix_always is true (lcall/ljmp). |
||
2484 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
||
2485 | on operand size prefix. |
||
5221 | serge | 2486 | |
2487 | 2 upper case letter macros: |
||
6324 | serge | 2488 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2489 | operands and no broadcast. |
||
2490 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no |
||
2491 | register operands and no broadcast. |
||
5221 | serge | 2492 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2493 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
||
2494 | or suffix_always is true |
||
2495 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
||
2496 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
||
2497 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
||
2498 | "LW" => print 'd', 'q' depending on the VEX.W bit |
||
6324 | serge | 2499 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2500 | an operand size prefix, or suffix_always is true. print |
||
2501 | 'q' if rex prefix is present. |
||
5221 | serge | 2502 | |
2503 | Many of the above letters print nothing in Intel mode. See "putop" |
||
2504 | for the details. |
||
2505 | |||
2506 | Braces '{' and '}', and vertical bars '|', indicate alternative |
||
2507 | mnemonic strings for AT&T and Intel. */ |
||
2508 | |||
2509 | static const struct dis386 dis386[] = { |
||
2510 | /* 00 */ |
||
6324 | serge | 2511 | { "addB", { Ebh1, Gb }, 0 }, |
2512 | { "addS", { Evh1, Gv }, 0 }, |
||
2513 | { "addB", { Gb, EbS }, 0 }, |
||
2514 | { "addS", { Gv, EvS }, 0 }, |
||
2515 | { "addB", { AL, Ib }, 0 }, |
||
2516 | { "addS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2517 | { X86_64_TABLE (X86_64_06) }, |
2518 | { X86_64_TABLE (X86_64_07) }, |
||
2519 | /* 08 */ |
||
6324 | serge | 2520 | { "orB", { Ebh1, Gb }, 0 }, |
2521 | { "orS", { Evh1, Gv }, 0 }, |
||
2522 | { "orB", { Gb, EbS }, 0 }, |
||
2523 | { "orS", { Gv, EvS }, 0 }, |
||
2524 | { "orB", { AL, Ib }, 0 }, |
||
2525 | { "orS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2526 | { X86_64_TABLE (X86_64_0D) }, |
2527 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
||
2528 | /* 10 */ |
||
6324 | serge | 2529 | { "adcB", { Ebh1, Gb }, 0 }, |
2530 | { "adcS", { Evh1, Gv }, 0 }, |
||
2531 | { "adcB", { Gb, EbS }, 0 }, |
||
2532 | { "adcS", { Gv, EvS }, 0 }, |
||
2533 | { "adcB", { AL, Ib }, 0 }, |
||
2534 | { "adcS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2535 | { X86_64_TABLE (X86_64_16) }, |
2536 | { X86_64_TABLE (X86_64_17) }, |
||
2537 | /* 18 */ |
||
6324 | serge | 2538 | { "sbbB", { Ebh1, Gb }, 0 }, |
2539 | { "sbbS", { Evh1, Gv }, 0 }, |
||
2540 | { "sbbB", { Gb, EbS }, 0 }, |
||
2541 | { "sbbS", { Gv, EvS }, 0 }, |
||
2542 | { "sbbB", { AL, Ib }, 0 }, |
||
2543 | { "sbbS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2544 | { X86_64_TABLE (X86_64_1E) }, |
2545 | { X86_64_TABLE (X86_64_1F) }, |
||
2546 | /* 20 */ |
||
6324 | serge | 2547 | { "andB", { Ebh1, Gb }, 0 }, |
2548 | { "andS", { Evh1, Gv }, 0 }, |
||
2549 | { "andB", { Gb, EbS }, 0 }, |
||
2550 | { "andS", { Gv, EvS }, 0 }, |
||
2551 | { "andB", { AL, Ib }, 0 }, |
||
2552 | { "andS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2553 | { Bad_Opcode }, /* SEG ES prefix */ |
2554 | { X86_64_TABLE (X86_64_27) }, |
||
2555 | /* 28 */ |
||
6324 | serge | 2556 | { "subB", { Ebh1, Gb }, 0 }, |
2557 | { "subS", { Evh1, Gv }, 0 }, |
||
2558 | { "subB", { Gb, EbS }, 0 }, |
||
2559 | { "subS", { Gv, EvS }, 0 }, |
||
2560 | { "subB", { AL, Ib }, 0 }, |
||
2561 | { "subS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2562 | { Bad_Opcode }, /* SEG CS prefix */ |
2563 | { X86_64_TABLE (X86_64_2F) }, |
||
2564 | /* 30 */ |
||
6324 | serge | 2565 | { "xorB", { Ebh1, Gb }, 0 }, |
2566 | { "xorS", { Evh1, Gv }, 0 }, |
||
2567 | { "xorB", { Gb, EbS }, 0 }, |
||
2568 | { "xorS", { Gv, EvS }, 0 }, |
||
2569 | { "xorB", { AL, Ib }, 0 }, |
||
2570 | { "xorS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2571 | { Bad_Opcode }, /* SEG SS prefix */ |
2572 | { X86_64_TABLE (X86_64_37) }, |
||
2573 | /* 38 */ |
||
6324 | serge | 2574 | { "cmpB", { Eb, Gb }, 0 }, |
2575 | { "cmpS", { Ev, Gv }, 0 }, |
||
2576 | { "cmpB", { Gb, EbS }, 0 }, |
||
2577 | { "cmpS", { Gv, EvS }, 0 }, |
||
2578 | { "cmpB", { AL, Ib }, 0 }, |
||
2579 | { "cmpS", { eAX, Iv }, 0 }, |
||
5221 | serge | 2580 | { Bad_Opcode }, /* SEG DS prefix */ |
2581 | { X86_64_TABLE (X86_64_3F) }, |
||
2582 | /* 40 */ |
||
6324 | serge | 2583 | { "inc{S|}", { RMeAX }, 0 }, |
2584 | { "inc{S|}", { RMeCX }, 0 }, |
||
2585 | { "inc{S|}", { RMeDX }, 0 }, |
||
2586 | { "inc{S|}", { RMeBX }, 0 }, |
||
2587 | { "inc{S|}", { RMeSP }, 0 }, |
||
2588 | { "inc{S|}", { RMeBP }, 0 }, |
||
2589 | { "inc{S|}", { RMeSI }, 0 }, |
||
2590 | { "inc{S|}", { RMeDI }, 0 }, |
||
5221 | serge | 2591 | /* 48 */ |
6324 | serge | 2592 | { "dec{S|}", { RMeAX }, 0 }, |
2593 | { "dec{S|}", { RMeCX }, 0 }, |
||
2594 | { "dec{S|}", { RMeDX }, 0 }, |
||
2595 | { "dec{S|}", { RMeBX }, 0 }, |
||
2596 | { "dec{S|}", { RMeSP }, 0 }, |
||
2597 | { "dec{S|}", { RMeBP }, 0 }, |
||
2598 | { "dec{S|}", { RMeSI }, 0 }, |
||
2599 | { "dec{S|}", { RMeDI }, 0 }, |
||
5221 | serge | 2600 | /* 50 */ |
6324 | serge | 2601 | { "pushV", { RMrAX }, 0 }, |
2602 | { "pushV", { RMrCX }, 0 }, |
||
2603 | { "pushV", { RMrDX }, 0 }, |
||
2604 | { "pushV", { RMrBX }, 0 }, |
||
2605 | { "pushV", { RMrSP }, 0 }, |
||
2606 | { "pushV", { RMrBP }, 0 }, |
||
2607 | { "pushV", { RMrSI }, 0 }, |
||
2608 | { "pushV", { RMrDI }, 0 }, |
||
5221 | serge | 2609 | /* 58 */ |
6324 | serge | 2610 | { "popV", { RMrAX }, 0 }, |
2611 | { "popV", { RMrCX }, 0 }, |
||
2612 | { "popV", { RMrDX }, 0 }, |
||
2613 | { "popV", { RMrBX }, 0 }, |
||
2614 | { "popV", { RMrSP }, 0 }, |
||
2615 | { "popV", { RMrBP }, 0 }, |
||
2616 | { "popV", { RMrSI }, 0 }, |
||
2617 | { "popV", { RMrDI }, 0 }, |
||
5221 | serge | 2618 | /* 60 */ |
2619 | { X86_64_TABLE (X86_64_60) }, |
||
2620 | { X86_64_TABLE (X86_64_61) }, |
||
2621 | { X86_64_TABLE (X86_64_62) }, |
||
2622 | { X86_64_TABLE (X86_64_63) }, |
||
2623 | { Bad_Opcode }, /* seg fs */ |
||
2624 | { Bad_Opcode }, /* seg gs */ |
||
2625 | { Bad_Opcode }, /* op size prefix */ |
||
2626 | { Bad_Opcode }, /* adr size prefix */ |
||
2627 | /* 68 */ |
||
6324 | serge | 2628 | { "pushT", { sIv }, 0 }, |
2629 | { "imulS", { Gv, Ev, Iv }, 0 }, |
||
2630 | { "pushT", { sIbT }, 0 }, |
||
2631 | { "imulS", { Gv, Ev, sIb }, 0 }, |
||
2632 | { "ins{b|}", { Ybr, indirDX }, 0 }, |
||
5221 | serge | 2633 | { X86_64_TABLE (X86_64_6D) }, |
6324 | serge | 2634 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
5221 | serge | 2635 | { X86_64_TABLE (X86_64_6F) }, |
2636 | /* 70 */ |
||
6324 | serge | 2637 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2638 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2639 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2640 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2641 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2642 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2643 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2644 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, |
||
5221 | serge | 2645 | /* 78 */ |
6324 | serge | 2646 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2647 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2648 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2649 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2650 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2651 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2652 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, |
||
2653 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, |
||
5221 | serge | 2654 | /* 80 */ |
2655 | { REG_TABLE (REG_80) }, |
||
2656 | { REG_TABLE (REG_81) }, |
||
2657 | { Bad_Opcode }, |
||
2658 | { REG_TABLE (REG_82) }, |
||
6324 | serge | 2659 | { "testB", { Eb, Gb }, 0 }, |
2660 | { "testS", { Ev, Gv }, 0 }, |
||
2661 | { "xchgB", { Ebh2, Gb }, 0 }, |
||
2662 | { "xchgS", { Evh2, Gv }, 0 }, |
||
5221 | serge | 2663 | /* 88 */ |
6324 | serge | 2664 | { "movB", { Ebh3, Gb }, 0 }, |
2665 | { "movS", { Evh3, Gv }, 0 }, |
||
2666 | { "movB", { Gb, EbS }, 0 }, |
||
2667 | { "movS", { Gv, EvS }, 0 }, |
||
2668 | { "movD", { Sv, Sw }, 0 }, |
||
5221 | serge | 2669 | { MOD_TABLE (MOD_8D) }, |
6324 | serge | 2670 | { "movD", { Sw, Sv }, 0 }, |
5221 | serge | 2671 | { REG_TABLE (REG_8F) }, |
2672 | /* 90 */ |
||
2673 | { PREFIX_TABLE (PREFIX_90) }, |
||
6324 | serge | 2674 | { "xchgS", { RMeCX, eAX }, 0 }, |
2675 | { "xchgS", { RMeDX, eAX }, 0 }, |
||
2676 | { "xchgS", { RMeBX, eAX }, 0 }, |
||
2677 | { "xchgS", { RMeSP, eAX }, 0 }, |
||
2678 | { "xchgS", { RMeBP, eAX }, 0 }, |
||
2679 | { "xchgS", { RMeSI, eAX }, 0 }, |
||
2680 | { "xchgS", { RMeDI, eAX }, 0 }, |
||
5221 | serge | 2681 | /* 98 */ |
6324 | serge | 2682 | { "cW{t|}R", { XX }, 0 }, |
2683 | { "cR{t|}O", { XX }, 0 }, |
||
5221 | serge | 2684 | { X86_64_TABLE (X86_64_9A) }, |
2685 | { Bad_Opcode }, /* fwait */ |
||
6324 | serge | 2686 | { "pushfT", { XX }, 0 }, |
2687 | { "popfT", { XX }, 0 }, |
||
2688 | { "sahf", { XX }, 0 }, |
||
2689 | { "lahf", { XX }, 0 }, |
||
5221 | serge | 2690 | /* a0 */ |
6324 | serge | 2691 | { "mov%LB", { AL, Ob }, 0 }, |
2692 | { "mov%LS", { eAX, Ov }, 0 }, |
||
2693 | { "mov%LB", { Ob, AL }, 0 }, |
||
2694 | { "mov%LS", { Ov, eAX }, 0 }, |
||
2695 | { "movs{b|}", { Ybr, Xb }, 0 }, |
||
2696 | { "movs{R|}", { Yvr, Xv }, 0 }, |
||
2697 | { "cmps{b|}", { Xb, Yb }, 0 }, |
||
2698 | { "cmps{R|}", { Xv, Yv }, 0 }, |
||
5221 | serge | 2699 | /* a8 */ |
6324 | serge | 2700 | { "testB", { AL, Ib }, 0 }, |
2701 | { "testS", { eAX, Iv }, 0 }, |
||
2702 | { "stosB", { Ybr, AL }, 0 }, |
||
2703 | { "stosS", { Yvr, eAX }, 0 }, |
||
2704 | { "lodsB", { ALr, Xb }, 0 }, |
||
2705 | { "lodsS", { eAXr, Xv }, 0 }, |
||
2706 | { "scasB", { AL, Yb }, 0 }, |
||
2707 | { "scasS", { eAX, Yv }, 0 }, |
||
5221 | serge | 2708 | /* b0 */ |
6324 | serge | 2709 | { "movB", { RMAL, Ib }, 0 }, |
2710 | { "movB", { RMCL, Ib }, 0 }, |
||
2711 | { "movB", { RMDL, Ib }, 0 }, |
||
2712 | { "movB", { RMBL, Ib }, 0 }, |
||
2713 | { "movB", { RMAH, Ib }, 0 }, |
||
2714 | { "movB", { RMCH, Ib }, 0 }, |
||
2715 | { "movB", { RMDH, Ib }, 0 }, |
||
2716 | { "movB", { RMBH, Ib }, 0 }, |
||
5221 | serge | 2717 | /* b8 */ |
6324 | serge | 2718 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2719 | { "mov%LV", { RMeCX, Iv64 }, 0 }, |
||
2720 | { "mov%LV", { RMeDX, Iv64 }, 0 }, |
||
2721 | { "mov%LV", { RMeBX, Iv64 }, 0 }, |
||
2722 | { "mov%LV", { RMeSP, Iv64 }, 0 }, |
||
2723 | { "mov%LV", { RMeBP, Iv64 }, 0 }, |
||
2724 | { "mov%LV", { RMeSI, Iv64 }, 0 }, |
||
2725 | { "mov%LV", { RMeDI, Iv64 }, 0 }, |
||
5221 | serge | 2726 | /* c0 */ |
2727 | { REG_TABLE (REG_C0) }, |
||
2728 | { REG_TABLE (REG_C1) }, |
||
6324 | serge | 2729 | { "retT", { Iw, BND }, 0 }, |
2730 | { "retT", { BND }, 0 }, |
||
5221 | serge | 2731 | { X86_64_TABLE (X86_64_C4) }, |
2732 | { X86_64_TABLE (X86_64_C5) }, |
||
2733 | { REG_TABLE (REG_C6) }, |
||
2734 | { REG_TABLE (REG_C7) }, |
||
2735 | /* c8 */ |
||
6324 | serge | 2736 | { "enterT", { Iw, Ib }, 0 }, |
2737 | { "leaveT", { XX }, 0 }, |
||
2738 | { "Jret{|f}P", { Iw }, 0 }, |
||
2739 | { "Jret{|f}P", { XX }, 0 }, |
||
2740 | { "int3", { XX }, 0 }, |
||
2741 | { "int", { Ib }, 0 }, |
||
5221 | serge | 2742 | { X86_64_TABLE (X86_64_CE) }, |
6324 | serge | 2743 | { "iret%LP", { XX }, 0 }, |
5221 | serge | 2744 | /* d0 */ |
2745 | { REG_TABLE (REG_D0) }, |
||
2746 | { REG_TABLE (REG_D1) }, |
||
2747 | { REG_TABLE (REG_D2) }, |
||
2748 | { REG_TABLE (REG_D3) }, |
||
2749 | { X86_64_TABLE (X86_64_D4) }, |
||
2750 | { X86_64_TABLE (X86_64_D5) }, |
||
2751 | { Bad_Opcode }, |
||
6324 | serge | 2752 | { "xlat", { DSBX }, 0 }, |
5221 | serge | 2753 | /* d8 */ |
2754 | { FLOAT }, |
||
2755 | { FLOAT }, |
||
2756 | { FLOAT }, |
||
2757 | { FLOAT }, |
||
2758 | { FLOAT }, |
||
2759 | { FLOAT }, |
||
2760 | { FLOAT }, |
||
2761 | { FLOAT }, |
||
2762 | /* e0 */ |
||
6324 | serge | 2763 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2764 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
||
2765 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
||
2766 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, |
||
2767 | { "inB", { AL, Ib }, 0 }, |
||
2768 | { "inG", { zAX, Ib }, 0 }, |
||
2769 | { "outB", { Ib, AL }, 0 }, |
||
2770 | { "outG", { Ib, zAX }, 0 }, |
||
5221 | serge | 2771 | /* e8 */ |
6324 | serge | 2772 | { X86_64_TABLE (X86_64_E8) }, |
2773 | { X86_64_TABLE (X86_64_E9) }, |
||
5221 | serge | 2774 | { X86_64_TABLE (X86_64_EA) }, |
6324 | serge | 2775 | { "jmp", { Jb, BND }, 0 }, |
2776 | { "inB", { AL, indirDX }, 0 }, |
||
2777 | { "inG", { zAX, indirDX }, 0 }, |
||
2778 | { "outB", { indirDX, AL }, 0 }, |
||
2779 | { "outG", { indirDX, zAX }, 0 }, |
||
5221 | serge | 2780 | /* f0 */ |
2781 | { Bad_Opcode }, /* lock prefix */ |
||
6324 | serge | 2782 | { "icebp", { XX }, 0 }, |
5221 | serge | 2783 | { Bad_Opcode }, /* repne */ |
2784 | { Bad_Opcode }, /* repz */ |
||
6324 | serge | 2785 | { "hlt", { XX }, 0 }, |
2786 | { "cmc", { XX }, 0 }, |
||
5221 | serge | 2787 | { REG_TABLE (REG_F6) }, |
2788 | { REG_TABLE (REG_F7) }, |
||
2789 | /* f8 */ |
||
6324 | serge | 2790 | { "clc", { XX }, 0 }, |
2791 | { "stc", { XX }, 0 }, |
||
2792 | { "cli", { XX }, 0 }, |
||
2793 | { "sti", { XX }, 0 }, |
||
2794 | { "cld", { XX }, 0 }, |
||
2795 | { "std", { XX }, 0 }, |
||
5221 | serge | 2796 | { REG_TABLE (REG_FE) }, |
2797 | { REG_TABLE (REG_FF) }, |
||
2798 | }; |
||
2799 | |||
2800 | static const struct dis386 dis386_twobyte[] = { |
||
2801 | /* 00 */ |
||
2802 | { REG_TABLE (REG_0F00 ) }, |
||
2803 | { REG_TABLE (REG_0F01 ) }, |
||
6324 | serge | 2804 | { "larS", { Gv, Ew }, 0 }, |
2805 | { "lslS", { Gv, Ew }, 0 }, |
||
5221 | serge | 2806 | { Bad_Opcode }, |
6324 | serge | 2807 | { "syscall", { XX }, 0 }, |
2808 | { "clts", { XX }, 0 }, |
||
2809 | { "sysret%LP", { XX }, 0 }, |
||
5221 | serge | 2810 | /* 08 */ |
6324 | serge | 2811 | { "invd", { XX }, 0 }, |
2812 | { "wbinvd", { XX }, 0 }, |
||
5221 | serge | 2813 | { Bad_Opcode }, |
6324 | serge | 2814 | { "ud2", { XX }, 0 }, |
5221 | serge | 2815 | { Bad_Opcode }, |
2816 | { REG_TABLE (REG_0F0D) }, |
||
6324 | serge | 2817 | { "femms", { XX }, 0 }, |
2818 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ |
||
5221 | serge | 2819 | /* 10 */ |
2820 | { PREFIX_TABLE (PREFIX_0F10) }, |
||
2821 | { PREFIX_TABLE (PREFIX_0F11) }, |
||
2822 | { PREFIX_TABLE (PREFIX_0F12) }, |
||
2823 | { MOD_TABLE (MOD_0F13) }, |
||
6324 | serge | 2824 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2825 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 2826 | { PREFIX_TABLE (PREFIX_0F16) }, |
2827 | { MOD_TABLE (MOD_0F17) }, |
||
2828 | /* 18 */ |
||
2829 | { REG_TABLE (REG_0F18) }, |
||
6324 | serge | 2830 | { "nopQ", { Ev }, 0 }, |
5221 | serge | 2831 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2832 | { PREFIX_TABLE (PREFIX_0F1B) }, |
||
6324 | serge | 2833 | { "nopQ", { Ev }, 0 }, |
2834 | { "nopQ", { Ev }, 0 }, |
||
2835 | { "nopQ", { Ev }, 0 }, |
||
2836 | { "nopQ", { Ev }, 0 }, |
||
5221 | serge | 2837 | /* 20 */ |
6324 | serge | 2838 | { "movZ", { Rm, Cm }, 0 }, |
2839 | { "movZ", { Rm, Dm }, 0 }, |
||
2840 | { "movZ", { Cm, Rm }, 0 }, |
||
2841 | { "movZ", { Dm, Rm }, 0 }, |
||
5221 | serge | 2842 | { MOD_TABLE (MOD_0F24) }, |
2843 | { Bad_Opcode }, |
||
2844 | { MOD_TABLE (MOD_0F26) }, |
||
2845 | { Bad_Opcode }, |
||
2846 | /* 28 */ |
||
6324 | serge | 2847 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2848 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, |
||
5221 | serge | 2849 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2850 | { PREFIX_TABLE (PREFIX_0F2B) }, |
||
2851 | { PREFIX_TABLE (PREFIX_0F2C) }, |
||
2852 | { PREFIX_TABLE (PREFIX_0F2D) }, |
||
2853 | { PREFIX_TABLE (PREFIX_0F2E) }, |
||
2854 | { PREFIX_TABLE (PREFIX_0F2F) }, |
||
2855 | /* 30 */ |
||
6324 | serge | 2856 | { "wrmsr", { XX }, 0 }, |
2857 | { "rdtsc", { XX }, 0 }, |
||
2858 | { "rdmsr", { XX }, 0 }, |
||
2859 | { "rdpmc", { XX }, 0 }, |
||
2860 | { "sysenter", { XX }, 0 }, |
||
2861 | { "sysexit", { XX }, 0 }, |
||
5221 | serge | 2862 | { Bad_Opcode }, |
6324 | serge | 2863 | { "getsec", { XX }, 0 }, |
5221 | serge | 2864 | /* 38 */ |
6324 | serge | 2865 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
5221 | serge | 2866 | { Bad_Opcode }, |
6324 | serge | 2867 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
5221 | serge | 2868 | { Bad_Opcode }, |
2869 | { Bad_Opcode }, |
||
2870 | { Bad_Opcode }, |
||
2871 | { Bad_Opcode }, |
||
2872 | { Bad_Opcode }, |
||
2873 | /* 40 */ |
||
6324 | serge | 2874 | { "cmovoS", { Gv, Ev }, 0 }, |
2875 | { "cmovnoS", { Gv, Ev }, 0 }, |
||
2876 | { "cmovbS", { Gv, Ev }, 0 }, |
||
2877 | { "cmovaeS", { Gv, Ev }, 0 }, |
||
2878 | { "cmoveS", { Gv, Ev }, 0 }, |
||
2879 | { "cmovneS", { Gv, Ev }, 0 }, |
||
2880 | { "cmovbeS", { Gv, Ev }, 0 }, |
||
2881 | { "cmovaS", { Gv, Ev }, 0 }, |
||
5221 | serge | 2882 | /* 48 */ |
6324 | serge | 2883 | { "cmovsS", { Gv, Ev }, 0 }, |
2884 | { "cmovnsS", { Gv, Ev }, 0 }, |
||
2885 | { "cmovpS", { Gv, Ev }, 0 }, |
||
2886 | { "cmovnpS", { Gv, Ev }, 0 }, |
||
2887 | { "cmovlS", { Gv, Ev }, 0 }, |
||
2888 | { "cmovgeS", { Gv, Ev }, 0 }, |
||
2889 | { "cmovleS", { Gv, Ev }, 0 }, |
||
2890 | { "cmovgS", { Gv, Ev }, 0 }, |
||
5221 | serge | 2891 | /* 50 */ |
2892 | { MOD_TABLE (MOD_0F51) }, |
||
2893 | { PREFIX_TABLE (PREFIX_0F51) }, |
||
2894 | { PREFIX_TABLE (PREFIX_0F52) }, |
||
2895 | { PREFIX_TABLE (PREFIX_0F53) }, |
||
6324 | serge | 2896 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2897 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, |
||
2898 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, |
||
2899 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 2900 | /* 58 */ |
2901 | { PREFIX_TABLE (PREFIX_0F58) }, |
||
2902 | { PREFIX_TABLE (PREFIX_0F59) }, |
||
2903 | { PREFIX_TABLE (PREFIX_0F5A) }, |
||
2904 | { PREFIX_TABLE (PREFIX_0F5B) }, |
||
2905 | { PREFIX_TABLE (PREFIX_0F5C) }, |
||
2906 | { PREFIX_TABLE (PREFIX_0F5D) }, |
||
2907 | { PREFIX_TABLE (PREFIX_0F5E) }, |
||
2908 | { PREFIX_TABLE (PREFIX_0F5F) }, |
||
2909 | /* 60 */ |
||
2910 | { PREFIX_TABLE (PREFIX_0F60) }, |
||
2911 | { PREFIX_TABLE (PREFIX_0F61) }, |
||
2912 | { PREFIX_TABLE (PREFIX_0F62) }, |
||
6324 | serge | 2913 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2914 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, |
||
2915 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, |
||
2916 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, |
||
2917 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 2918 | /* 68 */ |
6324 | serge | 2919 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2920 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, |
||
2921 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, |
||
2922 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 2923 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2924 | { PREFIX_TABLE (PREFIX_0F6D) }, |
||
6324 | serge | 2925 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
5221 | serge | 2926 | { PREFIX_TABLE (PREFIX_0F6F) }, |
2927 | /* 70 */ |
||
2928 | { PREFIX_TABLE (PREFIX_0F70) }, |
||
2929 | { REG_TABLE (REG_0F71) }, |
||
2930 | { REG_TABLE (REG_0F72) }, |
||
2931 | { REG_TABLE (REG_0F73) }, |
||
6324 | serge | 2932 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2933 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, |
||
2934 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, |
||
2935 | { "emms", { XX }, PREFIX_OPCODE }, |
||
5221 | serge | 2936 | /* 78 */ |
2937 | { PREFIX_TABLE (PREFIX_0F78) }, |
||
2938 | { PREFIX_TABLE (PREFIX_0F79) }, |
||
2939 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
||
2940 | { Bad_Opcode }, |
||
2941 | { PREFIX_TABLE (PREFIX_0F7C) }, |
||
2942 | { PREFIX_TABLE (PREFIX_0F7D) }, |
||
2943 | { PREFIX_TABLE (PREFIX_0F7E) }, |
||
2944 | { PREFIX_TABLE (PREFIX_0F7F) }, |
||
2945 | /* 80 */ |
||
6324 | serge | 2946 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2947 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2948 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2949 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2950 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2951 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2952 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2953 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, |
||
5221 | serge | 2954 | /* 88 */ |
6324 | serge | 2955 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2956 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2957 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2958 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2959 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2960 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2961 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, |
||
2962 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, |
||
5221 | serge | 2963 | /* 90 */ |
6324 | serge | 2964 | { "seto", { Eb }, 0 }, |
2965 | { "setno", { Eb }, 0 }, |
||
2966 | { "setb", { Eb }, 0 }, |
||
2967 | { "setae", { Eb }, 0 }, |
||
2968 | { "sete", { Eb }, 0 }, |
||
2969 | { "setne", { Eb }, 0 }, |
||
2970 | { "setbe", { Eb }, 0 }, |
||
2971 | { "seta", { Eb }, 0 }, |
||
5221 | serge | 2972 | /* 98 */ |
6324 | serge | 2973 | { "sets", { Eb }, 0 }, |
2974 | { "setns", { Eb }, 0 }, |
||
2975 | { "setp", { Eb }, 0 }, |
||
2976 | { "setnp", { Eb }, 0 }, |
||
2977 | { "setl", { Eb }, 0 }, |
||
2978 | { "setge", { Eb }, 0 }, |
||
2979 | { "setle", { Eb }, 0 }, |
||
2980 | { "setg", { Eb }, 0 }, |
||
5221 | serge | 2981 | /* a0 */ |
6324 | serge | 2982 | { "pushT", { fs }, 0 }, |
2983 | { "popT", { fs }, 0 }, |
||
2984 | { "cpuid", { XX }, 0 }, |
||
2985 | { "btS", { Ev, Gv }, 0 }, |
||
2986 | { "shldS", { Ev, Gv, Ib }, 0 }, |
||
2987 | { "shldS", { Ev, Gv, CL }, 0 }, |
||
5221 | serge | 2988 | { REG_TABLE (REG_0FA6) }, |
2989 | { REG_TABLE (REG_0FA7) }, |
||
2990 | /* a8 */ |
||
6324 | serge | 2991 | { "pushT", { gs }, 0 }, |
2992 | { "popT", { gs }, 0 }, |
||
2993 | { "rsm", { XX }, 0 }, |
||
2994 | { "btsS", { Evh1, Gv }, 0 }, |
||
2995 | { "shrdS", { Ev, Gv, Ib }, 0 }, |
||
2996 | { "shrdS", { Ev, Gv, CL }, 0 }, |
||
5221 | serge | 2997 | { REG_TABLE (REG_0FAE) }, |
6324 | serge | 2998 | { "imulS", { Gv, Ev }, 0 }, |
5221 | serge | 2999 | /* b0 */ |
6324 | serge | 3000 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3001 | { "cmpxchgS", { Evh1, Gv }, 0 }, |
||
5221 | serge | 3002 | { MOD_TABLE (MOD_0FB2) }, |
6324 | serge | 3003 | { "btrS", { Evh1, Gv }, 0 }, |
5221 | serge | 3004 | { MOD_TABLE (MOD_0FB4) }, |
3005 | { MOD_TABLE (MOD_0FB5) }, |
||
6324 | serge | 3006 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3007 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ |
||
5221 | serge | 3008 | /* b8 */ |
3009 | { PREFIX_TABLE (PREFIX_0FB8) }, |
||
6324 | serge | 3010 | { "ud1", { XX }, 0 }, |
5221 | serge | 3011 | { REG_TABLE (REG_0FBA) }, |
6324 | serge | 3012 | { "btcS", { Evh1, Gv }, 0 }, |
5221 | serge | 3013 | { PREFIX_TABLE (PREFIX_0FBC) }, |
3014 | { PREFIX_TABLE (PREFIX_0FBD) }, |
||
6324 | serge | 3015 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3016 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ |
||
5221 | serge | 3017 | /* c0 */ |
6324 | serge | 3018 | { "xaddB", { Ebh1, Gb }, 0 }, |
3019 | { "xaddS", { Evh1, Gv }, 0 }, |
||
5221 | serge | 3020 | { PREFIX_TABLE (PREFIX_0FC2) }, |
6324 | serge | 3021 | { MOD_TABLE (MOD_0FC3) }, |
3022 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
||
3023 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, |
||
3024 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, |
||
5221 | serge | 3025 | { REG_TABLE (REG_0FC7) }, |
3026 | /* c8 */ |
||
6324 | serge | 3027 | { "bswap", { RMeAX }, 0 }, |
3028 | { "bswap", { RMeCX }, 0 }, |
||
3029 | { "bswap", { RMeDX }, 0 }, |
||
3030 | { "bswap", { RMeBX }, 0 }, |
||
3031 | { "bswap", { RMeSP }, 0 }, |
||
3032 | { "bswap", { RMeBP }, 0 }, |
||
3033 | { "bswap", { RMeSI }, 0 }, |
||
3034 | { "bswap", { RMeDI }, 0 }, |
||
5221 | serge | 3035 | /* d0 */ |
3036 | { PREFIX_TABLE (PREFIX_0FD0) }, |
||
6324 | serge | 3037 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3038 | { "psrld", { MX, EM }, PREFIX_OPCODE }, |
||
3039 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, |
||
3040 | { "paddq", { MX, EM }, PREFIX_OPCODE }, |
||
3041 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 3042 | { PREFIX_TABLE (PREFIX_0FD6) }, |
3043 | { MOD_TABLE (MOD_0FD7) }, |
||
3044 | /* d8 */ |
||
6324 | serge | 3045 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3046 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, |
||
3047 | { "pminub", { MX, EM }, PREFIX_OPCODE }, |
||
3048 | { "pand", { MX, EM }, PREFIX_OPCODE }, |
||
3049 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, |
||
3050 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, |
||
3051 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, |
||
3052 | { "pandn", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 3053 | /* e0 */ |
6324 | serge | 3054 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3055 | { "psraw", { MX, EM }, PREFIX_OPCODE }, |
||
3056 | { "psrad", { MX, EM }, PREFIX_OPCODE }, |
||
3057 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, |
||
3058 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, |
||
3059 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 3060 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3061 | { PREFIX_TABLE (PREFIX_0FE7) }, |
||
3062 | /* e8 */ |
||
6324 | serge | 3063 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3064 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, |
||
3065 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, |
||
3066 | { "por", { MX, EM }, PREFIX_OPCODE }, |
||
3067 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, |
||
3068 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, |
||
3069 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, |
||
3070 | { "pxor", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 3071 | /* f0 */ |
3072 | { PREFIX_TABLE (PREFIX_0FF0) }, |
||
6324 | serge | 3073 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3074 | { "pslld", { MX, EM }, PREFIX_OPCODE }, |
||
3075 | { "psllq", { MX, EM }, PREFIX_OPCODE }, |
||
3076 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, |
||
3077 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, |
||
3078 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 3079 | { PREFIX_TABLE (PREFIX_0FF7) }, |
3080 | /* f8 */ |
||
6324 | serge | 3081 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3082 | { "psubw", { MX, EM }, PREFIX_OPCODE }, |
||
3083 | { "psubd", { MX, EM }, PREFIX_OPCODE }, |
||
3084 | { "psubq", { MX, EM }, PREFIX_OPCODE }, |
||
3085 | { "paddb", { MX, EM }, PREFIX_OPCODE }, |
||
3086 | { "paddw", { MX, EM }, PREFIX_OPCODE }, |
||
3087 | { "paddd", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 3088 | { Bad_Opcode }, |
3089 | }; |
||
3090 | |||
3091 | static const unsigned char onebyte_has_modrm[256] = { |
||
3092 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
||
3093 | /* ------------------------------- */ |
||
3094 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ |
||
3095 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ |
||
3096 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ |
||
3097 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ |
||
3098 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ |
||
3099 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ |
||
3100 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ |
||
3101 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ |
||
3102 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ |
||
3103 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ |
||
3104 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ |
||
3105 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ |
||
3106 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ |
||
3107 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ |
||
3108 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ |
||
3109 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ |
||
3110 | /* ------------------------------- */ |
||
3111 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
||
3112 | }; |
||
3113 | |||
3114 | static const unsigned char twobyte_has_modrm[256] = { |
||
3115 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
||
3116 | /* ------------------------------- */ |
||
3117 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
||
3118 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
||
3119 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
||
3120 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
||
3121 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
||
3122 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
||
3123 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ |
||
3124 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
||
3125 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
||
3126 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ |
||
3127 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
||
3128 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
||
3129 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
||
3130 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
||
3131 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
||
3132 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
||
3133 | /* ------------------------------- */ |
||
3134 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
||
3135 | }; |
||
3136 | |||
3137 | static char obuf[100]; |
||
3138 | static char *obufp; |
||
3139 | static char *mnemonicendp; |
||
3140 | static char scratchbuf[100]; |
||
3141 | static unsigned char *start_codep; |
||
3142 | static unsigned char *insn_codep; |
||
3143 | static unsigned char *codep; |
||
6324 | serge | 3144 | static unsigned char *end_codep; |
5221 | serge | 3145 | static int last_lock_prefix; |
3146 | static int last_repz_prefix; |
||
3147 | static int last_repnz_prefix; |
||
3148 | static int last_data_prefix; |
||
3149 | static int last_addr_prefix; |
||
3150 | static int last_rex_prefix; |
||
3151 | static int last_seg_prefix; |
||
6324 | serge | 3152 | static int fwait_prefix; |
3153 | /* The active segment register prefix. */ |
||
3154 | static int active_seg_prefix; |
||
5221 | serge | 3155 | #define MAX_CODE_LENGTH 15 |
3156 | /* We can up to 14 prefixes since the maximum instruction length is |
||
3157 | 15bytes. */ |
||
3158 | static int all_prefixes[MAX_CODE_LENGTH - 1]; |
||
3159 | static disassemble_info *the_info; |
||
3160 | static struct |
||
3161 | { |
||
3162 | int mod; |
||
3163 | int reg; |
||
3164 | int rm; |
||
3165 | } |
||
3166 | modrm; |
||
3167 | static unsigned char need_modrm; |
||
3168 | static struct |
||
3169 | { |
||
3170 | int scale; |
||
3171 | int index; |
||
3172 | int base; |
||
3173 | } |
||
3174 | sib; |
||
3175 | static struct |
||
3176 | { |
||
3177 | int register_specifier; |
||
3178 | int length; |
||
3179 | int prefix; |
||
3180 | int w; |
||
3181 | int evex; |
||
3182 | int r; |
||
3183 | int v; |
||
3184 | int mask_register_specifier; |
||
3185 | int zeroing; |
||
3186 | int ll; |
||
3187 | int b; |
||
3188 | } |
||
3189 | vex; |
||
3190 | static unsigned char need_vex; |
||
3191 | static unsigned char need_vex_reg; |
||
3192 | static unsigned char vex_w_done; |
||
3193 | |||
3194 | struct op |
||
3195 | { |
||
3196 | const char *name; |
||
3197 | unsigned int len; |
||
3198 | }; |
||
3199 | |||
3200 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
||
3201 | values are stale. Hitting this abort likely indicates that you |
||
3202 | need to update onebyte_has_modrm or twobyte_has_modrm. */ |
||
3203 | #define MODRM_CHECK if (!need_modrm) abort () |
||
3204 | |||
3205 | static const char **names64; |
||
3206 | static const char **names32; |
||
3207 | static const char **names16; |
||
3208 | static const char **names8; |
||
3209 | static const char **names8rex; |
||
3210 | static const char **names_seg; |
||
3211 | static const char *index64; |
||
3212 | static const char *index32; |
||
3213 | static const char **index16; |
||
3214 | static const char **names_bnd; |
||
3215 | |||
3216 | static const char *intel_names64[] = { |
||
3217 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
||
3218 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
||
3219 | }; |
||
3220 | static const char *intel_names32[] = { |
||
3221 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", |
||
3222 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" |
||
3223 | }; |
||
3224 | static const char *intel_names16[] = { |
||
3225 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", |
||
3226 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
||
3227 | }; |
||
3228 | static const char *intel_names8[] = { |
||
3229 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", |
||
3230 | }; |
||
3231 | static const char *intel_names8rex[] = { |
||
3232 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", |
||
3233 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" |
||
3234 | }; |
||
3235 | static const char *intel_names_seg[] = { |
||
3236 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", |
||
3237 | }; |
||
3238 | static const char *intel_index64 = "riz"; |
||
3239 | static const char *intel_index32 = "eiz"; |
||
3240 | static const char *intel_index16[] = { |
||
3241 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" |
||
3242 | }; |
||
3243 | |||
3244 | static const char *att_names64[] = { |
||
3245 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", |
||
3246 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
||
3247 | }; |
||
3248 | static const char *att_names32[] = { |
||
3249 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", |
||
3250 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
||
3251 | }; |
||
3252 | static const char *att_names16[] = { |
||
3253 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", |
||
3254 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
||
3255 | }; |
||
3256 | static const char *att_names8[] = { |
||
3257 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", |
||
3258 | }; |
||
3259 | static const char *att_names8rex[] = { |
||
3260 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", |
||
3261 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
||
3262 | }; |
||
3263 | static const char *att_names_seg[] = { |
||
3264 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", |
||
3265 | }; |
||
3266 | static const char *att_index64 = "%riz"; |
||
3267 | static const char *att_index32 = "%eiz"; |
||
3268 | static const char *att_index16[] = { |
||
3269 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" |
||
3270 | }; |
||
3271 | |||
3272 | static const char **names_mm; |
||
3273 | static const char *intel_names_mm[] = { |
||
3274 | "mm0", "mm1", "mm2", "mm3", |
||
3275 | "mm4", "mm5", "mm6", "mm7" |
||
3276 | }; |
||
3277 | static const char *att_names_mm[] = { |
||
3278 | "%mm0", "%mm1", "%mm2", "%mm3", |
||
3279 | "%mm4", "%mm5", "%mm6", "%mm7" |
||
3280 | }; |
||
3281 | |||
3282 | static const char *intel_names_bnd[] = { |
||
3283 | "bnd0", "bnd1", "bnd2", "bnd3" |
||
3284 | }; |
||
3285 | |||
3286 | static const char *att_names_bnd[] = { |
||
3287 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" |
||
3288 | }; |
||
3289 | |||
3290 | static const char **names_xmm; |
||
3291 | static const char *intel_names_xmm[] = { |
||
3292 | "xmm0", "xmm1", "xmm2", "xmm3", |
||
3293 | "xmm4", "xmm5", "xmm6", "xmm7", |
||
3294 | "xmm8", "xmm9", "xmm10", "xmm11", |
||
3295 | "xmm12", "xmm13", "xmm14", "xmm15", |
||
3296 | "xmm16", "xmm17", "xmm18", "xmm19", |
||
3297 | "xmm20", "xmm21", "xmm22", "xmm23", |
||
3298 | "xmm24", "xmm25", "xmm26", "xmm27", |
||
3299 | "xmm28", "xmm29", "xmm30", "xmm31" |
||
3300 | }; |
||
3301 | static const char *att_names_xmm[] = { |
||
3302 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
||
3303 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", |
||
3304 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", |
||
3305 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
||
3306 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", |
||
3307 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", |
||
3308 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", |
||
3309 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" |
||
3310 | }; |
||
3311 | |||
3312 | static const char **names_ymm; |
||
3313 | static const char *intel_names_ymm[] = { |
||
3314 | "ymm0", "ymm1", "ymm2", "ymm3", |
||
3315 | "ymm4", "ymm5", "ymm6", "ymm7", |
||
3316 | "ymm8", "ymm9", "ymm10", "ymm11", |
||
3317 | "ymm12", "ymm13", "ymm14", "ymm15", |
||
3318 | "ymm16", "ymm17", "ymm18", "ymm19", |
||
3319 | "ymm20", "ymm21", "ymm22", "ymm23", |
||
3320 | "ymm24", "ymm25", "ymm26", "ymm27", |
||
3321 | "ymm28", "ymm29", "ymm30", "ymm31" |
||
3322 | }; |
||
3323 | static const char *att_names_ymm[] = { |
||
3324 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", |
||
3325 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", |
||
3326 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", |
||
3327 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
||
3328 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", |
||
3329 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", |
||
3330 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", |
||
3331 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" |
||
3332 | }; |
||
3333 | |||
3334 | static const char **names_zmm; |
||
3335 | static const char *intel_names_zmm[] = { |
||
3336 | "zmm0", "zmm1", "zmm2", "zmm3", |
||
3337 | "zmm4", "zmm5", "zmm6", "zmm7", |
||
3338 | "zmm8", "zmm9", "zmm10", "zmm11", |
||
3339 | "zmm12", "zmm13", "zmm14", "zmm15", |
||
3340 | "zmm16", "zmm17", "zmm18", "zmm19", |
||
3341 | "zmm20", "zmm21", "zmm22", "zmm23", |
||
3342 | "zmm24", "zmm25", "zmm26", "zmm27", |
||
3343 | "zmm28", "zmm29", "zmm30", "zmm31" |
||
3344 | }; |
||
3345 | static const char *att_names_zmm[] = { |
||
3346 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", |
||
3347 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", |
||
3348 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", |
||
3349 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", |
||
3350 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", |
||
3351 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", |
||
3352 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", |
||
3353 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" |
||
3354 | }; |
||
3355 | |||
3356 | static const char **names_mask; |
||
3357 | static const char *intel_names_mask[] = { |
||
3358 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" |
||
3359 | }; |
||
3360 | static const char *att_names_mask[] = { |
||
3361 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" |
||
3362 | }; |
||
3363 | |||
3364 | static const char *names_rounding[] = |
||
3365 | { |
||
3366 | "{rn-sae}", |
||
3367 | "{rd-sae}", |
||
3368 | "{ru-sae}", |
||
3369 | "{rz-sae}" |
||
3370 | }; |
||
3371 | |||
3372 | static const struct dis386 reg_table[][8] = { |
||
3373 | /* REG_80 */ |
||
3374 | { |
||
6324 | serge | 3375 | { "addA", { Ebh1, Ib }, 0 }, |
3376 | { "orA", { Ebh1, Ib }, 0 }, |
||
3377 | { "adcA", { Ebh1, Ib }, 0 }, |
||
3378 | { "sbbA", { Ebh1, Ib }, 0 }, |
||
3379 | { "andA", { Ebh1, Ib }, 0 }, |
||
3380 | { "subA", { Ebh1, Ib }, 0 }, |
||
3381 | { "xorA", { Ebh1, Ib }, 0 }, |
||
3382 | { "cmpA", { Eb, Ib }, 0 }, |
||
5221 | serge | 3383 | }, |
3384 | /* REG_81 */ |
||
3385 | { |
||
6324 | serge | 3386 | { "addQ", { Evh1, Iv }, 0 }, |
3387 | { "orQ", { Evh1, Iv }, 0 }, |
||
3388 | { "adcQ", { Evh1, Iv }, 0 }, |
||
3389 | { "sbbQ", { Evh1, Iv }, 0 }, |
||
3390 | { "andQ", { Evh1, Iv }, 0 }, |
||
3391 | { "subQ", { Evh1, Iv }, 0 }, |
||
3392 | { "xorQ", { Evh1, Iv }, 0 }, |
||
3393 | { "cmpQ", { Ev, Iv }, 0 }, |
||
5221 | serge | 3394 | }, |
3395 | /* REG_82 */ |
||
3396 | { |
||
6324 | serge | 3397 | { "addQ", { Evh1, sIb }, 0 }, |
3398 | { "orQ", { Evh1, sIb }, 0 }, |
||
3399 | { "adcQ", { Evh1, sIb }, 0 }, |
||
3400 | { "sbbQ", { Evh1, sIb }, 0 }, |
||
3401 | { "andQ", { Evh1, sIb }, 0 }, |
||
3402 | { "subQ", { Evh1, sIb }, 0 }, |
||
3403 | { "xorQ", { Evh1, sIb }, 0 }, |
||
3404 | { "cmpQ", { Ev, sIb }, 0 }, |
||
5221 | serge | 3405 | }, |
3406 | /* REG_8F */ |
||
3407 | { |
||
6324 | serge | 3408 | { "popU", { stackEv }, 0 }, |
5221 | serge | 3409 | { XOP_8F_TABLE (XOP_09) }, |
3410 | { Bad_Opcode }, |
||
3411 | { Bad_Opcode }, |
||
3412 | { Bad_Opcode }, |
||
3413 | { XOP_8F_TABLE (XOP_09) }, |
||
3414 | }, |
||
3415 | /* REG_C0 */ |
||
3416 | { |
||
6324 | serge | 3417 | { "rolA", { Eb, Ib }, 0 }, |
3418 | { "rorA", { Eb, Ib }, 0 }, |
||
3419 | { "rclA", { Eb, Ib }, 0 }, |
||
3420 | { "rcrA", { Eb, Ib }, 0 }, |
||
3421 | { "shlA", { Eb, Ib }, 0 }, |
||
3422 | { "shrA", { Eb, Ib }, 0 }, |
||
5221 | serge | 3423 | { Bad_Opcode }, |
6324 | serge | 3424 | { "sarA", { Eb, Ib }, 0 }, |
5221 | serge | 3425 | }, |
3426 | /* REG_C1 */ |
||
3427 | { |
||
6324 | serge | 3428 | { "rolQ", { Ev, Ib }, 0 }, |
3429 | { "rorQ", { Ev, Ib }, 0 }, |
||
3430 | { "rclQ", { Ev, Ib }, 0 }, |
||
3431 | { "rcrQ", { Ev, Ib }, 0 }, |
||
3432 | { "shlQ", { Ev, Ib }, 0 }, |
||
3433 | { "shrQ", { Ev, Ib }, 0 }, |
||
5221 | serge | 3434 | { Bad_Opcode }, |
6324 | serge | 3435 | { "sarQ", { Ev, Ib }, 0 }, |
5221 | serge | 3436 | }, |
3437 | /* REG_C6 */ |
||
3438 | { |
||
6324 | serge | 3439 | { "movA", { Ebh3, Ib }, 0 }, |
5221 | serge | 3440 | { Bad_Opcode }, |
3441 | { Bad_Opcode }, |
||
3442 | { Bad_Opcode }, |
||
3443 | { Bad_Opcode }, |
||
3444 | { Bad_Opcode }, |
||
3445 | { Bad_Opcode }, |
||
3446 | { MOD_TABLE (MOD_C6_REG_7) }, |
||
3447 | }, |
||
3448 | /* REG_C7 */ |
||
3449 | { |
||
6324 | serge | 3450 | { "movQ", { Evh3, Iv }, 0 }, |
5221 | serge | 3451 | { Bad_Opcode }, |
3452 | { Bad_Opcode }, |
||
3453 | { Bad_Opcode }, |
||
3454 | { Bad_Opcode }, |
||
3455 | { Bad_Opcode }, |
||
3456 | { Bad_Opcode }, |
||
3457 | { MOD_TABLE (MOD_C7_REG_7) }, |
||
3458 | }, |
||
3459 | /* REG_D0 */ |
||
3460 | { |
||
6324 | serge | 3461 | { "rolA", { Eb, I1 }, 0 }, |
3462 | { "rorA", { Eb, I1 }, 0 }, |
||
3463 | { "rclA", { Eb, I1 }, 0 }, |
||
3464 | { "rcrA", { Eb, I1 }, 0 }, |
||
3465 | { "shlA", { Eb, I1 }, 0 }, |
||
3466 | { "shrA", { Eb, I1 }, 0 }, |
||
5221 | serge | 3467 | { Bad_Opcode }, |
6324 | serge | 3468 | { "sarA", { Eb, I1 }, 0 }, |
5221 | serge | 3469 | }, |
3470 | /* REG_D1 */ |
||
3471 | { |
||
6324 | serge | 3472 | { "rolQ", { Ev, I1 }, 0 }, |
3473 | { "rorQ", { Ev, I1 }, 0 }, |
||
3474 | { "rclQ", { Ev, I1 }, 0 }, |
||
3475 | { "rcrQ", { Ev, I1 }, 0 }, |
||
3476 | { "shlQ", { Ev, I1 }, 0 }, |
||
3477 | { "shrQ", { Ev, I1 }, 0 }, |
||
5221 | serge | 3478 | { Bad_Opcode }, |
6324 | serge | 3479 | { "sarQ", { Ev, I1 }, 0 }, |
5221 | serge | 3480 | }, |
3481 | /* REG_D2 */ |
||
3482 | { |
||
6324 | serge | 3483 | { "rolA", { Eb, CL }, 0 }, |
3484 | { "rorA", { Eb, CL }, 0 }, |
||
3485 | { "rclA", { Eb, CL }, 0 }, |
||
3486 | { "rcrA", { Eb, CL }, 0 }, |
||
3487 | { "shlA", { Eb, CL }, 0 }, |
||
3488 | { "shrA", { Eb, CL }, 0 }, |
||
5221 | serge | 3489 | { Bad_Opcode }, |
6324 | serge | 3490 | { "sarA", { Eb, CL }, 0 }, |
5221 | serge | 3491 | }, |
3492 | /* REG_D3 */ |
||
3493 | { |
||
6324 | serge | 3494 | { "rolQ", { Ev, CL }, 0 }, |
3495 | { "rorQ", { Ev, CL }, 0 }, |
||
3496 | { "rclQ", { Ev, CL }, 0 }, |
||
3497 | { "rcrQ", { Ev, CL }, 0 }, |
||
3498 | { "shlQ", { Ev, CL }, 0 }, |
||
3499 | { "shrQ", { Ev, CL }, 0 }, |
||
5221 | serge | 3500 | { Bad_Opcode }, |
6324 | serge | 3501 | { "sarQ", { Ev, CL }, 0 }, |
5221 | serge | 3502 | }, |
3503 | /* REG_F6 */ |
||
3504 | { |
||
6324 | serge | 3505 | { "testA", { Eb, Ib }, 0 }, |
5221 | serge | 3506 | { Bad_Opcode }, |
6324 | serge | 3507 | { "notA", { Ebh1 }, 0 }, |
3508 | { "negA", { Ebh1 }, 0 }, |
||
3509 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ |
||
3510 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ |
||
3511 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ |
||
3512 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ |
||
5221 | serge | 3513 | }, |
3514 | /* REG_F7 */ |
||
3515 | { |
||
6324 | serge | 3516 | { "testQ", { Ev, Iv }, 0 }, |
5221 | serge | 3517 | { Bad_Opcode }, |
6324 | serge | 3518 | { "notQ", { Evh1 }, 0 }, |
3519 | { "negQ", { Evh1 }, 0 }, |
||
3520 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ |
||
3521 | { "imulQ", { Ev }, 0 }, |
||
3522 | { "divQ", { Ev }, 0 }, |
||
3523 | { "idivQ", { Ev }, 0 }, |
||
5221 | serge | 3524 | }, |
3525 | /* REG_FE */ |
||
3526 | { |
||
6324 | serge | 3527 | { "incA", { Ebh1 }, 0 }, |
3528 | { "decA", { Ebh1 }, 0 }, |
||
5221 | serge | 3529 | }, |
3530 | /* REG_FF */ |
||
3531 | { |
||
6324 | serge | 3532 | { "incQ", { Evh1 }, 0 }, |
3533 | { "decQ", { Evh1 }, 0 }, |
||
3534 | { "call{T|}", { indirEv, BND }, 0 }, |
||
3535 | { MOD_TABLE (MOD_FF_REG_3) }, |
||
3536 | { "jmp{T|}", { indirEv, BND }, 0 }, |
||
3537 | { MOD_TABLE (MOD_FF_REG_5) }, |
||
3538 | { "pushU", { stackEv }, 0 }, |
||
5221 | serge | 3539 | { Bad_Opcode }, |
3540 | }, |
||
3541 | /* REG_0F00 */ |
||
3542 | { |
||
6324 | serge | 3543 | { "sldtD", { Sv }, 0 }, |
3544 | { "strD", { Sv }, 0 }, |
||
3545 | { "lldt", { Ew }, 0 }, |
||
3546 | { "ltr", { Ew }, 0 }, |
||
3547 | { "verr", { Ew }, 0 }, |
||
3548 | { "verw", { Ew }, 0 }, |
||
5221 | serge | 3549 | { Bad_Opcode }, |
3550 | { Bad_Opcode }, |
||
3551 | }, |
||
3552 | /* REG_0F01 */ |
||
3553 | { |
||
3554 | { MOD_TABLE (MOD_0F01_REG_0) }, |
||
3555 | { MOD_TABLE (MOD_0F01_REG_1) }, |
||
3556 | { MOD_TABLE (MOD_0F01_REG_2) }, |
||
3557 | { MOD_TABLE (MOD_0F01_REG_3) }, |
||
6324 | serge | 3558 | { "smswD", { Sv }, 0 }, |
3559 | { MOD_TABLE (MOD_0F01_REG_5) }, |
||
3560 | { "lmsw", { Ew }, 0 }, |
||
5221 | serge | 3561 | { MOD_TABLE (MOD_0F01_REG_7) }, |
3562 | }, |
||
3563 | /* REG_0F0D */ |
||
3564 | { |
||
6324 | serge | 3565 | { "prefetch", { Mb }, 0 }, |
3566 | { "prefetchw", { Mb }, 0 }, |
||
3567 | { "prefetchwt1", { Mb }, 0 }, |
||
3568 | { "prefetch", { Mb }, 0 }, |
||
3569 | { "prefetch", { Mb }, 0 }, |
||
3570 | { "prefetch", { Mb }, 0 }, |
||
3571 | { "prefetch", { Mb }, 0 }, |
||
3572 | { "prefetch", { Mb }, 0 }, |
||
5221 | serge | 3573 | }, |
3574 | /* REG_0F18 */ |
||
3575 | { |
||
3576 | { MOD_TABLE (MOD_0F18_REG_0) }, |
||
3577 | { MOD_TABLE (MOD_0F18_REG_1) }, |
||
3578 | { MOD_TABLE (MOD_0F18_REG_2) }, |
||
3579 | { MOD_TABLE (MOD_0F18_REG_3) }, |
||
3580 | { MOD_TABLE (MOD_0F18_REG_4) }, |
||
3581 | { MOD_TABLE (MOD_0F18_REG_5) }, |
||
3582 | { MOD_TABLE (MOD_0F18_REG_6) }, |
||
3583 | { MOD_TABLE (MOD_0F18_REG_7) }, |
||
3584 | }, |
||
3585 | /* REG_0F71 */ |
||
3586 | { |
||
3587 | { Bad_Opcode }, |
||
3588 | { Bad_Opcode }, |
||
3589 | { MOD_TABLE (MOD_0F71_REG_2) }, |
||
3590 | { Bad_Opcode }, |
||
3591 | { MOD_TABLE (MOD_0F71_REG_4) }, |
||
3592 | { Bad_Opcode }, |
||
3593 | { MOD_TABLE (MOD_0F71_REG_6) }, |
||
3594 | }, |
||
3595 | /* REG_0F72 */ |
||
3596 | { |
||
3597 | { Bad_Opcode }, |
||
3598 | { Bad_Opcode }, |
||
3599 | { MOD_TABLE (MOD_0F72_REG_2) }, |
||
3600 | { Bad_Opcode }, |
||
3601 | { MOD_TABLE (MOD_0F72_REG_4) }, |
||
3602 | { Bad_Opcode }, |
||
3603 | { MOD_TABLE (MOD_0F72_REG_6) }, |
||
3604 | }, |
||
3605 | /* REG_0F73 */ |
||
3606 | { |
||
3607 | { Bad_Opcode }, |
||
3608 | { Bad_Opcode }, |
||
3609 | { MOD_TABLE (MOD_0F73_REG_2) }, |
||
3610 | { MOD_TABLE (MOD_0F73_REG_3) }, |
||
3611 | { Bad_Opcode }, |
||
3612 | { Bad_Opcode }, |
||
3613 | { MOD_TABLE (MOD_0F73_REG_6) }, |
||
3614 | { MOD_TABLE (MOD_0F73_REG_7) }, |
||
3615 | }, |
||
3616 | /* REG_0FA6 */ |
||
3617 | { |
||
6324 | serge | 3618 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3619 | { "xsha1", { { OP_0f07, 0 } }, 0 }, |
||
3620 | { "xsha256", { { OP_0f07, 0 } }, 0 }, |
||
5221 | serge | 3621 | }, |
3622 | /* REG_0FA7 */ |
||
3623 | { |
||
6324 | serge | 3624 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3625 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, |
||
3626 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, |
||
3627 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, |
||
3628 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, |
||
3629 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, |
||
5221 | serge | 3630 | }, |
3631 | /* REG_0FAE */ |
||
3632 | { |
||
3633 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
||
3634 | { MOD_TABLE (MOD_0FAE_REG_1) }, |
||
3635 | { MOD_TABLE (MOD_0FAE_REG_2) }, |
||
3636 | { MOD_TABLE (MOD_0FAE_REG_3) }, |
||
3637 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
||
3638 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
||
3639 | { MOD_TABLE (MOD_0FAE_REG_6) }, |
||
3640 | { MOD_TABLE (MOD_0FAE_REG_7) }, |
||
3641 | }, |
||
3642 | /* REG_0FBA */ |
||
3643 | { |
||
3644 | { Bad_Opcode }, |
||
3645 | { Bad_Opcode }, |
||
3646 | { Bad_Opcode }, |
||
3647 | { Bad_Opcode }, |
||
6324 | serge | 3648 | { "btQ", { Ev, Ib }, 0 }, |
3649 | { "btsQ", { Evh1, Ib }, 0 }, |
||
3650 | { "btrQ", { Evh1, Ib }, 0 }, |
||
3651 | { "btcQ", { Evh1, Ib }, 0 }, |
||
5221 | serge | 3652 | }, |
3653 | /* REG_0FC7 */ |
||
3654 | { |
||
3655 | { Bad_Opcode }, |
||
6324 | serge | 3656 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
5221 | serge | 3657 | { Bad_Opcode }, |
6324 | serge | 3658 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3659 | { MOD_TABLE (MOD_0FC7_REG_4) }, |
||
3660 | { MOD_TABLE (MOD_0FC7_REG_5) }, |
||
5221 | serge | 3661 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3662 | { MOD_TABLE (MOD_0FC7_REG_7) }, |
||
3663 | }, |
||
3664 | /* REG_VEX_0F71 */ |
||
3665 | { |
||
3666 | { Bad_Opcode }, |
||
3667 | { Bad_Opcode }, |
||
3668 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
||
3669 | { Bad_Opcode }, |
||
3670 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
||
3671 | { Bad_Opcode }, |
||
3672 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
||
3673 | }, |
||
3674 | /* REG_VEX_0F72 */ |
||
3675 | { |
||
3676 | { Bad_Opcode }, |
||
3677 | { Bad_Opcode }, |
||
3678 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
||
3679 | { Bad_Opcode }, |
||
3680 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
||
3681 | { Bad_Opcode }, |
||
3682 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
||
3683 | }, |
||
3684 | /* REG_VEX_0F73 */ |
||
3685 | { |
||
3686 | { Bad_Opcode }, |
||
3687 | { Bad_Opcode }, |
||
3688 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
||
3689 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, |
||
3690 | { Bad_Opcode }, |
||
3691 | { Bad_Opcode }, |
||
3692 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
||
3693 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, |
||
3694 | }, |
||
3695 | /* REG_VEX_0FAE */ |
||
3696 | { |
||
3697 | { Bad_Opcode }, |
||
3698 | { Bad_Opcode }, |
||
3699 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
||
3700 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, |
||
3701 | }, |
||
3702 | /* REG_VEX_0F38F3 */ |
||
3703 | { |
||
3704 | { Bad_Opcode }, |
||
3705 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, |
||
3706 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, |
||
3707 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, |
||
3708 | }, |
||
3709 | /* REG_XOP_LWPCB */ |
||
3710 | { |
||
6324 | serge | 3711 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3712 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
||
5221 | serge | 3713 | }, |
3714 | /* REG_XOP_LWP */ |
||
3715 | { |
||
6324 | serge | 3716 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3717 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
||
5221 | serge | 3718 | }, |
3719 | /* REG_XOP_TBM_01 */ |
||
3720 | { |
||
3721 | { Bad_Opcode }, |
||
6324 | serge | 3722 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3723 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
||
3724 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, |
||
3725 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
||
3726 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, |
||
3727 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, |
||
3728 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, |
||
5221 | serge | 3729 | }, |
3730 | /* REG_XOP_TBM_02 */ |
||
3731 | { |
||
3732 | { Bad_Opcode }, |
||
6324 | serge | 3733 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
5221 | serge | 3734 | { Bad_Opcode }, |
3735 | { Bad_Opcode }, |
||
3736 | { Bad_Opcode }, |
||
3737 | { Bad_Opcode }, |
||
6324 | serge | 3738 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
5221 | serge | 3739 | }, |
3740 | #define NEED_REG_TABLE |
||
3741 | #include "i386-dis-evex.h" |
||
3742 | #undef NEED_REG_TABLE |
||
3743 | }; |
||
3744 | |||
3745 | static const struct dis386 prefix_table[][4] = { |
||
3746 | /* PREFIX_90 */ |
||
3747 | { |
||
6324 | serge | 3748 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3749 | { "pause", { XX }, 0 }, |
||
3750 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
||
3751 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
||
5221 | serge | 3752 | }, |
3753 | |||
3754 | /* PREFIX_0F10 */ |
||
3755 | { |
||
6324 | serge | 3756 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3757 | { "movss", { XM, EXd }, PREFIX_OPCODE }, |
||
3758 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, |
||
3759 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3760 | }, |
3761 | |||
3762 | /* PREFIX_0F11 */ |
||
3763 | { |
||
6324 | serge | 3764 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3765 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, |
||
3766 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, |
||
3767 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, |
||
5221 | serge | 3768 | }, |
3769 | |||
3770 | /* PREFIX_0F12 */ |
||
3771 | { |
||
3772 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
||
6324 | serge | 3773 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3774 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, |
||
3775 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3776 | }, |
3777 | |||
3778 | /* PREFIX_0F16 */ |
||
3779 | { |
||
3780 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
||
6324 | serge | 3781 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3782 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3783 | }, |
3784 | |||
3785 | /* PREFIX_0F1A */ |
||
3786 | { |
||
3787 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, |
||
6324 | serge | 3788 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3789 | { "bndmov", { Gbnd, Ebnd }, 0 }, |
||
3790 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, |
||
5221 | serge | 3791 | }, |
3792 | |||
3793 | /* PREFIX_0F1B */ |
||
3794 | { |
||
3795 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, |
||
3796 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, |
||
6324 | serge | 3797 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3798 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
||
5221 | serge | 3799 | }, |
3800 | |||
3801 | /* PREFIX_0F2A */ |
||
3802 | { |
||
6324 | serge | 3803 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3804 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, |
||
3805 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
||
3806 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
||
5221 | serge | 3807 | }, |
3808 | |||
3809 | /* PREFIX_0F2B */ |
||
3810 | { |
||
3811 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
||
3812 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, |
||
3813 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, |
||
3814 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, |
||
3815 | }, |
||
3816 | |||
3817 | /* PREFIX_0F2C */ |
||
3818 | { |
||
6324 | serge | 3819 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3820 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, |
||
3821 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
||
3822 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3823 | }, |
3824 | |||
3825 | /* PREFIX_0F2D */ |
||
3826 | { |
||
6324 | serge | 3827 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3828 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, |
||
3829 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
||
3830 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3831 | }, |
3832 | |||
3833 | /* PREFIX_0F2E */ |
||
3834 | { |
||
6324 | serge | 3835 | { "ucomiss",{ XM, EXd }, 0 }, |
5221 | serge | 3836 | { Bad_Opcode }, |
6324 | serge | 3837 | { "ucomisd",{ XM, EXq }, 0 }, |
5221 | serge | 3838 | }, |
3839 | |||
3840 | /* PREFIX_0F2F */ |
||
3841 | { |
||
6324 | serge | 3842 | { "comiss", { XM, EXd }, 0 }, |
5221 | serge | 3843 | { Bad_Opcode }, |
6324 | serge | 3844 | { "comisd", { XM, EXq }, 0 }, |
5221 | serge | 3845 | }, |
3846 | |||
3847 | /* PREFIX_0F51 */ |
||
3848 | { |
||
6324 | serge | 3849 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3850 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, |
||
3851 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3852 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3853 | }, |
3854 | |||
3855 | /* PREFIX_0F52 */ |
||
3856 | { |
||
6324 | serge | 3857 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3858 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, |
||
5221 | serge | 3859 | }, |
3860 | |||
3861 | /* PREFIX_0F53 */ |
||
3862 | { |
||
6324 | serge | 3863 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3864 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, |
||
5221 | serge | 3865 | }, |
3866 | |||
3867 | /* PREFIX_0F58 */ |
||
3868 | { |
||
6324 | serge | 3869 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3870 | { "addss", { XM, EXd }, PREFIX_OPCODE }, |
||
3871 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3872 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3873 | }, |
3874 | |||
3875 | /* PREFIX_0F59 */ |
||
3876 | { |
||
6324 | serge | 3877 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3878 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, |
||
3879 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3880 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3881 | }, |
3882 | |||
3883 | /* PREFIX_0F5A */ |
||
3884 | { |
||
6324 | serge | 3885 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3886 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, |
||
3887 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, |
||
3888 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3889 | }, |
3890 | |||
3891 | /* PREFIX_0F5B */ |
||
3892 | { |
||
6324 | serge | 3893 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3894 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, |
||
3895 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 3896 | }, |
3897 | |||
3898 | /* PREFIX_0F5C */ |
||
3899 | { |
||
6324 | serge | 3900 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3901 | { "subss", { XM, EXd }, PREFIX_OPCODE }, |
||
3902 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3903 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3904 | }, |
3905 | |||
3906 | /* PREFIX_0F5D */ |
||
3907 | { |
||
6324 | serge | 3908 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3909 | { "minss", { XM, EXd }, PREFIX_OPCODE }, |
||
3910 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3911 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3912 | }, |
3913 | |||
3914 | /* PREFIX_0F5E */ |
||
3915 | { |
||
6324 | serge | 3916 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3917 | { "divss", { XM, EXd }, PREFIX_OPCODE }, |
||
3918 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3919 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3920 | }, |
3921 | |||
3922 | /* PREFIX_0F5F */ |
||
3923 | { |
||
6324 | serge | 3924 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3925 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, |
||
3926 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, |
||
3927 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 3928 | }, |
3929 | |||
3930 | /* PREFIX_0F60 */ |
||
3931 | { |
||
6324 | serge | 3932 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
5221 | serge | 3933 | { Bad_Opcode }, |
6324 | serge | 3934 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
5221 | serge | 3935 | }, |
3936 | |||
3937 | /* PREFIX_0F61 */ |
||
3938 | { |
||
6324 | serge | 3939 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
5221 | serge | 3940 | { Bad_Opcode }, |
6324 | serge | 3941 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
5221 | serge | 3942 | }, |
3943 | |||
3944 | /* PREFIX_0F62 */ |
||
3945 | { |
||
6324 | serge | 3946 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
5221 | serge | 3947 | { Bad_Opcode }, |
6324 | serge | 3948 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
5221 | serge | 3949 | }, |
3950 | |||
3951 | /* PREFIX_0F6C */ |
||
3952 | { |
||
3953 | { Bad_Opcode }, |
||
3954 | { Bad_Opcode }, |
||
6324 | serge | 3955 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 3956 | }, |
3957 | |||
3958 | /* PREFIX_0F6D */ |
||
3959 | { |
||
3960 | { Bad_Opcode }, |
||
3961 | { Bad_Opcode }, |
||
6324 | serge | 3962 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 3963 | }, |
3964 | |||
3965 | /* PREFIX_0F6F */ |
||
3966 | { |
||
6324 | serge | 3967 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3968 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, |
||
3969 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 3970 | }, |
3971 | |||
3972 | /* PREFIX_0F70 */ |
||
3973 | { |
||
6324 | serge | 3974 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3975 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, |
||
3976 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
||
3977 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, |
||
5221 | serge | 3978 | }, |
3979 | |||
3980 | /* PREFIX_0F73_REG_3 */ |
||
3981 | { |
||
3982 | { Bad_Opcode }, |
||
3983 | { Bad_Opcode }, |
||
6324 | serge | 3984 | { "psrldq", { XS, Ib }, 0 }, |
5221 | serge | 3985 | }, |
3986 | |||
3987 | /* PREFIX_0F73_REG_7 */ |
||
3988 | { |
||
3989 | { Bad_Opcode }, |
||
3990 | { Bad_Opcode }, |
||
6324 | serge | 3991 | { "pslldq", { XS, Ib }, 0 }, |
5221 | serge | 3992 | }, |
3993 | |||
3994 | /* PREFIX_0F78 */ |
||
3995 | { |
||
6324 | serge | 3996 | {"vmread", { Em, Gm }, 0 }, |
5221 | serge | 3997 | { Bad_Opcode }, |
6324 | serge | 3998 | {"extrq", { XS, Ib, Ib }, 0 }, |
3999 | {"insertq", { XM, XS, Ib, Ib }, 0 }, |
||
5221 | serge | 4000 | }, |
4001 | |||
4002 | /* PREFIX_0F79 */ |
||
4003 | { |
||
6324 | serge | 4004 | {"vmwrite", { Gm, Em }, 0 }, |
5221 | serge | 4005 | { Bad_Opcode }, |
6324 | serge | 4006 | {"extrq", { XM, XS }, 0 }, |
4007 | {"insertq", { XM, XS }, 0 }, |
||
5221 | serge | 4008 | }, |
4009 | |||
4010 | /* PREFIX_0F7C */ |
||
4011 | { |
||
4012 | { Bad_Opcode }, |
||
4013 | { Bad_Opcode }, |
||
6324 | serge | 4014 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4015 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 4016 | }, |
4017 | |||
4018 | /* PREFIX_0F7D */ |
||
4019 | { |
||
4020 | { Bad_Opcode }, |
||
4021 | { Bad_Opcode }, |
||
6324 | serge | 4022 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4023 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 4024 | }, |
4025 | |||
4026 | /* PREFIX_0F7E */ |
||
4027 | { |
||
6324 | serge | 4028 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4029 | { "movq", { XM, EXq }, PREFIX_OPCODE }, |
||
4030 | { "movK", { Edq, XM }, PREFIX_OPCODE }, |
||
5221 | serge | 4031 | }, |
4032 | |||
4033 | /* PREFIX_0F7F */ |
||
4034 | { |
||
6324 | serge | 4035 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4036 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, |
||
4037 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, |
||
5221 | serge | 4038 | }, |
4039 | |||
4040 | /* PREFIX_0FAE_REG_0 */ |
||
4041 | { |
||
4042 | { Bad_Opcode }, |
||
6324 | serge | 4043 | { "rdfsbase", { Ev }, 0 }, |
5221 | serge | 4044 | }, |
4045 | |||
4046 | /* PREFIX_0FAE_REG_1 */ |
||
4047 | { |
||
4048 | { Bad_Opcode }, |
||
6324 | serge | 4049 | { "rdgsbase", { Ev }, 0 }, |
5221 | serge | 4050 | }, |
4051 | |||
4052 | /* PREFIX_0FAE_REG_2 */ |
||
4053 | { |
||
4054 | { Bad_Opcode }, |
||
6324 | serge | 4055 | { "wrfsbase", { Ev }, 0 }, |
5221 | serge | 4056 | }, |
4057 | |||
4058 | /* PREFIX_0FAE_REG_3 */ |
||
4059 | { |
||
4060 | { Bad_Opcode }, |
||
6324 | serge | 4061 | { "wrgsbase", { Ev }, 0 }, |
5221 | serge | 4062 | }, |
4063 | |||
6324 | serge | 4064 | /* PREFIX_0FAE_REG_6 */ |
4065 | { |
||
4066 | { "xsaveopt", { FXSAVE }, 0 }, |
||
4067 | { Bad_Opcode }, |
||
4068 | { "clwb", { Mb }, 0 }, |
||
4069 | }, |
||
4070 | |||
4071 | /* PREFIX_0FAE_REG_7 */ |
||
4072 | { |
||
4073 | { "clflush", { Mb }, 0 }, |
||
4074 | { Bad_Opcode }, |
||
4075 | { "clflushopt", { Mb }, 0 }, |
||
4076 | }, |
||
4077 | |||
4078 | /* PREFIX_RM_0_0FAE_REG_7 */ |
||
4079 | { |
||
4080 | { "sfence", { Skip_MODRM }, 0 }, |
||
4081 | { Bad_Opcode }, |
||
4082 | { "pcommit", { Skip_MODRM }, 0 }, |
||
4083 | }, |
||
4084 | |||
5221 | serge | 4085 | /* PREFIX_0FB8 */ |
4086 | { |
||
4087 | { Bad_Opcode }, |
||
6324 | serge | 4088 | { "popcntS", { Gv, Ev }, 0 }, |
5221 | serge | 4089 | }, |
4090 | |||
4091 | /* PREFIX_0FBC */ |
||
4092 | { |
||
6324 | serge | 4093 | { "bsfS", { Gv, Ev }, 0 }, |
4094 | { "tzcntS", { Gv, Ev }, 0 }, |
||
4095 | { "bsfS", { Gv, Ev }, 0 }, |
||
5221 | serge | 4096 | }, |
4097 | |||
4098 | /* PREFIX_0FBD */ |
||
4099 | { |
||
6324 | serge | 4100 | { "bsrS", { Gv, Ev }, 0 }, |
4101 | { "lzcntS", { Gv, Ev }, 0 }, |
||
4102 | { "bsrS", { Gv, Ev }, 0 }, |
||
5221 | serge | 4103 | }, |
4104 | |||
4105 | /* PREFIX_0FC2 */ |
||
4106 | { |
||
6324 | serge | 4107 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4108 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, |
||
4109 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, |
||
4110 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, |
||
5221 | serge | 4111 | }, |
4112 | |||
6324 | serge | 4113 | /* PREFIX_MOD_0_0FC3 */ |
5221 | serge | 4114 | { |
6324 | serge | 4115 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
5221 | serge | 4116 | }, |
4117 | |||
6324 | serge | 4118 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
5221 | serge | 4119 | { |
6324 | serge | 4120 | { "vmptrld",{ Mq }, 0 }, |
4121 | { "vmxon", { Mq }, 0 }, |
||
4122 | { "vmclear",{ Mq }, 0 }, |
||
5221 | serge | 4123 | }, |
4124 | |||
6324 | serge | 4125 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4126 | { |
||
4127 | { "rdrand", { Ev }, 0 }, |
||
4128 | { Bad_Opcode }, |
||
4129 | { "rdrand", { Ev }, 0 } |
||
4130 | }, |
||
4131 | |||
4132 | /* PREFIX_MOD_3_0FC7_REG_7 */ |
||
4133 | { |
||
4134 | { "rdseed", { Ev }, 0 }, |
||
4135 | { Bad_Opcode }, |
||
4136 | { "rdseed", { Ev }, 0 }, |
||
4137 | }, |
||
4138 | |||
5221 | serge | 4139 | /* PREFIX_0FD0 */ |
4140 | { |
||
4141 | { Bad_Opcode }, |
||
4142 | { Bad_Opcode }, |
||
6324 | serge | 4143 | { "addsubpd", { XM, EXx }, 0 }, |
4144 | { "addsubps", { XM, EXx }, 0 }, |
||
5221 | serge | 4145 | }, |
4146 | |||
4147 | /* PREFIX_0FD6 */ |
||
4148 | { |
||
4149 | { Bad_Opcode }, |
||
6324 | serge | 4150 | { "movq2dq",{ XM, MS }, 0 }, |
4151 | { "movq", { EXqS, XM }, 0 }, |
||
4152 | { "movdq2q",{ MX, XS }, 0 }, |
||
5221 | serge | 4153 | }, |
4154 | |||
4155 | /* PREFIX_0FE6 */ |
||
4156 | { |
||
4157 | { Bad_Opcode }, |
||
6324 | serge | 4158 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4159 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, |
||
4160 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, |
||
5221 | serge | 4161 | }, |
4162 | |||
4163 | /* PREFIX_0FE7 */ |
||
4164 | { |
||
6324 | serge | 4165 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
5221 | serge | 4166 | { Bad_Opcode }, |
4167 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
||
4168 | }, |
||
4169 | |||
4170 | /* PREFIX_0FF0 */ |
||
4171 | { |
||
4172 | { Bad_Opcode }, |
||
4173 | { Bad_Opcode }, |
||
4174 | { Bad_Opcode }, |
||
4175 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
||
4176 | }, |
||
4177 | |||
4178 | /* PREFIX_0FF7 */ |
||
4179 | { |
||
6324 | serge | 4180 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
5221 | serge | 4181 | { Bad_Opcode }, |
6324 | serge | 4182 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
5221 | serge | 4183 | }, |
4184 | |||
4185 | /* PREFIX_0F3810 */ |
||
4186 | { |
||
4187 | { Bad_Opcode }, |
||
4188 | { Bad_Opcode }, |
||
6324 | serge | 4189 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
5221 | serge | 4190 | }, |
4191 | |||
4192 | /* PREFIX_0F3814 */ |
||
4193 | { |
||
4194 | { Bad_Opcode }, |
||
4195 | { Bad_Opcode }, |
||
6324 | serge | 4196 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
5221 | serge | 4197 | }, |
4198 | |||
4199 | /* PREFIX_0F3815 */ |
||
4200 | { |
||
4201 | { Bad_Opcode }, |
||
4202 | { Bad_Opcode }, |
||
6324 | serge | 4203 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
5221 | serge | 4204 | }, |
4205 | |||
4206 | /* PREFIX_0F3817 */ |
||
4207 | { |
||
4208 | { Bad_Opcode }, |
||
4209 | { Bad_Opcode }, |
||
6324 | serge | 4210 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4211 | }, |
4212 | |||
4213 | /* PREFIX_0F3820 */ |
||
4214 | { |
||
4215 | { Bad_Opcode }, |
||
4216 | { Bad_Opcode }, |
||
6324 | serge | 4217 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 4218 | }, |
4219 | |||
4220 | /* PREFIX_0F3821 */ |
||
4221 | { |
||
4222 | { Bad_Opcode }, |
||
4223 | { Bad_Opcode }, |
||
6324 | serge | 4224 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
5221 | serge | 4225 | }, |
4226 | |||
4227 | /* PREFIX_0F3822 */ |
||
4228 | { |
||
4229 | { Bad_Opcode }, |
||
4230 | { Bad_Opcode }, |
||
6324 | serge | 4231 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
5221 | serge | 4232 | }, |
4233 | |||
4234 | /* PREFIX_0F3823 */ |
||
4235 | { |
||
4236 | { Bad_Opcode }, |
||
4237 | { Bad_Opcode }, |
||
6324 | serge | 4238 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 4239 | }, |
4240 | |||
4241 | /* PREFIX_0F3824 */ |
||
4242 | { |
||
4243 | { Bad_Opcode }, |
||
4244 | { Bad_Opcode }, |
||
6324 | serge | 4245 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
5221 | serge | 4246 | }, |
4247 | |||
4248 | /* PREFIX_0F3825 */ |
||
4249 | { |
||
4250 | { Bad_Opcode }, |
||
4251 | { Bad_Opcode }, |
||
6324 | serge | 4252 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 4253 | }, |
4254 | |||
4255 | /* PREFIX_0F3828 */ |
||
4256 | { |
||
4257 | { Bad_Opcode }, |
||
4258 | { Bad_Opcode }, |
||
6324 | serge | 4259 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4260 | }, |
4261 | |||
4262 | /* PREFIX_0F3829 */ |
||
4263 | { |
||
4264 | { Bad_Opcode }, |
||
4265 | { Bad_Opcode }, |
||
6324 | serge | 4266 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4267 | }, |
4268 | |||
4269 | /* PREFIX_0F382A */ |
||
4270 | { |
||
4271 | { Bad_Opcode }, |
||
4272 | { Bad_Opcode }, |
||
4273 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
||
4274 | }, |
||
4275 | |||
4276 | /* PREFIX_0F382B */ |
||
4277 | { |
||
4278 | { Bad_Opcode }, |
||
4279 | { Bad_Opcode }, |
||
6324 | serge | 4280 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4281 | }, |
4282 | |||
4283 | /* PREFIX_0F3830 */ |
||
4284 | { |
||
4285 | { Bad_Opcode }, |
||
4286 | { Bad_Opcode }, |
||
6324 | serge | 4287 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 4288 | }, |
4289 | |||
4290 | /* PREFIX_0F3831 */ |
||
4291 | { |
||
4292 | { Bad_Opcode }, |
||
4293 | { Bad_Opcode }, |
||
6324 | serge | 4294 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
5221 | serge | 4295 | }, |
4296 | |||
4297 | /* PREFIX_0F3832 */ |
||
4298 | { |
||
4299 | { Bad_Opcode }, |
||
4300 | { Bad_Opcode }, |
||
6324 | serge | 4301 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
5221 | serge | 4302 | }, |
4303 | |||
4304 | /* PREFIX_0F3833 */ |
||
4305 | { |
||
4306 | { Bad_Opcode }, |
||
4307 | { Bad_Opcode }, |
||
6324 | serge | 4308 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 4309 | }, |
4310 | |||
4311 | /* PREFIX_0F3834 */ |
||
4312 | { |
||
4313 | { Bad_Opcode }, |
||
4314 | { Bad_Opcode }, |
||
6324 | serge | 4315 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
5221 | serge | 4316 | }, |
4317 | |||
4318 | /* PREFIX_0F3835 */ |
||
4319 | { |
||
4320 | { Bad_Opcode }, |
||
4321 | { Bad_Opcode }, |
||
6324 | serge | 4322 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 4323 | }, |
4324 | |||
4325 | /* PREFIX_0F3837 */ |
||
4326 | { |
||
4327 | { Bad_Opcode }, |
||
4328 | { Bad_Opcode }, |
||
6324 | serge | 4329 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4330 | }, |
4331 | |||
4332 | /* PREFIX_0F3838 */ |
||
4333 | { |
||
4334 | { Bad_Opcode }, |
||
4335 | { Bad_Opcode }, |
||
6324 | serge | 4336 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4337 | }, |
4338 | |||
4339 | /* PREFIX_0F3839 */ |
||
4340 | { |
||
4341 | { Bad_Opcode }, |
||
4342 | { Bad_Opcode }, |
||
6324 | serge | 4343 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4344 | }, |
4345 | |||
4346 | /* PREFIX_0F383A */ |
||
4347 | { |
||
4348 | { Bad_Opcode }, |
||
4349 | { Bad_Opcode }, |
||
6324 | serge | 4350 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4351 | }, |
4352 | |||
4353 | /* PREFIX_0F383B */ |
||
4354 | { |
||
4355 | { Bad_Opcode }, |
||
4356 | { Bad_Opcode }, |
||
6324 | serge | 4357 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4358 | }, |
4359 | |||
4360 | /* PREFIX_0F383C */ |
||
4361 | { |
||
4362 | { Bad_Opcode }, |
||
4363 | { Bad_Opcode }, |
||
6324 | serge | 4364 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4365 | }, |
4366 | |||
4367 | /* PREFIX_0F383D */ |
||
4368 | { |
||
4369 | { Bad_Opcode }, |
||
4370 | { Bad_Opcode }, |
||
6324 | serge | 4371 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4372 | }, |
4373 | |||
4374 | /* PREFIX_0F383E */ |
||
4375 | { |
||
4376 | { Bad_Opcode }, |
||
4377 | { Bad_Opcode }, |
||
6324 | serge | 4378 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4379 | }, |
4380 | |||
4381 | /* PREFIX_0F383F */ |
||
4382 | { |
||
4383 | { Bad_Opcode }, |
||
4384 | { Bad_Opcode }, |
||
6324 | serge | 4385 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4386 | }, |
4387 | |||
4388 | /* PREFIX_0F3840 */ |
||
4389 | { |
||
4390 | { Bad_Opcode }, |
||
4391 | { Bad_Opcode }, |
||
6324 | serge | 4392 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4393 | }, |
4394 | |||
4395 | /* PREFIX_0F3841 */ |
||
4396 | { |
||
4397 | { Bad_Opcode }, |
||
4398 | { Bad_Opcode }, |
||
6324 | serge | 4399 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4400 | }, |
4401 | |||
4402 | /* PREFIX_0F3880 */ |
||
4403 | { |
||
4404 | { Bad_Opcode }, |
||
4405 | { Bad_Opcode }, |
||
6324 | serge | 4406 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
5221 | serge | 4407 | }, |
4408 | |||
4409 | /* PREFIX_0F3881 */ |
||
4410 | { |
||
4411 | { Bad_Opcode }, |
||
4412 | { Bad_Opcode }, |
||
6324 | serge | 4413 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
5221 | serge | 4414 | }, |
4415 | |||
4416 | /* PREFIX_0F3882 */ |
||
4417 | { |
||
4418 | { Bad_Opcode }, |
||
4419 | { Bad_Opcode }, |
||
6324 | serge | 4420 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
5221 | serge | 4421 | }, |
4422 | |||
4423 | /* PREFIX_0F38C8 */ |
||
4424 | { |
||
6324 | serge | 4425 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
5221 | serge | 4426 | }, |
4427 | |||
4428 | /* PREFIX_0F38C9 */ |
||
4429 | { |
||
6324 | serge | 4430 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
5221 | serge | 4431 | }, |
4432 | |||
4433 | /* PREFIX_0F38CA */ |
||
4434 | { |
||
6324 | serge | 4435 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
5221 | serge | 4436 | }, |
4437 | |||
4438 | /* PREFIX_0F38CB */ |
||
4439 | { |
||
6324 | serge | 4440 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
5221 | serge | 4441 | }, |
4442 | |||
4443 | /* PREFIX_0F38CC */ |
||
4444 | { |
||
6324 | serge | 4445 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
5221 | serge | 4446 | }, |
4447 | |||
4448 | /* PREFIX_0F38CD */ |
||
4449 | { |
||
6324 | serge | 4450 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
5221 | serge | 4451 | }, |
4452 | |||
4453 | /* PREFIX_0F38DB */ |
||
4454 | { |
||
4455 | { Bad_Opcode }, |
||
4456 | { Bad_Opcode }, |
||
6324 | serge | 4457 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4458 | }, |
4459 | |||
4460 | /* PREFIX_0F38DC */ |
||
4461 | { |
||
4462 | { Bad_Opcode }, |
||
4463 | { Bad_Opcode }, |
||
6324 | serge | 4464 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4465 | }, |
4466 | |||
4467 | /* PREFIX_0F38DD */ |
||
4468 | { |
||
4469 | { Bad_Opcode }, |
||
4470 | { Bad_Opcode }, |
||
6324 | serge | 4471 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4472 | }, |
4473 | |||
4474 | /* PREFIX_0F38DE */ |
||
4475 | { |
||
4476 | { Bad_Opcode }, |
||
4477 | { Bad_Opcode }, |
||
6324 | serge | 4478 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4479 | }, |
4480 | |||
4481 | /* PREFIX_0F38DF */ |
||
4482 | { |
||
4483 | { Bad_Opcode }, |
||
4484 | { Bad_Opcode }, |
||
6324 | serge | 4485 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
5221 | serge | 4486 | }, |
4487 | |||
4488 | /* PREFIX_0F38F0 */ |
||
4489 | { |
||
6324 | serge | 4490 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
5221 | serge | 4491 | { Bad_Opcode }, |
6324 | serge | 4492 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4493 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, |
||
5221 | serge | 4494 | }, |
4495 | |||
4496 | /* PREFIX_0F38F1 */ |
||
4497 | { |
||
6324 | serge | 4498 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
5221 | serge | 4499 | { Bad_Opcode }, |
6324 | serge | 4500 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4501 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, |
||
5221 | serge | 4502 | }, |
4503 | |||
4504 | /* PREFIX_0F38F6 */ |
||
4505 | { |
||
4506 | { Bad_Opcode }, |
||
6324 | serge | 4507 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4508 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, |
||
5221 | serge | 4509 | { Bad_Opcode }, |
4510 | }, |
||
4511 | |||
4512 | /* PREFIX_0F3A08 */ |
||
4513 | { |
||
4514 | { Bad_Opcode }, |
||
4515 | { Bad_Opcode }, |
||
6324 | serge | 4516 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4517 | }, |
4518 | |||
4519 | /* PREFIX_0F3A09 */ |
||
4520 | { |
||
4521 | { Bad_Opcode }, |
||
4522 | { Bad_Opcode }, |
||
6324 | serge | 4523 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4524 | }, |
4525 | |||
4526 | /* PREFIX_0F3A0A */ |
||
4527 | { |
||
4528 | { Bad_Opcode }, |
||
4529 | { Bad_Opcode }, |
||
6324 | serge | 4530 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4531 | }, |
4532 | |||
4533 | /* PREFIX_0F3A0B */ |
||
4534 | { |
||
4535 | { Bad_Opcode }, |
||
4536 | { Bad_Opcode }, |
||
6324 | serge | 4537 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4538 | }, |
4539 | |||
4540 | /* PREFIX_0F3A0C */ |
||
4541 | { |
||
4542 | { Bad_Opcode }, |
||
4543 | { Bad_Opcode }, |
||
6324 | serge | 4544 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4545 | }, |
4546 | |||
4547 | /* PREFIX_0F3A0D */ |
||
4548 | { |
||
4549 | { Bad_Opcode }, |
||
4550 | { Bad_Opcode }, |
||
6324 | serge | 4551 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4552 | }, |
4553 | |||
4554 | /* PREFIX_0F3A0E */ |
||
4555 | { |
||
4556 | { Bad_Opcode }, |
||
4557 | { Bad_Opcode }, |
||
6324 | serge | 4558 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4559 | }, |
4560 | |||
4561 | /* PREFIX_0F3A14 */ |
||
4562 | { |
||
4563 | { Bad_Opcode }, |
||
4564 | { Bad_Opcode }, |
||
6324 | serge | 4565 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4566 | }, |
4567 | |||
4568 | /* PREFIX_0F3A15 */ |
||
4569 | { |
||
4570 | { Bad_Opcode }, |
||
4571 | { Bad_Opcode }, |
||
6324 | serge | 4572 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4573 | }, |
4574 | |||
4575 | /* PREFIX_0F3A16 */ |
||
4576 | { |
||
4577 | { Bad_Opcode }, |
||
4578 | { Bad_Opcode }, |
||
6324 | serge | 4579 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4580 | }, |
4581 | |||
4582 | /* PREFIX_0F3A17 */ |
||
4583 | { |
||
4584 | { Bad_Opcode }, |
||
4585 | { Bad_Opcode }, |
||
6324 | serge | 4586 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4587 | }, |
4588 | |||
4589 | /* PREFIX_0F3A20 */ |
||
4590 | { |
||
4591 | { Bad_Opcode }, |
||
4592 | { Bad_Opcode }, |
||
6324 | serge | 4593 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4594 | }, |
4595 | |||
4596 | /* PREFIX_0F3A21 */ |
||
4597 | { |
||
4598 | { Bad_Opcode }, |
||
4599 | { Bad_Opcode }, |
||
6324 | serge | 4600 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4601 | }, |
4602 | |||
4603 | /* PREFIX_0F3A22 */ |
||
4604 | { |
||
4605 | { Bad_Opcode }, |
||
4606 | { Bad_Opcode }, |
||
6324 | serge | 4607 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4608 | }, |
4609 | |||
4610 | /* PREFIX_0F3A40 */ |
||
4611 | { |
||
4612 | { Bad_Opcode }, |
||
4613 | { Bad_Opcode }, |
||
6324 | serge | 4614 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4615 | }, |
4616 | |||
4617 | /* PREFIX_0F3A41 */ |
||
4618 | { |
||
4619 | { Bad_Opcode }, |
||
4620 | { Bad_Opcode }, |
||
6324 | serge | 4621 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4622 | }, |
4623 | |||
4624 | /* PREFIX_0F3A42 */ |
||
4625 | { |
||
4626 | { Bad_Opcode }, |
||
4627 | { Bad_Opcode }, |
||
6324 | serge | 4628 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4629 | }, |
4630 | |||
4631 | /* PREFIX_0F3A44 */ |
||
4632 | { |
||
4633 | { Bad_Opcode }, |
||
4634 | { Bad_Opcode }, |
||
6324 | serge | 4635 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
5221 | serge | 4636 | }, |
4637 | |||
4638 | /* PREFIX_0F3A60 */ |
||
4639 | { |
||
4640 | { Bad_Opcode }, |
||
4641 | { Bad_Opcode }, |
||
6324 | serge | 4642 | { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4643 | }, |
4644 | |||
4645 | /* PREFIX_0F3A61 */ |
||
4646 | { |
||
4647 | { Bad_Opcode }, |
||
4648 | { Bad_Opcode }, |
||
6324 | serge | 4649 | { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4650 | }, |
4651 | |||
4652 | /* PREFIX_0F3A62 */ |
||
4653 | { |
||
4654 | { Bad_Opcode }, |
||
4655 | { Bad_Opcode }, |
||
6324 | serge | 4656 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4657 | }, |
4658 | |||
4659 | /* PREFIX_0F3A63 */ |
||
4660 | { |
||
4661 | { Bad_Opcode }, |
||
4662 | { Bad_Opcode }, |
||
6324 | serge | 4663 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4664 | }, |
4665 | |||
4666 | /* PREFIX_0F3ACC */ |
||
4667 | { |
||
6324 | serge | 4668 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4669 | }, |
4670 | |||
4671 | /* PREFIX_0F3ADF */ |
||
4672 | { |
||
4673 | { Bad_Opcode }, |
||
4674 | { Bad_Opcode }, |
||
6324 | serge | 4675 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
5221 | serge | 4676 | }, |
4677 | |||
4678 | /* PREFIX_VEX_0F10 */ |
||
4679 | { |
||
4680 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
||
4681 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, |
||
4682 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, |
||
4683 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, |
||
4684 | }, |
||
4685 | |||
4686 | /* PREFIX_VEX_0F11 */ |
||
4687 | { |
||
4688 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
||
4689 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, |
||
4690 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, |
||
4691 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, |
||
4692 | }, |
||
4693 | |||
4694 | /* PREFIX_VEX_0F12 */ |
||
4695 | { |
||
4696 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
||
4697 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, |
||
4698 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
||
4699 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, |
||
4700 | }, |
||
4701 | |||
4702 | /* PREFIX_VEX_0F16 */ |
||
4703 | { |
||
4704 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
||
4705 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, |
||
4706 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
||
4707 | }, |
||
4708 | |||
4709 | /* PREFIX_VEX_0F2A */ |
||
4710 | { |
||
4711 | { Bad_Opcode }, |
||
4712 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
||
4713 | { Bad_Opcode }, |
||
4714 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
||
4715 | }, |
||
4716 | |||
4717 | /* PREFIX_VEX_0F2C */ |
||
4718 | { |
||
4719 | { Bad_Opcode }, |
||
4720 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
||
4721 | { Bad_Opcode }, |
||
4722 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
||
4723 | }, |
||
4724 | |||
4725 | /* PREFIX_VEX_0F2D */ |
||
4726 | { |
||
4727 | { Bad_Opcode }, |
||
4728 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
||
4729 | { Bad_Opcode }, |
||
4730 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
||
4731 | }, |
||
4732 | |||
4733 | /* PREFIX_VEX_0F2E */ |
||
4734 | { |
||
4735 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
||
4736 | { Bad_Opcode }, |
||
4737 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
||
4738 | }, |
||
4739 | |||
4740 | /* PREFIX_VEX_0F2F */ |
||
4741 | { |
||
4742 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
||
4743 | { Bad_Opcode }, |
||
4744 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
||
4745 | }, |
||
4746 | |||
4747 | /* PREFIX_VEX_0F41 */ |
||
4748 | { |
||
4749 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, |
||
6324 | serge | 4750 | { Bad_Opcode }, |
4751 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, |
||
5221 | serge | 4752 | }, |
4753 | |||
4754 | /* PREFIX_VEX_0F42 */ |
||
4755 | { |
||
4756 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, |
||
6324 | serge | 4757 | { Bad_Opcode }, |
4758 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, |
||
5221 | serge | 4759 | }, |
4760 | |||
4761 | /* PREFIX_VEX_0F44 */ |
||
4762 | { |
||
4763 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
||
6324 | serge | 4764 | { Bad_Opcode }, |
4765 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, |
||
5221 | serge | 4766 | }, |
4767 | |||
4768 | /* PREFIX_VEX_0F45 */ |
||
4769 | { |
||
4770 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
||
6324 | serge | 4771 | { Bad_Opcode }, |
4772 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, |
||
5221 | serge | 4773 | }, |
4774 | |||
4775 | /* PREFIX_VEX_0F46 */ |
||
4776 | { |
||
4777 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
||
6324 | serge | 4778 | { Bad_Opcode }, |
4779 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, |
||
5221 | serge | 4780 | }, |
4781 | |||
4782 | /* PREFIX_VEX_0F47 */ |
||
4783 | { |
||
4784 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
||
6324 | serge | 4785 | { Bad_Opcode }, |
4786 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, |
||
5221 | serge | 4787 | }, |
4788 | |||
6324 | serge | 4789 | /* PREFIX_VEX_0F4A */ |
4790 | { |
||
4791 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
||
4792 | { Bad_Opcode }, |
||
4793 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
||
4794 | }, |
||
4795 | |||
5221 | serge | 4796 | /* PREFIX_VEX_0F4B */ |
4797 | { |
||
6324 | serge | 4798 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, |
5221 | serge | 4799 | { Bad_Opcode }, |
4800 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, |
||
4801 | }, |
||
4802 | |||
4803 | /* PREFIX_VEX_0F51 */ |
||
4804 | { |
||
4805 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
||
4806 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, |
||
4807 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, |
||
4808 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, |
||
4809 | }, |
||
4810 | |||
4811 | /* PREFIX_VEX_0F52 */ |
||
4812 | { |
||
4813 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
||
4814 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, |
||
4815 | }, |
||
4816 | |||
4817 | /* PREFIX_VEX_0F53 */ |
||
4818 | { |
||
4819 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
||
4820 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, |
||
4821 | }, |
||
4822 | |||
4823 | /* PREFIX_VEX_0F58 */ |
||
4824 | { |
||
4825 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
||
4826 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, |
||
4827 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, |
||
4828 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, |
||
4829 | }, |
||
4830 | |||
4831 | /* PREFIX_VEX_0F59 */ |
||
4832 | { |
||
4833 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
||
4834 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, |
||
4835 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, |
||
4836 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, |
||
4837 | }, |
||
4838 | |||
4839 | /* PREFIX_VEX_0F5A */ |
||
4840 | { |
||
4841 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
||
4842 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, |
||
6324 | serge | 4843 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
5221 | serge | 4844 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
4845 | }, |
||
4846 | |||
4847 | /* PREFIX_VEX_0F5B */ |
||
4848 | { |
||
4849 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
||
4850 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, |
||
4851 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, |
||
4852 | }, |
||
4853 | |||
4854 | /* PREFIX_VEX_0F5C */ |
||
4855 | { |
||
4856 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
||
4857 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, |
||
4858 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, |
||
4859 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, |
||
4860 | }, |
||
4861 | |||
4862 | /* PREFIX_VEX_0F5D */ |
||
4863 | { |
||
4864 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
||
4865 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, |
||
4866 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, |
||
4867 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, |
||
4868 | }, |
||
4869 | |||
4870 | /* PREFIX_VEX_0F5E */ |
||
4871 | { |
||
4872 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
||
4873 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, |
||
4874 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, |
||
4875 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, |
||
4876 | }, |
||
4877 | |||
4878 | /* PREFIX_VEX_0F5F */ |
||
4879 | { |
||
4880 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
||
4881 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, |
||
4882 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, |
||
4883 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, |
||
4884 | }, |
||
4885 | |||
4886 | /* PREFIX_VEX_0F60 */ |
||
4887 | { |
||
4888 | { Bad_Opcode }, |
||
4889 | { Bad_Opcode }, |
||
4890 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
||
4891 | }, |
||
4892 | |||
4893 | /* PREFIX_VEX_0F61 */ |
||
4894 | { |
||
4895 | { Bad_Opcode }, |
||
4896 | { Bad_Opcode }, |
||
4897 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
||
4898 | }, |
||
4899 | |||
4900 | /* PREFIX_VEX_0F62 */ |
||
4901 | { |
||
4902 | { Bad_Opcode }, |
||
4903 | { Bad_Opcode }, |
||
4904 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
||
4905 | }, |
||
4906 | |||
4907 | /* PREFIX_VEX_0F63 */ |
||
4908 | { |
||
4909 | { Bad_Opcode }, |
||
4910 | { Bad_Opcode }, |
||
4911 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
||
4912 | }, |
||
4913 | |||
4914 | /* PREFIX_VEX_0F64 */ |
||
4915 | { |
||
4916 | { Bad_Opcode }, |
||
4917 | { Bad_Opcode }, |
||
4918 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
||
4919 | }, |
||
4920 | |||
4921 | /* PREFIX_VEX_0F65 */ |
||
4922 | { |
||
4923 | { Bad_Opcode }, |
||
4924 | { Bad_Opcode }, |
||
4925 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
||
4926 | }, |
||
4927 | |||
4928 | /* PREFIX_VEX_0F66 */ |
||
4929 | { |
||
4930 | { Bad_Opcode }, |
||
4931 | { Bad_Opcode }, |
||
4932 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
||
4933 | }, |
||
4934 | |||
4935 | /* PREFIX_VEX_0F67 */ |
||
4936 | { |
||
4937 | { Bad_Opcode }, |
||
4938 | { Bad_Opcode }, |
||
4939 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
||
4940 | }, |
||
4941 | |||
4942 | /* PREFIX_VEX_0F68 */ |
||
4943 | { |
||
4944 | { Bad_Opcode }, |
||
4945 | { Bad_Opcode }, |
||
4946 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
||
4947 | }, |
||
4948 | |||
4949 | /* PREFIX_VEX_0F69 */ |
||
4950 | { |
||
4951 | { Bad_Opcode }, |
||
4952 | { Bad_Opcode }, |
||
4953 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
||
4954 | }, |
||
4955 | |||
4956 | /* PREFIX_VEX_0F6A */ |
||
4957 | { |
||
4958 | { Bad_Opcode }, |
||
4959 | { Bad_Opcode }, |
||
4960 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
||
4961 | }, |
||
4962 | |||
4963 | /* PREFIX_VEX_0F6B */ |
||
4964 | { |
||
4965 | { Bad_Opcode }, |
||
4966 | { Bad_Opcode }, |
||
4967 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
||
4968 | }, |
||
4969 | |||
4970 | /* PREFIX_VEX_0F6C */ |
||
4971 | { |
||
4972 | { Bad_Opcode }, |
||
4973 | { Bad_Opcode }, |
||
4974 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
||
4975 | }, |
||
4976 | |||
4977 | /* PREFIX_VEX_0F6D */ |
||
4978 | { |
||
4979 | { Bad_Opcode }, |
||
4980 | { Bad_Opcode }, |
||
4981 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
||
4982 | }, |
||
4983 | |||
4984 | /* PREFIX_VEX_0F6E */ |
||
4985 | { |
||
4986 | { Bad_Opcode }, |
||
4987 | { Bad_Opcode }, |
||
4988 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
||
4989 | }, |
||
4990 | |||
4991 | /* PREFIX_VEX_0F6F */ |
||
4992 | { |
||
4993 | { Bad_Opcode }, |
||
4994 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
||
4995 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, |
||
4996 | }, |
||
4997 | |||
4998 | /* PREFIX_VEX_0F70 */ |
||
4999 | { |
||
5000 | { Bad_Opcode }, |
||
5001 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
||
5002 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, |
||
5003 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, |
||
5004 | }, |
||
5005 | |||
5006 | /* PREFIX_VEX_0F71_REG_2 */ |
||
5007 | { |
||
5008 | { Bad_Opcode }, |
||
5009 | { Bad_Opcode }, |
||
5010 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
||
5011 | }, |
||
5012 | |||
5013 | /* PREFIX_VEX_0F71_REG_4 */ |
||
5014 | { |
||
5015 | { Bad_Opcode }, |
||
5016 | { Bad_Opcode }, |
||
5017 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
||
5018 | }, |
||
5019 | |||
5020 | /* PREFIX_VEX_0F71_REG_6 */ |
||
5021 | { |
||
5022 | { Bad_Opcode }, |
||
5023 | { Bad_Opcode }, |
||
5024 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
||
5025 | }, |
||
5026 | |||
5027 | /* PREFIX_VEX_0F72_REG_2 */ |
||
5028 | { |
||
5029 | { Bad_Opcode }, |
||
5030 | { Bad_Opcode }, |
||
5031 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
||
5032 | }, |
||
5033 | |||
5034 | /* PREFIX_VEX_0F72_REG_4 */ |
||
5035 | { |
||
5036 | { Bad_Opcode }, |
||
5037 | { Bad_Opcode }, |
||
5038 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
||
5039 | }, |
||
5040 | |||
5041 | /* PREFIX_VEX_0F72_REG_6 */ |
||
5042 | { |
||
5043 | { Bad_Opcode }, |
||
5044 | { Bad_Opcode }, |
||
5045 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
||
5046 | }, |
||
5047 | |||
5048 | /* PREFIX_VEX_0F73_REG_2 */ |
||
5049 | { |
||
5050 | { Bad_Opcode }, |
||
5051 | { Bad_Opcode }, |
||
5052 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
||
5053 | }, |
||
5054 | |||
5055 | /* PREFIX_VEX_0F73_REG_3 */ |
||
5056 | { |
||
5057 | { Bad_Opcode }, |
||
5058 | { Bad_Opcode }, |
||
5059 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
||
5060 | }, |
||
5061 | |||
5062 | /* PREFIX_VEX_0F73_REG_6 */ |
||
5063 | { |
||
5064 | { Bad_Opcode }, |
||
5065 | { Bad_Opcode }, |
||
5066 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
||
5067 | }, |
||
5068 | |||
5069 | /* PREFIX_VEX_0F73_REG_7 */ |
||
5070 | { |
||
5071 | { Bad_Opcode }, |
||
5072 | { Bad_Opcode }, |
||
5073 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
||
5074 | }, |
||
5075 | |||
5076 | /* PREFIX_VEX_0F74 */ |
||
5077 | { |
||
5078 | { Bad_Opcode }, |
||
5079 | { Bad_Opcode }, |
||
5080 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
||
5081 | }, |
||
5082 | |||
5083 | /* PREFIX_VEX_0F75 */ |
||
5084 | { |
||
5085 | { Bad_Opcode }, |
||
5086 | { Bad_Opcode }, |
||
5087 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
||
5088 | }, |
||
5089 | |||
5090 | /* PREFIX_VEX_0F76 */ |
||
5091 | { |
||
5092 | { Bad_Opcode }, |
||
5093 | { Bad_Opcode }, |
||
5094 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
||
5095 | }, |
||
5096 | |||
5097 | /* PREFIX_VEX_0F77 */ |
||
5098 | { |
||
5099 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
||
5100 | }, |
||
5101 | |||
5102 | /* PREFIX_VEX_0F7C */ |
||
5103 | { |
||
5104 | { Bad_Opcode }, |
||
5105 | { Bad_Opcode }, |
||
5106 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
||
5107 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, |
||
5108 | }, |
||
5109 | |||
5110 | /* PREFIX_VEX_0F7D */ |
||
5111 | { |
||
5112 | { Bad_Opcode }, |
||
5113 | { Bad_Opcode }, |
||
5114 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
||
5115 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, |
||
5116 | }, |
||
5117 | |||
5118 | /* PREFIX_VEX_0F7E */ |
||
5119 | { |
||
5120 | { Bad_Opcode }, |
||
5121 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
||
5122 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, |
||
5123 | }, |
||
5124 | |||
5125 | /* PREFIX_VEX_0F7F */ |
||
5126 | { |
||
5127 | { Bad_Opcode }, |
||
5128 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
||
5129 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, |
||
5130 | }, |
||
5131 | |||
5132 | /* PREFIX_VEX_0F90 */ |
||
5133 | { |
||
5134 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
||
6324 | serge | 5135 | { Bad_Opcode }, |
5136 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, |
||
5221 | serge | 5137 | }, |
5138 | |||
5139 | /* PREFIX_VEX_0F91 */ |
||
5140 | { |
||
5141 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
||
6324 | serge | 5142 | { Bad_Opcode }, |
5143 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, |
||
5221 | serge | 5144 | }, |
5145 | |||
5146 | /* PREFIX_VEX_0F92 */ |
||
5147 | { |
||
5148 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
||
6324 | serge | 5149 | { Bad_Opcode }, |
5150 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
||
5151 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
||
5221 | serge | 5152 | }, |
5153 | |||
5154 | /* PREFIX_VEX_0F93 */ |
||
5155 | { |
||
5156 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
||
6324 | serge | 5157 | { Bad_Opcode }, |
5158 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
||
5159 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
||
5221 | serge | 5160 | }, |
5161 | |||
5162 | /* PREFIX_VEX_0F98 */ |
||
5163 | { |
||
5164 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
||
6324 | serge | 5165 | { Bad_Opcode }, |
5166 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, |
||
5221 | serge | 5167 | }, |
5168 | |||
6324 | serge | 5169 | /* PREFIX_VEX_0F99 */ |
5170 | { |
||
5171 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, |
||
5172 | { Bad_Opcode }, |
||
5173 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, |
||
5174 | }, |
||
5175 | |||
5221 | serge | 5176 | /* PREFIX_VEX_0FC2 */ |
5177 | { |
||
5178 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
||
5179 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, |
||
5180 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, |
||
5181 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, |
||
5182 | }, |
||
5183 | |||
5184 | /* PREFIX_VEX_0FC4 */ |
||
5185 | { |
||
5186 | { Bad_Opcode }, |
||
5187 | { Bad_Opcode }, |
||
5188 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
||
5189 | }, |
||
5190 | |||
5191 | /* PREFIX_VEX_0FC5 */ |
||
5192 | { |
||
5193 | { Bad_Opcode }, |
||
5194 | { Bad_Opcode }, |
||
5195 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
||
5196 | }, |
||
5197 | |||
5198 | /* PREFIX_VEX_0FD0 */ |
||
5199 | { |
||
5200 | { Bad_Opcode }, |
||
5201 | { Bad_Opcode }, |
||
5202 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
||
5203 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, |
||
5204 | }, |
||
5205 | |||
5206 | /* PREFIX_VEX_0FD1 */ |
||
5207 | { |
||
5208 | { Bad_Opcode }, |
||
5209 | { Bad_Opcode }, |
||
5210 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
||
5211 | }, |
||
5212 | |||
5213 | /* PREFIX_VEX_0FD2 */ |
||
5214 | { |
||
5215 | { Bad_Opcode }, |
||
5216 | { Bad_Opcode }, |
||
5217 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
||
5218 | }, |
||
5219 | |||
5220 | /* PREFIX_VEX_0FD3 */ |
||
5221 | { |
||
5222 | { Bad_Opcode }, |
||
5223 | { Bad_Opcode }, |
||
5224 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
||
5225 | }, |
||
5226 | |||
5227 | /* PREFIX_VEX_0FD4 */ |
||
5228 | { |
||
5229 | { Bad_Opcode }, |
||
5230 | { Bad_Opcode }, |
||
5231 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
||
5232 | }, |
||
5233 | |||
5234 | /* PREFIX_VEX_0FD5 */ |
||
5235 | { |
||
5236 | { Bad_Opcode }, |
||
5237 | { Bad_Opcode }, |
||
5238 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
||
5239 | }, |
||
5240 | |||
5241 | /* PREFIX_VEX_0FD6 */ |
||
5242 | { |
||
5243 | { Bad_Opcode }, |
||
5244 | { Bad_Opcode }, |
||
5245 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
||
5246 | }, |
||
5247 | |||
5248 | /* PREFIX_VEX_0FD7 */ |
||
5249 | { |
||
5250 | { Bad_Opcode }, |
||
5251 | { Bad_Opcode }, |
||
5252 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
||
5253 | }, |
||
5254 | |||
5255 | /* PREFIX_VEX_0FD8 */ |
||
5256 | { |
||
5257 | { Bad_Opcode }, |
||
5258 | { Bad_Opcode }, |
||
5259 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
||
5260 | }, |
||
5261 | |||
5262 | /* PREFIX_VEX_0FD9 */ |
||
5263 | { |
||
5264 | { Bad_Opcode }, |
||
5265 | { Bad_Opcode }, |
||
5266 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
||
5267 | }, |
||
5268 | |||
5269 | /* PREFIX_VEX_0FDA */ |
||
5270 | { |
||
5271 | { Bad_Opcode }, |
||
5272 | { Bad_Opcode }, |
||
5273 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
||
5274 | }, |
||
5275 | |||
5276 | /* PREFIX_VEX_0FDB */ |
||
5277 | { |
||
5278 | { Bad_Opcode }, |
||
5279 | { Bad_Opcode }, |
||
5280 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
||
5281 | }, |
||
5282 | |||
5283 | /* PREFIX_VEX_0FDC */ |
||
5284 | { |
||
5285 | { Bad_Opcode }, |
||
5286 | { Bad_Opcode }, |
||
5287 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
||
5288 | }, |
||
5289 | |||
5290 | /* PREFIX_VEX_0FDD */ |
||
5291 | { |
||
5292 | { Bad_Opcode }, |
||
5293 | { Bad_Opcode }, |
||
5294 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
||
5295 | }, |
||
5296 | |||
5297 | /* PREFIX_VEX_0FDE */ |
||
5298 | { |
||
5299 | { Bad_Opcode }, |
||
5300 | { Bad_Opcode }, |
||
5301 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
||
5302 | }, |
||
5303 | |||
5304 | /* PREFIX_VEX_0FDF */ |
||
5305 | { |
||
5306 | { Bad_Opcode }, |
||
5307 | { Bad_Opcode }, |
||
5308 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
||
5309 | }, |
||
5310 | |||
5311 | /* PREFIX_VEX_0FE0 */ |
||
5312 | { |
||
5313 | { Bad_Opcode }, |
||
5314 | { Bad_Opcode }, |
||
5315 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
||
5316 | }, |
||
5317 | |||
5318 | /* PREFIX_VEX_0FE1 */ |
||
5319 | { |
||
5320 | { Bad_Opcode }, |
||
5321 | { Bad_Opcode }, |
||
5322 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
||
5323 | }, |
||
5324 | |||
5325 | /* PREFIX_VEX_0FE2 */ |
||
5326 | { |
||
5327 | { Bad_Opcode }, |
||
5328 | { Bad_Opcode }, |
||
5329 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
||
5330 | }, |
||
5331 | |||
5332 | /* PREFIX_VEX_0FE3 */ |
||
5333 | { |
||
5334 | { Bad_Opcode }, |
||
5335 | { Bad_Opcode }, |
||
5336 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
||
5337 | }, |
||
5338 | |||
5339 | /* PREFIX_VEX_0FE4 */ |
||
5340 | { |
||
5341 | { Bad_Opcode }, |
||
5342 | { Bad_Opcode }, |
||
5343 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
||
5344 | }, |
||
5345 | |||
5346 | /* PREFIX_VEX_0FE5 */ |
||
5347 | { |
||
5348 | { Bad_Opcode }, |
||
5349 | { Bad_Opcode }, |
||
5350 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
||
5351 | }, |
||
5352 | |||
5353 | /* PREFIX_VEX_0FE6 */ |
||
5354 | { |
||
5355 | { Bad_Opcode }, |
||
5356 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
||
5357 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, |
||
5358 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, |
||
5359 | }, |
||
5360 | |||
5361 | /* PREFIX_VEX_0FE7 */ |
||
5362 | { |
||
5363 | { Bad_Opcode }, |
||
5364 | { Bad_Opcode }, |
||
5365 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
||
5366 | }, |
||
5367 | |||
5368 | /* PREFIX_VEX_0FE8 */ |
||
5369 | { |
||
5370 | { Bad_Opcode }, |
||
5371 | { Bad_Opcode }, |
||
5372 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
||
5373 | }, |
||
5374 | |||
5375 | /* PREFIX_VEX_0FE9 */ |
||
5376 | { |
||
5377 | { Bad_Opcode }, |
||
5378 | { Bad_Opcode }, |
||
5379 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
||
5380 | }, |
||
5381 | |||
5382 | /* PREFIX_VEX_0FEA */ |
||
5383 | { |
||
5384 | { Bad_Opcode }, |
||
5385 | { Bad_Opcode }, |
||
5386 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
||
5387 | }, |
||
5388 | |||
5389 | /* PREFIX_VEX_0FEB */ |
||
5390 | { |
||
5391 | { Bad_Opcode }, |
||
5392 | { Bad_Opcode }, |
||
5393 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
||
5394 | }, |
||
5395 | |||
5396 | /* PREFIX_VEX_0FEC */ |
||
5397 | { |
||
5398 | { Bad_Opcode }, |
||
5399 | { Bad_Opcode }, |
||
5400 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
||
5401 | }, |
||
5402 | |||
5403 | /* PREFIX_VEX_0FED */ |
||
5404 | { |
||
5405 | { Bad_Opcode }, |
||
5406 | { Bad_Opcode }, |
||
5407 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
||
5408 | }, |
||
5409 | |||
5410 | /* PREFIX_VEX_0FEE */ |
||
5411 | { |
||
5412 | { Bad_Opcode }, |
||
5413 | { Bad_Opcode }, |
||
5414 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
||
5415 | }, |
||
5416 | |||
5417 | /* PREFIX_VEX_0FEF */ |
||
5418 | { |
||
5419 | { Bad_Opcode }, |
||
5420 | { Bad_Opcode }, |
||
5421 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
||
5422 | }, |
||
5423 | |||
5424 | /* PREFIX_VEX_0FF0 */ |
||
5425 | { |
||
5426 | { Bad_Opcode }, |
||
5427 | { Bad_Opcode }, |
||
5428 | { Bad_Opcode }, |
||
5429 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
||
5430 | }, |
||
5431 | |||
5432 | /* PREFIX_VEX_0FF1 */ |
||
5433 | { |
||
5434 | { Bad_Opcode }, |
||
5435 | { Bad_Opcode }, |
||
5436 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
||
5437 | }, |
||
5438 | |||
5439 | /* PREFIX_VEX_0FF2 */ |
||
5440 | { |
||
5441 | { Bad_Opcode }, |
||
5442 | { Bad_Opcode }, |
||
5443 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
||
5444 | }, |
||
5445 | |||
5446 | /* PREFIX_VEX_0FF3 */ |
||
5447 | { |
||
5448 | { Bad_Opcode }, |
||
5449 | { Bad_Opcode }, |
||
5450 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
||
5451 | }, |
||
5452 | |||
5453 | /* PREFIX_VEX_0FF4 */ |
||
5454 | { |
||
5455 | { Bad_Opcode }, |
||
5456 | { Bad_Opcode }, |
||
5457 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
||
5458 | }, |
||
5459 | |||
5460 | /* PREFIX_VEX_0FF5 */ |
||
5461 | { |
||
5462 | { Bad_Opcode }, |
||
5463 | { Bad_Opcode }, |
||
5464 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
||
5465 | }, |
||
5466 | |||
5467 | /* PREFIX_VEX_0FF6 */ |
||
5468 | { |
||
5469 | { Bad_Opcode }, |
||
5470 | { Bad_Opcode }, |
||
5471 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
||
5472 | }, |
||
5473 | |||
5474 | /* PREFIX_VEX_0FF7 */ |
||
5475 | { |
||
5476 | { Bad_Opcode }, |
||
5477 | { Bad_Opcode }, |
||
5478 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
||
5479 | }, |
||
5480 | |||
5481 | /* PREFIX_VEX_0FF8 */ |
||
5482 | { |
||
5483 | { Bad_Opcode }, |
||
5484 | { Bad_Opcode }, |
||
5485 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
||
5486 | }, |
||
5487 | |||
5488 | /* PREFIX_VEX_0FF9 */ |
||
5489 | { |
||
5490 | { Bad_Opcode }, |
||
5491 | { Bad_Opcode }, |
||
5492 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
||
5493 | }, |
||
5494 | |||
5495 | /* PREFIX_VEX_0FFA */ |
||
5496 | { |
||
5497 | { Bad_Opcode }, |
||
5498 | { Bad_Opcode }, |
||
5499 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
||
5500 | }, |
||
5501 | |||
5502 | /* PREFIX_VEX_0FFB */ |
||
5503 | { |
||
5504 | { Bad_Opcode }, |
||
5505 | { Bad_Opcode }, |
||
5506 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
||
5507 | }, |
||
5508 | |||
5509 | /* PREFIX_VEX_0FFC */ |
||
5510 | { |
||
5511 | { Bad_Opcode }, |
||
5512 | { Bad_Opcode }, |
||
5513 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
||
5514 | }, |
||
5515 | |||
5516 | /* PREFIX_VEX_0FFD */ |
||
5517 | { |
||
5518 | { Bad_Opcode }, |
||
5519 | { Bad_Opcode }, |
||
5520 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
||
5521 | }, |
||
5522 | |||
5523 | /* PREFIX_VEX_0FFE */ |
||
5524 | { |
||
5525 | { Bad_Opcode }, |
||
5526 | { Bad_Opcode }, |
||
5527 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
||
5528 | }, |
||
5529 | |||
5530 | /* PREFIX_VEX_0F3800 */ |
||
5531 | { |
||
5532 | { Bad_Opcode }, |
||
5533 | { Bad_Opcode }, |
||
5534 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
||
5535 | }, |
||
5536 | |||
5537 | /* PREFIX_VEX_0F3801 */ |
||
5538 | { |
||
5539 | { Bad_Opcode }, |
||
5540 | { Bad_Opcode }, |
||
5541 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
||
5542 | }, |
||
5543 | |||
5544 | /* PREFIX_VEX_0F3802 */ |
||
5545 | { |
||
5546 | { Bad_Opcode }, |
||
5547 | { Bad_Opcode }, |
||
5548 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
||
5549 | }, |
||
5550 | |||
5551 | /* PREFIX_VEX_0F3803 */ |
||
5552 | { |
||
5553 | { Bad_Opcode }, |
||
5554 | { Bad_Opcode }, |
||
5555 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
||
5556 | }, |
||
5557 | |||
5558 | /* PREFIX_VEX_0F3804 */ |
||
5559 | { |
||
5560 | { Bad_Opcode }, |
||
5561 | { Bad_Opcode }, |
||
5562 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
||
5563 | }, |
||
5564 | |||
5565 | /* PREFIX_VEX_0F3805 */ |
||
5566 | { |
||
5567 | { Bad_Opcode }, |
||
5568 | { Bad_Opcode }, |
||
5569 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
||
5570 | }, |
||
5571 | |||
5572 | /* PREFIX_VEX_0F3806 */ |
||
5573 | { |
||
5574 | { Bad_Opcode }, |
||
5575 | { Bad_Opcode }, |
||
5576 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
||
5577 | }, |
||
5578 | |||
5579 | /* PREFIX_VEX_0F3807 */ |
||
5580 | { |
||
5581 | { Bad_Opcode }, |
||
5582 | { Bad_Opcode }, |
||
5583 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
||
5584 | }, |
||
5585 | |||
5586 | /* PREFIX_VEX_0F3808 */ |
||
5587 | { |
||
5588 | { Bad_Opcode }, |
||
5589 | { Bad_Opcode }, |
||
5590 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
||
5591 | }, |
||
5592 | |||
5593 | /* PREFIX_VEX_0F3809 */ |
||
5594 | { |
||
5595 | { Bad_Opcode }, |
||
5596 | { Bad_Opcode }, |
||
5597 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
||
5598 | }, |
||
5599 | |||
5600 | /* PREFIX_VEX_0F380A */ |
||
5601 | { |
||
5602 | { Bad_Opcode }, |
||
5603 | { Bad_Opcode }, |
||
5604 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
||
5605 | }, |
||
5606 | |||
5607 | /* PREFIX_VEX_0F380B */ |
||
5608 | { |
||
5609 | { Bad_Opcode }, |
||
5610 | { Bad_Opcode }, |
||
5611 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
||
5612 | }, |
||
5613 | |||
5614 | /* PREFIX_VEX_0F380C */ |
||
5615 | { |
||
5616 | { Bad_Opcode }, |
||
5617 | { Bad_Opcode }, |
||
5618 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
||
5619 | }, |
||
5620 | |||
5621 | /* PREFIX_VEX_0F380D */ |
||
5622 | { |
||
5623 | { Bad_Opcode }, |
||
5624 | { Bad_Opcode }, |
||
5625 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
||
5626 | }, |
||
5627 | |||
5628 | /* PREFIX_VEX_0F380E */ |
||
5629 | { |
||
5630 | { Bad_Opcode }, |
||
5631 | { Bad_Opcode }, |
||
5632 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
||
5633 | }, |
||
5634 | |||
5635 | /* PREFIX_VEX_0F380F */ |
||
5636 | { |
||
5637 | { Bad_Opcode }, |
||
5638 | { Bad_Opcode }, |
||
5639 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
||
5640 | }, |
||
5641 | |||
5642 | /* PREFIX_VEX_0F3813 */ |
||
5643 | { |
||
5644 | { Bad_Opcode }, |
||
5645 | { Bad_Opcode }, |
||
6324 | serge | 5646 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
5221 | serge | 5647 | }, |
5648 | |||
5649 | /* PREFIX_VEX_0F3816 */ |
||
5650 | { |
||
5651 | { Bad_Opcode }, |
||
5652 | { Bad_Opcode }, |
||
5653 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, |
||
5654 | }, |
||
5655 | |||
5656 | /* PREFIX_VEX_0F3817 */ |
||
5657 | { |
||
5658 | { Bad_Opcode }, |
||
5659 | { Bad_Opcode }, |
||
5660 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
||
5661 | }, |
||
5662 | |||
5663 | /* PREFIX_VEX_0F3818 */ |
||
5664 | { |
||
5665 | { Bad_Opcode }, |
||
5666 | { Bad_Opcode }, |
||
5667 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
||
5668 | }, |
||
5669 | |||
5670 | /* PREFIX_VEX_0F3819 */ |
||
5671 | { |
||
5672 | { Bad_Opcode }, |
||
5673 | { Bad_Opcode }, |
||
5674 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
||
5675 | }, |
||
5676 | |||
5677 | /* PREFIX_VEX_0F381A */ |
||
5678 | { |
||
5679 | { Bad_Opcode }, |
||
5680 | { Bad_Opcode }, |
||
5681 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
||
5682 | }, |
||
5683 | |||
5684 | /* PREFIX_VEX_0F381C */ |
||
5685 | { |
||
5686 | { Bad_Opcode }, |
||
5687 | { Bad_Opcode }, |
||
5688 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
||
5689 | }, |
||
5690 | |||
5691 | /* PREFIX_VEX_0F381D */ |
||
5692 | { |
||
5693 | { Bad_Opcode }, |
||
5694 | { Bad_Opcode }, |
||
5695 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
||
5696 | }, |
||
5697 | |||
5698 | /* PREFIX_VEX_0F381E */ |
||
5699 | { |
||
5700 | { Bad_Opcode }, |
||
5701 | { Bad_Opcode }, |
||
5702 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
||
5703 | }, |
||
5704 | |||
5705 | /* PREFIX_VEX_0F3820 */ |
||
5706 | { |
||
5707 | { Bad_Opcode }, |
||
5708 | { Bad_Opcode }, |
||
5709 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
||
5710 | }, |
||
5711 | |||
5712 | /* PREFIX_VEX_0F3821 */ |
||
5713 | { |
||
5714 | { Bad_Opcode }, |
||
5715 | { Bad_Opcode }, |
||
5716 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
||
5717 | }, |
||
5718 | |||
5719 | /* PREFIX_VEX_0F3822 */ |
||
5720 | { |
||
5721 | { Bad_Opcode }, |
||
5722 | { Bad_Opcode }, |
||
5723 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
||
5724 | }, |
||
5725 | |||
5726 | /* PREFIX_VEX_0F3823 */ |
||
5727 | { |
||
5728 | { Bad_Opcode }, |
||
5729 | { Bad_Opcode }, |
||
5730 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
||
5731 | }, |
||
5732 | |||
5733 | /* PREFIX_VEX_0F3824 */ |
||
5734 | { |
||
5735 | { Bad_Opcode }, |
||
5736 | { Bad_Opcode }, |
||
5737 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
||
5738 | }, |
||
5739 | |||
5740 | /* PREFIX_VEX_0F3825 */ |
||
5741 | { |
||
5742 | { Bad_Opcode }, |
||
5743 | { Bad_Opcode }, |
||
5744 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
||
5745 | }, |
||
5746 | |||
5747 | /* PREFIX_VEX_0F3828 */ |
||
5748 | { |
||
5749 | { Bad_Opcode }, |
||
5750 | { Bad_Opcode }, |
||
5751 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
||
5752 | }, |
||
5753 | |||
5754 | /* PREFIX_VEX_0F3829 */ |
||
5755 | { |
||
5756 | { Bad_Opcode }, |
||
5757 | { Bad_Opcode }, |
||
5758 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
||
5759 | }, |
||
5760 | |||
5761 | /* PREFIX_VEX_0F382A */ |
||
5762 | { |
||
5763 | { Bad_Opcode }, |
||
5764 | { Bad_Opcode }, |
||
5765 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
||
5766 | }, |
||
5767 | |||
5768 | /* PREFIX_VEX_0F382B */ |
||
5769 | { |
||
5770 | { Bad_Opcode }, |
||
5771 | { Bad_Opcode }, |
||
5772 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
||
5773 | }, |
||
5774 | |||
5775 | /* PREFIX_VEX_0F382C */ |
||
5776 | { |
||
5777 | { Bad_Opcode }, |
||
5778 | { Bad_Opcode }, |
||
5779 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
||
5780 | }, |
||
5781 | |||
5782 | /* PREFIX_VEX_0F382D */ |
||
5783 | { |
||
5784 | { Bad_Opcode }, |
||
5785 | { Bad_Opcode }, |
||
5786 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
||
5787 | }, |
||
5788 | |||
5789 | /* PREFIX_VEX_0F382E */ |
||
5790 | { |
||
5791 | { Bad_Opcode }, |
||
5792 | { Bad_Opcode }, |
||
5793 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
||
5794 | }, |
||
5795 | |||
5796 | /* PREFIX_VEX_0F382F */ |
||
5797 | { |
||
5798 | { Bad_Opcode }, |
||
5799 | { Bad_Opcode }, |
||
5800 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
||
5801 | }, |
||
5802 | |||
5803 | /* PREFIX_VEX_0F3830 */ |
||
5804 | { |
||
5805 | { Bad_Opcode }, |
||
5806 | { Bad_Opcode }, |
||
5807 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
||
5808 | }, |
||
5809 | |||
5810 | /* PREFIX_VEX_0F3831 */ |
||
5811 | { |
||
5812 | { Bad_Opcode }, |
||
5813 | { Bad_Opcode }, |
||
5814 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
||
5815 | }, |
||
5816 | |||
5817 | /* PREFIX_VEX_0F3832 */ |
||
5818 | { |
||
5819 | { Bad_Opcode }, |
||
5820 | { Bad_Opcode }, |
||
5821 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
||
5822 | }, |
||
5823 | |||
5824 | /* PREFIX_VEX_0F3833 */ |
||
5825 | { |
||
5826 | { Bad_Opcode }, |
||
5827 | { Bad_Opcode }, |
||
5828 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
||
5829 | }, |
||
5830 | |||
5831 | /* PREFIX_VEX_0F3834 */ |
||
5832 | { |
||
5833 | { Bad_Opcode }, |
||
5834 | { Bad_Opcode }, |
||
5835 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
||
5836 | }, |
||
5837 | |||
5838 | /* PREFIX_VEX_0F3835 */ |
||
5839 | { |
||
5840 | { Bad_Opcode }, |
||
5841 | { Bad_Opcode }, |
||
5842 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
||
5843 | }, |
||
5844 | |||
5845 | /* PREFIX_VEX_0F3836 */ |
||
5846 | { |
||
5847 | { Bad_Opcode }, |
||
5848 | { Bad_Opcode }, |
||
5849 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, |
||
5850 | }, |
||
5851 | |||
5852 | /* PREFIX_VEX_0F3837 */ |
||
5853 | { |
||
5854 | { Bad_Opcode }, |
||
5855 | { Bad_Opcode }, |
||
5856 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
||
5857 | }, |
||
5858 | |||
5859 | /* PREFIX_VEX_0F3838 */ |
||
5860 | { |
||
5861 | { Bad_Opcode }, |
||
5862 | { Bad_Opcode }, |
||
5863 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
||
5864 | }, |
||
5865 | |||
5866 | /* PREFIX_VEX_0F3839 */ |
||
5867 | { |
||
5868 | { Bad_Opcode }, |
||
5869 | { Bad_Opcode }, |
||
5870 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
||
5871 | }, |
||
5872 | |||
5873 | /* PREFIX_VEX_0F383A */ |
||
5874 | { |
||
5875 | { Bad_Opcode }, |
||
5876 | { Bad_Opcode }, |
||
5877 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
||
5878 | }, |
||
5879 | |||
5880 | /* PREFIX_VEX_0F383B */ |
||
5881 | { |
||
5882 | { Bad_Opcode }, |
||
5883 | { Bad_Opcode }, |
||
5884 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
||
5885 | }, |
||
5886 | |||
5887 | /* PREFIX_VEX_0F383C */ |
||
5888 | { |
||
5889 | { Bad_Opcode }, |
||
5890 | { Bad_Opcode }, |
||
5891 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
||
5892 | }, |
||
5893 | |||
5894 | /* PREFIX_VEX_0F383D */ |
||
5895 | { |
||
5896 | { Bad_Opcode }, |
||
5897 | { Bad_Opcode }, |
||
5898 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
||
5899 | }, |
||
5900 | |||
5901 | /* PREFIX_VEX_0F383E */ |
||
5902 | { |
||
5903 | { Bad_Opcode }, |
||
5904 | { Bad_Opcode }, |
||
5905 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
||
5906 | }, |
||
5907 | |||
5908 | /* PREFIX_VEX_0F383F */ |
||
5909 | { |
||
5910 | { Bad_Opcode }, |
||
5911 | { Bad_Opcode }, |
||
5912 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
||
5913 | }, |
||
5914 | |||
5915 | /* PREFIX_VEX_0F3840 */ |
||
5916 | { |
||
5917 | { Bad_Opcode }, |
||
5918 | { Bad_Opcode }, |
||
5919 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
||
5920 | }, |
||
5921 | |||
5922 | /* PREFIX_VEX_0F3841 */ |
||
5923 | { |
||
5924 | { Bad_Opcode }, |
||
5925 | { Bad_Opcode }, |
||
5926 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
||
5927 | }, |
||
5928 | |||
5929 | /* PREFIX_VEX_0F3845 */ |
||
5930 | { |
||
5931 | { Bad_Opcode }, |
||
5932 | { Bad_Opcode }, |
||
6324 | serge | 5933 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 5934 | }, |
5935 | |||
5936 | /* PREFIX_VEX_0F3846 */ |
||
5937 | { |
||
5938 | { Bad_Opcode }, |
||
5939 | { Bad_Opcode }, |
||
5940 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, |
||
5941 | }, |
||
5942 | |||
5943 | /* PREFIX_VEX_0F3847 */ |
||
5944 | { |
||
5945 | { Bad_Opcode }, |
||
5946 | { Bad_Opcode }, |
||
6324 | serge | 5947 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 5948 | }, |
5949 | |||
5950 | /* PREFIX_VEX_0F3858 */ |
||
5951 | { |
||
5952 | { Bad_Opcode }, |
||
5953 | { Bad_Opcode }, |
||
5954 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, |
||
5955 | }, |
||
5956 | |||
5957 | /* PREFIX_VEX_0F3859 */ |
||
5958 | { |
||
5959 | { Bad_Opcode }, |
||
5960 | { Bad_Opcode }, |
||
5961 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, |
||
5962 | }, |
||
5963 | |||
5964 | /* PREFIX_VEX_0F385A */ |
||
5965 | { |
||
5966 | { Bad_Opcode }, |
||
5967 | { Bad_Opcode }, |
||
5968 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, |
||
5969 | }, |
||
5970 | |||
5971 | /* PREFIX_VEX_0F3878 */ |
||
5972 | { |
||
5973 | { Bad_Opcode }, |
||
5974 | { Bad_Opcode }, |
||
5975 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, |
||
5976 | }, |
||
5977 | |||
5978 | /* PREFIX_VEX_0F3879 */ |
||
5979 | { |
||
5980 | { Bad_Opcode }, |
||
5981 | { Bad_Opcode }, |
||
5982 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, |
||
5983 | }, |
||
5984 | |||
5985 | /* PREFIX_VEX_0F388C */ |
||
5986 | { |
||
5987 | { Bad_Opcode }, |
||
5988 | { Bad_Opcode }, |
||
5989 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
||
5990 | }, |
||
5991 | |||
5992 | /* PREFIX_VEX_0F388E */ |
||
5993 | { |
||
5994 | { Bad_Opcode }, |
||
5995 | { Bad_Opcode }, |
||
5996 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
||
5997 | }, |
||
5998 | |||
5999 | /* PREFIX_VEX_0F3890 */ |
||
6000 | { |
||
6001 | { Bad_Opcode }, |
||
6002 | { Bad_Opcode }, |
||
6324 | serge | 6003 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
5221 | serge | 6004 | }, |
6005 | |||
6006 | /* PREFIX_VEX_0F3891 */ |
||
6007 | { |
||
6008 | { Bad_Opcode }, |
||
6009 | { Bad_Opcode }, |
||
6324 | serge | 6010 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
5221 | serge | 6011 | }, |
6012 | |||
6013 | /* PREFIX_VEX_0F3892 */ |
||
6014 | { |
||
6015 | { Bad_Opcode }, |
||
6016 | { Bad_Opcode }, |
||
6324 | serge | 6017 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
5221 | serge | 6018 | }, |
6019 | |||
6020 | /* PREFIX_VEX_0F3893 */ |
||
6021 | { |
||
6022 | { Bad_Opcode }, |
||
6023 | { Bad_Opcode }, |
||
6324 | serge | 6024 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
5221 | serge | 6025 | }, |
6026 | |||
6027 | /* PREFIX_VEX_0F3896 */ |
||
6028 | { |
||
6029 | { Bad_Opcode }, |
||
6030 | { Bad_Opcode }, |
||
6324 | serge | 6031 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6032 | }, |
6033 | |||
6034 | /* PREFIX_VEX_0F3897 */ |
||
6035 | { |
||
6036 | { Bad_Opcode }, |
||
6037 | { Bad_Opcode }, |
||
6324 | serge | 6038 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6039 | }, |
6040 | |||
6041 | /* PREFIX_VEX_0F3898 */ |
||
6042 | { |
||
6043 | { Bad_Opcode }, |
||
6044 | { Bad_Opcode }, |
||
6324 | serge | 6045 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6046 | }, |
6047 | |||
6048 | /* PREFIX_VEX_0F3899 */ |
||
6049 | { |
||
6050 | { Bad_Opcode }, |
||
6051 | { Bad_Opcode }, |
||
6324 | serge | 6052 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6053 | }, |
6054 | |||
6055 | /* PREFIX_VEX_0F389A */ |
||
6056 | { |
||
6057 | { Bad_Opcode }, |
||
6058 | { Bad_Opcode }, |
||
6324 | serge | 6059 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6060 | }, |
6061 | |||
6062 | /* PREFIX_VEX_0F389B */ |
||
6063 | { |
||
6064 | { Bad_Opcode }, |
||
6065 | { Bad_Opcode }, |
||
6324 | serge | 6066 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6067 | }, |
6068 | |||
6069 | /* PREFIX_VEX_0F389C */ |
||
6070 | { |
||
6071 | { Bad_Opcode }, |
||
6072 | { Bad_Opcode }, |
||
6324 | serge | 6073 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6074 | }, |
6075 | |||
6076 | /* PREFIX_VEX_0F389D */ |
||
6077 | { |
||
6078 | { Bad_Opcode }, |
||
6079 | { Bad_Opcode }, |
||
6324 | serge | 6080 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6081 | }, |
6082 | |||
6083 | /* PREFIX_VEX_0F389E */ |
||
6084 | { |
||
6085 | { Bad_Opcode }, |
||
6086 | { Bad_Opcode }, |
||
6324 | serge | 6087 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6088 | }, |
6089 | |||
6090 | /* PREFIX_VEX_0F389F */ |
||
6091 | { |
||
6092 | { Bad_Opcode }, |
||
6093 | { Bad_Opcode }, |
||
6324 | serge | 6094 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6095 | }, |
6096 | |||
6097 | /* PREFIX_VEX_0F38A6 */ |
||
6098 | { |
||
6099 | { Bad_Opcode }, |
||
6100 | { Bad_Opcode }, |
||
6324 | serge | 6101 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6102 | { Bad_Opcode }, |
6103 | }, |
||
6104 | |||
6105 | /* PREFIX_VEX_0F38A7 */ |
||
6106 | { |
||
6107 | { Bad_Opcode }, |
||
6108 | { Bad_Opcode }, |
||
6324 | serge | 6109 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6110 | }, |
6111 | |||
6112 | /* PREFIX_VEX_0F38A8 */ |
||
6113 | { |
||
6114 | { Bad_Opcode }, |
||
6115 | { Bad_Opcode }, |
||
6324 | serge | 6116 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6117 | }, |
6118 | |||
6119 | /* PREFIX_VEX_0F38A9 */ |
||
6120 | { |
||
6121 | { Bad_Opcode }, |
||
6122 | { Bad_Opcode }, |
||
6324 | serge | 6123 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6124 | }, |
6125 | |||
6126 | /* PREFIX_VEX_0F38AA */ |
||
6127 | { |
||
6128 | { Bad_Opcode }, |
||
6129 | { Bad_Opcode }, |
||
6324 | serge | 6130 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6131 | }, |
6132 | |||
6133 | /* PREFIX_VEX_0F38AB */ |
||
6134 | { |
||
6135 | { Bad_Opcode }, |
||
6136 | { Bad_Opcode }, |
||
6324 | serge | 6137 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6138 | }, |
6139 | |||
6140 | /* PREFIX_VEX_0F38AC */ |
||
6141 | { |
||
6142 | { Bad_Opcode }, |
||
6143 | { Bad_Opcode }, |
||
6324 | serge | 6144 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6145 | }, |
6146 | |||
6147 | /* PREFIX_VEX_0F38AD */ |
||
6148 | { |
||
6149 | { Bad_Opcode }, |
||
6150 | { Bad_Opcode }, |
||
6324 | serge | 6151 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6152 | }, |
6153 | |||
6154 | /* PREFIX_VEX_0F38AE */ |
||
6155 | { |
||
6156 | { Bad_Opcode }, |
||
6157 | { Bad_Opcode }, |
||
6324 | serge | 6158 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6159 | }, |
6160 | |||
6161 | /* PREFIX_VEX_0F38AF */ |
||
6162 | { |
||
6163 | { Bad_Opcode }, |
||
6164 | { Bad_Opcode }, |
||
6324 | serge | 6165 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6166 | }, |
6167 | |||
6168 | /* PREFIX_VEX_0F38B6 */ |
||
6169 | { |
||
6170 | { Bad_Opcode }, |
||
6171 | { Bad_Opcode }, |
||
6324 | serge | 6172 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6173 | }, |
6174 | |||
6175 | /* PREFIX_VEX_0F38B7 */ |
||
6176 | { |
||
6177 | { Bad_Opcode }, |
||
6178 | { Bad_Opcode }, |
||
6324 | serge | 6179 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6180 | }, |
6181 | |||
6182 | /* PREFIX_VEX_0F38B8 */ |
||
6183 | { |
||
6184 | { Bad_Opcode }, |
||
6185 | { Bad_Opcode }, |
||
6324 | serge | 6186 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6187 | }, |
6188 | |||
6189 | /* PREFIX_VEX_0F38B9 */ |
||
6190 | { |
||
6191 | { Bad_Opcode }, |
||
6192 | { Bad_Opcode }, |
||
6324 | serge | 6193 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6194 | }, |
6195 | |||
6196 | /* PREFIX_VEX_0F38BA */ |
||
6197 | { |
||
6198 | { Bad_Opcode }, |
||
6199 | { Bad_Opcode }, |
||
6324 | serge | 6200 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6201 | }, |
6202 | |||
6203 | /* PREFIX_VEX_0F38BB */ |
||
6204 | { |
||
6205 | { Bad_Opcode }, |
||
6206 | { Bad_Opcode }, |
||
6324 | serge | 6207 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6208 | }, |
6209 | |||
6210 | /* PREFIX_VEX_0F38BC */ |
||
6211 | { |
||
6212 | { Bad_Opcode }, |
||
6213 | { Bad_Opcode }, |
||
6324 | serge | 6214 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6215 | }, |
6216 | |||
6217 | /* PREFIX_VEX_0F38BD */ |
||
6218 | { |
||
6219 | { Bad_Opcode }, |
||
6220 | { Bad_Opcode }, |
||
6324 | serge | 6221 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6222 | }, |
6223 | |||
6224 | /* PREFIX_VEX_0F38BE */ |
||
6225 | { |
||
6226 | { Bad_Opcode }, |
||
6227 | { Bad_Opcode }, |
||
6324 | serge | 6228 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 6229 | }, |
6230 | |||
6231 | /* PREFIX_VEX_0F38BF */ |
||
6232 | { |
||
6233 | { Bad_Opcode }, |
||
6234 | { Bad_Opcode }, |
||
6324 | serge | 6235 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5221 | serge | 6236 | }, |
6237 | |||
6238 | /* PREFIX_VEX_0F38DB */ |
||
6239 | { |
||
6240 | { Bad_Opcode }, |
||
6241 | { Bad_Opcode }, |
||
6242 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
||
6243 | }, |
||
6244 | |||
6245 | /* PREFIX_VEX_0F38DC */ |
||
6246 | { |
||
6247 | { Bad_Opcode }, |
||
6248 | { Bad_Opcode }, |
||
6249 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
||
6250 | }, |
||
6251 | |||
6252 | /* PREFIX_VEX_0F38DD */ |
||
6253 | { |
||
6254 | { Bad_Opcode }, |
||
6255 | { Bad_Opcode }, |
||
6256 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
||
6257 | }, |
||
6258 | |||
6259 | /* PREFIX_VEX_0F38DE */ |
||
6260 | { |
||
6261 | { Bad_Opcode }, |
||
6262 | { Bad_Opcode }, |
||
6263 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
||
6264 | }, |
||
6265 | |||
6266 | /* PREFIX_VEX_0F38DF */ |
||
6267 | { |
||
6268 | { Bad_Opcode }, |
||
6269 | { Bad_Opcode }, |
||
6270 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
||
6271 | }, |
||
6272 | |||
6273 | /* PREFIX_VEX_0F38F2 */ |
||
6274 | { |
||
6275 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, |
||
6276 | }, |
||
6277 | |||
6278 | /* PREFIX_VEX_0F38F3_REG_1 */ |
||
6279 | { |
||
6280 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, |
||
6281 | }, |
||
6282 | |||
6283 | /* PREFIX_VEX_0F38F3_REG_2 */ |
||
6284 | { |
||
6285 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, |
||
6286 | }, |
||
6287 | |||
6288 | /* PREFIX_VEX_0F38F3_REG_3 */ |
||
6289 | { |
||
6290 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, |
||
6291 | }, |
||
6292 | |||
6293 | /* PREFIX_VEX_0F38F5 */ |
||
6294 | { |
||
6295 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
||
6296 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, |
||
6297 | { Bad_Opcode }, |
||
6298 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
||
6299 | }, |
||
6300 | |||
6301 | /* PREFIX_VEX_0F38F6 */ |
||
6302 | { |
||
6303 | { Bad_Opcode }, |
||
6304 | { Bad_Opcode }, |
||
6305 | { Bad_Opcode }, |
||
6306 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, |
||
6307 | }, |
||
6308 | |||
6309 | /* PREFIX_VEX_0F38F7 */ |
||
6310 | { |
||
6311 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
||
6312 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
||
6313 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, |
||
6314 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, |
||
6315 | }, |
||
6316 | |||
6317 | /* PREFIX_VEX_0F3A00 */ |
||
6318 | { |
||
6319 | { Bad_Opcode }, |
||
6320 | { Bad_Opcode }, |
||
6321 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, |
||
6322 | }, |
||
6323 | |||
6324 | /* PREFIX_VEX_0F3A01 */ |
||
6325 | { |
||
6326 | { Bad_Opcode }, |
||
6327 | { Bad_Opcode }, |
||
6328 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, |
||
6329 | }, |
||
6330 | |||
6331 | /* PREFIX_VEX_0F3A02 */ |
||
6332 | { |
||
6333 | { Bad_Opcode }, |
||
6334 | { Bad_Opcode }, |
||
6335 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, |
||
6336 | }, |
||
6337 | |||
6338 | /* PREFIX_VEX_0F3A04 */ |
||
6339 | { |
||
6340 | { Bad_Opcode }, |
||
6341 | { Bad_Opcode }, |
||
6342 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
||
6343 | }, |
||
6344 | |||
6345 | /* PREFIX_VEX_0F3A05 */ |
||
6346 | { |
||
6347 | { Bad_Opcode }, |
||
6348 | { Bad_Opcode }, |
||
6349 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
||
6350 | }, |
||
6351 | |||
6352 | /* PREFIX_VEX_0F3A06 */ |
||
6353 | { |
||
6354 | { Bad_Opcode }, |
||
6355 | { Bad_Opcode }, |
||
6356 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
||
6357 | }, |
||
6358 | |||
6359 | /* PREFIX_VEX_0F3A08 */ |
||
6360 | { |
||
6361 | { Bad_Opcode }, |
||
6362 | { Bad_Opcode }, |
||
6363 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
||
6364 | }, |
||
6365 | |||
6366 | /* PREFIX_VEX_0F3A09 */ |
||
6367 | { |
||
6368 | { Bad_Opcode }, |
||
6369 | { Bad_Opcode }, |
||
6370 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
||
6371 | }, |
||
6372 | |||
6373 | /* PREFIX_VEX_0F3A0A */ |
||
6374 | { |
||
6375 | { Bad_Opcode }, |
||
6376 | { Bad_Opcode }, |
||
6377 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
||
6378 | }, |
||
6379 | |||
6380 | /* PREFIX_VEX_0F3A0B */ |
||
6381 | { |
||
6382 | { Bad_Opcode }, |
||
6383 | { Bad_Opcode }, |
||
6384 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
||
6385 | }, |
||
6386 | |||
6387 | /* PREFIX_VEX_0F3A0C */ |
||
6388 | { |
||
6389 | { Bad_Opcode }, |
||
6390 | { Bad_Opcode }, |
||
6391 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
||
6392 | }, |
||
6393 | |||
6394 | /* PREFIX_VEX_0F3A0D */ |
||
6395 | { |
||
6396 | { Bad_Opcode }, |
||
6397 | { Bad_Opcode }, |
||
6398 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
||
6399 | }, |
||
6400 | |||
6401 | /* PREFIX_VEX_0F3A0E */ |
||
6402 | { |
||
6403 | { Bad_Opcode }, |
||
6404 | { Bad_Opcode }, |
||
6405 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
||
6406 | }, |
||
6407 | |||
6408 | /* PREFIX_VEX_0F3A0F */ |
||
6409 | { |
||
6410 | { Bad_Opcode }, |
||
6411 | { Bad_Opcode }, |
||
6412 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
||
6413 | }, |
||
6414 | |||
6415 | /* PREFIX_VEX_0F3A14 */ |
||
6416 | { |
||
6417 | { Bad_Opcode }, |
||
6418 | { Bad_Opcode }, |
||
6419 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
||
6420 | }, |
||
6421 | |||
6422 | /* PREFIX_VEX_0F3A15 */ |
||
6423 | { |
||
6424 | { Bad_Opcode }, |
||
6425 | { Bad_Opcode }, |
||
6426 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
||
6427 | }, |
||
6428 | |||
6429 | /* PREFIX_VEX_0F3A16 */ |
||
6430 | { |
||
6431 | { Bad_Opcode }, |
||
6432 | { Bad_Opcode }, |
||
6433 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
||
6434 | }, |
||
6435 | |||
6436 | /* PREFIX_VEX_0F3A17 */ |
||
6437 | { |
||
6438 | { Bad_Opcode }, |
||
6439 | { Bad_Opcode }, |
||
6440 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
||
6441 | }, |
||
6442 | |||
6443 | /* PREFIX_VEX_0F3A18 */ |
||
6444 | { |
||
6445 | { Bad_Opcode }, |
||
6446 | { Bad_Opcode }, |
||
6447 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
||
6448 | }, |
||
6449 | |||
6450 | /* PREFIX_VEX_0F3A19 */ |
||
6451 | { |
||
6452 | { Bad_Opcode }, |
||
6453 | { Bad_Opcode }, |
||
6454 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
||
6455 | }, |
||
6456 | |||
6457 | /* PREFIX_VEX_0F3A1D */ |
||
6458 | { |
||
6459 | { Bad_Opcode }, |
||
6460 | { Bad_Opcode }, |
||
6324 | serge | 6461 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
5221 | serge | 6462 | }, |
6463 | |||
6464 | /* PREFIX_VEX_0F3A20 */ |
||
6465 | { |
||
6466 | { Bad_Opcode }, |
||
6467 | { Bad_Opcode }, |
||
6468 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
||
6469 | }, |
||
6470 | |||
6471 | /* PREFIX_VEX_0F3A21 */ |
||
6472 | { |
||
6473 | { Bad_Opcode }, |
||
6474 | { Bad_Opcode }, |
||
6475 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
||
6476 | }, |
||
6477 | |||
6478 | /* PREFIX_VEX_0F3A22 */ |
||
6479 | { |
||
6480 | { Bad_Opcode }, |
||
6481 | { Bad_Opcode }, |
||
6482 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
||
6483 | }, |
||
6484 | |||
6485 | /* PREFIX_VEX_0F3A30 */ |
||
6486 | { |
||
6487 | { Bad_Opcode }, |
||
6488 | { Bad_Opcode }, |
||
6489 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, |
||
6490 | }, |
||
6491 | |||
6324 | serge | 6492 | /* PREFIX_VEX_0F3A31 */ |
6493 | { |
||
6494 | { Bad_Opcode }, |
||
6495 | { Bad_Opcode }, |
||
6496 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, |
||
6497 | }, |
||
6498 | |||
5221 | serge | 6499 | /* PREFIX_VEX_0F3A32 */ |
6500 | { |
||
6501 | { Bad_Opcode }, |
||
6502 | { Bad_Opcode }, |
||
6503 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, |
||
6504 | }, |
||
6505 | |||
6324 | serge | 6506 | /* PREFIX_VEX_0F3A33 */ |
6507 | { |
||
6508 | { Bad_Opcode }, |
||
6509 | { Bad_Opcode }, |
||
6510 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, |
||
6511 | }, |
||
6512 | |||
5221 | serge | 6513 | /* PREFIX_VEX_0F3A38 */ |
6514 | { |
||
6515 | { Bad_Opcode }, |
||
6516 | { Bad_Opcode }, |
||
6517 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, |
||
6518 | }, |
||
6519 | |||
6520 | /* PREFIX_VEX_0F3A39 */ |
||
6521 | { |
||
6522 | { Bad_Opcode }, |
||
6523 | { Bad_Opcode }, |
||
6524 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, |
||
6525 | }, |
||
6526 | |||
6527 | /* PREFIX_VEX_0F3A40 */ |
||
6528 | { |
||
6529 | { Bad_Opcode }, |
||
6530 | { Bad_Opcode }, |
||
6531 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
||
6532 | }, |
||
6533 | |||
6534 | /* PREFIX_VEX_0F3A41 */ |
||
6535 | { |
||
6536 | { Bad_Opcode }, |
||
6537 | { Bad_Opcode }, |
||
6538 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
||
6539 | }, |
||
6540 | |||
6541 | /* PREFIX_VEX_0F3A42 */ |
||
6542 | { |
||
6543 | { Bad_Opcode }, |
||
6544 | { Bad_Opcode }, |
||
6545 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
||
6546 | }, |
||
6547 | |||
6548 | /* PREFIX_VEX_0F3A44 */ |
||
6549 | { |
||
6550 | { Bad_Opcode }, |
||
6551 | { Bad_Opcode }, |
||
6552 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
||
6553 | }, |
||
6554 | |||
6555 | /* PREFIX_VEX_0F3A46 */ |
||
6556 | { |
||
6557 | { Bad_Opcode }, |
||
6558 | { Bad_Opcode }, |
||
6559 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, |
||
6560 | }, |
||
6561 | |||
6562 | /* PREFIX_VEX_0F3A48 */ |
||
6563 | { |
||
6564 | { Bad_Opcode }, |
||
6565 | { Bad_Opcode }, |
||
6566 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
||
6567 | }, |
||
6568 | |||
6569 | /* PREFIX_VEX_0F3A49 */ |
||
6570 | { |
||
6571 | { Bad_Opcode }, |
||
6572 | { Bad_Opcode }, |
||
6573 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
||
6574 | }, |
||
6575 | |||
6576 | /* PREFIX_VEX_0F3A4A */ |
||
6577 | { |
||
6578 | { Bad_Opcode }, |
||
6579 | { Bad_Opcode }, |
||
6580 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
||
6581 | }, |
||
6582 | |||
6583 | /* PREFIX_VEX_0F3A4B */ |
||
6584 | { |
||
6585 | { Bad_Opcode }, |
||
6586 | { Bad_Opcode }, |
||
6587 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
||
6588 | }, |
||
6589 | |||
6590 | /* PREFIX_VEX_0F3A4C */ |
||
6591 | { |
||
6592 | { Bad_Opcode }, |
||
6593 | { Bad_Opcode }, |
||
6594 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
||
6595 | }, |
||
6596 | |||
6597 | /* PREFIX_VEX_0F3A5C */ |
||
6598 | { |
||
6599 | { Bad_Opcode }, |
||
6600 | { Bad_Opcode }, |
||
6324 | serge | 6601 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6602 | }, |
6603 | |||
6604 | /* PREFIX_VEX_0F3A5D */ |
||
6605 | { |
||
6606 | { Bad_Opcode }, |
||
6607 | { Bad_Opcode }, |
||
6324 | serge | 6608 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6609 | }, |
6610 | |||
6611 | /* PREFIX_VEX_0F3A5E */ |
||
6612 | { |
||
6613 | { Bad_Opcode }, |
||
6614 | { Bad_Opcode }, |
||
6324 | serge | 6615 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6616 | }, |
6617 | |||
6618 | /* PREFIX_VEX_0F3A5F */ |
||
6619 | { |
||
6620 | { Bad_Opcode }, |
||
6621 | { Bad_Opcode }, |
||
6324 | serge | 6622 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6623 | }, |
6624 | |||
6625 | /* PREFIX_VEX_0F3A60 */ |
||
6626 | { |
||
6627 | { Bad_Opcode }, |
||
6628 | { Bad_Opcode }, |
||
6629 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
||
6630 | { Bad_Opcode }, |
||
6631 | }, |
||
6632 | |||
6633 | /* PREFIX_VEX_0F3A61 */ |
||
6634 | { |
||
6635 | { Bad_Opcode }, |
||
6636 | { Bad_Opcode }, |
||
6637 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
||
6638 | }, |
||
6639 | |||
6640 | /* PREFIX_VEX_0F3A62 */ |
||
6641 | { |
||
6642 | { Bad_Opcode }, |
||
6643 | { Bad_Opcode }, |
||
6644 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
||
6645 | }, |
||
6646 | |||
6647 | /* PREFIX_VEX_0F3A63 */ |
||
6648 | { |
||
6649 | { Bad_Opcode }, |
||
6650 | { Bad_Opcode }, |
||
6651 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
||
6652 | }, |
||
6653 | |||
6654 | /* PREFIX_VEX_0F3A68 */ |
||
6655 | { |
||
6656 | { Bad_Opcode }, |
||
6657 | { Bad_Opcode }, |
||
6324 | serge | 6658 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6659 | }, |
6660 | |||
6661 | /* PREFIX_VEX_0F3A69 */ |
||
6662 | { |
||
6663 | { Bad_Opcode }, |
||
6664 | { Bad_Opcode }, |
||
6324 | serge | 6665 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6666 | }, |
6667 | |||
6668 | /* PREFIX_VEX_0F3A6A */ |
||
6669 | { |
||
6670 | { Bad_Opcode }, |
||
6671 | { Bad_Opcode }, |
||
6672 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
||
6673 | }, |
||
6674 | |||
6675 | /* PREFIX_VEX_0F3A6B */ |
||
6676 | { |
||
6677 | { Bad_Opcode }, |
||
6678 | { Bad_Opcode }, |
||
6679 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
||
6680 | }, |
||
6681 | |||
6682 | /* PREFIX_VEX_0F3A6C */ |
||
6683 | { |
||
6684 | { Bad_Opcode }, |
||
6685 | { Bad_Opcode }, |
||
6324 | serge | 6686 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6687 | }, |
6688 | |||
6689 | /* PREFIX_VEX_0F3A6D */ |
||
6690 | { |
||
6691 | { Bad_Opcode }, |
||
6692 | { Bad_Opcode }, |
||
6324 | serge | 6693 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6694 | }, |
6695 | |||
6696 | /* PREFIX_VEX_0F3A6E */ |
||
6697 | { |
||
6698 | { Bad_Opcode }, |
||
6699 | { Bad_Opcode }, |
||
6700 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
||
6701 | }, |
||
6702 | |||
6703 | /* PREFIX_VEX_0F3A6F */ |
||
6704 | { |
||
6705 | { Bad_Opcode }, |
||
6706 | { Bad_Opcode }, |
||
6707 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
||
6708 | }, |
||
6709 | |||
6710 | /* PREFIX_VEX_0F3A78 */ |
||
6711 | { |
||
6712 | { Bad_Opcode }, |
||
6713 | { Bad_Opcode }, |
||
6324 | serge | 6714 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6715 | }, |
6716 | |||
6717 | /* PREFIX_VEX_0F3A79 */ |
||
6718 | { |
||
6719 | { Bad_Opcode }, |
||
6720 | { Bad_Opcode }, |
||
6324 | serge | 6721 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6722 | }, |
6723 | |||
6724 | /* PREFIX_VEX_0F3A7A */ |
||
6725 | { |
||
6726 | { Bad_Opcode }, |
||
6727 | { Bad_Opcode }, |
||
6728 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
||
6729 | }, |
||
6730 | |||
6731 | /* PREFIX_VEX_0F3A7B */ |
||
6732 | { |
||
6733 | { Bad_Opcode }, |
||
6734 | { Bad_Opcode }, |
||
6735 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
||
6736 | }, |
||
6737 | |||
6738 | /* PREFIX_VEX_0F3A7C */ |
||
6739 | { |
||
6740 | { Bad_Opcode }, |
||
6741 | { Bad_Opcode }, |
||
6324 | serge | 6742 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6743 | { Bad_Opcode }, |
6744 | }, |
||
6745 | |||
6746 | /* PREFIX_VEX_0F3A7D */ |
||
6747 | { |
||
6748 | { Bad_Opcode }, |
||
6749 | { Bad_Opcode }, |
||
6324 | serge | 6750 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 6751 | }, |
6752 | |||
6753 | /* PREFIX_VEX_0F3A7E */ |
||
6754 | { |
||
6755 | { Bad_Opcode }, |
||
6756 | { Bad_Opcode }, |
||
6757 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
||
6758 | }, |
||
6759 | |||
6760 | /* PREFIX_VEX_0F3A7F */ |
||
6761 | { |
||
6762 | { Bad_Opcode }, |
||
6763 | { Bad_Opcode }, |
||
6764 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
||
6765 | }, |
||
6766 | |||
6767 | /* PREFIX_VEX_0F3ADF */ |
||
6768 | { |
||
6769 | { Bad_Opcode }, |
||
6770 | { Bad_Opcode }, |
||
6771 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
||
6772 | }, |
||
6773 | |||
6774 | /* PREFIX_VEX_0F3AF0 */ |
||
6775 | { |
||
6776 | { Bad_Opcode }, |
||
6777 | { Bad_Opcode }, |
||
6778 | { Bad_Opcode }, |
||
6779 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, |
||
6780 | }, |
||
6781 | |||
6782 | #define NEED_PREFIX_TABLE |
||
6783 | #include "i386-dis-evex.h" |
||
6784 | #undef NEED_PREFIX_TABLE |
||
6785 | }; |
||
6786 | |||
6787 | static const struct dis386 x86_64_table[][2] = { |
||
6788 | /* X86_64_06 */ |
||
6789 | { |
||
6324 | serge | 6790 | { "pushP", { es }, 0 }, |
5221 | serge | 6791 | }, |
6792 | |||
6793 | /* X86_64_07 */ |
||
6794 | { |
||
6324 | serge | 6795 | { "popP", { es }, 0 }, |
5221 | serge | 6796 | }, |
6797 | |||
6798 | /* X86_64_0D */ |
||
6799 | { |
||
6324 | serge | 6800 | { "pushP", { cs }, 0 }, |
5221 | serge | 6801 | }, |
6802 | |||
6803 | /* X86_64_16 */ |
||
6804 | { |
||
6324 | serge | 6805 | { "pushP", { ss }, 0 }, |
5221 | serge | 6806 | }, |
6807 | |||
6808 | /* X86_64_17 */ |
||
6809 | { |
||
6324 | serge | 6810 | { "popP", { ss }, 0 }, |
5221 | serge | 6811 | }, |
6812 | |||
6813 | /* X86_64_1E */ |
||
6814 | { |
||
6324 | serge | 6815 | { "pushP", { ds }, 0 }, |
5221 | serge | 6816 | }, |
6817 | |||
6818 | /* X86_64_1F */ |
||
6819 | { |
||
6324 | serge | 6820 | { "popP", { ds }, 0 }, |
5221 | serge | 6821 | }, |
6822 | |||
6823 | /* X86_64_27 */ |
||
6824 | { |
||
6324 | serge | 6825 | { "daa", { XX }, 0 }, |
5221 | serge | 6826 | }, |
6827 | |||
6828 | /* X86_64_2F */ |
||
6829 | { |
||
6324 | serge | 6830 | { "das", { XX }, 0 }, |
5221 | serge | 6831 | }, |
6832 | |||
6833 | /* X86_64_37 */ |
||
6834 | { |
||
6324 | serge | 6835 | { "aaa", { XX }, 0 }, |
5221 | serge | 6836 | }, |
6837 | |||
6838 | /* X86_64_3F */ |
||
6839 | { |
||
6324 | serge | 6840 | { "aas", { XX }, 0 }, |
5221 | serge | 6841 | }, |
6842 | |||
6843 | /* X86_64_60 */ |
||
6844 | { |
||
6324 | serge | 6845 | { "pushaP", { XX }, 0 }, |
5221 | serge | 6846 | }, |
6847 | |||
6848 | /* X86_64_61 */ |
||
6849 | { |
||
6324 | serge | 6850 | { "popaP", { XX }, 0 }, |
5221 | serge | 6851 | }, |
6852 | |||
6853 | /* X86_64_62 */ |
||
6854 | { |
||
6855 | { MOD_TABLE (MOD_62_32BIT) }, |
||
6856 | { EVEX_TABLE (EVEX_0F) }, |
||
6857 | }, |
||
6858 | |||
6859 | /* X86_64_63 */ |
||
6860 | { |
||
6324 | serge | 6861 | { "arpl", { Ew, Gw }, 0 }, |
6862 | { "movs{lq|xd}", { Gv, Ed }, 0 }, |
||
5221 | serge | 6863 | }, |
6864 | |||
6865 | /* X86_64_6D */ |
||
6866 | { |
||
6324 | serge | 6867 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6868 | { "ins{G|}", { Yzr, indirDX }, 0 }, |
||
5221 | serge | 6869 | }, |
6870 | |||
6871 | /* X86_64_6F */ |
||
6872 | { |
||
6324 | serge | 6873 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6874 | { "outs{G|}", { indirDXr, Xz }, 0 }, |
||
5221 | serge | 6875 | }, |
6876 | |||
6877 | /* X86_64_9A */ |
||
6878 | { |
||
6324 | serge | 6879 | { "Jcall{T|}", { Ap }, 0 }, |
5221 | serge | 6880 | }, |
6881 | |||
6882 | /* X86_64_C4 */ |
||
6883 | { |
||
6884 | { MOD_TABLE (MOD_C4_32BIT) }, |
||
6885 | { VEX_C4_TABLE (VEX_0F) }, |
||
6886 | }, |
||
6887 | |||
6888 | /* X86_64_C5 */ |
||
6889 | { |
||
6890 | { MOD_TABLE (MOD_C5_32BIT) }, |
||
6891 | { VEX_C5_TABLE (VEX_0F) }, |
||
6892 | }, |
||
6893 | |||
6894 | /* X86_64_CE */ |
||
6895 | { |
||
6324 | serge | 6896 | { "into", { XX }, 0 }, |
5221 | serge | 6897 | }, |
6898 | |||
6899 | /* X86_64_D4 */ |
||
6900 | { |
||
6324 | serge | 6901 | { "aam", { Ib }, 0 }, |
5221 | serge | 6902 | }, |
6903 | |||
6904 | /* X86_64_D5 */ |
||
6905 | { |
||
6324 | serge | 6906 | { "aad", { Ib }, 0 }, |
5221 | serge | 6907 | }, |
6908 | |||
6324 | serge | 6909 | /* X86_64_E8 */ |
6910 | { |
||
6911 | { "callP", { Jv, BND }, 0 }, |
||
6912 | { "call@", { Jv, BND }, 0 } |
||
6913 | }, |
||
6914 | |||
6915 | /* X86_64_E9 */ |
||
6916 | { |
||
6917 | { "jmpP", { Jv, BND }, 0 }, |
||
6918 | { "jmp@", { Jv, BND }, 0 } |
||
6919 | }, |
||
6920 | |||
5221 | serge | 6921 | /* X86_64_EA */ |
6922 | { |
||
6324 | serge | 6923 | { "Jjmp{T|}", { Ap }, 0 }, |
5221 | serge | 6924 | }, |
6925 | |||
6926 | /* X86_64_0F01_REG_0 */ |
||
6927 | { |
||
6324 | serge | 6928 | { "sgdt{Q|IQ}", { M }, 0 }, |
6929 | { "sgdt", { M }, 0 }, |
||
5221 | serge | 6930 | }, |
6931 | |||
6932 | /* X86_64_0F01_REG_1 */ |
||
6933 | { |
||
6324 | serge | 6934 | { "sidt{Q|IQ}", { M }, 0 }, |
6935 | { "sidt", { M }, 0 }, |
||
5221 | serge | 6936 | }, |
6937 | |||
6938 | /* X86_64_0F01_REG_2 */ |
||
6939 | { |
||
6324 | serge | 6940 | { "lgdt{Q|Q}", { M }, 0 }, |
6941 | { "lgdt", { M }, 0 }, |
||
5221 | serge | 6942 | }, |
6943 | |||
6944 | /* X86_64_0F01_REG_3 */ |
||
6945 | { |
||
6324 | serge | 6946 | { "lidt{Q|Q}", { M }, 0 }, |
6947 | { "lidt", { M }, 0 }, |
||
5221 | serge | 6948 | }, |
6949 | }; |
||
6950 | |||
6951 | static const struct dis386 three_byte_table[][256] = { |
||
6952 | |||
6953 | /* THREE_BYTE_0F38 */ |
||
6954 | { |
||
6955 | /* 00 */ |
||
6324 | serge | 6956 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6957 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, |
||
6958 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, |
||
6959 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, |
||
6960 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, |
||
6961 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, |
||
6962 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, |
||
6963 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 6964 | /* 08 */ |
6324 | serge | 6965 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6966 | { "psignw", { MX, EM }, PREFIX_OPCODE }, |
||
6967 | { "psignd", { MX, EM }, PREFIX_OPCODE }, |
||
6968 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 6969 | { Bad_Opcode }, |
6970 | { Bad_Opcode }, |
||
6971 | { Bad_Opcode }, |
||
6972 | { Bad_Opcode }, |
||
6973 | /* 10 */ |
||
6974 | { PREFIX_TABLE (PREFIX_0F3810) }, |
||
6975 | { Bad_Opcode }, |
||
6976 | { Bad_Opcode }, |
||
6977 | { Bad_Opcode }, |
||
6978 | { PREFIX_TABLE (PREFIX_0F3814) }, |
||
6979 | { PREFIX_TABLE (PREFIX_0F3815) }, |
||
6980 | { Bad_Opcode }, |
||
6981 | { PREFIX_TABLE (PREFIX_0F3817) }, |
||
6982 | /* 18 */ |
||
6983 | { Bad_Opcode }, |
||
6984 | { Bad_Opcode }, |
||
6985 | { Bad_Opcode }, |
||
6986 | { Bad_Opcode }, |
||
6324 | serge | 6987 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6988 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, |
||
6989 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, |
||
5221 | serge | 6990 | { Bad_Opcode }, |
6991 | /* 20 */ |
||
6992 | { PREFIX_TABLE (PREFIX_0F3820) }, |
||
6993 | { PREFIX_TABLE (PREFIX_0F3821) }, |
||
6994 | { PREFIX_TABLE (PREFIX_0F3822) }, |
||
6995 | { PREFIX_TABLE (PREFIX_0F3823) }, |
||
6996 | { PREFIX_TABLE (PREFIX_0F3824) }, |
||
6997 | { PREFIX_TABLE (PREFIX_0F3825) }, |
||
6998 | { Bad_Opcode }, |
||
6999 | { Bad_Opcode }, |
||
7000 | /* 28 */ |
||
7001 | { PREFIX_TABLE (PREFIX_0F3828) }, |
||
7002 | { PREFIX_TABLE (PREFIX_0F3829) }, |
||
7003 | { PREFIX_TABLE (PREFIX_0F382A) }, |
||
7004 | { PREFIX_TABLE (PREFIX_0F382B) }, |
||
7005 | { Bad_Opcode }, |
||
7006 | { Bad_Opcode }, |
||
7007 | { Bad_Opcode }, |
||
7008 | { Bad_Opcode }, |
||
7009 | /* 30 */ |
||
7010 | { PREFIX_TABLE (PREFIX_0F3830) }, |
||
7011 | { PREFIX_TABLE (PREFIX_0F3831) }, |
||
7012 | { PREFIX_TABLE (PREFIX_0F3832) }, |
||
7013 | { PREFIX_TABLE (PREFIX_0F3833) }, |
||
7014 | { PREFIX_TABLE (PREFIX_0F3834) }, |
||
7015 | { PREFIX_TABLE (PREFIX_0F3835) }, |
||
7016 | { Bad_Opcode }, |
||
7017 | { PREFIX_TABLE (PREFIX_0F3837) }, |
||
7018 | /* 38 */ |
||
7019 | { PREFIX_TABLE (PREFIX_0F3838) }, |
||
7020 | { PREFIX_TABLE (PREFIX_0F3839) }, |
||
7021 | { PREFIX_TABLE (PREFIX_0F383A) }, |
||
7022 | { PREFIX_TABLE (PREFIX_0F383B) }, |
||
7023 | { PREFIX_TABLE (PREFIX_0F383C) }, |
||
7024 | { PREFIX_TABLE (PREFIX_0F383D) }, |
||
7025 | { PREFIX_TABLE (PREFIX_0F383E) }, |
||
7026 | { PREFIX_TABLE (PREFIX_0F383F) }, |
||
7027 | /* 40 */ |
||
7028 | { PREFIX_TABLE (PREFIX_0F3840) }, |
||
7029 | { PREFIX_TABLE (PREFIX_0F3841) }, |
||
7030 | { Bad_Opcode }, |
||
7031 | { Bad_Opcode }, |
||
7032 | { Bad_Opcode }, |
||
7033 | { Bad_Opcode }, |
||
7034 | { Bad_Opcode }, |
||
7035 | { Bad_Opcode }, |
||
7036 | /* 48 */ |
||
7037 | { Bad_Opcode }, |
||
7038 | { Bad_Opcode }, |
||
7039 | { Bad_Opcode }, |
||
7040 | { Bad_Opcode }, |
||
7041 | { Bad_Opcode }, |
||
7042 | { Bad_Opcode }, |
||
7043 | { Bad_Opcode }, |
||
7044 | { Bad_Opcode }, |
||
7045 | /* 50 */ |
||
7046 | { Bad_Opcode }, |
||
7047 | { Bad_Opcode }, |
||
7048 | { Bad_Opcode }, |
||
7049 | { Bad_Opcode }, |
||
7050 | { Bad_Opcode }, |
||
7051 | { Bad_Opcode }, |
||
7052 | { Bad_Opcode }, |
||
7053 | { Bad_Opcode }, |
||
7054 | /* 58 */ |
||
7055 | { Bad_Opcode }, |
||
7056 | { Bad_Opcode }, |
||
7057 | { Bad_Opcode }, |
||
7058 | { Bad_Opcode }, |
||
7059 | { Bad_Opcode }, |
||
7060 | { Bad_Opcode }, |
||
7061 | { Bad_Opcode }, |
||
7062 | { Bad_Opcode }, |
||
7063 | /* 60 */ |
||
7064 | { Bad_Opcode }, |
||
7065 | { Bad_Opcode }, |
||
7066 | { Bad_Opcode }, |
||
7067 | { Bad_Opcode }, |
||
7068 | { Bad_Opcode }, |
||
7069 | { Bad_Opcode }, |
||
7070 | { Bad_Opcode }, |
||
7071 | { Bad_Opcode }, |
||
7072 | /* 68 */ |
||
7073 | { Bad_Opcode }, |
||
7074 | { Bad_Opcode }, |
||
7075 | { Bad_Opcode }, |
||
7076 | { Bad_Opcode }, |
||
7077 | { Bad_Opcode }, |
||
7078 | { Bad_Opcode }, |
||
7079 | { Bad_Opcode }, |
||
7080 | { Bad_Opcode }, |
||
7081 | /* 70 */ |
||
7082 | { Bad_Opcode }, |
||
7083 | { Bad_Opcode }, |
||
7084 | { Bad_Opcode }, |
||
7085 | { Bad_Opcode }, |
||
7086 | { Bad_Opcode }, |
||
7087 | { Bad_Opcode }, |
||
7088 | { Bad_Opcode }, |
||
7089 | { Bad_Opcode }, |
||
7090 | /* 78 */ |
||
7091 | { Bad_Opcode }, |
||
7092 | { Bad_Opcode }, |
||
7093 | { Bad_Opcode }, |
||
7094 | { Bad_Opcode }, |
||
7095 | { Bad_Opcode }, |
||
7096 | { Bad_Opcode }, |
||
7097 | { Bad_Opcode }, |
||
7098 | { Bad_Opcode }, |
||
7099 | /* 80 */ |
||
7100 | { PREFIX_TABLE (PREFIX_0F3880) }, |
||
7101 | { PREFIX_TABLE (PREFIX_0F3881) }, |
||
7102 | { PREFIX_TABLE (PREFIX_0F3882) }, |
||
7103 | { Bad_Opcode }, |
||
7104 | { Bad_Opcode }, |
||
7105 | { Bad_Opcode }, |
||
7106 | { Bad_Opcode }, |
||
7107 | { Bad_Opcode }, |
||
7108 | /* 88 */ |
||
7109 | { Bad_Opcode }, |
||
7110 | { Bad_Opcode }, |
||
7111 | { Bad_Opcode }, |
||
7112 | { Bad_Opcode }, |
||
7113 | { Bad_Opcode }, |
||
7114 | { Bad_Opcode }, |
||
7115 | { Bad_Opcode }, |
||
7116 | { Bad_Opcode }, |
||
7117 | /* 90 */ |
||
7118 | { Bad_Opcode }, |
||
7119 | { Bad_Opcode }, |
||
7120 | { Bad_Opcode }, |
||
7121 | { Bad_Opcode }, |
||
7122 | { Bad_Opcode }, |
||
7123 | { Bad_Opcode }, |
||
7124 | { Bad_Opcode }, |
||
7125 | { Bad_Opcode }, |
||
7126 | /* 98 */ |
||
7127 | { Bad_Opcode }, |
||
7128 | { Bad_Opcode }, |
||
7129 | { Bad_Opcode }, |
||
7130 | { Bad_Opcode }, |
||
7131 | { Bad_Opcode }, |
||
7132 | { Bad_Opcode }, |
||
7133 | { Bad_Opcode }, |
||
7134 | { Bad_Opcode }, |
||
7135 | /* a0 */ |
||
7136 | { Bad_Opcode }, |
||
7137 | { Bad_Opcode }, |
||
7138 | { Bad_Opcode }, |
||
7139 | { Bad_Opcode }, |
||
7140 | { Bad_Opcode }, |
||
7141 | { Bad_Opcode }, |
||
7142 | { Bad_Opcode }, |
||
7143 | { Bad_Opcode }, |
||
7144 | /* a8 */ |
||
7145 | { Bad_Opcode }, |
||
7146 | { Bad_Opcode }, |
||
7147 | { Bad_Opcode }, |
||
7148 | { Bad_Opcode }, |
||
7149 | { Bad_Opcode }, |
||
7150 | { Bad_Opcode }, |
||
7151 | { Bad_Opcode }, |
||
7152 | { Bad_Opcode }, |
||
7153 | /* b0 */ |
||
7154 | { Bad_Opcode }, |
||
7155 | { Bad_Opcode }, |
||
7156 | { Bad_Opcode }, |
||
7157 | { Bad_Opcode }, |
||
7158 | { Bad_Opcode }, |
||
7159 | { Bad_Opcode }, |
||
7160 | { Bad_Opcode }, |
||
7161 | { Bad_Opcode }, |
||
7162 | /* b8 */ |
||
7163 | { Bad_Opcode }, |
||
7164 | { Bad_Opcode }, |
||
7165 | { Bad_Opcode }, |
||
7166 | { Bad_Opcode }, |
||
7167 | { Bad_Opcode }, |
||
7168 | { Bad_Opcode }, |
||
7169 | { Bad_Opcode }, |
||
7170 | { Bad_Opcode }, |
||
7171 | /* c0 */ |
||
7172 | { Bad_Opcode }, |
||
7173 | { Bad_Opcode }, |
||
7174 | { Bad_Opcode }, |
||
7175 | { Bad_Opcode }, |
||
7176 | { Bad_Opcode }, |
||
7177 | { Bad_Opcode }, |
||
7178 | { Bad_Opcode }, |
||
7179 | { Bad_Opcode }, |
||
7180 | /* c8 */ |
||
7181 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
||
7182 | { PREFIX_TABLE (PREFIX_0F38C9) }, |
||
7183 | { PREFIX_TABLE (PREFIX_0F38CA) }, |
||
7184 | { PREFIX_TABLE (PREFIX_0F38CB) }, |
||
7185 | { PREFIX_TABLE (PREFIX_0F38CC) }, |
||
7186 | { PREFIX_TABLE (PREFIX_0F38CD) }, |
||
7187 | { Bad_Opcode }, |
||
7188 | { Bad_Opcode }, |
||
7189 | /* d0 */ |
||
7190 | { Bad_Opcode }, |
||
7191 | { Bad_Opcode }, |
||
7192 | { Bad_Opcode }, |
||
7193 | { Bad_Opcode }, |
||
7194 | { Bad_Opcode }, |
||
7195 | { Bad_Opcode }, |
||
7196 | { Bad_Opcode }, |
||
7197 | { Bad_Opcode }, |
||
7198 | /* d8 */ |
||
7199 | { Bad_Opcode }, |
||
7200 | { Bad_Opcode }, |
||
7201 | { Bad_Opcode }, |
||
7202 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
||
7203 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
||
7204 | { PREFIX_TABLE (PREFIX_0F38DD) }, |
||
7205 | { PREFIX_TABLE (PREFIX_0F38DE) }, |
||
7206 | { PREFIX_TABLE (PREFIX_0F38DF) }, |
||
7207 | /* e0 */ |
||
7208 | { Bad_Opcode }, |
||
7209 | { Bad_Opcode }, |
||
7210 | { Bad_Opcode }, |
||
7211 | { Bad_Opcode }, |
||
7212 | { Bad_Opcode }, |
||
7213 | { Bad_Opcode }, |
||
7214 | { Bad_Opcode }, |
||
7215 | { Bad_Opcode }, |
||
7216 | /* e8 */ |
||
7217 | { Bad_Opcode }, |
||
7218 | { Bad_Opcode }, |
||
7219 | { Bad_Opcode }, |
||
7220 | { Bad_Opcode }, |
||
7221 | { Bad_Opcode }, |
||
7222 | { Bad_Opcode }, |
||
7223 | { Bad_Opcode }, |
||
7224 | { Bad_Opcode }, |
||
7225 | /* f0 */ |
||
7226 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
||
7227 | { PREFIX_TABLE (PREFIX_0F38F1) }, |
||
7228 | { Bad_Opcode }, |
||
7229 | { Bad_Opcode }, |
||
7230 | { Bad_Opcode }, |
||
7231 | { Bad_Opcode }, |
||
7232 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
||
7233 | { Bad_Opcode }, |
||
7234 | /* f8 */ |
||
7235 | { Bad_Opcode }, |
||
7236 | { Bad_Opcode }, |
||
7237 | { Bad_Opcode }, |
||
7238 | { Bad_Opcode }, |
||
7239 | { Bad_Opcode }, |
||
7240 | { Bad_Opcode }, |
||
7241 | { Bad_Opcode }, |
||
7242 | { Bad_Opcode }, |
||
7243 | }, |
||
7244 | /* THREE_BYTE_0F3A */ |
||
7245 | { |
||
7246 | /* 00 */ |
||
7247 | { Bad_Opcode }, |
||
7248 | { Bad_Opcode }, |
||
7249 | { Bad_Opcode }, |
||
7250 | { Bad_Opcode }, |
||
7251 | { Bad_Opcode }, |
||
7252 | { Bad_Opcode }, |
||
7253 | { Bad_Opcode }, |
||
7254 | { Bad_Opcode }, |
||
7255 | /* 08 */ |
||
7256 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
||
7257 | { PREFIX_TABLE (PREFIX_0F3A09) }, |
||
7258 | { PREFIX_TABLE (PREFIX_0F3A0A) }, |
||
7259 | { PREFIX_TABLE (PREFIX_0F3A0B) }, |
||
7260 | { PREFIX_TABLE (PREFIX_0F3A0C) }, |
||
7261 | { PREFIX_TABLE (PREFIX_0F3A0D) }, |
||
7262 | { PREFIX_TABLE (PREFIX_0F3A0E) }, |
||
6324 | serge | 7263 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
5221 | serge | 7264 | /* 10 */ |
7265 | { Bad_Opcode }, |
||
7266 | { Bad_Opcode }, |
||
7267 | { Bad_Opcode }, |
||
7268 | { Bad_Opcode }, |
||
7269 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
||
7270 | { PREFIX_TABLE (PREFIX_0F3A15) }, |
||
7271 | { PREFIX_TABLE (PREFIX_0F3A16) }, |
||
7272 | { PREFIX_TABLE (PREFIX_0F3A17) }, |
||
7273 | /* 18 */ |
||
7274 | { Bad_Opcode }, |
||
7275 | { Bad_Opcode }, |
||
7276 | { Bad_Opcode }, |
||
7277 | { Bad_Opcode }, |
||
7278 | { Bad_Opcode }, |
||
7279 | { Bad_Opcode }, |
||
7280 | { Bad_Opcode }, |
||
7281 | { Bad_Opcode }, |
||
7282 | /* 20 */ |
||
7283 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
||
7284 | { PREFIX_TABLE (PREFIX_0F3A21) }, |
||
7285 | { PREFIX_TABLE (PREFIX_0F3A22) }, |
||
7286 | { Bad_Opcode }, |
||
7287 | { Bad_Opcode }, |
||
7288 | { Bad_Opcode }, |
||
7289 | { Bad_Opcode }, |
||
7290 | { Bad_Opcode }, |
||
7291 | /* 28 */ |
||
7292 | { Bad_Opcode }, |
||
7293 | { Bad_Opcode }, |
||
7294 | { Bad_Opcode }, |
||
7295 | { Bad_Opcode }, |
||
7296 | { Bad_Opcode }, |
||
7297 | { Bad_Opcode }, |
||
7298 | { Bad_Opcode }, |
||
7299 | { Bad_Opcode }, |
||
7300 | /* 30 */ |
||
7301 | { Bad_Opcode }, |
||
7302 | { Bad_Opcode }, |
||
7303 | { Bad_Opcode }, |
||
7304 | { Bad_Opcode }, |
||
7305 | { Bad_Opcode }, |
||
7306 | { Bad_Opcode }, |
||
7307 | { Bad_Opcode }, |
||
7308 | { Bad_Opcode }, |
||
7309 | /* 38 */ |
||
7310 | { Bad_Opcode }, |
||
7311 | { Bad_Opcode }, |
||
7312 | { Bad_Opcode }, |
||
7313 | { Bad_Opcode }, |
||
7314 | { Bad_Opcode }, |
||
7315 | { Bad_Opcode }, |
||
7316 | { Bad_Opcode }, |
||
7317 | { Bad_Opcode }, |
||
7318 | /* 40 */ |
||
7319 | { PREFIX_TABLE (PREFIX_0F3A40) }, |
||
7320 | { PREFIX_TABLE (PREFIX_0F3A41) }, |
||
7321 | { PREFIX_TABLE (PREFIX_0F3A42) }, |
||
7322 | { Bad_Opcode }, |
||
7323 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
||
7324 | { Bad_Opcode }, |
||
7325 | { Bad_Opcode }, |
||
7326 | { Bad_Opcode }, |
||
7327 | /* 48 */ |
||
7328 | { Bad_Opcode }, |
||
7329 | { Bad_Opcode }, |
||
7330 | { Bad_Opcode }, |
||
7331 | { Bad_Opcode }, |
||
7332 | { Bad_Opcode }, |
||
7333 | { Bad_Opcode }, |
||
7334 | { Bad_Opcode }, |
||
7335 | { Bad_Opcode }, |
||
7336 | /* 50 */ |
||
7337 | { Bad_Opcode }, |
||
7338 | { Bad_Opcode }, |
||
7339 | { Bad_Opcode }, |
||
7340 | { Bad_Opcode }, |
||
7341 | { Bad_Opcode }, |
||
7342 | { Bad_Opcode }, |
||
7343 | { Bad_Opcode }, |
||
7344 | { Bad_Opcode }, |
||
7345 | /* 58 */ |
||
7346 | { Bad_Opcode }, |
||
7347 | { Bad_Opcode }, |
||
7348 | { Bad_Opcode }, |
||
7349 | { Bad_Opcode }, |
||
7350 | { Bad_Opcode }, |
||
7351 | { Bad_Opcode }, |
||
7352 | { Bad_Opcode }, |
||
7353 | { Bad_Opcode }, |
||
7354 | /* 60 */ |
||
7355 | { PREFIX_TABLE (PREFIX_0F3A60) }, |
||
7356 | { PREFIX_TABLE (PREFIX_0F3A61) }, |
||
7357 | { PREFIX_TABLE (PREFIX_0F3A62) }, |
||
7358 | { PREFIX_TABLE (PREFIX_0F3A63) }, |
||
7359 | { Bad_Opcode }, |
||
7360 | { Bad_Opcode }, |
||
7361 | { Bad_Opcode }, |
||
7362 | { Bad_Opcode }, |
||
7363 | /* 68 */ |
||
7364 | { Bad_Opcode }, |
||
7365 | { Bad_Opcode }, |
||
7366 | { Bad_Opcode }, |
||
7367 | { Bad_Opcode }, |
||
7368 | { Bad_Opcode }, |
||
7369 | { Bad_Opcode }, |
||
7370 | { Bad_Opcode }, |
||
7371 | { Bad_Opcode }, |
||
7372 | /* 70 */ |
||
7373 | { Bad_Opcode }, |
||
7374 | { Bad_Opcode }, |
||
7375 | { Bad_Opcode }, |
||
7376 | { Bad_Opcode }, |
||
7377 | { Bad_Opcode }, |
||
7378 | { Bad_Opcode }, |
||
7379 | { Bad_Opcode }, |
||
7380 | { Bad_Opcode }, |
||
7381 | /* 78 */ |
||
7382 | { Bad_Opcode }, |
||
7383 | { Bad_Opcode }, |
||
7384 | { Bad_Opcode }, |
||
7385 | { Bad_Opcode }, |
||
7386 | { Bad_Opcode }, |
||
7387 | { Bad_Opcode }, |
||
7388 | { Bad_Opcode }, |
||
7389 | { Bad_Opcode }, |
||
7390 | /* 80 */ |
||
7391 | { Bad_Opcode }, |
||
7392 | { Bad_Opcode }, |
||
7393 | { Bad_Opcode }, |
||
7394 | { Bad_Opcode }, |
||
7395 | { Bad_Opcode }, |
||
7396 | { Bad_Opcode }, |
||
7397 | { Bad_Opcode }, |
||
7398 | { Bad_Opcode }, |
||
7399 | /* 88 */ |
||
7400 | { Bad_Opcode }, |
||
7401 | { Bad_Opcode }, |
||
7402 | { Bad_Opcode }, |
||
7403 | { Bad_Opcode }, |
||
7404 | { Bad_Opcode }, |
||
7405 | { Bad_Opcode }, |
||
7406 | { Bad_Opcode }, |
||
7407 | { Bad_Opcode }, |
||
7408 | /* 90 */ |
||
7409 | { Bad_Opcode }, |
||
7410 | { Bad_Opcode }, |
||
7411 | { Bad_Opcode }, |
||
7412 | { Bad_Opcode }, |
||
7413 | { Bad_Opcode }, |
||
7414 | { Bad_Opcode }, |
||
7415 | { Bad_Opcode }, |
||
7416 | { Bad_Opcode }, |
||
7417 | /* 98 */ |
||
7418 | { Bad_Opcode }, |
||
7419 | { Bad_Opcode }, |
||
7420 | { Bad_Opcode }, |
||
7421 | { Bad_Opcode }, |
||
7422 | { Bad_Opcode }, |
||
7423 | { Bad_Opcode }, |
||
7424 | { Bad_Opcode }, |
||
7425 | { Bad_Opcode }, |
||
7426 | /* a0 */ |
||
7427 | { Bad_Opcode }, |
||
7428 | { Bad_Opcode }, |
||
7429 | { Bad_Opcode }, |
||
7430 | { Bad_Opcode }, |
||
7431 | { Bad_Opcode }, |
||
7432 | { Bad_Opcode }, |
||
7433 | { Bad_Opcode }, |
||
7434 | { Bad_Opcode }, |
||
7435 | /* a8 */ |
||
7436 | { Bad_Opcode }, |
||
7437 | { Bad_Opcode }, |
||
7438 | { Bad_Opcode }, |
||
7439 | { Bad_Opcode }, |
||
7440 | { Bad_Opcode }, |
||
7441 | { Bad_Opcode }, |
||
7442 | { Bad_Opcode }, |
||
7443 | { Bad_Opcode }, |
||
7444 | /* b0 */ |
||
7445 | { Bad_Opcode }, |
||
7446 | { Bad_Opcode }, |
||
7447 | { Bad_Opcode }, |
||
7448 | { Bad_Opcode }, |
||
7449 | { Bad_Opcode }, |
||
7450 | { Bad_Opcode }, |
||
7451 | { Bad_Opcode }, |
||
7452 | { Bad_Opcode }, |
||
7453 | /* b8 */ |
||
7454 | { Bad_Opcode }, |
||
7455 | { Bad_Opcode }, |
||
7456 | { Bad_Opcode }, |
||
7457 | { Bad_Opcode }, |
||
7458 | { Bad_Opcode }, |
||
7459 | { Bad_Opcode }, |
||
7460 | { Bad_Opcode }, |
||
7461 | { Bad_Opcode }, |
||
7462 | /* c0 */ |
||
7463 | { Bad_Opcode }, |
||
7464 | { Bad_Opcode }, |
||
7465 | { Bad_Opcode }, |
||
7466 | { Bad_Opcode }, |
||
7467 | { Bad_Opcode }, |
||
7468 | { Bad_Opcode }, |
||
7469 | { Bad_Opcode }, |
||
7470 | { Bad_Opcode }, |
||
7471 | /* c8 */ |
||
7472 | { Bad_Opcode }, |
||
7473 | { Bad_Opcode }, |
||
7474 | { Bad_Opcode }, |
||
7475 | { Bad_Opcode }, |
||
7476 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
||
7477 | { Bad_Opcode }, |
||
7478 | { Bad_Opcode }, |
||
7479 | { Bad_Opcode }, |
||
7480 | /* d0 */ |
||
7481 | { Bad_Opcode }, |
||
7482 | { Bad_Opcode }, |
||
7483 | { Bad_Opcode }, |
||
7484 | { Bad_Opcode }, |
||
7485 | { Bad_Opcode }, |
||
7486 | { Bad_Opcode }, |
||
7487 | { Bad_Opcode }, |
||
7488 | { Bad_Opcode }, |
||
7489 | /* d8 */ |
||
7490 | { Bad_Opcode }, |
||
7491 | { Bad_Opcode }, |
||
7492 | { Bad_Opcode }, |
||
7493 | { Bad_Opcode }, |
||
7494 | { Bad_Opcode }, |
||
7495 | { Bad_Opcode }, |
||
7496 | { Bad_Opcode }, |
||
7497 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
||
7498 | /* e0 */ |
||
7499 | { Bad_Opcode }, |
||
7500 | { Bad_Opcode }, |
||
7501 | { Bad_Opcode }, |
||
7502 | { Bad_Opcode }, |
||
7503 | { Bad_Opcode }, |
||
7504 | { Bad_Opcode }, |
||
7505 | { Bad_Opcode }, |
||
7506 | { Bad_Opcode }, |
||
7507 | /* e8 */ |
||
7508 | { Bad_Opcode }, |
||
7509 | { Bad_Opcode }, |
||
7510 | { Bad_Opcode }, |
||
7511 | { Bad_Opcode }, |
||
7512 | { Bad_Opcode }, |
||
7513 | { Bad_Opcode }, |
||
7514 | { Bad_Opcode }, |
||
7515 | { Bad_Opcode }, |
||
7516 | /* f0 */ |
||
7517 | { Bad_Opcode }, |
||
7518 | { Bad_Opcode }, |
||
7519 | { Bad_Opcode }, |
||
7520 | { Bad_Opcode }, |
||
7521 | { Bad_Opcode }, |
||
7522 | { Bad_Opcode }, |
||
7523 | { Bad_Opcode }, |
||
7524 | { Bad_Opcode }, |
||
7525 | /* f8 */ |
||
7526 | { Bad_Opcode }, |
||
7527 | { Bad_Opcode }, |
||
7528 | { Bad_Opcode }, |
||
7529 | { Bad_Opcode }, |
||
7530 | { Bad_Opcode }, |
||
7531 | { Bad_Opcode }, |
||
7532 | { Bad_Opcode }, |
||
7533 | { Bad_Opcode }, |
||
7534 | }, |
||
7535 | |||
7536 | /* THREE_BYTE_0F7A */ |
||
7537 | { |
||
7538 | /* 00 */ |
||
7539 | { Bad_Opcode }, |
||
7540 | { Bad_Opcode }, |
||
7541 | { Bad_Opcode }, |
||
7542 | { Bad_Opcode }, |
||
7543 | { Bad_Opcode }, |
||
7544 | { Bad_Opcode }, |
||
7545 | { Bad_Opcode }, |
||
7546 | { Bad_Opcode }, |
||
7547 | /* 08 */ |
||
7548 | { Bad_Opcode }, |
||
7549 | { Bad_Opcode }, |
||
7550 | { Bad_Opcode }, |
||
7551 | { Bad_Opcode }, |
||
7552 | { Bad_Opcode }, |
||
7553 | { Bad_Opcode }, |
||
7554 | { Bad_Opcode }, |
||
7555 | { Bad_Opcode }, |
||
7556 | /* 10 */ |
||
7557 | { Bad_Opcode }, |
||
7558 | { Bad_Opcode }, |
||
7559 | { Bad_Opcode }, |
||
7560 | { Bad_Opcode }, |
||
7561 | { Bad_Opcode }, |
||
7562 | { Bad_Opcode }, |
||
7563 | { Bad_Opcode }, |
||
7564 | { Bad_Opcode }, |
||
7565 | /* 18 */ |
||
7566 | { Bad_Opcode }, |
||
7567 | { Bad_Opcode }, |
||
7568 | { Bad_Opcode }, |
||
7569 | { Bad_Opcode }, |
||
7570 | { Bad_Opcode }, |
||
7571 | { Bad_Opcode }, |
||
7572 | { Bad_Opcode }, |
||
7573 | { Bad_Opcode }, |
||
7574 | /* 20 */ |
||
6324 | serge | 7575 | { "ptest", { XX }, PREFIX_OPCODE }, |
5221 | serge | 7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, |
||
7578 | { Bad_Opcode }, |
||
7579 | { Bad_Opcode }, |
||
7580 | { Bad_Opcode }, |
||
7581 | { Bad_Opcode }, |
||
7582 | { Bad_Opcode }, |
||
7583 | /* 28 */ |
||
7584 | { Bad_Opcode }, |
||
7585 | { Bad_Opcode }, |
||
7586 | { Bad_Opcode }, |
||
7587 | { Bad_Opcode }, |
||
7588 | { Bad_Opcode }, |
||
7589 | { Bad_Opcode }, |
||
7590 | { Bad_Opcode }, |
||
7591 | { Bad_Opcode }, |
||
7592 | /* 30 */ |
||
7593 | { Bad_Opcode }, |
||
7594 | { Bad_Opcode }, |
||
7595 | { Bad_Opcode }, |
||
7596 | { Bad_Opcode }, |
||
7597 | { Bad_Opcode }, |
||
7598 | { Bad_Opcode }, |
||
7599 | { Bad_Opcode }, |
||
7600 | { Bad_Opcode }, |
||
7601 | /* 38 */ |
||
7602 | { Bad_Opcode }, |
||
7603 | { Bad_Opcode }, |
||
7604 | { Bad_Opcode }, |
||
7605 | { Bad_Opcode }, |
||
7606 | { Bad_Opcode }, |
||
7607 | { Bad_Opcode }, |
||
7608 | { Bad_Opcode }, |
||
7609 | { Bad_Opcode }, |
||
7610 | /* 40 */ |
||
7611 | { Bad_Opcode }, |
||
6324 | serge | 7612 | { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, |
7613 | { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, |
||
7614 | { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 7615 | { Bad_Opcode }, |
7616 | { Bad_Opcode }, |
||
6324 | serge | 7617 | { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, |
7618 | { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 7619 | /* 48 */ |
7620 | { Bad_Opcode }, |
||
7621 | { Bad_Opcode }, |
||
7622 | { Bad_Opcode }, |
||
6324 | serge | 7623 | { "phadddq", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 7624 | { Bad_Opcode }, |
7625 | { Bad_Opcode }, |
||
7626 | { Bad_Opcode }, |
||
7627 | { Bad_Opcode }, |
||
7628 | /* 50 */ |
||
7629 | { Bad_Opcode }, |
||
6324 | serge | 7630 | { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, |
7631 | { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, |
||
7632 | { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 7633 | { Bad_Opcode }, |
7634 | { Bad_Opcode }, |
||
6324 | serge | 7635 | { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, |
7636 | { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 7637 | /* 58 */ |
7638 | { Bad_Opcode }, |
||
7639 | { Bad_Opcode }, |
||
7640 | { Bad_Opcode }, |
||
6324 | serge | 7641 | { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, |
5221 | serge | 7642 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, |
||
7644 | { Bad_Opcode }, |
||
7645 | { Bad_Opcode }, |
||
7646 | /* 60 */ |
||
7647 | { Bad_Opcode }, |
||
6324 | serge | 7648 | { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, |
7649 | { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, |
||
7650 | { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 7651 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, |
||
7653 | { Bad_Opcode }, |
||
7654 | { Bad_Opcode }, |
||
7655 | /* 68 */ |
||
7656 | { Bad_Opcode }, |
||
7657 | { Bad_Opcode }, |
||
7658 | { Bad_Opcode }, |
||
7659 | { Bad_Opcode }, |
||
7660 | { Bad_Opcode }, |
||
7661 | { Bad_Opcode }, |
||
7662 | { Bad_Opcode }, |
||
7663 | { Bad_Opcode }, |
||
7664 | /* 70 */ |
||
7665 | { Bad_Opcode }, |
||
7666 | { Bad_Opcode }, |
||
7667 | { Bad_Opcode }, |
||
7668 | { Bad_Opcode }, |
||
7669 | { Bad_Opcode }, |
||
7670 | { Bad_Opcode }, |
||
7671 | { Bad_Opcode }, |
||
7672 | { Bad_Opcode }, |
||
7673 | /* 78 */ |
||
7674 | { Bad_Opcode }, |
||
7675 | { Bad_Opcode }, |
||
7676 | { Bad_Opcode }, |
||
7677 | { Bad_Opcode }, |
||
7678 | { Bad_Opcode }, |
||
7679 | { Bad_Opcode }, |
||
7680 | { Bad_Opcode }, |
||
7681 | { Bad_Opcode }, |
||
7682 | /* 80 */ |
||
7683 | { Bad_Opcode }, |
||
7684 | { Bad_Opcode }, |
||
7685 | { Bad_Opcode }, |
||
7686 | { Bad_Opcode }, |
||
7687 | { Bad_Opcode }, |
||
7688 | { Bad_Opcode }, |
||
7689 | { Bad_Opcode }, |
||
7690 | { Bad_Opcode }, |
||
7691 | /* 88 */ |
||
7692 | { Bad_Opcode }, |
||
7693 | { Bad_Opcode }, |
||
7694 | { Bad_Opcode }, |
||
7695 | { Bad_Opcode }, |
||
7696 | { Bad_Opcode }, |
||
7697 | { Bad_Opcode }, |
||
7698 | { Bad_Opcode }, |
||
7699 | { Bad_Opcode }, |
||
7700 | /* 90 */ |
||
7701 | { Bad_Opcode }, |
||
7702 | { Bad_Opcode }, |
||
7703 | { Bad_Opcode }, |
||
7704 | { Bad_Opcode }, |
||
7705 | { Bad_Opcode }, |
||
7706 | { Bad_Opcode }, |
||
7707 | { Bad_Opcode }, |
||
7708 | { Bad_Opcode }, |
||
7709 | /* 98 */ |
||
7710 | { Bad_Opcode }, |
||
7711 | { Bad_Opcode }, |
||
7712 | { Bad_Opcode }, |
||
7713 | { Bad_Opcode }, |
||
7714 | { Bad_Opcode }, |
||
7715 | { Bad_Opcode }, |
||
7716 | { Bad_Opcode }, |
||
7717 | { Bad_Opcode }, |
||
7718 | /* a0 */ |
||
7719 | { Bad_Opcode }, |
||
7720 | { Bad_Opcode }, |
||
7721 | { Bad_Opcode }, |
||
7722 | { Bad_Opcode }, |
||
7723 | { Bad_Opcode }, |
||
7724 | { Bad_Opcode }, |
||
7725 | { Bad_Opcode }, |
||
7726 | { Bad_Opcode }, |
||
7727 | /* a8 */ |
||
7728 | { Bad_Opcode }, |
||
7729 | { Bad_Opcode }, |
||
7730 | { Bad_Opcode }, |
||
7731 | { Bad_Opcode }, |
||
7732 | { Bad_Opcode }, |
||
7733 | { Bad_Opcode }, |
||
7734 | { Bad_Opcode }, |
||
7735 | { Bad_Opcode }, |
||
7736 | /* b0 */ |
||
7737 | { Bad_Opcode }, |
||
7738 | { Bad_Opcode }, |
||
7739 | { Bad_Opcode }, |
||
7740 | { Bad_Opcode }, |
||
7741 | { Bad_Opcode }, |
||
7742 | { Bad_Opcode }, |
||
7743 | { Bad_Opcode }, |
||
7744 | { Bad_Opcode }, |
||
7745 | /* b8 */ |
||
7746 | { Bad_Opcode }, |
||
7747 | { Bad_Opcode }, |
||
7748 | { Bad_Opcode }, |
||
7749 | { Bad_Opcode }, |
||
7750 | { Bad_Opcode }, |
||
7751 | { Bad_Opcode }, |
||
7752 | { Bad_Opcode }, |
||
7753 | { Bad_Opcode }, |
||
7754 | /* c0 */ |
||
7755 | { Bad_Opcode }, |
||
7756 | { Bad_Opcode }, |
||
7757 | { Bad_Opcode }, |
||
7758 | { Bad_Opcode }, |
||
7759 | { Bad_Opcode }, |
||
7760 | { Bad_Opcode }, |
||
7761 | { Bad_Opcode }, |
||
7762 | { Bad_Opcode }, |
||
7763 | /* c8 */ |
||
7764 | { Bad_Opcode }, |
||
7765 | { Bad_Opcode }, |
||
7766 | { Bad_Opcode }, |
||
7767 | { Bad_Opcode }, |
||
7768 | { Bad_Opcode }, |
||
7769 | { Bad_Opcode }, |
||
7770 | { Bad_Opcode }, |
||
7771 | { Bad_Opcode }, |
||
7772 | /* d0 */ |
||
7773 | { Bad_Opcode }, |
||
7774 | { Bad_Opcode }, |
||
7775 | { Bad_Opcode }, |
||
7776 | { Bad_Opcode }, |
||
7777 | { Bad_Opcode }, |
||
7778 | { Bad_Opcode }, |
||
7779 | { Bad_Opcode }, |
||
7780 | { Bad_Opcode }, |
||
7781 | /* d8 */ |
||
7782 | { Bad_Opcode }, |
||
7783 | { Bad_Opcode }, |
||
7784 | { Bad_Opcode }, |
||
7785 | { Bad_Opcode }, |
||
7786 | { Bad_Opcode }, |
||
7787 | { Bad_Opcode }, |
||
7788 | { Bad_Opcode }, |
||
7789 | { Bad_Opcode }, |
||
7790 | /* e0 */ |
||
7791 | { Bad_Opcode }, |
||
7792 | { Bad_Opcode }, |
||
7793 | { Bad_Opcode }, |
||
7794 | { Bad_Opcode }, |
||
7795 | { Bad_Opcode }, |
||
7796 | { Bad_Opcode }, |
||
7797 | { Bad_Opcode }, |
||
7798 | { Bad_Opcode }, |
||
7799 | /* e8 */ |
||
7800 | { Bad_Opcode }, |
||
7801 | { Bad_Opcode }, |
||
7802 | { Bad_Opcode }, |
||
7803 | { Bad_Opcode }, |
||
7804 | { Bad_Opcode }, |
||
7805 | { Bad_Opcode }, |
||
7806 | { Bad_Opcode }, |
||
7807 | { Bad_Opcode }, |
||
7808 | /* f0 */ |
||
7809 | { Bad_Opcode }, |
||
7810 | { Bad_Opcode }, |
||
7811 | { Bad_Opcode }, |
||
7812 | { Bad_Opcode }, |
||
7813 | { Bad_Opcode }, |
||
7814 | { Bad_Opcode }, |
||
7815 | { Bad_Opcode }, |
||
7816 | { Bad_Opcode }, |
||
7817 | /* f8 */ |
||
7818 | { Bad_Opcode }, |
||
7819 | { Bad_Opcode }, |
||
7820 | { Bad_Opcode }, |
||
7821 | { Bad_Opcode }, |
||
7822 | { Bad_Opcode }, |
||
7823 | { Bad_Opcode }, |
||
7824 | { Bad_Opcode }, |
||
7825 | { Bad_Opcode }, |
||
7826 | }, |
||
7827 | }; |
||
7828 | |||
7829 | static const struct dis386 xop_table[][256] = { |
||
7830 | /* XOP_08 */ |
||
7831 | { |
||
7832 | /* 00 */ |
||
7833 | { Bad_Opcode }, |
||
7834 | { Bad_Opcode }, |
||
7835 | { Bad_Opcode }, |
||
7836 | { Bad_Opcode }, |
||
7837 | { Bad_Opcode }, |
||
7838 | { Bad_Opcode }, |
||
7839 | { Bad_Opcode }, |
||
7840 | { Bad_Opcode }, |
||
7841 | /* 08 */ |
||
7842 | { Bad_Opcode }, |
||
7843 | { Bad_Opcode }, |
||
7844 | { Bad_Opcode }, |
||
7845 | { Bad_Opcode }, |
||
7846 | { Bad_Opcode }, |
||
7847 | { Bad_Opcode }, |
||
7848 | { Bad_Opcode }, |
||
7849 | { Bad_Opcode }, |
||
7850 | /* 10 */ |
||
7851 | { Bad_Opcode }, |
||
7852 | { Bad_Opcode }, |
||
7853 | { Bad_Opcode }, |
||
7854 | { Bad_Opcode }, |
||
7855 | { Bad_Opcode }, |
||
7856 | { Bad_Opcode }, |
||
7857 | { Bad_Opcode }, |
||
7858 | { Bad_Opcode }, |
||
7859 | /* 18 */ |
||
7860 | { Bad_Opcode }, |
||
7861 | { Bad_Opcode }, |
||
7862 | { Bad_Opcode }, |
||
7863 | { Bad_Opcode }, |
||
7864 | { Bad_Opcode }, |
||
7865 | { Bad_Opcode }, |
||
7866 | { Bad_Opcode }, |
||
7867 | { Bad_Opcode }, |
||
7868 | /* 20 */ |
||
7869 | { Bad_Opcode }, |
||
7870 | { Bad_Opcode }, |
||
7871 | { Bad_Opcode }, |
||
7872 | { Bad_Opcode }, |
||
7873 | { Bad_Opcode }, |
||
7874 | { Bad_Opcode }, |
||
7875 | { Bad_Opcode }, |
||
7876 | { Bad_Opcode }, |
||
7877 | /* 28 */ |
||
7878 | { Bad_Opcode }, |
||
7879 | { Bad_Opcode }, |
||
7880 | { Bad_Opcode }, |
||
7881 | { Bad_Opcode }, |
||
7882 | { Bad_Opcode }, |
||
7883 | { Bad_Opcode }, |
||
7884 | { Bad_Opcode }, |
||
7885 | { Bad_Opcode }, |
||
7886 | /* 30 */ |
||
7887 | { Bad_Opcode }, |
||
7888 | { Bad_Opcode }, |
||
7889 | { Bad_Opcode }, |
||
7890 | { Bad_Opcode }, |
||
7891 | { Bad_Opcode }, |
||
7892 | { Bad_Opcode }, |
||
7893 | { Bad_Opcode }, |
||
7894 | { Bad_Opcode }, |
||
7895 | /* 38 */ |
||
7896 | { Bad_Opcode }, |
||
7897 | { Bad_Opcode }, |
||
7898 | { Bad_Opcode }, |
||
7899 | { Bad_Opcode }, |
||
7900 | { Bad_Opcode }, |
||
7901 | { Bad_Opcode }, |
||
7902 | { Bad_Opcode }, |
||
7903 | { Bad_Opcode }, |
||
7904 | /* 40 */ |
||
7905 | { Bad_Opcode }, |
||
7906 | { Bad_Opcode }, |
||
7907 | { Bad_Opcode }, |
||
7908 | { Bad_Opcode }, |
||
7909 | { Bad_Opcode }, |
||
7910 | { Bad_Opcode }, |
||
7911 | { Bad_Opcode }, |
||
7912 | { Bad_Opcode }, |
||
7913 | /* 48 */ |
||
7914 | { Bad_Opcode }, |
||
7915 | { Bad_Opcode }, |
||
7916 | { Bad_Opcode }, |
||
7917 | { Bad_Opcode }, |
||
7918 | { Bad_Opcode }, |
||
7919 | { Bad_Opcode }, |
||
7920 | { Bad_Opcode }, |
||
7921 | { Bad_Opcode }, |
||
7922 | /* 50 */ |
||
7923 | { Bad_Opcode }, |
||
7924 | { Bad_Opcode }, |
||
7925 | { Bad_Opcode }, |
||
7926 | { Bad_Opcode }, |
||
7927 | { Bad_Opcode }, |
||
7928 | { Bad_Opcode }, |
||
7929 | { Bad_Opcode }, |
||
7930 | { Bad_Opcode }, |
||
7931 | /* 58 */ |
||
7932 | { Bad_Opcode }, |
||
7933 | { Bad_Opcode }, |
||
7934 | { Bad_Opcode }, |
||
7935 | { Bad_Opcode }, |
||
7936 | { Bad_Opcode }, |
||
7937 | { Bad_Opcode }, |
||
7938 | { Bad_Opcode }, |
||
7939 | { Bad_Opcode }, |
||
7940 | /* 60 */ |
||
7941 | { Bad_Opcode }, |
||
7942 | { Bad_Opcode }, |
||
7943 | { Bad_Opcode }, |
||
7944 | { Bad_Opcode }, |
||
7945 | { Bad_Opcode }, |
||
7946 | { Bad_Opcode }, |
||
7947 | { Bad_Opcode }, |
||
7948 | { Bad_Opcode }, |
||
7949 | /* 68 */ |
||
7950 | { Bad_Opcode }, |
||
7951 | { Bad_Opcode }, |
||
7952 | { Bad_Opcode }, |
||
7953 | { Bad_Opcode }, |
||
7954 | { Bad_Opcode }, |
||
7955 | { Bad_Opcode }, |
||
7956 | { Bad_Opcode }, |
||
7957 | { Bad_Opcode }, |
||
7958 | /* 70 */ |
||
7959 | { Bad_Opcode }, |
||
7960 | { Bad_Opcode }, |
||
7961 | { Bad_Opcode }, |
||
7962 | { Bad_Opcode }, |
||
7963 | { Bad_Opcode }, |
||
7964 | { Bad_Opcode }, |
||
7965 | { Bad_Opcode }, |
||
7966 | { Bad_Opcode }, |
||
7967 | /* 78 */ |
||
7968 | { Bad_Opcode }, |
||
7969 | { Bad_Opcode }, |
||
7970 | { Bad_Opcode }, |
||
7971 | { Bad_Opcode }, |
||
7972 | { Bad_Opcode }, |
||
7973 | { Bad_Opcode }, |
||
7974 | { Bad_Opcode }, |
||
7975 | { Bad_Opcode }, |
||
7976 | /* 80 */ |
||
7977 | { Bad_Opcode }, |
||
7978 | { Bad_Opcode }, |
||
7979 | { Bad_Opcode }, |
||
7980 | { Bad_Opcode }, |
||
7981 | { Bad_Opcode }, |
||
6324 | serge | 7982 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7983 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
7984 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
5221 | serge | 7985 | /* 88 */ |
7986 | { Bad_Opcode }, |
||
7987 | { Bad_Opcode }, |
||
7988 | { Bad_Opcode }, |
||
7989 | { Bad_Opcode }, |
||
7990 | { Bad_Opcode }, |
||
7991 | { Bad_Opcode }, |
||
6324 | serge | 7992 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7993 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
5221 | serge | 7994 | /* 90 */ |
7995 | { Bad_Opcode }, |
||
7996 | { Bad_Opcode }, |
||
7997 | { Bad_Opcode }, |
||
7998 | { Bad_Opcode }, |
||
7999 | { Bad_Opcode }, |
||
6324 | serge | 8000 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8001 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
8002 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
5221 | serge | 8003 | /* 98 */ |
8004 | { Bad_Opcode }, |
||
8005 | { Bad_Opcode }, |
||
8006 | { Bad_Opcode }, |
||
8007 | { Bad_Opcode }, |
||
8008 | { Bad_Opcode }, |
||
8009 | { Bad_Opcode }, |
||
6324 | serge | 8010 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8011 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
5221 | serge | 8012 | /* a0 */ |
8013 | { Bad_Opcode }, |
||
8014 | { Bad_Opcode }, |
||
6324 | serge | 8015 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8016 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
||
5221 | serge | 8017 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, |
||
6324 | serge | 8019 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 8020 | { Bad_Opcode }, |
8021 | /* a8 */ |
||
8022 | { Bad_Opcode }, |
||
8023 | { Bad_Opcode }, |
||
8024 | { Bad_Opcode }, |
||
8025 | { Bad_Opcode }, |
||
8026 | { Bad_Opcode }, |
||
8027 | { Bad_Opcode }, |
||
8028 | { Bad_Opcode }, |
||
8029 | { Bad_Opcode }, |
||
8030 | /* b0 */ |
||
8031 | { Bad_Opcode }, |
||
8032 | { Bad_Opcode }, |
||
8033 | { Bad_Opcode }, |
||
8034 | { Bad_Opcode }, |
||
8035 | { Bad_Opcode }, |
||
8036 | { Bad_Opcode }, |
||
6324 | serge | 8037 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
5221 | serge | 8038 | { Bad_Opcode }, |
8039 | /* b8 */ |
||
8040 | { Bad_Opcode }, |
||
8041 | { Bad_Opcode }, |
||
8042 | { Bad_Opcode }, |
||
8043 | { Bad_Opcode }, |
||
8044 | { Bad_Opcode }, |
||
8045 | { Bad_Opcode }, |
||
8046 | { Bad_Opcode }, |
||
8047 | { Bad_Opcode }, |
||
8048 | /* c0 */ |
||
6324 | serge | 8049 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
8050 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, |
||
8051 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, |
||
8052 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, |
||
5221 | serge | 8053 | { Bad_Opcode }, |
8054 | { Bad_Opcode }, |
||
8055 | { Bad_Opcode }, |
||
8056 | { Bad_Opcode }, |
||
8057 | /* c8 */ |
||
8058 | { Bad_Opcode }, |
||
8059 | { Bad_Opcode }, |
||
8060 | { Bad_Opcode }, |
||
8061 | { Bad_Opcode }, |
||
8062 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
||
8063 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, |
||
8064 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, |
||
8065 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, |
||
8066 | /* d0 */ |
||
8067 | { Bad_Opcode }, |
||
8068 | { Bad_Opcode }, |
||
8069 | { Bad_Opcode }, |
||
8070 | { Bad_Opcode }, |
||
8071 | { Bad_Opcode }, |
||
8072 | { Bad_Opcode }, |
||
8073 | { Bad_Opcode }, |
||
8074 | { Bad_Opcode }, |
||
8075 | /* d8 */ |
||
8076 | { Bad_Opcode }, |
||
8077 | { Bad_Opcode }, |
||
8078 | { Bad_Opcode }, |
||
8079 | { Bad_Opcode }, |
||
8080 | { Bad_Opcode }, |
||
8081 | { Bad_Opcode }, |
||
8082 | { Bad_Opcode }, |
||
8083 | { Bad_Opcode }, |
||
8084 | /* e0 */ |
||
8085 | { Bad_Opcode }, |
||
8086 | { Bad_Opcode }, |
||
8087 | { Bad_Opcode }, |
||
8088 | { Bad_Opcode }, |
||
8089 | { Bad_Opcode }, |
||
8090 | { Bad_Opcode }, |
||
8091 | { Bad_Opcode }, |
||
8092 | { Bad_Opcode }, |
||
8093 | /* e8 */ |
||
8094 | { Bad_Opcode }, |
||
8095 | { Bad_Opcode }, |
||
8096 | { Bad_Opcode }, |
||
8097 | { Bad_Opcode }, |
||
8098 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
||
8099 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, |
||
8100 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, |
||
8101 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, |
||
8102 | /* f0 */ |
||
8103 | { Bad_Opcode }, |
||
8104 | { Bad_Opcode }, |
||
8105 | { Bad_Opcode }, |
||
8106 | { Bad_Opcode }, |
||
8107 | { Bad_Opcode }, |
||
8108 | { Bad_Opcode }, |
||
8109 | { Bad_Opcode }, |
||
8110 | { Bad_Opcode }, |
||
8111 | /* f8 */ |
||
8112 | { Bad_Opcode }, |
||
8113 | { Bad_Opcode }, |
||
8114 | { Bad_Opcode }, |
||
8115 | { Bad_Opcode }, |
||
8116 | { Bad_Opcode }, |
||
8117 | { Bad_Opcode }, |
||
8118 | { Bad_Opcode }, |
||
8119 | { Bad_Opcode }, |
||
8120 | }, |
||
8121 | /* XOP_09 */ |
||
8122 | { |
||
8123 | /* 00 */ |
||
8124 | { Bad_Opcode }, |
||
8125 | { REG_TABLE (REG_XOP_TBM_01) }, |
||
8126 | { REG_TABLE (REG_XOP_TBM_02) }, |
||
8127 | { Bad_Opcode }, |
||
8128 | { Bad_Opcode }, |
||
8129 | { Bad_Opcode }, |
||
8130 | { Bad_Opcode }, |
||
8131 | { Bad_Opcode }, |
||
8132 | /* 08 */ |
||
8133 | { Bad_Opcode }, |
||
8134 | { Bad_Opcode }, |
||
8135 | { Bad_Opcode }, |
||
8136 | { Bad_Opcode }, |
||
8137 | { Bad_Opcode }, |
||
8138 | { Bad_Opcode }, |
||
8139 | { Bad_Opcode }, |
||
8140 | { Bad_Opcode }, |
||
8141 | /* 10 */ |
||
8142 | { Bad_Opcode }, |
||
8143 | { Bad_Opcode }, |
||
8144 | { REG_TABLE (REG_XOP_LWPCB) }, |
||
8145 | { Bad_Opcode }, |
||
8146 | { Bad_Opcode }, |
||
8147 | { Bad_Opcode }, |
||
8148 | { Bad_Opcode }, |
||
8149 | { Bad_Opcode }, |
||
8150 | /* 18 */ |
||
8151 | { Bad_Opcode }, |
||
8152 | { Bad_Opcode }, |
||
8153 | { Bad_Opcode }, |
||
8154 | { Bad_Opcode }, |
||
8155 | { Bad_Opcode }, |
||
8156 | { Bad_Opcode }, |
||
8157 | { Bad_Opcode }, |
||
8158 | { Bad_Opcode }, |
||
8159 | /* 20 */ |
||
8160 | { Bad_Opcode }, |
||
8161 | { Bad_Opcode }, |
||
8162 | { Bad_Opcode }, |
||
8163 | { Bad_Opcode }, |
||
8164 | { Bad_Opcode }, |
||
8165 | { Bad_Opcode }, |
||
8166 | { Bad_Opcode }, |
||
8167 | { Bad_Opcode }, |
||
8168 | /* 28 */ |
||
8169 | { Bad_Opcode }, |
||
8170 | { Bad_Opcode }, |
||
8171 | { Bad_Opcode }, |
||
8172 | { Bad_Opcode }, |
||
8173 | { Bad_Opcode }, |
||
8174 | { Bad_Opcode }, |
||
8175 | { Bad_Opcode }, |
||
8176 | { Bad_Opcode }, |
||
8177 | /* 30 */ |
||
8178 | { Bad_Opcode }, |
||
8179 | { Bad_Opcode }, |
||
8180 | { Bad_Opcode }, |
||
8181 | { Bad_Opcode }, |
||
8182 | { Bad_Opcode }, |
||
8183 | { Bad_Opcode }, |
||
8184 | { Bad_Opcode }, |
||
8185 | { Bad_Opcode }, |
||
8186 | /* 38 */ |
||
8187 | { Bad_Opcode }, |
||
8188 | { Bad_Opcode }, |
||
8189 | { Bad_Opcode }, |
||
8190 | { Bad_Opcode }, |
||
8191 | { Bad_Opcode }, |
||
8192 | { Bad_Opcode }, |
||
8193 | { Bad_Opcode }, |
||
8194 | { Bad_Opcode }, |
||
8195 | /* 40 */ |
||
8196 | { Bad_Opcode }, |
||
8197 | { Bad_Opcode }, |
||
8198 | { Bad_Opcode }, |
||
8199 | { Bad_Opcode }, |
||
8200 | { Bad_Opcode }, |
||
8201 | { Bad_Opcode }, |
||
8202 | { Bad_Opcode }, |
||
8203 | { Bad_Opcode }, |
||
8204 | /* 48 */ |
||
8205 | { Bad_Opcode }, |
||
8206 | { Bad_Opcode }, |
||
8207 | { Bad_Opcode }, |
||
8208 | { Bad_Opcode }, |
||
8209 | { Bad_Opcode }, |
||
8210 | { Bad_Opcode }, |
||
8211 | { Bad_Opcode }, |
||
8212 | { Bad_Opcode }, |
||
8213 | /* 50 */ |
||
8214 | { Bad_Opcode }, |
||
8215 | { Bad_Opcode }, |
||
8216 | { Bad_Opcode }, |
||
8217 | { Bad_Opcode }, |
||
8218 | { Bad_Opcode }, |
||
8219 | { Bad_Opcode }, |
||
8220 | { Bad_Opcode }, |
||
8221 | { Bad_Opcode }, |
||
8222 | /* 58 */ |
||
8223 | { Bad_Opcode }, |
||
8224 | { Bad_Opcode }, |
||
8225 | { Bad_Opcode }, |
||
8226 | { Bad_Opcode }, |
||
8227 | { Bad_Opcode }, |
||
8228 | { Bad_Opcode }, |
||
8229 | { Bad_Opcode }, |
||
8230 | { Bad_Opcode }, |
||
8231 | /* 60 */ |
||
8232 | { Bad_Opcode }, |
||
8233 | { Bad_Opcode }, |
||
8234 | { Bad_Opcode }, |
||
8235 | { Bad_Opcode }, |
||
8236 | { Bad_Opcode }, |
||
8237 | { Bad_Opcode }, |
||
8238 | { Bad_Opcode }, |
||
8239 | { Bad_Opcode }, |
||
8240 | /* 68 */ |
||
8241 | { Bad_Opcode }, |
||
8242 | { Bad_Opcode }, |
||
8243 | { Bad_Opcode }, |
||
8244 | { Bad_Opcode }, |
||
8245 | { Bad_Opcode }, |
||
8246 | { Bad_Opcode }, |
||
8247 | { Bad_Opcode }, |
||
8248 | { Bad_Opcode }, |
||
8249 | /* 70 */ |
||
8250 | { Bad_Opcode }, |
||
8251 | { Bad_Opcode }, |
||
8252 | { Bad_Opcode }, |
||
8253 | { Bad_Opcode }, |
||
8254 | { Bad_Opcode }, |
||
8255 | { Bad_Opcode }, |
||
8256 | { Bad_Opcode }, |
||
8257 | { Bad_Opcode }, |
||
8258 | /* 78 */ |
||
8259 | { Bad_Opcode }, |
||
8260 | { Bad_Opcode }, |
||
8261 | { Bad_Opcode }, |
||
8262 | { Bad_Opcode }, |
||
8263 | { Bad_Opcode }, |
||
8264 | { Bad_Opcode }, |
||
8265 | { Bad_Opcode }, |
||
8266 | { Bad_Opcode }, |
||
8267 | /* 80 */ |
||
8268 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
||
8269 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, |
||
6324 | serge | 8270 | { "vfrczss", { XM, EXd }, 0 }, |
8271 | { "vfrczsd", { XM, EXq }, 0 }, |
||
5221 | serge | 8272 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, |
||
8274 | { Bad_Opcode }, |
||
8275 | { Bad_Opcode }, |
||
8276 | /* 88 */ |
||
8277 | { Bad_Opcode }, |
||
8278 | { Bad_Opcode }, |
||
8279 | { Bad_Opcode }, |
||
8280 | { Bad_Opcode }, |
||
8281 | { Bad_Opcode }, |
||
8282 | { Bad_Opcode }, |
||
8283 | { Bad_Opcode }, |
||
8284 | { Bad_Opcode }, |
||
8285 | /* 90 */ |
||
6324 | serge | 8286 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8287 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8288 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8289 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8290 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8291 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8292 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8293 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
5221 | serge | 8294 | /* 98 */ |
6324 | serge | 8295 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8296 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8297 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
8298 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
||
5221 | serge | 8299 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, |
||
8301 | { Bad_Opcode }, |
||
8302 | { Bad_Opcode }, |
||
8303 | /* a0 */ |
||
8304 | { Bad_Opcode }, |
||
8305 | { Bad_Opcode }, |
||
8306 | { Bad_Opcode }, |
||
8307 | { Bad_Opcode }, |
||
8308 | { Bad_Opcode }, |
||
8309 | { Bad_Opcode }, |
||
8310 | { Bad_Opcode }, |
||
8311 | { Bad_Opcode }, |
||
8312 | /* a8 */ |
||
8313 | { Bad_Opcode }, |
||
8314 | { Bad_Opcode }, |
||
8315 | { Bad_Opcode }, |
||
8316 | { Bad_Opcode }, |
||
8317 | { Bad_Opcode }, |
||
8318 | { Bad_Opcode }, |
||
8319 | { Bad_Opcode }, |
||
8320 | { Bad_Opcode }, |
||
8321 | /* b0 */ |
||
8322 | { Bad_Opcode }, |
||
8323 | { Bad_Opcode }, |
||
8324 | { Bad_Opcode }, |
||
8325 | { Bad_Opcode }, |
||
8326 | { Bad_Opcode }, |
||
8327 | { Bad_Opcode }, |
||
8328 | { Bad_Opcode }, |
||
8329 | { Bad_Opcode }, |
||
8330 | /* b8 */ |
||
8331 | { Bad_Opcode }, |
||
8332 | { Bad_Opcode }, |
||
8333 | { Bad_Opcode }, |
||
8334 | { Bad_Opcode }, |
||
8335 | { Bad_Opcode }, |
||
8336 | { Bad_Opcode }, |
||
8337 | { Bad_Opcode }, |
||
8338 | { Bad_Opcode }, |
||
8339 | /* c0 */ |
||
8340 | { Bad_Opcode }, |
||
6324 | serge | 8341 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8342 | { "vphaddbd", { XM, EXxmm }, 0 }, |
||
8343 | { "vphaddbq", { XM, EXxmm }, 0 }, |
||
5221 | serge | 8344 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, |
||
6324 | serge | 8346 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8347 | { "vphaddwq", { XM, EXxmm }, 0 }, |
||
5221 | serge | 8348 | /* c8 */ |
8349 | { Bad_Opcode }, |
||
8350 | { Bad_Opcode }, |
||
8351 | { Bad_Opcode }, |
||
6324 | serge | 8352 | { "vphadddq", { XM, EXxmm }, 0 }, |
5221 | serge | 8353 | { Bad_Opcode }, |
8354 | { Bad_Opcode }, |
||
8355 | { Bad_Opcode }, |
||
8356 | { Bad_Opcode }, |
||
8357 | /* d0 */ |
||
8358 | { Bad_Opcode }, |
||
6324 | serge | 8359 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8360 | { "vphaddubd", { XM, EXxmm }, 0 }, |
||
8361 | { "vphaddubq", { XM, EXxmm }, 0 }, |
||
5221 | serge | 8362 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, |
||
6324 | serge | 8364 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8365 | { "vphadduwq", { XM, EXxmm }, 0 }, |
||
5221 | serge | 8366 | /* d8 */ |
8367 | { Bad_Opcode }, |
||
8368 | { Bad_Opcode }, |
||
8369 | { Bad_Opcode }, |
||
6324 | serge | 8370 | { "vphaddudq", { XM, EXxmm }, 0 }, |
5221 | serge | 8371 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, |
||
8373 | { Bad_Opcode }, |
||
8374 | { Bad_Opcode }, |
||
8375 | /* e0 */ |
||
8376 | { Bad_Opcode }, |
||
6324 | serge | 8377 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8378 | { "vphsubwd", { XM, EXxmm }, 0 }, |
||
8379 | { "vphsubdq", { XM, EXxmm }, 0 }, |
||
5221 | serge | 8380 | { Bad_Opcode }, |
8381 | { Bad_Opcode }, |
||
8382 | { Bad_Opcode }, |
||
8383 | { Bad_Opcode }, |
||
8384 | /* e8 */ |
||
8385 | { Bad_Opcode }, |
||
8386 | { Bad_Opcode }, |
||
8387 | { Bad_Opcode }, |
||
8388 | { Bad_Opcode }, |
||
8389 | { Bad_Opcode }, |
||
8390 | { Bad_Opcode }, |
||
8391 | { Bad_Opcode }, |
||
8392 | { Bad_Opcode }, |
||
8393 | /* f0 */ |
||
8394 | { Bad_Opcode }, |
||
8395 | { Bad_Opcode }, |
||
8396 | { Bad_Opcode }, |
||
8397 | { Bad_Opcode }, |
||
8398 | { Bad_Opcode }, |
||
8399 | { Bad_Opcode }, |
||
8400 | { Bad_Opcode }, |
||
8401 | { Bad_Opcode }, |
||
8402 | /* f8 */ |
||
8403 | { Bad_Opcode }, |
||
8404 | { Bad_Opcode }, |
||
8405 | { Bad_Opcode }, |
||
8406 | { Bad_Opcode }, |
||
8407 | { Bad_Opcode }, |
||
8408 | { Bad_Opcode }, |
||
8409 | { Bad_Opcode }, |
||
8410 | { Bad_Opcode }, |
||
8411 | }, |
||
8412 | /* XOP_0A */ |
||
8413 | { |
||
8414 | /* 00 */ |
||
8415 | { Bad_Opcode }, |
||
8416 | { Bad_Opcode }, |
||
8417 | { Bad_Opcode }, |
||
8418 | { Bad_Opcode }, |
||
8419 | { Bad_Opcode }, |
||
8420 | { Bad_Opcode }, |
||
8421 | { Bad_Opcode }, |
||
8422 | { Bad_Opcode }, |
||
8423 | /* 08 */ |
||
8424 | { Bad_Opcode }, |
||
8425 | { Bad_Opcode }, |
||
8426 | { Bad_Opcode }, |
||
8427 | { Bad_Opcode }, |
||
8428 | { Bad_Opcode }, |
||
8429 | { Bad_Opcode }, |
||
8430 | { Bad_Opcode }, |
||
8431 | { Bad_Opcode }, |
||
8432 | /* 10 */ |
||
6324 | serge | 8433 | { "bextr", { Gv, Ev, Iq }, 0 }, |
5221 | serge | 8434 | { Bad_Opcode }, |
8435 | { REG_TABLE (REG_XOP_LWP) }, |
||
8436 | { Bad_Opcode }, |
||
8437 | { Bad_Opcode }, |
||
8438 | { Bad_Opcode }, |
||
8439 | { Bad_Opcode }, |
||
8440 | { Bad_Opcode }, |
||
8441 | /* 18 */ |
||
8442 | { Bad_Opcode }, |
||
8443 | { Bad_Opcode }, |
||
8444 | { Bad_Opcode }, |
||
8445 | { Bad_Opcode }, |
||
8446 | { Bad_Opcode }, |
||
8447 | { Bad_Opcode }, |
||
8448 | { Bad_Opcode }, |
||
8449 | { Bad_Opcode }, |
||
8450 | /* 20 */ |
||
8451 | { Bad_Opcode }, |
||
8452 | { Bad_Opcode }, |
||
8453 | { Bad_Opcode }, |
||
8454 | { Bad_Opcode }, |
||
8455 | { Bad_Opcode }, |
||
8456 | { Bad_Opcode }, |
||
8457 | { Bad_Opcode }, |
||
8458 | { Bad_Opcode }, |
||
8459 | /* 28 */ |
||
8460 | { Bad_Opcode }, |
||
8461 | { Bad_Opcode }, |
||
8462 | { Bad_Opcode }, |
||
8463 | { Bad_Opcode }, |
||
8464 | { Bad_Opcode }, |
||
8465 | { Bad_Opcode }, |
||
8466 | { Bad_Opcode }, |
||
8467 | { Bad_Opcode }, |
||
8468 | /* 30 */ |
||
8469 | { Bad_Opcode }, |
||
8470 | { Bad_Opcode }, |
||
8471 | { Bad_Opcode }, |
||
8472 | { Bad_Opcode }, |
||
8473 | { Bad_Opcode }, |
||
8474 | { Bad_Opcode }, |
||
8475 | { Bad_Opcode }, |
||
8476 | { Bad_Opcode }, |
||
8477 | /* 38 */ |
||
8478 | { Bad_Opcode }, |
||
8479 | { Bad_Opcode }, |
||
8480 | { Bad_Opcode }, |
||
8481 | { Bad_Opcode }, |
||
8482 | { Bad_Opcode }, |
||
8483 | { Bad_Opcode }, |
||
8484 | { Bad_Opcode }, |
||
8485 | { Bad_Opcode }, |
||
8486 | /* 40 */ |
||
8487 | { Bad_Opcode }, |
||
8488 | { Bad_Opcode }, |
||
8489 | { Bad_Opcode }, |
||
8490 | { Bad_Opcode }, |
||
8491 | { Bad_Opcode }, |
||
8492 | { Bad_Opcode }, |
||
8493 | { Bad_Opcode }, |
||
8494 | { Bad_Opcode }, |
||
8495 | /* 48 */ |
||
8496 | { Bad_Opcode }, |
||
8497 | { Bad_Opcode }, |
||
8498 | { Bad_Opcode }, |
||
8499 | { Bad_Opcode }, |
||
8500 | { Bad_Opcode }, |
||
8501 | { Bad_Opcode }, |
||
8502 | { Bad_Opcode }, |
||
8503 | { Bad_Opcode }, |
||
8504 | /* 50 */ |
||
8505 | { Bad_Opcode }, |
||
8506 | { Bad_Opcode }, |
||
8507 | { Bad_Opcode }, |
||
8508 | { Bad_Opcode }, |
||
8509 | { Bad_Opcode }, |
||
8510 | { Bad_Opcode }, |
||
8511 | { Bad_Opcode }, |
||
8512 | { Bad_Opcode }, |
||
8513 | /* 58 */ |
||
8514 | { Bad_Opcode }, |
||
8515 | { Bad_Opcode }, |
||
8516 | { Bad_Opcode }, |
||
8517 | { Bad_Opcode }, |
||
8518 | { Bad_Opcode }, |
||
8519 | { Bad_Opcode }, |
||
8520 | { Bad_Opcode }, |
||
8521 | { Bad_Opcode }, |
||
8522 | /* 60 */ |
||
8523 | { Bad_Opcode }, |
||
8524 | { Bad_Opcode }, |
||
8525 | { Bad_Opcode }, |
||
8526 | { Bad_Opcode }, |
||
8527 | { Bad_Opcode }, |
||
8528 | { Bad_Opcode }, |
||
8529 | { Bad_Opcode }, |
||
8530 | { Bad_Opcode }, |
||
8531 | /* 68 */ |
||
8532 | { Bad_Opcode }, |
||
8533 | { Bad_Opcode }, |
||
8534 | { Bad_Opcode }, |
||
8535 | { Bad_Opcode }, |
||
8536 | { Bad_Opcode }, |
||
8537 | { Bad_Opcode }, |
||
8538 | { Bad_Opcode }, |
||
8539 | { Bad_Opcode }, |
||
8540 | /* 70 */ |
||
8541 | { Bad_Opcode }, |
||
8542 | { Bad_Opcode }, |
||
8543 | { Bad_Opcode }, |
||
8544 | { Bad_Opcode }, |
||
8545 | { Bad_Opcode }, |
||
8546 | { Bad_Opcode }, |
||
8547 | { Bad_Opcode }, |
||
8548 | { Bad_Opcode }, |
||
8549 | /* 78 */ |
||
8550 | { Bad_Opcode }, |
||
8551 | { Bad_Opcode }, |
||
8552 | { Bad_Opcode }, |
||
8553 | { Bad_Opcode }, |
||
8554 | { Bad_Opcode }, |
||
8555 | { Bad_Opcode }, |
||
8556 | { Bad_Opcode }, |
||
8557 | { Bad_Opcode }, |
||
8558 | /* 80 */ |
||
8559 | { Bad_Opcode }, |
||
8560 | { Bad_Opcode }, |
||
8561 | { Bad_Opcode }, |
||
8562 | { Bad_Opcode }, |
||
8563 | { Bad_Opcode }, |
||
8564 | { Bad_Opcode }, |
||
8565 | { Bad_Opcode }, |
||
8566 | { Bad_Opcode }, |
||
8567 | /* 88 */ |
||
8568 | { Bad_Opcode }, |
||
8569 | { Bad_Opcode }, |
||
8570 | { Bad_Opcode }, |
||
8571 | { Bad_Opcode }, |
||
8572 | { Bad_Opcode }, |
||
8573 | { Bad_Opcode }, |
||
8574 | { Bad_Opcode }, |
||
8575 | { Bad_Opcode }, |
||
8576 | /* 90 */ |
||
8577 | { Bad_Opcode }, |
||
8578 | { Bad_Opcode }, |
||
8579 | { Bad_Opcode }, |
||
8580 | { Bad_Opcode }, |
||
8581 | { Bad_Opcode }, |
||
8582 | { Bad_Opcode }, |
||
8583 | { Bad_Opcode }, |
||
8584 | { Bad_Opcode }, |
||
8585 | /* 98 */ |
||
8586 | { Bad_Opcode }, |
||
8587 | { Bad_Opcode }, |
||
8588 | { Bad_Opcode }, |
||
8589 | { Bad_Opcode }, |
||
8590 | { Bad_Opcode }, |
||
8591 | { Bad_Opcode }, |
||
8592 | { Bad_Opcode }, |
||
8593 | { Bad_Opcode }, |
||
8594 | /* a0 */ |
||
8595 | { Bad_Opcode }, |
||
8596 | { Bad_Opcode }, |
||
8597 | { Bad_Opcode }, |
||
8598 | { Bad_Opcode }, |
||
8599 | { Bad_Opcode }, |
||
8600 | { Bad_Opcode }, |
||
8601 | { Bad_Opcode }, |
||
8602 | { Bad_Opcode }, |
||
8603 | /* a8 */ |
||
8604 | { Bad_Opcode }, |
||
8605 | { Bad_Opcode }, |
||
8606 | { Bad_Opcode }, |
||
8607 | { Bad_Opcode }, |
||
8608 | { Bad_Opcode }, |
||
8609 | { Bad_Opcode }, |
||
8610 | { Bad_Opcode }, |
||
8611 | { Bad_Opcode }, |
||
8612 | /* b0 */ |
||
8613 | { Bad_Opcode }, |
||
8614 | { Bad_Opcode }, |
||
8615 | { Bad_Opcode }, |
||
8616 | { Bad_Opcode }, |
||
8617 | { Bad_Opcode }, |
||
8618 | { Bad_Opcode }, |
||
8619 | { Bad_Opcode }, |
||
8620 | { Bad_Opcode }, |
||
8621 | /* b8 */ |
||
8622 | { Bad_Opcode }, |
||
8623 | { Bad_Opcode }, |
||
8624 | { Bad_Opcode }, |
||
8625 | { Bad_Opcode }, |
||
8626 | { Bad_Opcode }, |
||
8627 | { Bad_Opcode }, |
||
8628 | { Bad_Opcode }, |
||
8629 | { Bad_Opcode }, |
||
8630 | /* c0 */ |
||
8631 | { Bad_Opcode }, |
||
8632 | { Bad_Opcode }, |
||
8633 | { Bad_Opcode }, |
||
8634 | { Bad_Opcode }, |
||
8635 | { Bad_Opcode }, |
||
8636 | { Bad_Opcode }, |
||
8637 | { Bad_Opcode }, |
||
8638 | { Bad_Opcode }, |
||
8639 | /* c8 */ |
||
8640 | { Bad_Opcode }, |
||
8641 | { Bad_Opcode }, |
||
8642 | { Bad_Opcode }, |
||
8643 | { Bad_Opcode }, |
||
8644 | { Bad_Opcode }, |
||
8645 | { Bad_Opcode }, |
||
8646 | { Bad_Opcode }, |
||
8647 | { Bad_Opcode }, |
||
8648 | /* d0 */ |
||
8649 | { Bad_Opcode }, |
||
8650 | { Bad_Opcode }, |
||
8651 | { Bad_Opcode }, |
||
8652 | { Bad_Opcode }, |
||
8653 | { Bad_Opcode }, |
||
8654 | { Bad_Opcode }, |
||
8655 | { Bad_Opcode }, |
||
8656 | { Bad_Opcode }, |
||
8657 | /* d8 */ |
||
8658 | { Bad_Opcode }, |
||
8659 | { Bad_Opcode }, |
||
8660 | { Bad_Opcode }, |
||
8661 | { Bad_Opcode }, |
||
8662 | { Bad_Opcode }, |
||
8663 | { Bad_Opcode }, |
||
8664 | { Bad_Opcode }, |
||
8665 | { Bad_Opcode }, |
||
8666 | /* e0 */ |
||
8667 | { Bad_Opcode }, |
||
8668 | { Bad_Opcode }, |
||
8669 | { Bad_Opcode }, |
||
8670 | { Bad_Opcode }, |
||
8671 | { Bad_Opcode }, |
||
8672 | { Bad_Opcode }, |
||
8673 | { Bad_Opcode }, |
||
8674 | { Bad_Opcode }, |
||
8675 | /* e8 */ |
||
8676 | { Bad_Opcode }, |
||
8677 | { Bad_Opcode }, |
||
8678 | { Bad_Opcode }, |
||
8679 | { Bad_Opcode }, |
||
8680 | { Bad_Opcode }, |
||
8681 | { Bad_Opcode }, |
||
8682 | { Bad_Opcode }, |
||
8683 | { Bad_Opcode }, |
||
8684 | /* f0 */ |
||
8685 | { Bad_Opcode }, |
||
8686 | { Bad_Opcode }, |
||
8687 | { Bad_Opcode }, |
||
8688 | { Bad_Opcode }, |
||
8689 | { Bad_Opcode }, |
||
8690 | { Bad_Opcode }, |
||
8691 | { Bad_Opcode }, |
||
8692 | { Bad_Opcode }, |
||
8693 | /* f8 */ |
||
8694 | { Bad_Opcode }, |
||
8695 | { Bad_Opcode }, |
||
8696 | { Bad_Opcode }, |
||
8697 | { Bad_Opcode }, |
||
8698 | { Bad_Opcode }, |
||
8699 | { Bad_Opcode }, |
||
8700 | { Bad_Opcode }, |
||
8701 | { Bad_Opcode }, |
||
8702 | }, |
||
8703 | }; |
||
8704 | |||
8705 | static const struct dis386 vex_table[][256] = { |
||
8706 | /* VEX_0F */ |
||
8707 | { |
||
8708 | /* 00 */ |
||
8709 | { Bad_Opcode }, |
||
8710 | { Bad_Opcode }, |
||
8711 | { Bad_Opcode }, |
||
8712 | { Bad_Opcode }, |
||
8713 | { Bad_Opcode }, |
||
8714 | { Bad_Opcode }, |
||
8715 | { Bad_Opcode }, |
||
8716 | { Bad_Opcode }, |
||
8717 | /* 08 */ |
||
8718 | { Bad_Opcode }, |
||
8719 | { Bad_Opcode }, |
||
8720 | { Bad_Opcode }, |
||
8721 | { Bad_Opcode }, |
||
8722 | { Bad_Opcode }, |
||
8723 | { Bad_Opcode }, |
||
8724 | { Bad_Opcode }, |
||
8725 | { Bad_Opcode }, |
||
8726 | /* 10 */ |
||
8727 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
||
8728 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, |
||
8729 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, |
||
8730 | { MOD_TABLE (MOD_VEX_0F13) }, |
||
8731 | { VEX_W_TABLE (VEX_W_0F14) }, |
||
8732 | { VEX_W_TABLE (VEX_W_0F15) }, |
||
8733 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
||
8734 | { MOD_TABLE (MOD_VEX_0F17) }, |
||
8735 | /* 18 */ |
||
8736 | { Bad_Opcode }, |
||
8737 | { Bad_Opcode }, |
||
8738 | { Bad_Opcode }, |
||
8739 | { Bad_Opcode }, |
||
8740 | { Bad_Opcode }, |
||
8741 | { Bad_Opcode }, |
||
8742 | { Bad_Opcode }, |
||
8743 | { Bad_Opcode }, |
||
8744 | /* 20 */ |
||
8745 | { Bad_Opcode }, |
||
8746 | { Bad_Opcode }, |
||
8747 | { Bad_Opcode }, |
||
8748 | { Bad_Opcode }, |
||
8749 | { Bad_Opcode }, |
||
8750 | { Bad_Opcode }, |
||
8751 | { Bad_Opcode }, |
||
8752 | { Bad_Opcode }, |
||
8753 | /* 28 */ |
||
8754 | { VEX_W_TABLE (VEX_W_0F28) }, |
||
8755 | { VEX_W_TABLE (VEX_W_0F29) }, |
||
8756 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
||
8757 | { MOD_TABLE (MOD_VEX_0F2B) }, |
||
8758 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, |
||
8759 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, |
||
8760 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, |
||
8761 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, |
||
8762 | /* 30 */ |
||
8763 | { Bad_Opcode }, |
||
8764 | { Bad_Opcode }, |
||
8765 | { Bad_Opcode }, |
||
8766 | { Bad_Opcode }, |
||
8767 | { Bad_Opcode }, |
||
8768 | { Bad_Opcode }, |
||
8769 | { Bad_Opcode }, |
||
8770 | { Bad_Opcode }, |
||
8771 | /* 38 */ |
||
8772 | { Bad_Opcode }, |
||
8773 | { Bad_Opcode }, |
||
8774 | { Bad_Opcode }, |
||
8775 | { Bad_Opcode }, |
||
8776 | { Bad_Opcode }, |
||
8777 | { Bad_Opcode }, |
||
8778 | { Bad_Opcode }, |
||
8779 | { Bad_Opcode }, |
||
8780 | /* 40 */ |
||
8781 | { Bad_Opcode }, |
||
8782 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
||
8783 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, |
||
8784 | { Bad_Opcode }, |
||
8785 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
||
8786 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, |
||
8787 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, |
||
8788 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, |
||
8789 | /* 48 */ |
||
8790 | { Bad_Opcode }, |
||
8791 | { Bad_Opcode }, |
||
6324 | serge | 8792 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
5221 | serge | 8793 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
8794 | { Bad_Opcode }, |
||
8795 | { Bad_Opcode }, |
||
8796 | { Bad_Opcode }, |
||
8797 | { Bad_Opcode }, |
||
8798 | /* 50 */ |
||
8799 | { MOD_TABLE (MOD_VEX_0F50) }, |
||
8800 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, |
||
8801 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, |
||
8802 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, |
||
6324 | serge | 8803 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8804 | { "vandnpX", { XM, Vex, EXx }, 0 }, |
||
8805 | { "vorpX", { XM, Vex, EXx }, 0 }, |
||
8806 | { "vxorpX", { XM, Vex, EXx }, 0 }, |
||
5221 | serge | 8807 | /* 58 */ |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
||
8809 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, |
||
8810 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, |
||
8811 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, |
||
8812 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, |
||
8813 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, |
||
8814 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, |
||
8815 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, |
||
8816 | /* 60 */ |
||
8817 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
||
8818 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, |
||
8819 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, |
||
8820 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, |
||
8821 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, |
||
8822 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, |
||
8823 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, |
||
8824 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, |
||
8825 | /* 68 */ |
||
8826 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
||
8827 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, |
||
8828 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, |
||
8829 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, |
||
8830 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, |
||
8831 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, |
||
8832 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, |
||
8833 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
||
8834 | /* 70 */ |
||
8835 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
||
8836 | { REG_TABLE (REG_VEX_0F71) }, |
||
8837 | { REG_TABLE (REG_VEX_0F72) }, |
||
8838 | { REG_TABLE (REG_VEX_0F73) }, |
||
8839 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, |
||
8840 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, |
||
8841 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, |
||
8842 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, |
||
8843 | /* 78 */ |
||
8844 | { Bad_Opcode }, |
||
8845 | { Bad_Opcode }, |
||
8846 | { Bad_Opcode }, |
||
8847 | { Bad_Opcode }, |
||
8848 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
||
8849 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, |
||
8850 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, |
||
8851 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, |
||
8852 | /* 80 */ |
||
8853 | { Bad_Opcode }, |
||
8854 | { Bad_Opcode }, |
||
8855 | { Bad_Opcode }, |
||
8856 | { Bad_Opcode }, |
||
8857 | { Bad_Opcode }, |
||
8858 | { Bad_Opcode }, |
||
8859 | { Bad_Opcode }, |
||
8860 | { Bad_Opcode }, |
||
8861 | /* 88 */ |
||
8862 | { Bad_Opcode }, |
||
8863 | { Bad_Opcode }, |
||
8864 | { Bad_Opcode }, |
||
8865 | { Bad_Opcode }, |
||
8866 | { Bad_Opcode }, |
||
8867 | { Bad_Opcode }, |
||
8868 | { Bad_Opcode }, |
||
8869 | { Bad_Opcode }, |
||
8870 | /* 90 */ |
||
8871 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
||
8872 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, |
||
8873 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, |
||
8874 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, |
||
8875 | { Bad_Opcode }, |
||
8876 | { Bad_Opcode }, |
||
8877 | { Bad_Opcode }, |
||
8878 | { Bad_Opcode }, |
||
8879 | /* 98 */ |
||
8880 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
||
6324 | serge | 8881 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
5221 | serge | 8882 | { Bad_Opcode }, |
8883 | { Bad_Opcode }, |
||
8884 | { Bad_Opcode }, |
||
8885 | { Bad_Opcode }, |
||
8886 | { Bad_Opcode }, |
||
8887 | { Bad_Opcode }, |
||
8888 | /* a0 */ |
||
8889 | { Bad_Opcode }, |
||
8890 | { Bad_Opcode }, |
||
8891 | { Bad_Opcode }, |
||
8892 | { Bad_Opcode }, |
||
8893 | { Bad_Opcode }, |
||
8894 | { Bad_Opcode }, |
||
8895 | { Bad_Opcode }, |
||
8896 | { Bad_Opcode }, |
||
8897 | /* a8 */ |
||
8898 | { Bad_Opcode }, |
||
8899 | { Bad_Opcode }, |
||
8900 | { Bad_Opcode }, |
||
8901 | { Bad_Opcode }, |
||
8902 | { Bad_Opcode }, |
||
8903 | { Bad_Opcode }, |
||
8904 | { REG_TABLE (REG_VEX_0FAE) }, |
||
8905 | { Bad_Opcode }, |
||
8906 | /* b0 */ |
||
8907 | { Bad_Opcode }, |
||
8908 | { Bad_Opcode }, |
||
8909 | { Bad_Opcode }, |
||
8910 | { Bad_Opcode }, |
||
8911 | { Bad_Opcode }, |
||
8912 | { Bad_Opcode }, |
||
8913 | { Bad_Opcode }, |
||
8914 | { Bad_Opcode }, |
||
8915 | /* b8 */ |
||
8916 | { Bad_Opcode }, |
||
8917 | { Bad_Opcode }, |
||
8918 | { Bad_Opcode }, |
||
8919 | { Bad_Opcode }, |
||
8920 | { Bad_Opcode }, |
||
8921 | { Bad_Opcode }, |
||
8922 | { Bad_Opcode }, |
||
8923 | { Bad_Opcode }, |
||
8924 | /* c0 */ |
||
8925 | { Bad_Opcode }, |
||
8926 | { Bad_Opcode }, |
||
8927 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
||
8928 | { Bad_Opcode }, |
||
8929 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
||
8930 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, |
||
6324 | serge | 8931 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 8932 | { Bad_Opcode }, |
8933 | /* c8 */ |
||
8934 | { Bad_Opcode }, |
||
8935 | { Bad_Opcode }, |
||
8936 | { Bad_Opcode }, |
||
8937 | { Bad_Opcode }, |
||
8938 | { Bad_Opcode }, |
||
8939 | { Bad_Opcode }, |
||
8940 | { Bad_Opcode }, |
||
8941 | { Bad_Opcode }, |
||
8942 | /* d0 */ |
||
8943 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
||
8944 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, |
||
8945 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, |
||
8946 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, |
||
8947 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, |
||
8948 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, |
||
8949 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, |
||
8950 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, |
||
8951 | /* d8 */ |
||
8952 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
||
8953 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, |
||
8954 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, |
||
8955 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, |
||
8956 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, |
||
8957 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, |
||
8958 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, |
||
8959 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, |
||
8960 | /* e0 */ |
||
8961 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
||
8962 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, |
||
8963 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, |
||
8964 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, |
||
8965 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, |
||
8966 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, |
||
8967 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
||
8968 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, |
||
8969 | /* e8 */ |
||
8970 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
||
8971 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, |
||
8972 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, |
||
8973 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, |
||
8974 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, |
||
8975 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, |
||
8976 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, |
||
8977 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, |
||
8978 | /* f0 */ |
||
8979 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
||
8980 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, |
||
8981 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, |
||
8982 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, |
||
8983 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, |
||
8984 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, |
||
8985 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, |
||
8986 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, |
||
8987 | /* f8 */ |
||
8988 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
||
8989 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, |
||
8990 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, |
||
8991 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, |
||
8992 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, |
||
8993 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, |
||
8994 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, |
||
8995 | { Bad_Opcode }, |
||
8996 | }, |
||
8997 | /* VEX_0F38 */ |
||
8998 | { |
||
8999 | /* 00 */ |
||
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
||
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, |
||
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, |
||
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, |
||
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, |
||
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, |
||
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, |
||
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, |
||
9008 | /* 08 */ |
||
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
||
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, |
||
9011 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, |
||
9012 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, |
||
9013 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, |
||
9014 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, |
||
9015 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, |
||
9016 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, |
||
9017 | /* 10 */ |
||
9018 | { Bad_Opcode }, |
||
9019 | { Bad_Opcode }, |
||
9020 | { Bad_Opcode }, |
||
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
||
9022 | { Bad_Opcode }, |
||
9023 | { Bad_Opcode }, |
||
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
||
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
||
9026 | /* 18 */ |
||
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
||
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, |
||
9029 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, |
||
9030 | { Bad_Opcode }, |
||
9031 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
||
9032 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, |
||
9033 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, |
||
9034 | { Bad_Opcode }, |
||
9035 | /* 20 */ |
||
9036 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
||
9037 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, |
||
9038 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, |
||
9039 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, |
||
9040 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, |
||
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, |
||
9042 | { Bad_Opcode }, |
||
9043 | { Bad_Opcode }, |
||
9044 | /* 28 */ |
||
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
||
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, |
||
9047 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, |
||
9048 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, |
||
9049 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, |
||
9050 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, |
||
9051 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, |
||
9052 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, |
||
9053 | /* 30 */ |
||
9054 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
||
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, |
||
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, |
||
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, |
||
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, |
||
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, |
||
9060 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
||
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
||
9062 | /* 38 */ |
||
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
||
9064 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, |
||
9065 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, |
||
9066 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, |
||
9067 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, |
||
9068 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, |
||
9069 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, |
||
9070 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, |
||
9071 | /* 40 */ |
||
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
||
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, |
||
9074 | { Bad_Opcode }, |
||
9075 | { Bad_Opcode }, |
||
9076 | { Bad_Opcode }, |
||
9077 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
||
9078 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, |
||
9079 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, |
||
9080 | /* 48 */ |
||
9081 | { Bad_Opcode }, |
||
9082 | { Bad_Opcode }, |
||
9083 | { Bad_Opcode }, |
||
9084 | { Bad_Opcode }, |
||
9085 | { Bad_Opcode }, |
||
9086 | { Bad_Opcode }, |
||
9087 | { Bad_Opcode }, |
||
9088 | { Bad_Opcode }, |
||
9089 | /* 50 */ |
||
9090 | { Bad_Opcode }, |
||
9091 | { Bad_Opcode }, |
||
9092 | { Bad_Opcode }, |
||
9093 | { Bad_Opcode }, |
||
9094 | { Bad_Opcode }, |
||
9095 | { Bad_Opcode }, |
||
9096 | { Bad_Opcode }, |
||
9097 | { Bad_Opcode }, |
||
9098 | /* 58 */ |
||
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
||
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, |
||
9101 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, |
||
9102 | { Bad_Opcode }, |
||
9103 | { Bad_Opcode }, |
||
9104 | { Bad_Opcode }, |
||
9105 | { Bad_Opcode }, |
||
9106 | { Bad_Opcode }, |
||
9107 | /* 60 */ |
||
9108 | { Bad_Opcode }, |
||
9109 | { Bad_Opcode }, |
||
9110 | { Bad_Opcode }, |
||
9111 | { Bad_Opcode }, |
||
9112 | { Bad_Opcode }, |
||
9113 | { Bad_Opcode }, |
||
9114 | { Bad_Opcode }, |
||
9115 | { Bad_Opcode }, |
||
9116 | /* 68 */ |
||
9117 | { Bad_Opcode }, |
||
9118 | { Bad_Opcode }, |
||
9119 | { Bad_Opcode }, |
||
9120 | { Bad_Opcode }, |
||
9121 | { Bad_Opcode }, |
||
9122 | { Bad_Opcode }, |
||
9123 | { Bad_Opcode }, |
||
9124 | { Bad_Opcode }, |
||
9125 | /* 70 */ |
||
9126 | { Bad_Opcode }, |
||
9127 | { Bad_Opcode }, |
||
9128 | { Bad_Opcode }, |
||
9129 | { Bad_Opcode }, |
||
9130 | { Bad_Opcode }, |
||
9131 | { Bad_Opcode }, |
||
9132 | { Bad_Opcode }, |
||
9133 | { Bad_Opcode }, |
||
9134 | /* 78 */ |
||
9135 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
||
9136 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, |
||
9137 | { Bad_Opcode }, |
||
9138 | { Bad_Opcode }, |
||
9139 | { Bad_Opcode }, |
||
9140 | { Bad_Opcode }, |
||
9141 | { Bad_Opcode }, |
||
9142 | { Bad_Opcode }, |
||
9143 | /* 80 */ |
||
9144 | { Bad_Opcode }, |
||
9145 | { Bad_Opcode }, |
||
9146 | { Bad_Opcode }, |
||
9147 | { Bad_Opcode }, |
||
9148 | { Bad_Opcode }, |
||
9149 | { Bad_Opcode }, |
||
9150 | { Bad_Opcode }, |
||
9151 | { Bad_Opcode }, |
||
9152 | /* 88 */ |
||
9153 | { Bad_Opcode }, |
||
9154 | { Bad_Opcode }, |
||
9155 | { Bad_Opcode }, |
||
9156 | { Bad_Opcode }, |
||
9157 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
||
9158 | { Bad_Opcode }, |
||
9159 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
||
9160 | { Bad_Opcode }, |
||
9161 | /* 90 */ |
||
9162 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
||
9163 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, |
||
9164 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, |
||
9165 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, |
||
9166 | { Bad_Opcode }, |
||
9167 | { Bad_Opcode }, |
||
9168 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
||
9169 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, |
||
9170 | /* 98 */ |
||
9171 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
||
9172 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, |
||
9173 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, |
||
9174 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, |
||
9175 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, |
||
9176 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, |
||
9177 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, |
||
9178 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, |
||
9179 | /* a0 */ |
||
9180 | { Bad_Opcode }, |
||
9181 | { Bad_Opcode }, |
||
9182 | { Bad_Opcode }, |
||
9183 | { Bad_Opcode }, |
||
9184 | { Bad_Opcode }, |
||
9185 | { Bad_Opcode }, |
||
9186 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
||
9187 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, |
||
9188 | /* a8 */ |
||
9189 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
||
9190 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, |
||
9191 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, |
||
9192 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, |
||
9193 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, |
||
9194 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, |
||
9195 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, |
||
9196 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, |
||
9197 | /* b0 */ |
||
9198 | { Bad_Opcode }, |
||
9199 | { Bad_Opcode }, |
||
9200 | { Bad_Opcode }, |
||
9201 | { Bad_Opcode }, |
||
9202 | { Bad_Opcode }, |
||
9203 | { Bad_Opcode }, |
||
9204 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
||
9205 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, |
||
9206 | /* b8 */ |
||
9207 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
||
9208 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, |
||
9209 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, |
||
9210 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, |
||
9211 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, |
||
9212 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, |
||
9213 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, |
||
9214 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, |
||
9215 | /* c0 */ |
||
9216 | { Bad_Opcode }, |
||
9217 | { Bad_Opcode }, |
||
9218 | { Bad_Opcode }, |
||
9219 | { Bad_Opcode }, |
||
9220 | { Bad_Opcode }, |
||
9221 | { Bad_Opcode }, |
||
9222 | { Bad_Opcode }, |
||
9223 | { Bad_Opcode }, |
||
9224 | /* c8 */ |
||
9225 | { Bad_Opcode }, |
||
9226 | { Bad_Opcode }, |
||
9227 | { Bad_Opcode }, |
||
9228 | { Bad_Opcode }, |
||
9229 | { Bad_Opcode }, |
||
9230 | { Bad_Opcode }, |
||
9231 | { Bad_Opcode }, |
||
9232 | { Bad_Opcode }, |
||
9233 | /* d0 */ |
||
9234 | { Bad_Opcode }, |
||
9235 | { Bad_Opcode }, |
||
9236 | { Bad_Opcode }, |
||
9237 | { Bad_Opcode }, |
||
9238 | { Bad_Opcode }, |
||
9239 | { Bad_Opcode }, |
||
9240 | { Bad_Opcode }, |
||
9241 | { Bad_Opcode }, |
||
9242 | /* d8 */ |
||
9243 | { Bad_Opcode }, |
||
9244 | { Bad_Opcode }, |
||
9245 | { Bad_Opcode }, |
||
9246 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
||
9247 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, |
||
9248 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, |
||
9249 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, |
||
9250 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, |
||
9251 | /* e0 */ |
||
9252 | { Bad_Opcode }, |
||
9253 | { Bad_Opcode }, |
||
9254 | { Bad_Opcode }, |
||
9255 | { Bad_Opcode }, |
||
9256 | { Bad_Opcode }, |
||
9257 | { Bad_Opcode }, |
||
9258 | { Bad_Opcode }, |
||
9259 | { Bad_Opcode }, |
||
9260 | /* e8 */ |
||
9261 | { Bad_Opcode }, |
||
9262 | { Bad_Opcode }, |
||
9263 | { Bad_Opcode }, |
||
9264 | { Bad_Opcode }, |
||
9265 | { Bad_Opcode }, |
||
9266 | { Bad_Opcode }, |
||
9267 | { Bad_Opcode }, |
||
9268 | { Bad_Opcode }, |
||
9269 | /* f0 */ |
||
9270 | { Bad_Opcode }, |
||
9271 | { Bad_Opcode }, |
||
9272 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
||
9273 | { REG_TABLE (REG_VEX_0F38F3) }, |
||
9274 | { Bad_Opcode }, |
||
9275 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
||
9276 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, |
||
9277 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
||
9278 | /* f8 */ |
||
9279 | { Bad_Opcode }, |
||
9280 | { Bad_Opcode }, |
||
9281 | { Bad_Opcode }, |
||
9282 | { Bad_Opcode }, |
||
9283 | { Bad_Opcode }, |
||
9284 | { Bad_Opcode }, |
||
9285 | { Bad_Opcode }, |
||
9286 | { Bad_Opcode }, |
||
9287 | }, |
||
9288 | /* VEX_0F3A */ |
||
9289 | { |
||
9290 | /* 00 */ |
||
9291 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
||
9292 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, |
||
9293 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, |
||
9294 | { Bad_Opcode }, |
||
9295 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
||
9296 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, |
||
9297 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, |
||
9298 | { Bad_Opcode }, |
||
9299 | /* 08 */ |
||
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
||
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, |
||
9302 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, |
||
9303 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, |
||
9304 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, |
||
9305 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, |
||
9306 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, |
||
9307 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, |
||
9308 | /* 10 */ |
||
9309 | { Bad_Opcode }, |
||
9310 | { Bad_Opcode }, |
||
9311 | { Bad_Opcode }, |
||
9312 | { Bad_Opcode }, |
||
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
||
9314 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, |
||
9315 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, |
||
9316 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, |
||
9317 | /* 18 */ |
||
9318 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
||
9319 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, |
||
9320 | { Bad_Opcode }, |
||
9321 | { Bad_Opcode }, |
||
9322 | { Bad_Opcode }, |
||
9323 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
||
9324 | { Bad_Opcode }, |
||
9325 | { Bad_Opcode }, |
||
9326 | /* 20 */ |
||
9327 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
||
9328 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, |
||
9329 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, |
||
9330 | { Bad_Opcode }, |
||
9331 | { Bad_Opcode }, |
||
9332 | { Bad_Opcode }, |
||
9333 | { Bad_Opcode }, |
||
9334 | { Bad_Opcode }, |
||
9335 | /* 28 */ |
||
9336 | { Bad_Opcode }, |
||
9337 | { Bad_Opcode }, |
||
9338 | { Bad_Opcode }, |
||
9339 | { Bad_Opcode }, |
||
9340 | { Bad_Opcode }, |
||
9341 | { Bad_Opcode }, |
||
9342 | { Bad_Opcode }, |
||
9343 | { Bad_Opcode }, |
||
9344 | /* 30 */ |
||
9345 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
||
6324 | serge | 9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
5221 | serge | 9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
6324 | serge | 9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
5221 | serge | 9349 | { Bad_Opcode }, |
9350 | { Bad_Opcode }, |
||
9351 | { Bad_Opcode }, |
||
9352 | { Bad_Opcode }, |
||
9353 | /* 38 */ |
||
9354 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
||
9355 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, |
||
9356 | { Bad_Opcode }, |
||
9357 | { Bad_Opcode }, |
||
9358 | { Bad_Opcode }, |
||
9359 | { Bad_Opcode }, |
||
9360 | { Bad_Opcode }, |
||
9361 | { Bad_Opcode }, |
||
9362 | /* 40 */ |
||
9363 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
||
9364 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, |
||
9365 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, |
||
9366 | { Bad_Opcode }, |
||
9367 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
||
9368 | { Bad_Opcode }, |
||
9369 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
||
9370 | { Bad_Opcode }, |
||
9371 | /* 48 */ |
||
9372 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
||
9373 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, |
||
9374 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, |
||
9375 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, |
||
9376 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, |
||
9377 | { Bad_Opcode }, |
||
9378 | { Bad_Opcode }, |
||
9379 | { Bad_Opcode }, |
||
9380 | /* 50 */ |
||
9381 | { Bad_Opcode }, |
||
9382 | { Bad_Opcode }, |
||
9383 | { Bad_Opcode }, |
||
9384 | { Bad_Opcode }, |
||
9385 | { Bad_Opcode }, |
||
9386 | { Bad_Opcode }, |
||
9387 | { Bad_Opcode }, |
||
9388 | { Bad_Opcode }, |
||
9389 | /* 58 */ |
||
9390 | { Bad_Opcode }, |
||
9391 | { Bad_Opcode }, |
||
9392 | { Bad_Opcode }, |
||
9393 | { Bad_Opcode }, |
||
9394 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
||
9395 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, |
||
9396 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, |
||
9397 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, |
||
9398 | /* 60 */ |
||
9399 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
||
9400 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, |
||
9401 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, |
||
9402 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, |
||
9403 | { Bad_Opcode }, |
||
9404 | { Bad_Opcode }, |
||
9405 | { Bad_Opcode }, |
||
9406 | { Bad_Opcode }, |
||
9407 | /* 68 */ |
||
9408 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
||
9409 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, |
||
9410 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, |
||
9411 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, |
||
9412 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, |
||
9413 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, |
||
9414 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, |
||
9415 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, |
||
9416 | /* 70 */ |
||
9417 | { Bad_Opcode }, |
||
9418 | { Bad_Opcode }, |
||
9419 | { Bad_Opcode }, |
||
9420 | { Bad_Opcode }, |
||
9421 | { Bad_Opcode }, |
||
9422 | { Bad_Opcode }, |
||
9423 | { Bad_Opcode }, |
||
9424 | { Bad_Opcode }, |
||
9425 | /* 78 */ |
||
9426 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
||
9427 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, |
||
9428 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, |
||
9429 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, |
||
9430 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, |
||
9431 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, |
||
9432 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, |
||
9433 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, |
||
9434 | /* 80 */ |
||
9435 | { Bad_Opcode }, |
||
9436 | { Bad_Opcode }, |
||
9437 | { Bad_Opcode }, |
||
9438 | { Bad_Opcode }, |
||
9439 | { Bad_Opcode }, |
||
9440 | { Bad_Opcode }, |
||
9441 | { Bad_Opcode }, |
||
9442 | { Bad_Opcode }, |
||
9443 | /* 88 */ |
||
9444 | { Bad_Opcode }, |
||
9445 | { Bad_Opcode }, |
||
9446 | { Bad_Opcode }, |
||
9447 | { Bad_Opcode }, |
||
9448 | { Bad_Opcode }, |
||
9449 | { Bad_Opcode }, |
||
9450 | { Bad_Opcode }, |
||
9451 | { Bad_Opcode }, |
||
9452 | /* 90 */ |
||
9453 | { Bad_Opcode }, |
||
9454 | { Bad_Opcode }, |
||
9455 | { Bad_Opcode }, |
||
9456 | { Bad_Opcode }, |
||
9457 | { Bad_Opcode }, |
||
9458 | { Bad_Opcode }, |
||
9459 | { Bad_Opcode }, |
||
9460 | { Bad_Opcode }, |
||
9461 | /* 98 */ |
||
9462 | { Bad_Opcode }, |
||
9463 | { Bad_Opcode }, |
||
9464 | { Bad_Opcode }, |
||
9465 | { Bad_Opcode }, |
||
9466 | { Bad_Opcode }, |
||
9467 | { Bad_Opcode }, |
||
9468 | { Bad_Opcode }, |
||
9469 | { Bad_Opcode }, |
||
9470 | /* a0 */ |
||
9471 | { Bad_Opcode }, |
||
9472 | { Bad_Opcode }, |
||
9473 | { Bad_Opcode }, |
||
9474 | { Bad_Opcode }, |
||
9475 | { Bad_Opcode }, |
||
9476 | { Bad_Opcode }, |
||
9477 | { Bad_Opcode }, |
||
9478 | { Bad_Opcode }, |
||
9479 | /* a8 */ |
||
9480 | { Bad_Opcode }, |
||
9481 | { Bad_Opcode }, |
||
9482 | { Bad_Opcode }, |
||
9483 | { Bad_Opcode }, |
||
9484 | { Bad_Opcode }, |
||
9485 | { Bad_Opcode }, |
||
9486 | { Bad_Opcode }, |
||
9487 | { Bad_Opcode }, |
||
9488 | /* b0 */ |
||
9489 | { Bad_Opcode }, |
||
9490 | { Bad_Opcode }, |
||
9491 | { Bad_Opcode }, |
||
9492 | { Bad_Opcode }, |
||
9493 | { Bad_Opcode }, |
||
9494 | { Bad_Opcode }, |
||
9495 | { Bad_Opcode }, |
||
9496 | { Bad_Opcode }, |
||
9497 | /* b8 */ |
||
9498 | { Bad_Opcode }, |
||
9499 | { Bad_Opcode }, |
||
9500 | { Bad_Opcode }, |
||
9501 | { Bad_Opcode }, |
||
9502 | { Bad_Opcode }, |
||
9503 | { Bad_Opcode }, |
||
9504 | { Bad_Opcode }, |
||
9505 | { Bad_Opcode }, |
||
9506 | /* c0 */ |
||
9507 | { Bad_Opcode }, |
||
9508 | { Bad_Opcode }, |
||
9509 | { Bad_Opcode }, |
||
9510 | { Bad_Opcode }, |
||
9511 | { Bad_Opcode }, |
||
9512 | { Bad_Opcode }, |
||
9513 | { Bad_Opcode }, |
||
9514 | { Bad_Opcode }, |
||
9515 | /* c8 */ |
||
9516 | { Bad_Opcode }, |
||
9517 | { Bad_Opcode }, |
||
9518 | { Bad_Opcode }, |
||
9519 | { Bad_Opcode }, |
||
9520 | { Bad_Opcode }, |
||
9521 | { Bad_Opcode }, |
||
9522 | { Bad_Opcode }, |
||
9523 | { Bad_Opcode }, |
||
9524 | /* d0 */ |
||
9525 | { Bad_Opcode }, |
||
9526 | { Bad_Opcode }, |
||
9527 | { Bad_Opcode }, |
||
9528 | { Bad_Opcode }, |
||
9529 | { Bad_Opcode }, |
||
9530 | { Bad_Opcode }, |
||
9531 | { Bad_Opcode }, |
||
9532 | { Bad_Opcode }, |
||
9533 | /* d8 */ |
||
9534 | { Bad_Opcode }, |
||
9535 | { Bad_Opcode }, |
||
9536 | { Bad_Opcode }, |
||
9537 | { Bad_Opcode }, |
||
9538 | { Bad_Opcode }, |
||
9539 | { Bad_Opcode }, |
||
9540 | { Bad_Opcode }, |
||
9541 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
||
9542 | /* e0 */ |
||
9543 | { Bad_Opcode }, |
||
9544 | { Bad_Opcode }, |
||
9545 | { Bad_Opcode }, |
||
9546 | { Bad_Opcode }, |
||
9547 | { Bad_Opcode }, |
||
9548 | { Bad_Opcode }, |
||
9549 | { Bad_Opcode }, |
||
9550 | { Bad_Opcode }, |
||
9551 | /* e8 */ |
||
9552 | { Bad_Opcode }, |
||
9553 | { Bad_Opcode }, |
||
9554 | { Bad_Opcode }, |
||
9555 | { Bad_Opcode }, |
||
9556 | { Bad_Opcode }, |
||
9557 | { Bad_Opcode }, |
||
9558 | { Bad_Opcode }, |
||
9559 | { Bad_Opcode }, |
||
9560 | /* f0 */ |
||
9561 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
||
9562 | { Bad_Opcode }, |
||
9563 | { Bad_Opcode }, |
||
9564 | { Bad_Opcode }, |
||
9565 | { Bad_Opcode }, |
||
9566 | { Bad_Opcode }, |
||
9567 | { Bad_Opcode }, |
||
9568 | { Bad_Opcode }, |
||
9569 | /* f8 */ |
||
9570 | { Bad_Opcode }, |
||
9571 | { Bad_Opcode }, |
||
9572 | { Bad_Opcode }, |
||
9573 | { Bad_Opcode }, |
||
9574 | { Bad_Opcode }, |
||
9575 | { Bad_Opcode }, |
||
9576 | { Bad_Opcode }, |
||
9577 | { Bad_Opcode }, |
||
9578 | }, |
||
9579 | }; |
||
9580 | |||
9581 | #define NEED_OPCODE_TABLE |
||
9582 | #include "i386-dis-evex.h" |
||
9583 | #undef NEED_OPCODE_TABLE |
||
9584 | static const struct dis386 vex_len_table[][2] = { |
||
9585 | /* VEX_LEN_0F10_P_1 */ |
||
9586 | { |
||
9587 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
||
9588 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
||
9589 | }, |
||
9590 | |||
9591 | /* VEX_LEN_0F10_P_3 */ |
||
9592 | { |
||
9593 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
||
9594 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
||
9595 | }, |
||
9596 | |||
9597 | /* VEX_LEN_0F11_P_1 */ |
||
9598 | { |
||
9599 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
||
9600 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
||
9601 | }, |
||
9602 | |||
9603 | /* VEX_LEN_0F11_P_3 */ |
||
9604 | { |
||
9605 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
||
9606 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
||
9607 | }, |
||
9608 | |||
9609 | /* VEX_LEN_0F12_P_0_M_0 */ |
||
9610 | { |
||
9611 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
||
9612 | }, |
||
9613 | |||
9614 | /* VEX_LEN_0F12_P_0_M_1 */ |
||
9615 | { |
||
9616 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
||
9617 | }, |
||
9618 | |||
9619 | /* VEX_LEN_0F12_P_2 */ |
||
9620 | { |
||
9621 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
||
9622 | }, |
||
9623 | |||
9624 | /* VEX_LEN_0F13_M_0 */ |
||
9625 | { |
||
9626 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
||
9627 | }, |
||
9628 | |||
9629 | /* VEX_LEN_0F16_P_0_M_0 */ |
||
9630 | { |
||
9631 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
||
9632 | }, |
||
9633 | |||
9634 | /* VEX_LEN_0F16_P_0_M_1 */ |
||
9635 | { |
||
9636 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
||
9637 | }, |
||
9638 | |||
9639 | /* VEX_LEN_0F16_P_2 */ |
||
9640 | { |
||
9641 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
||
9642 | }, |
||
9643 | |||
9644 | /* VEX_LEN_0F17_M_0 */ |
||
9645 | { |
||
9646 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
||
9647 | }, |
||
9648 | |||
9649 | /* VEX_LEN_0F2A_P_1 */ |
||
9650 | { |
||
6324 | serge | 9651 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9652 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
||
5221 | serge | 9653 | }, |
9654 | |||
9655 | /* VEX_LEN_0F2A_P_3 */ |
||
9656 | { |
||
6324 | serge | 9657 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9658 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
||
5221 | serge | 9659 | }, |
9660 | |||
9661 | /* VEX_LEN_0F2C_P_1 */ |
||
9662 | { |
||
6324 | serge | 9663 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9664 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
||
5221 | serge | 9665 | }, |
9666 | |||
9667 | /* VEX_LEN_0F2C_P_3 */ |
||
9668 | { |
||
6324 | serge | 9669 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9670 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
||
5221 | serge | 9671 | }, |
9672 | |||
9673 | /* VEX_LEN_0F2D_P_1 */ |
||
9674 | { |
||
6324 | serge | 9675 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9676 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
||
5221 | serge | 9677 | }, |
9678 | |||
9679 | /* VEX_LEN_0F2D_P_3 */ |
||
9680 | { |
||
6324 | serge | 9681 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9682 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
||
5221 | serge | 9683 | }, |
9684 | |||
9685 | /* VEX_LEN_0F2E_P_0 */ |
||
9686 | { |
||
9687 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
||
9688 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
||
9689 | }, |
||
9690 | |||
9691 | /* VEX_LEN_0F2E_P_2 */ |
||
9692 | { |
||
9693 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
||
9694 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
||
9695 | }, |
||
9696 | |||
9697 | /* VEX_LEN_0F2F_P_0 */ |
||
9698 | { |
||
9699 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
||
9700 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
||
9701 | }, |
||
9702 | |||
9703 | /* VEX_LEN_0F2F_P_2 */ |
||
9704 | { |
||
9705 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
||
9706 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
||
9707 | }, |
||
9708 | |||
9709 | /* VEX_LEN_0F41_P_0 */ |
||
9710 | { |
||
9711 | { Bad_Opcode }, |
||
9712 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, |
||
9713 | }, |
||
6324 | serge | 9714 | /* VEX_LEN_0F41_P_2 */ |
9715 | { |
||
9716 | { Bad_Opcode }, |
||
9717 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, |
||
9718 | }, |
||
5221 | serge | 9719 | /* VEX_LEN_0F42_P_0 */ |
9720 | { |
||
9721 | { Bad_Opcode }, |
||
9722 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, |
||
9723 | }, |
||
6324 | serge | 9724 | /* VEX_LEN_0F42_P_2 */ |
9725 | { |
||
9726 | { Bad_Opcode }, |
||
9727 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, |
||
9728 | }, |
||
5221 | serge | 9729 | /* VEX_LEN_0F44_P_0 */ |
9730 | { |
||
9731 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, |
||
9732 | }, |
||
6324 | serge | 9733 | /* VEX_LEN_0F44_P_2 */ |
9734 | { |
||
9735 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, |
||
9736 | }, |
||
5221 | serge | 9737 | /* VEX_LEN_0F45_P_0 */ |
9738 | { |
||
9739 | { Bad_Opcode }, |
||
9740 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, |
||
9741 | }, |
||
6324 | serge | 9742 | /* VEX_LEN_0F45_P_2 */ |
9743 | { |
||
9744 | { Bad_Opcode }, |
||
9745 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, |
||
9746 | }, |
||
5221 | serge | 9747 | /* VEX_LEN_0F46_P_0 */ |
9748 | { |
||
9749 | { Bad_Opcode }, |
||
9750 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, |
||
9751 | }, |
||
6324 | serge | 9752 | /* VEX_LEN_0F46_P_2 */ |
9753 | { |
||
9754 | { Bad_Opcode }, |
||
9755 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, |
||
9756 | }, |
||
5221 | serge | 9757 | /* VEX_LEN_0F47_P_0 */ |
9758 | { |
||
9759 | { Bad_Opcode }, |
||
9760 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, |
||
9761 | }, |
||
6324 | serge | 9762 | /* VEX_LEN_0F47_P_2 */ |
9763 | { |
||
9764 | { Bad_Opcode }, |
||
9765 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, |
||
9766 | }, |
||
9767 | /* VEX_LEN_0F4A_P_0 */ |
||
9768 | { |
||
9769 | { Bad_Opcode }, |
||
9770 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, |
||
9771 | }, |
||
9772 | /* VEX_LEN_0F4A_P_2 */ |
||
9773 | { |
||
9774 | { Bad_Opcode }, |
||
9775 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, |
||
9776 | }, |
||
9777 | /* VEX_LEN_0F4B_P_0 */ |
||
9778 | { |
||
9779 | { Bad_Opcode }, |
||
9780 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, |
||
9781 | }, |
||
5221 | serge | 9782 | /* VEX_LEN_0F4B_P_2 */ |
9783 | { |
||
9784 | { Bad_Opcode }, |
||
9785 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, |
||
9786 | }, |
||
9787 | |||
9788 | /* VEX_LEN_0F51_P_1 */ |
||
9789 | { |
||
9790 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
||
9791 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
||
9792 | }, |
||
9793 | |||
9794 | /* VEX_LEN_0F51_P_3 */ |
||
9795 | { |
||
9796 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
||
9797 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
||
9798 | }, |
||
9799 | |||
9800 | /* VEX_LEN_0F52_P_1 */ |
||
9801 | { |
||
9802 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
||
9803 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
||
9804 | }, |
||
9805 | |||
9806 | /* VEX_LEN_0F53_P_1 */ |
||
9807 | { |
||
9808 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
||
9809 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
||
9810 | }, |
||
9811 | |||
9812 | /* VEX_LEN_0F58_P_1 */ |
||
9813 | { |
||
9814 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
||
9815 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
||
9816 | }, |
||
9817 | |||
9818 | /* VEX_LEN_0F58_P_3 */ |
||
9819 | { |
||
9820 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
||
9821 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
||
9822 | }, |
||
9823 | |||
9824 | /* VEX_LEN_0F59_P_1 */ |
||
9825 | { |
||
9826 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
||
9827 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
||
9828 | }, |
||
9829 | |||
9830 | /* VEX_LEN_0F59_P_3 */ |
||
9831 | { |
||
9832 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
||
9833 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
||
9834 | }, |
||
9835 | |||
9836 | /* VEX_LEN_0F5A_P_1 */ |
||
9837 | { |
||
9838 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
||
9839 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
||
9840 | }, |
||
9841 | |||
9842 | /* VEX_LEN_0F5A_P_3 */ |
||
9843 | { |
||
9844 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
||
9845 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
||
9846 | }, |
||
9847 | |||
9848 | /* VEX_LEN_0F5C_P_1 */ |
||
9849 | { |
||
9850 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
||
9851 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
||
9852 | }, |
||
9853 | |||
9854 | /* VEX_LEN_0F5C_P_3 */ |
||
9855 | { |
||
9856 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
||
9857 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
||
9858 | }, |
||
9859 | |||
9860 | /* VEX_LEN_0F5D_P_1 */ |
||
9861 | { |
||
9862 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
||
9863 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
||
9864 | }, |
||
9865 | |||
9866 | /* VEX_LEN_0F5D_P_3 */ |
||
9867 | { |
||
9868 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
||
9869 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
||
9870 | }, |
||
9871 | |||
9872 | /* VEX_LEN_0F5E_P_1 */ |
||
9873 | { |
||
9874 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
||
9875 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
||
9876 | }, |
||
9877 | |||
9878 | /* VEX_LEN_0F5E_P_3 */ |
||
9879 | { |
||
9880 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
||
9881 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
||
9882 | }, |
||
9883 | |||
9884 | /* VEX_LEN_0F5F_P_1 */ |
||
9885 | { |
||
9886 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
||
9887 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
||
9888 | }, |
||
9889 | |||
9890 | /* VEX_LEN_0F5F_P_3 */ |
||
9891 | { |
||
9892 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
||
9893 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
||
9894 | }, |
||
9895 | |||
9896 | /* VEX_LEN_0F6E_P_2 */ |
||
9897 | { |
||
6324 | serge | 9898 | { "vmovK", { XMScalar, Edq }, 0 }, |
9899 | { "vmovK", { XMScalar, Edq }, 0 }, |
||
5221 | serge | 9900 | }, |
9901 | |||
9902 | /* VEX_LEN_0F7E_P_1 */ |
||
9903 | { |
||
9904 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
||
9905 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
||
9906 | }, |
||
9907 | |||
9908 | /* VEX_LEN_0F7E_P_2 */ |
||
9909 | { |
||
6324 | serge | 9910 | { "vmovK", { Edq, XMScalar }, 0 }, |
9911 | { "vmovK", { Edq, XMScalar }, 0 }, |
||
5221 | serge | 9912 | }, |
9913 | |||
9914 | /* VEX_LEN_0F90_P_0 */ |
||
9915 | { |
||
9916 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
||
9917 | }, |
||
9918 | |||
6324 | serge | 9919 | /* VEX_LEN_0F90_P_2 */ |
9920 | { |
||
9921 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
||
9922 | }, |
||
9923 | |||
5221 | serge | 9924 | /* VEX_LEN_0F91_P_0 */ |
9925 | { |
||
9926 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
||
9927 | }, |
||
9928 | |||
6324 | serge | 9929 | /* VEX_LEN_0F91_P_2 */ |
9930 | { |
||
9931 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
||
9932 | }, |
||
9933 | |||
5221 | serge | 9934 | /* VEX_LEN_0F92_P_0 */ |
9935 | { |
||
9936 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
||
9937 | }, |
||
9938 | |||
6324 | serge | 9939 | /* VEX_LEN_0F92_P_2 */ |
9940 | { |
||
9941 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
||
9942 | }, |
||
9943 | |||
9944 | /* VEX_LEN_0F92_P_3 */ |
||
9945 | { |
||
9946 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, |
||
9947 | }, |
||
9948 | |||
5221 | serge | 9949 | /* VEX_LEN_0F93_P_0 */ |
9950 | { |
||
9951 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
||
9952 | }, |
||
9953 | |||
6324 | serge | 9954 | /* VEX_LEN_0F93_P_2 */ |
9955 | { |
||
9956 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
||
9957 | }, |
||
9958 | |||
9959 | /* VEX_LEN_0F93_P_3 */ |
||
9960 | { |
||
9961 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, |
||
9962 | }, |
||
9963 | |||
5221 | serge | 9964 | /* VEX_LEN_0F98_P_0 */ |
9965 | { |
||
9966 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, |
||
9967 | }, |
||
9968 | |||
6324 | serge | 9969 | /* VEX_LEN_0F98_P_2 */ |
9970 | { |
||
9971 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, |
||
9972 | }, |
||
9973 | |||
9974 | /* VEX_LEN_0F99_P_0 */ |
||
9975 | { |
||
9976 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, |
||
9977 | }, |
||
9978 | |||
9979 | /* VEX_LEN_0F99_P_2 */ |
||
9980 | { |
||
9981 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, |
||
9982 | }, |
||
9983 | |||
5221 | serge | 9984 | /* VEX_LEN_0FAE_R_2_M_0 */ |
9985 | { |
||
9986 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
||
9987 | }, |
||
9988 | |||
9989 | /* VEX_LEN_0FAE_R_3_M_0 */ |
||
9990 | { |
||
9991 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
||
9992 | }, |
||
9993 | |||
9994 | /* VEX_LEN_0FC2_P_1 */ |
||
9995 | { |
||
9996 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
||
9997 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
||
9998 | }, |
||
9999 | |||
10000 | /* VEX_LEN_0FC2_P_3 */ |
||
10001 | { |
||
10002 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
||
10003 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
||
10004 | }, |
||
10005 | |||
10006 | /* VEX_LEN_0FC4_P_2 */ |
||
10007 | { |
||
10008 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
||
10009 | }, |
||
10010 | |||
10011 | /* VEX_LEN_0FC5_P_2 */ |
||
10012 | { |
||
10013 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
||
10014 | }, |
||
10015 | |||
10016 | /* VEX_LEN_0FD6_P_2 */ |
||
10017 | { |
||
10018 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
||
10019 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
||
10020 | }, |
||
10021 | |||
10022 | /* VEX_LEN_0FF7_P_2 */ |
||
10023 | { |
||
10024 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
||
10025 | }, |
||
10026 | |||
10027 | /* VEX_LEN_0F3816_P_2 */ |
||
10028 | { |
||
10029 | { Bad_Opcode }, |
||
10030 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, |
||
10031 | }, |
||
10032 | |||
10033 | /* VEX_LEN_0F3819_P_2 */ |
||
10034 | { |
||
10035 | { Bad_Opcode }, |
||
10036 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, |
||
10037 | }, |
||
10038 | |||
10039 | /* VEX_LEN_0F381A_P_2_M_0 */ |
||
10040 | { |
||
10041 | { Bad_Opcode }, |
||
10042 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, |
||
10043 | }, |
||
10044 | |||
10045 | /* VEX_LEN_0F3836_P_2 */ |
||
10046 | { |
||
10047 | { Bad_Opcode }, |
||
10048 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, |
||
10049 | }, |
||
10050 | |||
10051 | /* VEX_LEN_0F3841_P_2 */ |
||
10052 | { |
||
10053 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
||
10054 | }, |
||
10055 | |||
10056 | /* VEX_LEN_0F385A_P_2_M_0 */ |
||
10057 | { |
||
10058 | { Bad_Opcode }, |
||
10059 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, |
||
10060 | }, |
||
10061 | |||
10062 | /* VEX_LEN_0F38DB_P_2 */ |
||
10063 | { |
||
10064 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
||
10065 | }, |
||
10066 | |||
10067 | /* VEX_LEN_0F38DC_P_2 */ |
||
10068 | { |
||
10069 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
||
10070 | }, |
||
10071 | |||
10072 | /* VEX_LEN_0F38DD_P_2 */ |
||
10073 | { |
||
10074 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
||
10075 | }, |
||
10076 | |||
10077 | /* VEX_LEN_0F38DE_P_2 */ |
||
10078 | { |
||
10079 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
||
10080 | }, |
||
10081 | |||
10082 | /* VEX_LEN_0F38DF_P_2 */ |
||
10083 | { |
||
10084 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
||
10085 | }, |
||
10086 | |||
10087 | /* VEX_LEN_0F38F2_P_0 */ |
||
10088 | { |
||
6324 | serge | 10089 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
5221 | serge | 10090 | }, |
10091 | |||
10092 | /* VEX_LEN_0F38F3_R_1_P_0 */ |
||
10093 | { |
||
6324 | serge | 10094 | { "blsrS", { VexGdq, Edq }, 0 }, |
5221 | serge | 10095 | }, |
10096 | |||
10097 | /* VEX_LEN_0F38F3_R_2_P_0 */ |
||
10098 | { |
||
6324 | serge | 10099 | { "blsmskS", { VexGdq, Edq }, 0 }, |
5221 | serge | 10100 | }, |
10101 | |||
10102 | /* VEX_LEN_0F38F3_R_3_P_0 */ |
||
10103 | { |
||
6324 | serge | 10104 | { "blsiS", { VexGdq, Edq }, 0 }, |
5221 | serge | 10105 | }, |
10106 | |||
10107 | /* VEX_LEN_0F38F5_P_0 */ |
||
10108 | { |
||
6324 | serge | 10109 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
5221 | serge | 10110 | }, |
10111 | |||
10112 | /* VEX_LEN_0F38F5_P_1 */ |
||
10113 | { |
||
6324 | serge | 10114 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
5221 | serge | 10115 | }, |
10116 | |||
10117 | /* VEX_LEN_0F38F5_P_3 */ |
||
10118 | { |
||
6324 | serge | 10119 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
5221 | serge | 10120 | }, |
10121 | |||
10122 | /* VEX_LEN_0F38F6_P_3 */ |
||
10123 | { |
||
6324 | serge | 10124 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
5221 | serge | 10125 | }, |
10126 | |||
10127 | /* VEX_LEN_0F38F7_P_0 */ |
||
10128 | { |
||
6324 | serge | 10129 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
5221 | serge | 10130 | }, |
10131 | |||
10132 | /* VEX_LEN_0F38F7_P_1 */ |
||
10133 | { |
||
6324 | serge | 10134 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
5221 | serge | 10135 | }, |
10136 | |||
10137 | /* VEX_LEN_0F38F7_P_2 */ |
||
10138 | { |
||
6324 | serge | 10139 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
5221 | serge | 10140 | }, |
10141 | |||
10142 | /* VEX_LEN_0F38F7_P_3 */ |
||
10143 | { |
||
6324 | serge | 10144 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
5221 | serge | 10145 | }, |
10146 | |||
10147 | /* VEX_LEN_0F3A00_P_2 */ |
||
10148 | { |
||
10149 | { Bad_Opcode }, |
||
10150 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, |
||
10151 | }, |
||
10152 | |||
10153 | /* VEX_LEN_0F3A01_P_2 */ |
||
10154 | { |
||
10155 | { Bad_Opcode }, |
||
10156 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, |
||
10157 | }, |
||
10158 | |||
10159 | /* VEX_LEN_0F3A06_P_2 */ |
||
10160 | { |
||
10161 | { Bad_Opcode }, |
||
10162 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
||
10163 | }, |
||
10164 | |||
10165 | /* VEX_LEN_0F3A0A_P_2 */ |
||
10166 | { |
||
10167 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
||
10168 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
||
10169 | }, |
||
10170 | |||
10171 | /* VEX_LEN_0F3A0B_P_2 */ |
||
10172 | { |
||
10173 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
||
10174 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
||
10175 | }, |
||
10176 | |||
10177 | /* VEX_LEN_0F3A14_P_2 */ |
||
10178 | { |
||
10179 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
||
10180 | }, |
||
10181 | |||
10182 | /* VEX_LEN_0F3A15_P_2 */ |
||
10183 | { |
||
10184 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
||
10185 | }, |
||
10186 | |||
10187 | /* VEX_LEN_0F3A16_P_2 */ |
||
10188 | { |
||
6324 | serge | 10189 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
5221 | serge | 10190 | }, |
10191 | |||
10192 | /* VEX_LEN_0F3A17_P_2 */ |
||
10193 | { |
||
6324 | serge | 10194 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
5221 | serge | 10195 | }, |
10196 | |||
10197 | /* VEX_LEN_0F3A18_P_2 */ |
||
10198 | { |
||
10199 | { Bad_Opcode }, |
||
10200 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
||
10201 | }, |
||
10202 | |||
10203 | /* VEX_LEN_0F3A19_P_2 */ |
||
10204 | { |
||
10205 | { Bad_Opcode }, |
||
10206 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
||
10207 | }, |
||
10208 | |||
10209 | /* VEX_LEN_0F3A20_P_2 */ |
||
10210 | { |
||
10211 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
||
10212 | }, |
||
10213 | |||
10214 | /* VEX_LEN_0F3A21_P_2 */ |
||
10215 | { |
||
10216 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
||
10217 | }, |
||
10218 | |||
10219 | /* VEX_LEN_0F3A22_P_2 */ |
||
10220 | { |
||
6324 | serge | 10221 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
5221 | serge | 10222 | }, |
10223 | |||
10224 | /* VEX_LEN_0F3A30_P_2 */ |
||
10225 | { |
||
10226 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, |
||
10227 | }, |
||
10228 | |||
6324 | serge | 10229 | /* VEX_LEN_0F3A31_P_2 */ |
10230 | { |
||
10231 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, |
||
10232 | }, |
||
10233 | |||
5221 | serge | 10234 | /* VEX_LEN_0F3A32_P_2 */ |
10235 | { |
||
10236 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, |
||
10237 | }, |
||
10238 | |||
6324 | serge | 10239 | /* VEX_LEN_0F3A33_P_2 */ |
10240 | { |
||
10241 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, |
||
10242 | }, |
||
10243 | |||
5221 | serge | 10244 | /* VEX_LEN_0F3A38_P_2 */ |
10245 | { |
||
10246 | { Bad_Opcode }, |
||
10247 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, |
||
10248 | }, |
||
10249 | |||
10250 | /* VEX_LEN_0F3A39_P_2 */ |
||
10251 | { |
||
10252 | { Bad_Opcode }, |
||
10253 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, |
||
10254 | }, |
||
10255 | |||
10256 | /* VEX_LEN_0F3A41_P_2 */ |
||
10257 | { |
||
10258 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, |
||
10259 | }, |
||
10260 | |||
10261 | /* VEX_LEN_0F3A44_P_2 */ |
||
10262 | { |
||
10263 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
||
10264 | }, |
||
10265 | |||
10266 | /* VEX_LEN_0F3A46_P_2 */ |
||
10267 | { |
||
10268 | { Bad_Opcode }, |
||
10269 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, |
||
10270 | }, |
||
10271 | |||
10272 | /* VEX_LEN_0F3A60_P_2 */ |
||
10273 | { |
||
10274 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
||
10275 | }, |
||
10276 | |||
10277 | /* VEX_LEN_0F3A61_P_2 */ |
||
10278 | { |
||
10279 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
||
10280 | }, |
||
10281 | |||
10282 | /* VEX_LEN_0F3A62_P_2 */ |
||
10283 | { |
||
10284 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
||
10285 | }, |
||
10286 | |||
10287 | /* VEX_LEN_0F3A63_P_2 */ |
||
10288 | { |
||
10289 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
||
10290 | }, |
||
10291 | |||
10292 | /* VEX_LEN_0F3A6A_P_2 */ |
||
10293 | { |
||
6324 | serge | 10294 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
5221 | serge | 10295 | }, |
10296 | |||
10297 | /* VEX_LEN_0F3A6B_P_2 */ |
||
10298 | { |
||
6324 | serge | 10299 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
5221 | serge | 10300 | }, |
10301 | |||
10302 | /* VEX_LEN_0F3A6E_P_2 */ |
||
10303 | { |
||
6324 | serge | 10304 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
5221 | serge | 10305 | }, |
10306 | |||
10307 | /* VEX_LEN_0F3A6F_P_2 */ |
||
10308 | { |
||
6324 | serge | 10309 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
5221 | serge | 10310 | }, |
10311 | |||
10312 | /* VEX_LEN_0F3A7A_P_2 */ |
||
10313 | { |
||
6324 | serge | 10314 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
5221 | serge | 10315 | }, |
10316 | |||
10317 | /* VEX_LEN_0F3A7B_P_2 */ |
||
10318 | { |
||
6324 | serge | 10319 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
5221 | serge | 10320 | }, |
10321 | |||
10322 | /* VEX_LEN_0F3A7E_P_2 */ |
||
10323 | { |
||
6324 | serge | 10324 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
5221 | serge | 10325 | }, |
10326 | |||
10327 | /* VEX_LEN_0F3A7F_P_2 */ |
||
10328 | { |
||
6324 | serge | 10329 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
5221 | serge | 10330 | }, |
10331 | |||
10332 | /* VEX_LEN_0F3ADF_P_2 */ |
||
10333 | { |
||
10334 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
||
10335 | }, |
||
10336 | |||
10337 | /* VEX_LEN_0F3AF0_P_3 */ |
||
10338 | { |
||
6324 | serge | 10339 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
5221 | serge | 10340 | }, |
10341 | |||
10342 | /* VEX_LEN_0FXOP_08_CC */ |
||
10343 | { |
||
6324 | serge | 10344 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10345 | }, |
10346 | |||
10347 | /* VEX_LEN_0FXOP_08_CD */ |
||
10348 | { |
||
6324 | serge | 10349 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10350 | }, |
10351 | |||
10352 | /* VEX_LEN_0FXOP_08_CE */ |
||
10353 | { |
||
6324 | serge | 10354 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10355 | }, |
10356 | |||
10357 | /* VEX_LEN_0FXOP_08_CF */ |
||
10358 | { |
||
6324 | serge | 10359 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10360 | }, |
10361 | |||
10362 | /* VEX_LEN_0FXOP_08_EC */ |
||
10363 | { |
||
6324 | serge | 10364 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10365 | }, |
10366 | |||
10367 | /* VEX_LEN_0FXOP_08_ED */ |
||
10368 | { |
||
6324 | serge | 10369 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10370 | }, |
10371 | |||
10372 | /* VEX_LEN_0FXOP_08_EE */ |
||
10373 | { |
||
6324 | serge | 10374 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10375 | }, |
10376 | |||
10377 | /* VEX_LEN_0FXOP_08_EF */ |
||
10378 | { |
||
6324 | serge | 10379 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 10380 | }, |
10381 | |||
10382 | /* VEX_LEN_0FXOP_09_80 */ |
||
10383 | { |
||
6324 | serge | 10384 | { "vfrczps", { XM, EXxmm }, 0 }, |
10385 | { "vfrczps", { XM, EXymmq }, 0 }, |
||
5221 | serge | 10386 | }, |
10387 | |||
10388 | /* VEX_LEN_0FXOP_09_81 */ |
||
10389 | { |
||
6324 | serge | 10390 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10391 | { "vfrczpd", { XM, EXymmq }, 0 }, |
||
5221 | serge | 10392 | }, |
10393 | }; |
||
10394 | |||
10395 | static const struct dis386 vex_w_table[][2] = { |
||
10396 | { |
||
10397 | /* VEX_W_0F10_P_0 */ |
||
6324 | serge | 10398 | { "vmovups", { XM, EXx }, 0 }, |
5221 | serge | 10399 | }, |
10400 | { |
||
10401 | /* VEX_W_0F10_P_1 */ |
||
6324 | serge | 10402 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10403 | }, |
10404 | { |
||
10405 | /* VEX_W_0F10_P_2 */ |
||
6324 | serge | 10406 | { "vmovupd", { XM, EXx }, 0 }, |
5221 | serge | 10407 | }, |
10408 | { |
||
10409 | /* VEX_W_0F10_P_3 */ |
||
6324 | serge | 10410 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10411 | }, |
10412 | { |
||
10413 | /* VEX_W_0F11_P_0 */ |
||
6324 | serge | 10414 | { "vmovups", { EXxS, XM }, 0 }, |
5221 | serge | 10415 | }, |
10416 | { |
||
10417 | /* VEX_W_0F11_P_1 */ |
||
6324 | serge | 10418 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
5221 | serge | 10419 | }, |
10420 | { |
||
10421 | /* VEX_W_0F11_P_2 */ |
||
6324 | serge | 10422 | { "vmovupd", { EXxS, XM }, 0 }, |
5221 | serge | 10423 | }, |
10424 | { |
||
10425 | /* VEX_W_0F11_P_3 */ |
||
6324 | serge | 10426 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
5221 | serge | 10427 | }, |
10428 | { |
||
10429 | /* VEX_W_0F12_P_0_M_0 */ |
||
6324 | serge | 10430 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
5221 | serge | 10431 | }, |
10432 | { |
||
10433 | /* VEX_W_0F12_P_0_M_1 */ |
||
6324 | serge | 10434 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
5221 | serge | 10435 | }, |
10436 | { |
||
10437 | /* VEX_W_0F12_P_1 */ |
||
6324 | serge | 10438 | { "vmovsldup", { XM, EXx }, 0 }, |
5221 | serge | 10439 | }, |
10440 | { |
||
10441 | /* VEX_W_0F12_P_2 */ |
||
6324 | serge | 10442 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
5221 | serge | 10443 | }, |
10444 | { |
||
10445 | /* VEX_W_0F12_P_3 */ |
||
6324 | serge | 10446 | { "vmovddup", { XM, EXymmq }, 0 }, |
5221 | serge | 10447 | }, |
10448 | { |
||
10449 | /* VEX_W_0F13_M_0 */ |
||
6324 | serge | 10450 | { "vmovlpX", { EXq, XM }, 0 }, |
5221 | serge | 10451 | }, |
10452 | { |
||
10453 | /* VEX_W_0F14 */ |
||
6324 | serge | 10454 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10455 | }, |
10456 | { |
||
10457 | /* VEX_W_0F15 */ |
||
6324 | serge | 10458 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10459 | }, |
10460 | { |
||
10461 | /* VEX_W_0F16_P_0_M_0 */ |
||
6324 | serge | 10462 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
5221 | serge | 10463 | }, |
10464 | { |
||
10465 | /* VEX_W_0F16_P_0_M_1 */ |
||
6324 | serge | 10466 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
5221 | serge | 10467 | }, |
10468 | { |
||
10469 | /* VEX_W_0F16_P_1 */ |
||
6324 | serge | 10470 | { "vmovshdup", { XM, EXx }, 0 }, |
5221 | serge | 10471 | }, |
10472 | { |
||
10473 | /* VEX_W_0F16_P_2 */ |
||
6324 | serge | 10474 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
5221 | serge | 10475 | }, |
10476 | { |
||
10477 | /* VEX_W_0F17_M_0 */ |
||
6324 | serge | 10478 | { "vmovhpX", { EXq, XM }, 0 }, |
5221 | serge | 10479 | }, |
10480 | { |
||
10481 | /* VEX_W_0F28 */ |
||
6324 | serge | 10482 | { "vmovapX", { XM, EXx }, 0 }, |
5221 | serge | 10483 | }, |
10484 | { |
||
10485 | /* VEX_W_0F29 */ |
||
6324 | serge | 10486 | { "vmovapX", { EXxS, XM }, 0 }, |
5221 | serge | 10487 | }, |
10488 | { |
||
10489 | /* VEX_W_0F2B_M_0 */ |
||
6324 | serge | 10490 | { "vmovntpX", { Mx, XM }, 0 }, |
5221 | serge | 10491 | }, |
10492 | { |
||
10493 | /* VEX_W_0F2E_P_0 */ |
||
6324 | serge | 10494 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
5221 | serge | 10495 | }, |
10496 | { |
||
10497 | /* VEX_W_0F2E_P_2 */ |
||
6324 | serge | 10498 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
5221 | serge | 10499 | }, |
10500 | { |
||
10501 | /* VEX_W_0F2F_P_0 */ |
||
6324 | serge | 10502 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
5221 | serge | 10503 | }, |
10504 | { |
||
10505 | /* VEX_W_0F2F_P_2 */ |
||
6324 | serge | 10506 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
5221 | serge | 10507 | }, |
10508 | { |
||
10509 | /* VEX_W_0F41_P_0_LEN_1 */ |
||
6324 | serge | 10510 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10511 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, |
||
5221 | serge | 10512 | }, |
10513 | { |
||
6324 | serge | 10514 | /* VEX_W_0F41_P_2_LEN_1 */ |
10515 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
||
10516 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } |
||
10517 | }, |
||
10518 | { |
||
5221 | serge | 10519 | /* VEX_W_0F42_P_0_LEN_1 */ |
6324 | serge | 10520 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10521 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, |
||
5221 | serge | 10522 | }, |
10523 | { |
||
6324 | serge | 10524 | /* VEX_W_0F42_P_2_LEN_1 */ |
10525 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
||
10526 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, |
||
10527 | }, |
||
10528 | { |
||
5221 | serge | 10529 | /* VEX_W_0F44_P_0_LEN_0 */ |
6324 | serge | 10530 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10531 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, |
||
5221 | serge | 10532 | }, |
10533 | { |
||
6324 | serge | 10534 | /* VEX_W_0F44_P_2_LEN_0 */ |
10535 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
||
10536 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, |
||
10537 | }, |
||
10538 | { |
||
5221 | serge | 10539 | /* VEX_W_0F45_P_0_LEN_1 */ |
6324 | serge | 10540 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10541 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, |
||
5221 | serge | 10542 | }, |
10543 | { |
||
6324 | serge | 10544 | /* VEX_W_0F45_P_2_LEN_1 */ |
10545 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
||
10546 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, |
||
10547 | }, |
||
10548 | { |
||
5221 | serge | 10549 | /* VEX_W_0F46_P_0_LEN_1 */ |
6324 | serge | 10550 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10551 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, |
||
5221 | serge | 10552 | }, |
10553 | { |
||
6324 | serge | 10554 | /* VEX_W_0F46_P_2_LEN_1 */ |
10555 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
||
10556 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, |
||
10557 | }, |
||
10558 | { |
||
5221 | serge | 10559 | /* VEX_W_0F47_P_0_LEN_1 */ |
6324 | serge | 10560 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10561 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, |
||
5221 | serge | 10562 | }, |
10563 | { |
||
6324 | serge | 10564 | /* VEX_W_0F47_P_2_LEN_1 */ |
10565 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
||
10566 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, |
||
10567 | }, |
||
10568 | { |
||
10569 | /* VEX_W_0F4A_P_0_LEN_1 */ |
||
10570 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
||
10571 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, |
||
10572 | }, |
||
10573 | { |
||
10574 | /* VEX_W_0F4A_P_2_LEN_1 */ |
||
10575 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
||
10576 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, |
||
10577 | }, |
||
10578 | { |
||
10579 | /* VEX_W_0F4B_P_0_LEN_1 */ |
||
10580 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
||
10581 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, |
||
10582 | }, |
||
10583 | { |
||
5221 | serge | 10584 | /* VEX_W_0F4B_P_2_LEN_1 */ |
6324 | serge | 10585 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
5221 | serge | 10586 | }, |
10587 | { |
||
10588 | /* VEX_W_0F50_M_0 */ |
||
6324 | serge | 10589 | { "vmovmskpX", { Gdq, XS }, 0 }, |
5221 | serge | 10590 | }, |
10591 | { |
||
10592 | /* VEX_W_0F51_P_0 */ |
||
6324 | serge | 10593 | { "vsqrtps", { XM, EXx }, 0 }, |
5221 | serge | 10594 | }, |
10595 | { |
||
10596 | /* VEX_W_0F51_P_1 */ |
||
6324 | serge | 10597 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10598 | }, |
10599 | { |
||
10600 | /* VEX_W_0F51_P_2 */ |
||
6324 | serge | 10601 | { "vsqrtpd", { XM, EXx }, 0 }, |
5221 | serge | 10602 | }, |
10603 | { |
||
10604 | /* VEX_W_0F51_P_3 */ |
||
6324 | serge | 10605 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10606 | }, |
10607 | { |
||
10608 | /* VEX_W_0F52_P_0 */ |
||
6324 | serge | 10609 | { "vrsqrtps", { XM, EXx }, 0 }, |
5221 | serge | 10610 | }, |
10611 | { |
||
10612 | /* VEX_W_0F52_P_1 */ |
||
6324 | serge | 10613 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10614 | }, |
10615 | { |
||
10616 | /* VEX_W_0F53_P_0 */ |
||
6324 | serge | 10617 | { "vrcpps", { XM, EXx }, 0 }, |
5221 | serge | 10618 | }, |
10619 | { |
||
10620 | /* VEX_W_0F53_P_1 */ |
||
6324 | serge | 10621 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10622 | }, |
10623 | { |
||
10624 | /* VEX_W_0F58_P_0 */ |
||
6324 | serge | 10625 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10626 | }, |
10627 | { |
||
10628 | /* VEX_W_0F58_P_1 */ |
||
6324 | serge | 10629 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10630 | }, |
10631 | { |
||
10632 | /* VEX_W_0F58_P_2 */ |
||
6324 | serge | 10633 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10634 | }, |
10635 | { |
||
10636 | /* VEX_W_0F58_P_3 */ |
||
6324 | serge | 10637 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10638 | }, |
10639 | { |
||
10640 | /* VEX_W_0F59_P_0 */ |
||
6324 | serge | 10641 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10642 | }, |
10643 | { |
||
10644 | /* VEX_W_0F59_P_1 */ |
||
6324 | serge | 10645 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10646 | }, |
10647 | { |
||
10648 | /* VEX_W_0F59_P_2 */ |
||
6324 | serge | 10649 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10650 | }, |
10651 | { |
||
10652 | /* VEX_W_0F59_P_3 */ |
||
6324 | serge | 10653 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10654 | }, |
10655 | { |
||
10656 | /* VEX_W_0F5A_P_0 */ |
||
6324 | serge | 10657 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5221 | serge | 10658 | }, |
10659 | { |
||
10660 | /* VEX_W_0F5A_P_1 */ |
||
6324 | serge | 10661 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10662 | }, |
10663 | { |
||
10664 | /* VEX_W_0F5A_P_3 */ |
||
6324 | serge | 10665 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10666 | }, |
10667 | { |
||
10668 | /* VEX_W_0F5B_P_0 */ |
||
6324 | serge | 10669 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
5221 | serge | 10670 | }, |
10671 | { |
||
10672 | /* VEX_W_0F5B_P_1 */ |
||
6324 | serge | 10673 | { "vcvttps2dq", { XM, EXx }, 0 }, |
5221 | serge | 10674 | }, |
10675 | { |
||
10676 | /* VEX_W_0F5B_P_2 */ |
||
6324 | serge | 10677 | { "vcvtps2dq", { XM, EXx }, 0 }, |
5221 | serge | 10678 | }, |
10679 | { |
||
10680 | /* VEX_W_0F5C_P_0 */ |
||
6324 | serge | 10681 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10682 | }, |
10683 | { |
||
10684 | /* VEX_W_0F5C_P_1 */ |
||
6324 | serge | 10685 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10686 | }, |
10687 | { |
||
10688 | /* VEX_W_0F5C_P_2 */ |
||
6324 | serge | 10689 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10690 | }, |
10691 | { |
||
10692 | /* VEX_W_0F5C_P_3 */ |
||
6324 | serge | 10693 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10694 | }, |
10695 | { |
||
10696 | /* VEX_W_0F5D_P_0 */ |
||
6324 | serge | 10697 | { "vminps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10698 | }, |
10699 | { |
||
10700 | /* VEX_W_0F5D_P_1 */ |
||
6324 | serge | 10701 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10702 | }, |
10703 | { |
||
10704 | /* VEX_W_0F5D_P_2 */ |
||
6324 | serge | 10705 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10706 | }, |
10707 | { |
||
10708 | /* VEX_W_0F5D_P_3 */ |
||
6324 | serge | 10709 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10710 | }, |
10711 | { |
||
10712 | /* VEX_W_0F5E_P_0 */ |
||
6324 | serge | 10713 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10714 | }, |
10715 | { |
||
10716 | /* VEX_W_0F5E_P_1 */ |
||
6324 | serge | 10717 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10718 | }, |
10719 | { |
||
10720 | /* VEX_W_0F5E_P_2 */ |
||
6324 | serge | 10721 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10722 | }, |
10723 | { |
||
10724 | /* VEX_W_0F5E_P_3 */ |
||
6324 | serge | 10725 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10726 | }, |
10727 | { |
||
10728 | /* VEX_W_0F5F_P_0 */ |
||
6324 | serge | 10729 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10730 | }, |
10731 | { |
||
10732 | /* VEX_W_0F5F_P_1 */ |
||
6324 | serge | 10733 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
5221 | serge | 10734 | }, |
10735 | { |
||
10736 | /* VEX_W_0F5F_P_2 */ |
||
6324 | serge | 10737 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10738 | }, |
10739 | { |
||
10740 | /* VEX_W_0F5F_P_3 */ |
||
6324 | serge | 10741 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
5221 | serge | 10742 | }, |
10743 | { |
||
10744 | /* VEX_W_0F60_P_2 */ |
||
6324 | serge | 10745 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10746 | }, |
10747 | { |
||
10748 | /* VEX_W_0F61_P_2 */ |
||
6324 | serge | 10749 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10750 | }, |
10751 | { |
||
10752 | /* VEX_W_0F62_P_2 */ |
||
6324 | serge | 10753 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10754 | }, |
10755 | { |
||
10756 | /* VEX_W_0F63_P_2 */ |
||
6324 | serge | 10757 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10758 | }, |
10759 | { |
||
10760 | /* VEX_W_0F64_P_2 */ |
||
6324 | serge | 10761 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10762 | }, |
10763 | { |
||
10764 | /* VEX_W_0F65_P_2 */ |
||
6324 | serge | 10765 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10766 | }, |
10767 | { |
||
10768 | /* VEX_W_0F66_P_2 */ |
||
6324 | serge | 10769 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10770 | }, |
10771 | { |
||
10772 | /* VEX_W_0F67_P_2 */ |
||
6324 | serge | 10773 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10774 | }, |
10775 | { |
||
10776 | /* VEX_W_0F68_P_2 */ |
||
6324 | serge | 10777 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10778 | }, |
10779 | { |
||
10780 | /* VEX_W_0F69_P_2 */ |
||
6324 | serge | 10781 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10782 | }, |
10783 | { |
||
10784 | /* VEX_W_0F6A_P_2 */ |
||
6324 | serge | 10785 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10786 | }, |
10787 | { |
||
10788 | /* VEX_W_0F6B_P_2 */ |
||
6324 | serge | 10789 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10790 | }, |
10791 | { |
||
10792 | /* VEX_W_0F6C_P_2 */ |
||
6324 | serge | 10793 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10794 | }, |
10795 | { |
||
10796 | /* VEX_W_0F6D_P_2 */ |
||
6324 | serge | 10797 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10798 | }, |
10799 | { |
||
10800 | /* VEX_W_0F6F_P_1 */ |
||
6324 | serge | 10801 | { "vmovdqu", { XM, EXx }, 0 }, |
5221 | serge | 10802 | }, |
10803 | { |
||
10804 | /* VEX_W_0F6F_P_2 */ |
||
6324 | serge | 10805 | { "vmovdqa", { XM, EXx }, 0 }, |
5221 | serge | 10806 | }, |
10807 | { |
||
10808 | /* VEX_W_0F70_P_1 */ |
||
6324 | serge | 10809 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
5221 | serge | 10810 | }, |
10811 | { |
||
10812 | /* VEX_W_0F70_P_2 */ |
||
6324 | serge | 10813 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 10814 | }, |
10815 | { |
||
10816 | /* VEX_W_0F70_P_3 */ |
||
6324 | serge | 10817 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
5221 | serge | 10818 | }, |
10819 | { |
||
10820 | /* VEX_W_0F71_R_2_P_2 */ |
||
6324 | serge | 10821 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10822 | }, |
10823 | { |
||
10824 | /* VEX_W_0F71_R_4_P_2 */ |
||
6324 | serge | 10825 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10826 | }, |
10827 | { |
||
10828 | /* VEX_W_0F71_R_6_P_2 */ |
||
6324 | serge | 10829 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10830 | }, |
10831 | { |
||
10832 | /* VEX_W_0F72_R_2_P_2 */ |
||
6324 | serge | 10833 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10834 | }, |
10835 | { |
||
10836 | /* VEX_W_0F72_R_4_P_2 */ |
||
6324 | serge | 10837 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10838 | }, |
10839 | { |
||
10840 | /* VEX_W_0F72_R_6_P_2 */ |
||
6324 | serge | 10841 | { "vpslld", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10842 | }, |
10843 | { |
||
10844 | /* VEX_W_0F73_R_2_P_2 */ |
||
6324 | serge | 10845 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10846 | }, |
10847 | { |
||
10848 | /* VEX_W_0F73_R_3_P_2 */ |
||
6324 | serge | 10849 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10850 | }, |
10851 | { |
||
10852 | /* VEX_W_0F73_R_6_P_2 */ |
||
6324 | serge | 10853 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10854 | }, |
10855 | { |
||
10856 | /* VEX_W_0F73_R_7_P_2 */ |
||
6324 | serge | 10857 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
5221 | serge | 10858 | }, |
10859 | { |
||
10860 | /* VEX_W_0F74_P_2 */ |
||
6324 | serge | 10861 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10862 | }, |
10863 | { |
||
10864 | /* VEX_W_0F75_P_2 */ |
||
6324 | serge | 10865 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10866 | }, |
10867 | { |
||
10868 | /* VEX_W_0F76_P_2 */ |
||
6324 | serge | 10869 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10870 | }, |
10871 | { |
||
10872 | /* VEX_W_0F77_P_0 */ |
||
6324 | serge | 10873 | { "", { VZERO }, 0 }, |
5221 | serge | 10874 | }, |
10875 | { |
||
10876 | /* VEX_W_0F7C_P_2 */ |
||
6324 | serge | 10877 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10878 | }, |
10879 | { |
||
10880 | /* VEX_W_0F7C_P_3 */ |
||
6324 | serge | 10881 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10882 | }, |
10883 | { |
||
10884 | /* VEX_W_0F7D_P_2 */ |
||
6324 | serge | 10885 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10886 | }, |
10887 | { |
||
10888 | /* VEX_W_0F7D_P_3 */ |
||
6324 | serge | 10889 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 10890 | }, |
10891 | { |
||
10892 | /* VEX_W_0F7E_P_1 */ |
||
6324 | serge | 10893 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
5221 | serge | 10894 | }, |
10895 | { |
||
10896 | /* VEX_W_0F7F_P_1 */ |
||
6324 | serge | 10897 | { "vmovdqu", { EXxS, XM }, 0 }, |
5221 | serge | 10898 | }, |
10899 | { |
||
10900 | /* VEX_W_0F7F_P_2 */ |
||
6324 | serge | 10901 | { "vmovdqa", { EXxS, XM }, 0 }, |
5221 | serge | 10902 | }, |
10903 | { |
||
10904 | /* VEX_W_0F90_P_0_LEN_0 */ |
||
6324 | serge | 10905 | { "kmovw", { MaskG, MaskE }, 0 }, |
10906 | { "kmovq", { MaskG, MaskE }, 0 }, |
||
5221 | serge | 10907 | }, |
10908 | { |
||
6324 | serge | 10909 | /* VEX_W_0F90_P_2_LEN_0 */ |
10910 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
||
10911 | { "kmovd", { MaskG, MaskBDE }, 0 }, |
||
10912 | }, |
||
10913 | { |
||
5221 | serge | 10914 | /* VEX_W_0F91_P_0_LEN_0 */ |
6324 | serge | 10915 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10916 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, |
||
5221 | serge | 10917 | }, |
10918 | { |
||
6324 | serge | 10919 | /* VEX_W_0F91_P_2_LEN_0 */ |
10920 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
||
10921 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, |
||
10922 | }, |
||
10923 | { |
||
5221 | serge | 10924 | /* VEX_W_0F92_P_0_LEN_0 */ |
6324 | serge | 10925 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
5221 | serge | 10926 | }, |
10927 | { |
||
6324 | serge | 10928 | /* VEX_W_0F92_P_2_LEN_0 */ |
10929 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
||
10930 | }, |
||
10931 | { |
||
10932 | /* VEX_W_0F92_P_3_LEN_0 */ |
||
10933 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
||
10934 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, |
||
10935 | }, |
||
10936 | { |
||
5221 | serge | 10937 | /* VEX_W_0F93_P_0_LEN_0 */ |
6324 | serge | 10938 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
5221 | serge | 10939 | }, |
10940 | { |
||
6324 | serge | 10941 | /* VEX_W_0F93_P_2_LEN_0 */ |
10942 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
||
10943 | }, |
||
10944 | { |
||
10945 | /* VEX_W_0F93_P_3_LEN_0 */ |
||
10946 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
||
10947 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, |
||
10948 | }, |
||
10949 | { |
||
5221 | serge | 10950 | /* VEX_W_0F98_P_0_LEN_0 */ |
6324 | serge | 10951 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10952 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, |
||
5221 | serge | 10953 | }, |
10954 | { |
||
6324 | serge | 10955 | /* VEX_W_0F98_P_2_LEN_0 */ |
10956 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
||
10957 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, |
||
10958 | }, |
||
10959 | { |
||
10960 | /* VEX_W_0F99_P_0_LEN_0 */ |
||
10961 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
||
10962 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, |
||
10963 | }, |
||
10964 | { |
||
10965 | /* VEX_W_0F99_P_2_LEN_0 */ |
||
10966 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
||
10967 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, |
||
10968 | }, |
||
10969 | { |
||
5221 | serge | 10970 | /* VEX_W_0FAE_R_2_M_0 */ |
6324 | serge | 10971 | { "vldmxcsr", { Md }, 0 }, |
5221 | serge | 10972 | }, |
10973 | { |
||
10974 | /* VEX_W_0FAE_R_3_M_0 */ |
||
6324 | serge | 10975 | { "vstmxcsr", { Md }, 0 }, |
5221 | serge | 10976 | }, |
10977 | { |
||
10978 | /* VEX_W_0FC2_P_0 */ |
||
6324 | serge | 10979 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5221 | serge | 10980 | }, |
10981 | { |
||
10982 | /* VEX_W_0FC2_P_1 */ |
||
6324 | serge | 10983 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
5221 | serge | 10984 | }, |
10985 | { |
||
10986 | /* VEX_W_0FC2_P_2 */ |
||
6324 | serge | 10987 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
5221 | serge | 10988 | }, |
10989 | { |
||
10990 | /* VEX_W_0FC2_P_3 */ |
||
6324 | serge | 10991 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
5221 | serge | 10992 | }, |
10993 | { |
||
10994 | /* VEX_W_0FC4_P_2 */ |
||
6324 | serge | 10995 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
5221 | serge | 10996 | }, |
10997 | { |
||
10998 | /* VEX_W_0FC5_P_2 */ |
||
6324 | serge | 10999 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
5221 | serge | 11000 | }, |
11001 | { |
||
11002 | /* VEX_W_0FD0_P_2 */ |
||
6324 | serge | 11003 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11004 | }, |
11005 | { |
||
11006 | /* VEX_W_0FD0_P_3 */ |
||
6324 | serge | 11007 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11008 | }, |
11009 | { |
||
11010 | /* VEX_W_0FD1_P_2 */ |
||
6324 | serge | 11011 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11012 | }, |
11013 | { |
||
11014 | /* VEX_W_0FD2_P_2 */ |
||
6324 | serge | 11015 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11016 | }, |
11017 | { |
||
11018 | /* VEX_W_0FD3_P_2 */ |
||
6324 | serge | 11019 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11020 | }, |
11021 | { |
||
11022 | /* VEX_W_0FD4_P_2 */ |
||
6324 | serge | 11023 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11024 | }, |
11025 | { |
||
11026 | /* VEX_W_0FD5_P_2 */ |
||
6324 | serge | 11027 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11028 | }, |
11029 | { |
||
11030 | /* VEX_W_0FD6_P_2 */ |
||
6324 | serge | 11031 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
5221 | serge | 11032 | }, |
11033 | { |
||
11034 | /* VEX_W_0FD7_P_2_M_1 */ |
||
6324 | serge | 11035 | { "vpmovmskb", { Gdq, XS }, 0 }, |
5221 | serge | 11036 | }, |
11037 | { |
||
11038 | /* VEX_W_0FD8_P_2 */ |
||
6324 | serge | 11039 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11040 | }, |
11041 | { |
||
11042 | /* VEX_W_0FD9_P_2 */ |
||
6324 | serge | 11043 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11044 | }, |
11045 | { |
||
11046 | /* VEX_W_0FDA_P_2 */ |
||
6324 | serge | 11047 | { "vpminub", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11048 | }, |
11049 | { |
||
11050 | /* VEX_W_0FDB_P_2 */ |
||
6324 | serge | 11051 | { "vpand", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11052 | }, |
11053 | { |
||
11054 | /* VEX_W_0FDC_P_2 */ |
||
6324 | serge | 11055 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11056 | }, |
11057 | { |
||
11058 | /* VEX_W_0FDD_P_2 */ |
||
6324 | serge | 11059 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11060 | }, |
11061 | { |
||
11062 | /* VEX_W_0FDE_P_2 */ |
||
6324 | serge | 11063 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11064 | }, |
11065 | { |
||
11066 | /* VEX_W_0FDF_P_2 */ |
||
6324 | serge | 11067 | { "vpandn", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11068 | }, |
11069 | { |
||
11070 | /* VEX_W_0FE0_P_2 */ |
||
6324 | serge | 11071 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11072 | }, |
11073 | { |
||
11074 | /* VEX_W_0FE1_P_2 */ |
||
6324 | serge | 11075 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11076 | }, |
11077 | { |
||
11078 | /* VEX_W_0FE2_P_2 */ |
||
6324 | serge | 11079 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11080 | }, |
11081 | { |
||
11082 | /* VEX_W_0FE3_P_2 */ |
||
6324 | serge | 11083 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11084 | }, |
11085 | { |
||
11086 | /* VEX_W_0FE4_P_2 */ |
||
6324 | serge | 11087 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11088 | }, |
11089 | { |
||
11090 | /* VEX_W_0FE5_P_2 */ |
||
6324 | serge | 11091 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11092 | }, |
11093 | { |
||
11094 | /* VEX_W_0FE6_P_1 */ |
||
6324 | serge | 11095 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5221 | serge | 11096 | }, |
11097 | { |
||
11098 | /* VEX_W_0FE6_P_2 */ |
||
6324 | serge | 11099 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
5221 | serge | 11100 | }, |
11101 | { |
||
11102 | /* VEX_W_0FE6_P_3 */ |
||
6324 | serge | 11103 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
5221 | serge | 11104 | }, |
11105 | { |
||
11106 | /* VEX_W_0FE7_P_2_M_0 */ |
||
6324 | serge | 11107 | { "vmovntdq", { Mx, XM }, 0 }, |
5221 | serge | 11108 | }, |
11109 | { |
||
11110 | /* VEX_W_0FE8_P_2 */ |
||
6324 | serge | 11111 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11112 | }, |
11113 | { |
||
11114 | /* VEX_W_0FE9_P_2 */ |
||
6324 | serge | 11115 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11116 | }, |
11117 | { |
||
11118 | /* VEX_W_0FEA_P_2 */ |
||
6324 | serge | 11119 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11120 | }, |
11121 | { |
||
11122 | /* VEX_W_0FEB_P_2 */ |
||
6324 | serge | 11123 | { "vpor", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11124 | }, |
11125 | { |
||
11126 | /* VEX_W_0FEC_P_2 */ |
||
6324 | serge | 11127 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11128 | }, |
11129 | { |
||
11130 | /* VEX_W_0FED_P_2 */ |
||
6324 | serge | 11131 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11132 | }, |
11133 | { |
||
11134 | /* VEX_W_0FEE_P_2 */ |
||
6324 | serge | 11135 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11136 | }, |
11137 | { |
||
11138 | /* VEX_W_0FEF_P_2 */ |
||
6324 | serge | 11139 | { "vpxor", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11140 | }, |
11141 | { |
||
11142 | /* VEX_W_0FF0_P_3_M_0 */ |
||
6324 | serge | 11143 | { "vlddqu", { XM, M }, 0 }, |
5221 | serge | 11144 | }, |
11145 | { |
||
11146 | /* VEX_W_0FF1_P_2 */ |
||
6324 | serge | 11147 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11148 | }, |
11149 | { |
||
11150 | /* VEX_W_0FF2_P_2 */ |
||
6324 | serge | 11151 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11152 | }, |
11153 | { |
||
11154 | /* VEX_W_0FF3_P_2 */ |
||
6324 | serge | 11155 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 11156 | }, |
11157 | { |
||
11158 | /* VEX_W_0FF4_P_2 */ |
||
6324 | serge | 11159 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11160 | }, |
11161 | { |
||
11162 | /* VEX_W_0FF5_P_2 */ |
||
6324 | serge | 11163 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11164 | }, |
11165 | { |
||
11166 | /* VEX_W_0FF6_P_2 */ |
||
6324 | serge | 11167 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11168 | }, |
11169 | { |
||
11170 | /* VEX_W_0FF7_P_2 */ |
||
6324 | serge | 11171 | { "vmaskmovdqu", { XM, XS }, 0 }, |
5221 | serge | 11172 | }, |
11173 | { |
||
11174 | /* VEX_W_0FF8_P_2 */ |
||
6324 | serge | 11175 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11176 | }, |
11177 | { |
||
11178 | /* VEX_W_0FF9_P_2 */ |
||
6324 | serge | 11179 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11180 | }, |
11181 | { |
||
11182 | /* VEX_W_0FFA_P_2 */ |
||
6324 | serge | 11183 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11184 | }, |
11185 | { |
||
11186 | /* VEX_W_0FFB_P_2 */ |
||
6324 | serge | 11187 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11188 | }, |
11189 | { |
||
11190 | /* VEX_W_0FFC_P_2 */ |
||
6324 | serge | 11191 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11192 | }, |
11193 | { |
||
11194 | /* VEX_W_0FFD_P_2 */ |
||
6324 | serge | 11195 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11196 | }, |
11197 | { |
||
11198 | /* VEX_W_0FFE_P_2 */ |
||
6324 | serge | 11199 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11200 | }, |
11201 | { |
||
11202 | /* VEX_W_0F3800_P_2 */ |
||
6324 | serge | 11203 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11204 | }, |
11205 | { |
||
11206 | /* VEX_W_0F3801_P_2 */ |
||
6324 | serge | 11207 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11208 | }, |
11209 | { |
||
11210 | /* VEX_W_0F3802_P_2 */ |
||
6324 | serge | 11211 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11212 | }, |
11213 | { |
||
11214 | /* VEX_W_0F3803_P_2 */ |
||
6324 | serge | 11215 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11216 | }, |
11217 | { |
||
11218 | /* VEX_W_0F3804_P_2 */ |
||
6324 | serge | 11219 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11220 | }, |
11221 | { |
||
11222 | /* VEX_W_0F3805_P_2 */ |
||
6324 | serge | 11223 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11224 | }, |
11225 | { |
||
11226 | /* VEX_W_0F3806_P_2 */ |
||
6324 | serge | 11227 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11228 | }, |
11229 | { |
||
11230 | /* VEX_W_0F3807_P_2 */ |
||
6324 | serge | 11231 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11232 | }, |
11233 | { |
||
11234 | /* VEX_W_0F3808_P_2 */ |
||
6324 | serge | 11235 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11236 | }, |
11237 | { |
||
11238 | /* VEX_W_0F3809_P_2 */ |
||
6324 | serge | 11239 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11240 | }, |
11241 | { |
||
11242 | /* VEX_W_0F380A_P_2 */ |
||
6324 | serge | 11243 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11244 | }, |
11245 | { |
||
11246 | /* VEX_W_0F380B_P_2 */ |
||
6324 | serge | 11247 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11248 | }, |
11249 | { |
||
11250 | /* VEX_W_0F380C_P_2 */ |
||
6324 | serge | 11251 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11252 | }, |
11253 | { |
||
11254 | /* VEX_W_0F380D_P_2 */ |
||
6324 | serge | 11255 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11256 | }, |
11257 | { |
||
11258 | /* VEX_W_0F380E_P_2 */ |
||
6324 | serge | 11259 | { "vtestps", { XM, EXx }, 0 }, |
5221 | serge | 11260 | }, |
11261 | { |
||
11262 | /* VEX_W_0F380F_P_2 */ |
||
6324 | serge | 11263 | { "vtestpd", { XM, EXx }, 0 }, |
5221 | serge | 11264 | }, |
11265 | { |
||
11266 | /* VEX_W_0F3816_P_2 */ |
||
6324 | serge | 11267 | { "vpermps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11268 | }, |
11269 | { |
||
11270 | /* VEX_W_0F3817_P_2 */ |
||
6324 | serge | 11271 | { "vptest", { XM, EXx }, 0 }, |
5221 | serge | 11272 | }, |
11273 | { |
||
11274 | /* VEX_W_0F3818_P_2 */ |
||
6324 | serge | 11275 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
5221 | serge | 11276 | }, |
11277 | { |
||
11278 | /* VEX_W_0F3819_P_2 */ |
||
6324 | serge | 11279 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
5221 | serge | 11280 | }, |
11281 | { |
||
11282 | /* VEX_W_0F381A_P_2_M_0 */ |
||
6324 | serge | 11283 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
5221 | serge | 11284 | }, |
11285 | { |
||
11286 | /* VEX_W_0F381C_P_2 */ |
||
6324 | serge | 11287 | { "vpabsb", { XM, EXx }, 0 }, |
5221 | serge | 11288 | }, |
11289 | { |
||
11290 | /* VEX_W_0F381D_P_2 */ |
||
6324 | serge | 11291 | { "vpabsw", { XM, EXx }, 0 }, |
5221 | serge | 11292 | }, |
11293 | { |
||
11294 | /* VEX_W_0F381E_P_2 */ |
||
6324 | serge | 11295 | { "vpabsd", { XM, EXx }, 0 }, |
5221 | serge | 11296 | }, |
11297 | { |
||
11298 | /* VEX_W_0F3820_P_2 */ |
||
6324 | serge | 11299 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
5221 | serge | 11300 | }, |
11301 | { |
||
11302 | /* VEX_W_0F3821_P_2 */ |
||
6324 | serge | 11303 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
5221 | serge | 11304 | }, |
11305 | { |
||
11306 | /* VEX_W_0F3822_P_2 */ |
||
6324 | serge | 11307 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
5221 | serge | 11308 | }, |
11309 | { |
||
11310 | /* VEX_W_0F3823_P_2 */ |
||
6324 | serge | 11311 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
5221 | serge | 11312 | }, |
11313 | { |
||
11314 | /* VEX_W_0F3824_P_2 */ |
||
6324 | serge | 11315 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
5221 | serge | 11316 | }, |
11317 | { |
||
11318 | /* VEX_W_0F3825_P_2 */ |
||
6324 | serge | 11319 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
5221 | serge | 11320 | }, |
11321 | { |
||
11322 | /* VEX_W_0F3828_P_2 */ |
||
6324 | serge | 11323 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11324 | }, |
11325 | { |
||
11326 | /* VEX_W_0F3829_P_2 */ |
||
6324 | serge | 11327 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11328 | }, |
11329 | { |
||
11330 | /* VEX_W_0F382A_P_2_M_0 */ |
||
6324 | serge | 11331 | { "vmovntdqa", { XM, Mx }, 0 }, |
5221 | serge | 11332 | }, |
11333 | { |
||
11334 | /* VEX_W_0F382B_P_2 */ |
||
6324 | serge | 11335 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11336 | }, |
11337 | { |
||
11338 | /* VEX_W_0F382C_P_2_M_0 */ |
||
6324 | serge | 11339 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
5221 | serge | 11340 | }, |
11341 | { |
||
11342 | /* VEX_W_0F382D_P_2_M_0 */ |
||
6324 | serge | 11343 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
5221 | serge | 11344 | }, |
11345 | { |
||
11346 | /* VEX_W_0F382E_P_2_M_0 */ |
||
6324 | serge | 11347 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
5221 | serge | 11348 | }, |
11349 | { |
||
11350 | /* VEX_W_0F382F_P_2_M_0 */ |
||
6324 | serge | 11351 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
5221 | serge | 11352 | }, |
11353 | { |
||
11354 | /* VEX_W_0F3830_P_2 */ |
||
6324 | serge | 11355 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
5221 | serge | 11356 | }, |
11357 | { |
||
11358 | /* VEX_W_0F3831_P_2 */ |
||
6324 | serge | 11359 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
5221 | serge | 11360 | }, |
11361 | { |
||
11362 | /* VEX_W_0F3832_P_2 */ |
||
6324 | serge | 11363 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
5221 | serge | 11364 | }, |
11365 | { |
||
11366 | /* VEX_W_0F3833_P_2 */ |
||
6324 | serge | 11367 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
5221 | serge | 11368 | }, |
11369 | { |
||
11370 | /* VEX_W_0F3834_P_2 */ |
||
6324 | serge | 11371 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
5221 | serge | 11372 | }, |
11373 | { |
||
11374 | /* VEX_W_0F3835_P_2 */ |
||
6324 | serge | 11375 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
5221 | serge | 11376 | }, |
11377 | { |
||
11378 | /* VEX_W_0F3836_P_2 */ |
||
6324 | serge | 11379 | { "vpermd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11380 | }, |
11381 | { |
||
11382 | /* VEX_W_0F3837_P_2 */ |
||
6324 | serge | 11383 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11384 | }, |
11385 | { |
||
11386 | /* VEX_W_0F3838_P_2 */ |
||
6324 | serge | 11387 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11388 | }, |
11389 | { |
||
11390 | /* VEX_W_0F3839_P_2 */ |
||
6324 | serge | 11391 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11392 | }, |
11393 | { |
||
11394 | /* VEX_W_0F383A_P_2 */ |
||
6324 | serge | 11395 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11396 | }, |
11397 | { |
||
11398 | /* VEX_W_0F383B_P_2 */ |
||
6324 | serge | 11399 | { "vpminud", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11400 | }, |
11401 | { |
||
11402 | /* VEX_W_0F383C_P_2 */ |
||
6324 | serge | 11403 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11404 | }, |
11405 | { |
||
11406 | /* VEX_W_0F383D_P_2 */ |
||
6324 | serge | 11407 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11408 | }, |
11409 | { |
||
11410 | /* VEX_W_0F383E_P_2 */ |
||
6324 | serge | 11411 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11412 | }, |
11413 | { |
||
11414 | /* VEX_W_0F383F_P_2 */ |
||
6324 | serge | 11415 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11416 | }, |
11417 | { |
||
11418 | /* VEX_W_0F3840_P_2 */ |
||
6324 | serge | 11419 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11420 | }, |
11421 | { |
||
11422 | /* VEX_W_0F3841_P_2 */ |
||
6324 | serge | 11423 | { "vphminposuw", { XM, EXx }, 0 }, |
5221 | serge | 11424 | }, |
11425 | { |
||
11426 | /* VEX_W_0F3846_P_2 */ |
||
6324 | serge | 11427 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 11428 | }, |
11429 | { |
||
11430 | /* VEX_W_0F3858_P_2 */ |
||
6324 | serge | 11431 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
5221 | serge | 11432 | }, |
11433 | { |
||
11434 | /* VEX_W_0F3859_P_2 */ |
||
6324 | serge | 11435 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
5221 | serge | 11436 | }, |
11437 | { |
||
11438 | /* VEX_W_0F385A_P_2_M_0 */ |
||
6324 | serge | 11439 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
5221 | serge | 11440 | }, |
11441 | { |
||
11442 | /* VEX_W_0F3878_P_2 */ |
||
6324 | serge | 11443 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
5221 | serge | 11444 | }, |
11445 | { |
||
11446 | /* VEX_W_0F3879_P_2 */ |
||
6324 | serge | 11447 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
5221 | serge | 11448 | }, |
11449 | { |
||
11450 | /* VEX_W_0F38DB_P_2 */ |
||
6324 | serge | 11451 | { "vaesimc", { XM, EXx }, 0 }, |
5221 | serge | 11452 | }, |
11453 | { |
||
11454 | /* VEX_W_0F38DC_P_2 */ |
||
6324 | serge | 11455 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
5221 | serge | 11456 | }, |
11457 | { |
||
11458 | /* VEX_W_0F38DD_P_2 */ |
||
6324 | serge | 11459 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
5221 | serge | 11460 | }, |
11461 | { |
||
11462 | /* VEX_W_0F38DE_P_2 */ |
||
6324 | serge | 11463 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
5221 | serge | 11464 | }, |
11465 | { |
||
11466 | /* VEX_W_0F38DF_P_2 */ |
||
6324 | serge | 11467 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
5221 | serge | 11468 | }, |
11469 | { |
||
11470 | /* VEX_W_0F3A00_P_2 */ |
||
11471 | { Bad_Opcode }, |
||
6324 | serge | 11472 | { "vpermq", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11473 | }, |
11474 | { |
||
11475 | /* VEX_W_0F3A01_P_2 */ |
||
11476 | { Bad_Opcode }, |
||
6324 | serge | 11477 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11478 | }, |
11479 | { |
||
11480 | /* VEX_W_0F3A02_P_2 */ |
||
6324 | serge | 11481 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11482 | }, |
11483 | { |
||
11484 | /* VEX_W_0F3A04_P_2 */ |
||
6324 | serge | 11485 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11486 | }, |
11487 | { |
||
11488 | /* VEX_W_0F3A05_P_2 */ |
||
6324 | serge | 11489 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11490 | }, |
11491 | { |
||
11492 | /* VEX_W_0F3A06_P_2 */ |
||
6324 | serge | 11493 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
5221 | serge | 11494 | }, |
11495 | { |
||
11496 | /* VEX_W_0F3A08_P_2 */ |
||
6324 | serge | 11497 | { "vroundps", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11498 | }, |
11499 | { |
||
11500 | /* VEX_W_0F3A09_P_2 */ |
||
6324 | serge | 11501 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11502 | }, |
11503 | { |
||
11504 | /* VEX_W_0F3A0A_P_2 */ |
||
6324 | serge | 11505 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
5221 | serge | 11506 | }, |
11507 | { |
||
11508 | /* VEX_W_0F3A0B_P_2 */ |
||
6324 | serge | 11509 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
5221 | serge | 11510 | }, |
11511 | { |
||
11512 | /* VEX_W_0F3A0C_P_2 */ |
||
6324 | serge | 11513 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11514 | }, |
11515 | { |
||
11516 | /* VEX_W_0F3A0D_P_2 */ |
||
6324 | serge | 11517 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11518 | }, |
11519 | { |
||
11520 | /* VEX_W_0F3A0E_P_2 */ |
||
6324 | serge | 11521 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11522 | }, |
11523 | { |
||
11524 | /* VEX_W_0F3A0F_P_2 */ |
||
6324 | serge | 11525 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11526 | }, |
11527 | { |
||
11528 | /* VEX_W_0F3A14_P_2 */ |
||
6324 | serge | 11529 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
5221 | serge | 11530 | }, |
11531 | { |
||
11532 | /* VEX_W_0F3A15_P_2 */ |
||
6324 | serge | 11533 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
5221 | serge | 11534 | }, |
11535 | { |
||
11536 | /* VEX_W_0F3A18_P_2 */ |
||
6324 | serge | 11537 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
5221 | serge | 11538 | }, |
11539 | { |
||
11540 | /* VEX_W_0F3A19_P_2 */ |
||
6324 | serge | 11541 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
5221 | serge | 11542 | }, |
11543 | { |
||
11544 | /* VEX_W_0F3A20_P_2 */ |
||
6324 | serge | 11545 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
5221 | serge | 11546 | }, |
11547 | { |
||
11548 | /* VEX_W_0F3A21_P_2 */ |
||
6324 | serge | 11549 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
5221 | serge | 11550 | }, |
11551 | { |
||
6324 | serge | 11552 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
11553 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
||
11554 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, |
||
5221 | serge | 11555 | }, |
11556 | { |
||
6324 | serge | 11557 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
11558 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
||
11559 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, |
||
5221 | serge | 11560 | }, |
11561 | { |
||
6324 | serge | 11562 | /* VEX_W_0F3A32_P_2_LEN_0 */ |
11563 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
||
11564 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, |
||
11565 | }, |
||
11566 | { |
||
11567 | /* VEX_W_0F3A33_P_2_LEN_0 */ |
||
11568 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
||
11569 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, |
||
11570 | }, |
||
11571 | { |
||
5221 | serge | 11572 | /* VEX_W_0F3A38_P_2 */ |
6324 | serge | 11573 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
5221 | serge | 11574 | }, |
11575 | { |
||
11576 | /* VEX_W_0F3A39_P_2 */ |
||
6324 | serge | 11577 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
5221 | serge | 11578 | }, |
11579 | { |
||
11580 | /* VEX_W_0F3A40_P_2 */ |
||
6324 | serge | 11581 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11582 | }, |
11583 | { |
||
11584 | /* VEX_W_0F3A41_P_2 */ |
||
6324 | serge | 11585 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
5221 | serge | 11586 | }, |
11587 | { |
||
11588 | /* VEX_W_0F3A42_P_2 */ |
||
6324 | serge | 11589 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 11590 | }, |
11591 | { |
||
11592 | /* VEX_W_0F3A44_P_2 */ |
||
6324 | serge | 11593 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
5221 | serge | 11594 | }, |
11595 | { |
||
11596 | /* VEX_W_0F3A46_P_2 */ |
||
6324 | serge | 11597 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
5221 | serge | 11598 | }, |
11599 | { |
||
11600 | /* VEX_W_0F3A48_P_2 */ |
||
6324 | serge | 11601 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11602 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
||
5221 | serge | 11603 | }, |
11604 | { |
||
11605 | /* VEX_W_0F3A49_P_2 */ |
||
6324 | serge | 11606 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11607 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
||
5221 | serge | 11608 | }, |
11609 | { |
||
11610 | /* VEX_W_0F3A4A_P_2 */ |
||
6324 | serge | 11611 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
5221 | serge | 11612 | }, |
11613 | { |
||
11614 | /* VEX_W_0F3A4B_P_2 */ |
||
6324 | serge | 11615 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
5221 | serge | 11616 | }, |
11617 | { |
||
11618 | /* VEX_W_0F3A4C_P_2 */ |
||
6324 | serge | 11619 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
5221 | serge | 11620 | }, |
11621 | { |
||
11622 | /* VEX_W_0F3A60_P_2 */ |
||
6324 | serge | 11623 | { "vpcmpestrm", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11624 | }, |
11625 | { |
||
11626 | /* VEX_W_0F3A61_P_2 */ |
||
6324 | serge | 11627 | { "vpcmpestri", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11628 | }, |
11629 | { |
||
11630 | /* VEX_W_0F3A62_P_2 */ |
||
6324 | serge | 11631 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11632 | }, |
11633 | { |
||
11634 | /* VEX_W_0F3A63_P_2 */ |
||
6324 | serge | 11635 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11636 | }, |
11637 | { |
||
11638 | /* VEX_W_0F3ADF_P_2 */ |
||
6324 | serge | 11639 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
5221 | serge | 11640 | }, |
11641 | #define NEED_VEX_W_TABLE |
||
11642 | #include "i386-dis-evex.h" |
||
11643 | #undef NEED_VEX_W_TABLE |
||
11644 | }; |
||
11645 | |||
11646 | static const struct dis386 mod_table[][2] = { |
||
11647 | { |
||
11648 | /* MOD_8D */ |
||
6324 | serge | 11649 | { "leaS", { Gv, M }, 0 }, |
5221 | serge | 11650 | }, |
11651 | { |
||
11652 | /* MOD_C6_REG_7 */ |
||
11653 | { Bad_Opcode }, |
||
11654 | { RM_TABLE (RM_C6_REG_7) }, |
||
11655 | }, |
||
11656 | { |
||
11657 | /* MOD_C7_REG_7 */ |
||
11658 | { Bad_Opcode }, |
||
11659 | { RM_TABLE (RM_C7_REG_7) }, |
||
11660 | }, |
||
11661 | { |
||
6324 | serge | 11662 | /* MOD_FF_REG_3 */ |
11663 | { "Jcall^", { indirEp }, 0 }, |
||
11664 | }, |
||
11665 | { |
||
11666 | /* MOD_FF_REG_5 */ |
||
11667 | { "Jjmp^", { indirEp }, 0 }, |
||
11668 | }, |
||
11669 | { |
||
5221 | serge | 11670 | /* MOD_0F01_REG_0 */ |
11671 | { X86_64_TABLE (X86_64_0F01_REG_0) }, |
||
11672 | { RM_TABLE (RM_0F01_REG_0) }, |
||
11673 | }, |
||
11674 | { |
||
11675 | /* MOD_0F01_REG_1 */ |
||
11676 | { X86_64_TABLE (X86_64_0F01_REG_1) }, |
||
11677 | { RM_TABLE (RM_0F01_REG_1) }, |
||
11678 | }, |
||
11679 | { |
||
11680 | /* MOD_0F01_REG_2 */ |
||
11681 | { X86_64_TABLE (X86_64_0F01_REG_2) }, |
||
11682 | { RM_TABLE (RM_0F01_REG_2) }, |
||
11683 | }, |
||
11684 | { |
||
11685 | /* MOD_0F01_REG_3 */ |
||
11686 | { X86_64_TABLE (X86_64_0F01_REG_3) }, |
||
11687 | { RM_TABLE (RM_0F01_REG_3) }, |
||
11688 | }, |
||
11689 | { |
||
6324 | serge | 11690 | /* MOD_0F01_REG_5 */ |
11691 | { Bad_Opcode }, |
||
11692 | { RM_TABLE (RM_0F01_REG_5) }, |
||
11693 | }, |
||
11694 | { |
||
5221 | serge | 11695 | /* MOD_0F01_REG_7 */ |
6324 | serge | 11696 | { "invlpg", { Mb }, 0 }, |
5221 | serge | 11697 | { RM_TABLE (RM_0F01_REG_7) }, |
11698 | }, |
||
11699 | { |
||
11700 | /* MOD_0F12_PREFIX_0 */ |
||
6324 | serge | 11701 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11702 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, |
||
5221 | serge | 11703 | }, |
11704 | { |
||
11705 | /* MOD_0F13 */ |
||
6324 | serge | 11706 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
5221 | serge | 11707 | }, |
11708 | { |
||
11709 | /* MOD_0F16_PREFIX_0 */ |
||
6324 | serge | 11710 | { "movhps", { XM, EXq }, 0 }, |
11711 | { "movlhps", { XM, EXq }, 0 }, |
||
5221 | serge | 11712 | }, |
11713 | { |
||
11714 | /* MOD_0F17 */ |
||
6324 | serge | 11715 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
5221 | serge | 11716 | }, |
11717 | { |
||
11718 | /* MOD_0F18_REG_0 */ |
||
6324 | serge | 11719 | { "prefetchnta", { Mb }, 0 }, |
5221 | serge | 11720 | }, |
11721 | { |
||
11722 | /* MOD_0F18_REG_1 */ |
||
6324 | serge | 11723 | { "prefetcht0", { Mb }, 0 }, |
5221 | serge | 11724 | }, |
11725 | { |
||
11726 | /* MOD_0F18_REG_2 */ |
||
6324 | serge | 11727 | { "prefetcht1", { Mb }, 0 }, |
5221 | serge | 11728 | }, |
11729 | { |
||
11730 | /* MOD_0F18_REG_3 */ |
||
6324 | serge | 11731 | { "prefetcht2", { Mb }, 0 }, |
5221 | serge | 11732 | }, |
11733 | { |
||
11734 | /* MOD_0F18_REG_4 */ |
||
6324 | serge | 11735 | { "nop/reserved", { Mb }, 0 }, |
5221 | serge | 11736 | }, |
11737 | { |
||
11738 | /* MOD_0F18_REG_5 */ |
||
6324 | serge | 11739 | { "nop/reserved", { Mb }, 0 }, |
5221 | serge | 11740 | }, |
11741 | { |
||
11742 | /* MOD_0F18_REG_6 */ |
||
6324 | serge | 11743 | { "nop/reserved", { Mb }, 0 }, |
5221 | serge | 11744 | }, |
11745 | { |
||
11746 | /* MOD_0F18_REG_7 */ |
||
6324 | serge | 11747 | { "nop/reserved", { Mb }, 0 }, |
5221 | serge | 11748 | }, |
11749 | { |
||
11750 | /* MOD_0F1A_PREFIX_0 */ |
||
6324 | serge | 11751 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11752 | { "nopQ", { Ev }, 0 }, |
||
5221 | serge | 11753 | }, |
11754 | { |
||
11755 | /* MOD_0F1B_PREFIX_0 */ |
||
6324 | serge | 11756 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11757 | { "nopQ", { Ev }, 0 }, |
||
5221 | serge | 11758 | }, |
11759 | { |
||
11760 | /* MOD_0F1B_PREFIX_1 */ |
||
6324 | serge | 11761 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11762 | { "nopQ", { Ev }, 0 }, |
||
5221 | serge | 11763 | }, |
11764 | { |
||
11765 | /* MOD_0F24 */ |
||
11766 | { Bad_Opcode }, |
||
6324 | serge | 11767 | { "movL", { Rd, Td }, 0 }, |
5221 | serge | 11768 | }, |
11769 | { |
||
11770 | /* MOD_0F26 */ |
||
11771 | { Bad_Opcode }, |
||
6324 | serge | 11772 | { "movL", { Td, Rd }, 0 }, |
5221 | serge | 11773 | }, |
11774 | { |
||
11775 | /* MOD_0F2B_PREFIX_0 */ |
||
6324 | serge | 11776 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
5221 | serge | 11777 | }, |
11778 | { |
||
11779 | /* MOD_0F2B_PREFIX_1 */ |
||
6324 | serge | 11780 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
5221 | serge | 11781 | }, |
11782 | { |
||
11783 | /* MOD_0F2B_PREFIX_2 */ |
||
6324 | serge | 11784 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
5221 | serge | 11785 | }, |
11786 | { |
||
11787 | /* MOD_0F2B_PREFIX_3 */ |
||
6324 | serge | 11788 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
5221 | serge | 11789 | }, |
11790 | { |
||
11791 | /* MOD_0F51 */ |
||
11792 | { Bad_Opcode }, |
||
6324 | serge | 11793 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
5221 | serge | 11794 | }, |
11795 | { |
||
11796 | /* MOD_0F71_REG_2 */ |
||
11797 | { Bad_Opcode }, |
||
6324 | serge | 11798 | { "psrlw", { MS, Ib }, 0 }, |
5221 | serge | 11799 | }, |
11800 | { |
||
11801 | /* MOD_0F71_REG_4 */ |
||
11802 | { Bad_Opcode }, |
||
6324 | serge | 11803 | { "psraw", { MS, Ib }, 0 }, |
5221 | serge | 11804 | }, |
11805 | { |
||
11806 | /* MOD_0F71_REG_6 */ |
||
11807 | { Bad_Opcode }, |
||
6324 | serge | 11808 | { "psllw", { MS, Ib }, 0 }, |
5221 | serge | 11809 | }, |
11810 | { |
||
11811 | /* MOD_0F72_REG_2 */ |
||
11812 | { Bad_Opcode }, |
||
6324 | serge | 11813 | { "psrld", { MS, Ib }, 0 }, |
5221 | serge | 11814 | }, |
11815 | { |
||
11816 | /* MOD_0F72_REG_4 */ |
||
11817 | { Bad_Opcode }, |
||
6324 | serge | 11818 | { "psrad", { MS, Ib }, 0 }, |
5221 | serge | 11819 | }, |
11820 | { |
||
11821 | /* MOD_0F72_REG_6 */ |
||
11822 | { Bad_Opcode }, |
||
6324 | serge | 11823 | { "pslld", { MS, Ib }, 0 }, |
5221 | serge | 11824 | }, |
11825 | { |
||
11826 | /* MOD_0F73_REG_2 */ |
||
11827 | { Bad_Opcode }, |
||
6324 | serge | 11828 | { "psrlq", { MS, Ib }, 0 }, |
5221 | serge | 11829 | }, |
11830 | { |
||
11831 | /* MOD_0F73_REG_3 */ |
||
11832 | { Bad_Opcode }, |
||
11833 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
||
11834 | }, |
||
11835 | { |
||
11836 | /* MOD_0F73_REG_6 */ |
||
11837 | { Bad_Opcode }, |
||
6324 | serge | 11838 | { "psllq", { MS, Ib }, 0 }, |
5221 | serge | 11839 | }, |
11840 | { |
||
11841 | /* MOD_0F73_REG_7 */ |
||
11842 | { Bad_Opcode }, |
||
11843 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
||
11844 | }, |
||
11845 | { |
||
11846 | /* MOD_0FAE_REG_0 */ |
||
6324 | serge | 11847 | { "fxsave", { FXSAVE }, 0 }, |
5221 | serge | 11848 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
11849 | }, |
||
11850 | { |
||
11851 | /* MOD_0FAE_REG_1 */ |
||
6324 | serge | 11852 | { "fxrstor", { FXSAVE }, 0 }, |
5221 | serge | 11853 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
11854 | }, |
||
11855 | { |
||
11856 | /* MOD_0FAE_REG_2 */ |
||
6324 | serge | 11857 | { "ldmxcsr", { Md }, 0 }, |
5221 | serge | 11858 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
11859 | }, |
||
11860 | { |
||
11861 | /* MOD_0FAE_REG_3 */ |
||
6324 | serge | 11862 | { "stmxcsr", { Md }, 0 }, |
5221 | serge | 11863 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
11864 | }, |
||
11865 | { |
||
11866 | /* MOD_0FAE_REG_4 */ |
||
6324 | serge | 11867 | { "xsave", { FXSAVE }, 0 }, |
5221 | serge | 11868 | }, |
11869 | { |
||
11870 | /* MOD_0FAE_REG_5 */ |
||
6324 | serge | 11871 | { "xrstor", { FXSAVE }, 0 }, |
5221 | serge | 11872 | { RM_TABLE (RM_0FAE_REG_5) }, |
11873 | }, |
||
11874 | { |
||
11875 | /* MOD_0FAE_REG_6 */ |
||
6324 | serge | 11876 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
5221 | serge | 11877 | { RM_TABLE (RM_0FAE_REG_6) }, |
11878 | }, |
||
11879 | { |
||
11880 | /* MOD_0FAE_REG_7 */ |
||
6324 | serge | 11881 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
5221 | serge | 11882 | { RM_TABLE (RM_0FAE_REG_7) }, |
11883 | }, |
||
11884 | { |
||
11885 | /* MOD_0FB2 */ |
||
6324 | serge | 11886 | { "lssS", { Gv, Mp }, 0 }, |
5221 | serge | 11887 | }, |
11888 | { |
||
11889 | /* MOD_0FB4 */ |
||
6324 | serge | 11890 | { "lfsS", { Gv, Mp }, 0 }, |
5221 | serge | 11891 | }, |
11892 | { |
||
11893 | /* MOD_0FB5 */ |
||
6324 | serge | 11894 | { "lgsS", { Gv, Mp }, 0 }, |
5221 | serge | 11895 | }, |
11896 | { |
||
6324 | serge | 11897 | /* MOD_0FC3 */ |
11898 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, |
||
11899 | }, |
||
11900 | { |
||
11901 | /* MOD_0FC7_REG_3 */ |
||
11902 | { "xrstors", { FXSAVE }, 0 }, |
||
11903 | }, |
||
11904 | { |
||
11905 | /* MOD_0FC7_REG_4 */ |
||
11906 | { "xsavec", { FXSAVE }, 0 }, |
||
11907 | }, |
||
11908 | { |
||
11909 | /* MOD_0FC7_REG_5 */ |
||
11910 | { "xsaves", { FXSAVE }, 0 }, |
||
11911 | }, |
||
11912 | { |
||
5221 | serge | 11913 | /* MOD_0FC7_REG_6 */ |
6324 | serge | 11914 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11915 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } |
||
5221 | serge | 11916 | }, |
11917 | { |
||
11918 | /* MOD_0FC7_REG_7 */ |
||
6324 | serge | 11919 | { "vmptrst", { Mq }, 0 }, |
11920 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
||
5221 | serge | 11921 | }, |
11922 | { |
||
11923 | /* MOD_0FD7 */ |
||
11924 | { Bad_Opcode }, |
||
6324 | serge | 11925 | { "pmovmskb", { Gdq, MS }, 0 }, |
5221 | serge | 11926 | }, |
11927 | { |
||
11928 | /* MOD_0FE7_PREFIX_2 */ |
||
6324 | serge | 11929 | { "movntdq", { Mx, XM }, 0 }, |
5221 | serge | 11930 | }, |
11931 | { |
||
11932 | /* MOD_0FF0_PREFIX_3 */ |
||
6324 | serge | 11933 | { "lddqu", { XM, M }, 0 }, |
5221 | serge | 11934 | }, |
11935 | { |
||
11936 | /* MOD_0F382A_PREFIX_2 */ |
||
6324 | serge | 11937 | { "movntdqa", { XM, Mx }, 0 }, |
5221 | serge | 11938 | }, |
11939 | { |
||
11940 | /* MOD_62_32BIT */ |
||
6324 | serge | 11941 | { "bound{S|}", { Gv, Ma }, 0 }, |
5221 | serge | 11942 | { EVEX_TABLE (EVEX_0F) }, |
11943 | }, |
||
11944 | { |
||
11945 | /* MOD_C4_32BIT */ |
||
6324 | serge | 11946 | { "lesS", { Gv, Mp }, 0 }, |
5221 | serge | 11947 | { VEX_C4_TABLE (VEX_0F) }, |
11948 | }, |
||
11949 | { |
||
11950 | /* MOD_C5_32BIT */ |
||
6324 | serge | 11951 | { "ldsS", { Gv, Mp }, 0 }, |
5221 | serge | 11952 | { VEX_C5_TABLE (VEX_0F) }, |
11953 | }, |
||
11954 | { |
||
11955 | /* MOD_VEX_0F12_PREFIX_0 */ |
||
11956 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, |
||
11957 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, |
||
11958 | }, |
||
11959 | { |
||
11960 | /* MOD_VEX_0F13 */ |
||
11961 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, |
||
11962 | }, |
||
11963 | { |
||
11964 | /* MOD_VEX_0F16_PREFIX_0 */ |
||
11965 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, |
||
11966 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, |
||
11967 | }, |
||
11968 | { |
||
11969 | /* MOD_VEX_0F17 */ |
||
11970 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, |
||
11971 | }, |
||
11972 | { |
||
11973 | /* MOD_VEX_0F2B */ |
||
11974 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, |
||
11975 | }, |
||
11976 | { |
||
6324 | serge | 11977 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ |
11978 | { Bad_Opcode }, |
||
11979 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, |
||
11980 | }, |
||
11981 | { |
||
11982 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ |
||
11983 | { Bad_Opcode }, |
||
11984 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, |
||
11985 | }, |
||
11986 | { |
||
11987 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ |
||
11988 | { Bad_Opcode }, |
||
11989 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, |
||
11990 | }, |
||
11991 | { |
||
11992 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ |
||
11993 | { Bad_Opcode }, |
||
11994 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, |
||
11995 | }, |
||
11996 | { |
||
11997 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ |
||
11998 | { Bad_Opcode }, |
||
11999 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, |
||
12000 | }, |
||
12001 | { |
||
12002 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ |
||
12003 | { Bad_Opcode }, |
||
12004 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, |
||
12005 | }, |
||
12006 | { |
||
12007 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ |
||
12008 | { Bad_Opcode }, |
||
12009 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, |
||
12010 | }, |
||
12011 | { |
||
12012 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ |
||
12013 | { Bad_Opcode }, |
||
12014 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, |
||
12015 | }, |
||
12016 | { |
||
12017 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ |
||
12018 | { Bad_Opcode }, |
||
12019 | { "knotw", { MaskG, MaskR }, 0 }, |
||
12020 | }, |
||
12021 | { |
||
12022 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ |
||
12023 | { Bad_Opcode }, |
||
12024 | { "knotq", { MaskG, MaskR }, 0 }, |
||
12025 | }, |
||
12026 | { |
||
12027 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ |
||
12028 | { Bad_Opcode }, |
||
12029 | { "knotb", { MaskG, MaskR }, 0 }, |
||
12030 | }, |
||
12031 | { |
||
12032 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ |
||
12033 | { Bad_Opcode }, |
||
12034 | { "knotd", { MaskG, MaskR }, 0 }, |
||
12035 | }, |
||
12036 | { |
||
12037 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ |
||
12038 | { Bad_Opcode }, |
||
12039 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, |
||
12040 | }, |
||
12041 | { |
||
12042 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ |
||
12043 | { Bad_Opcode }, |
||
12044 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, |
||
12045 | }, |
||
12046 | { |
||
12047 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ |
||
12048 | { Bad_Opcode }, |
||
12049 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, |
||
12050 | }, |
||
12051 | { |
||
12052 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ |
||
12053 | { Bad_Opcode }, |
||
12054 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, |
||
12055 | }, |
||
12056 | { |
||
12057 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ |
||
12058 | { Bad_Opcode }, |
||
12059 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, |
||
12060 | }, |
||
12061 | { |
||
12062 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ |
||
12063 | { Bad_Opcode }, |
||
12064 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, |
||
12065 | }, |
||
12066 | { |
||
12067 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ |
||
12068 | { Bad_Opcode }, |
||
12069 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, |
||
12070 | }, |
||
12071 | { |
||
12072 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ |
||
12073 | { Bad_Opcode }, |
||
12074 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, |
||
12075 | }, |
||
12076 | { |
||
12077 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ |
||
12078 | { Bad_Opcode }, |
||
12079 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, |
||
12080 | }, |
||
12081 | { |
||
12082 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ |
||
12083 | { Bad_Opcode }, |
||
12084 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, |
||
12085 | }, |
||
12086 | { |
||
12087 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ |
||
12088 | { Bad_Opcode }, |
||
12089 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, |
||
12090 | }, |
||
12091 | { |
||
12092 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ |
||
12093 | { Bad_Opcode }, |
||
12094 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, |
||
12095 | }, |
||
12096 | { |
||
12097 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ |
||
12098 | { Bad_Opcode }, |
||
12099 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, |
||
12100 | }, |
||
12101 | { |
||
12102 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ |
||
12103 | { Bad_Opcode }, |
||
12104 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, |
||
12105 | }, |
||
12106 | { |
||
12107 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ |
||
12108 | { Bad_Opcode }, |
||
12109 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, |
||
12110 | }, |
||
12111 | { |
||
12112 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ |
||
12113 | { Bad_Opcode }, |
||
12114 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, |
||
12115 | }, |
||
12116 | { |
||
12117 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ |
||
12118 | { Bad_Opcode }, |
||
12119 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, |
||
12120 | }, |
||
12121 | { |
||
12122 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ |
||
12123 | { Bad_Opcode }, |
||
12124 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, |
||
12125 | }, |
||
12126 | { |
||
12127 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ |
||
12128 | { Bad_Opcode }, |
||
12129 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, |
||
12130 | }, |
||
12131 | { |
||
5221 | serge | 12132 | /* MOD_VEX_0F50 */ |
12133 | { Bad_Opcode }, |
||
12134 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
||
12135 | }, |
||
12136 | { |
||
12137 | /* MOD_VEX_0F71_REG_2 */ |
||
12138 | { Bad_Opcode }, |
||
12139 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
||
12140 | }, |
||
12141 | { |
||
12142 | /* MOD_VEX_0F71_REG_4 */ |
||
12143 | { Bad_Opcode }, |
||
12144 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
||
12145 | }, |
||
12146 | { |
||
12147 | /* MOD_VEX_0F71_REG_6 */ |
||
12148 | { Bad_Opcode }, |
||
12149 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
||
12150 | }, |
||
12151 | { |
||
12152 | /* MOD_VEX_0F72_REG_2 */ |
||
12153 | { Bad_Opcode }, |
||
12154 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
||
12155 | }, |
||
12156 | { |
||
12157 | /* MOD_VEX_0F72_REG_4 */ |
||
12158 | { Bad_Opcode }, |
||
12159 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
||
12160 | }, |
||
12161 | { |
||
12162 | /* MOD_VEX_0F72_REG_6 */ |
||
12163 | { Bad_Opcode }, |
||
12164 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
||
12165 | }, |
||
12166 | { |
||
12167 | /* MOD_VEX_0F73_REG_2 */ |
||
12168 | { Bad_Opcode }, |
||
12169 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
||
12170 | }, |
||
12171 | { |
||
12172 | /* MOD_VEX_0F73_REG_3 */ |
||
12173 | { Bad_Opcode }, |
||
12174 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
||
12175 | }, |
||
12176 | { |
||
12177 | /* MOD_VEX_0F73_REG_6 */ |
||
12178 | { Bad_Opcode }, |
||
12179 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
||
12180 | }, |
||
12181 | { |
||
12182 | /* MOD_VEX_0F73_REG_7 */ |
||
12183 | { Bad_Opcode }, |
||
12184 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
||
12185 | }, |
||
12186 | { |
||
6324 | serge | 12187 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ |
12188 | { "kmovw", { Ew, MaskG }, 0 }, |
||
12189 | { Bad_Opcode }, |
||
12190 | }, |
||
12191 | { |
||
12192 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ |
||
12193 | { "kmovq", { Eq, MaskG }, 0 }, |
||
12194 | { Bad_Opcode }, |
||
12195 | }, |
||
12196 | { |
||
12197 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ |
||
12198 | { "kmovb", { Eb, MaskG }, 0 }, |
||
12199 | { Bad_Opcode }, |
||
12200 | }, |
||
12201 | { |
||
12202 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ |
||
12203 | { "kmovd", { Ed, MaskG }, 0 }, |
||
12204 | { Bad_Opcode }, |
||
12205 | }, |
||
12206 | { |
||
12207 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ |
||
12208 | { Bad_Opcode }, |
||
12209 | { "kmovw", { MaskG, Rdq }, 0 }, |
||
12210 | }, |
||
12211 | { |
||
12212 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ |
||
12213 | { Bad_Opcode }, |
||
12214 | { "kmovb", { MaskG, Rdq }, 0 }, |
||
12215 | }, |
||
12216 | { |
||
12217 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ |
||
12218 | { Bad_Opcode }, |
||
12219 | { "kmovd", { MaskG, Rdq }, 0 }, |
||
12220 | }, |
||
12221 | { |
||
12222 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ |
||
12223 | { Bad_Opcode }, |
||
12224 | { "kmovq", { MaskG, Rdq }, 0 }, |
||
12225 | }, |
||
12226 | { |
||
12227 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ |
||
12228 | { Bad_Opcode }, |
||
12229 | { "kmovw", { Gdq, MaskR }, 0 }, |
||
12230 | }, |
||
12231 | { |
||
12232 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ |
||
12233 | { Bad_Opcode }, |
||
12234 | { "kmovb", { Gdq, MaskR }, 0 }, |
||
12235 | }, |
||
12236 | { |
||
12237 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ |
||
12238 | { Bad_Opcode }, |
||
12239 | { "kmovd", { Gdq, MaskR }, 0 }, |
||
12240 | }, |
||
12241 | { |
||
12242 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ |
||
12243 | { Bad_Opcode }, |
||
12244 | { "kmovq", { Gdq, MaskR }, 0 }, |
||
12245 | }, |
||
12246 | { |
||
12247 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ |
||
12248 | { Bad_Opcode }, |
||
12249 | { "kortestw", { MaskG, MaskR }, 0 }, |
||
12250 | }, |
||
12251 | { |
||
12252 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ |
||
12253 | { Bad_Opcode }, |
||
12254 | { "kortestq", { MaskG, MaskR }, 0 }, |
||
12255 | }, |
||
12256 | { |
||
12257 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ |
||
12258 | { Bad_Opcode }, |
||
12259 | { "kortestb", { MaskG, MaskR }, 0 }, |
||
12260 | }, |
||
12261 | { |
||
12262 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ |
||
12263 | { Bad_Opcode }, |
||
12264 | { "kortestd", { MaskG, MaskR }, 0 }, |
||
12265 | }, |
||
12266 | { |
||
12267 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ |
||
12268 | { Bad_Opcode }, |
||
12269 | { "ktestw", { MaskG, MaskR }, 0 }, |
||
12270 | }, |
||
12271 | { |
||
12272 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ |
||
12273 | { Bad_Opcode }, |
||
12274 | { "ktestq", { MaskG, MaskR }, 0 }, |
||
12275 | }, |
||
12276 | { |
||
12277 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ |
||
12278 | { Bad_Opcode }, |
||
12279 | { "ktestb", { MaskG, MaskR }, 0 }, |
||
12280 | }, |
||
12281 | { |
||
12282 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ |
||
12283 | { Bad_Opcode }, |
||
12284 | { "ktestd", { MaskG, MaskR }, 0 }, |
||
12285 | }, |
||
12286 | { |
||
5221 | serge | 12287 | /* MOD_VEX_0FAE_REG_2 */ |
12288 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, |
||
12289 | }, |
||
12290 | { |
||
12291 | /* MOD_VEX_0FAE_REG_3 */ |
||
12292 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, |
||
12293 | }, |
||
12294 | { |
||
12295 | /* MOD_VEX_0FD7_PREFIX_2 */ |
||
12296 | { Bad_Opcode }, |
||
12297 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
||
12298 | }, |
||
12299 | { |
||
12300 | /* MOD_VEX_0FE7_PREFIX_2 */ |
||
12301 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, |
||
12302 | }, |
||
12303 | { |
||
12304 | /* MOD_VEX_0FF0_PREFIX_3 */ |
||
12305 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, |
||
12306 | }, |
||
12307 | { |
||
12308 | /* MOD_VEX_0F381A_PREFIX_2 */ |
||
12309 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, |
||
12310 | }, |
||
12311 | { |
||
12312 | /* MOD_VEX_0F382A_PREFIX_2 */ |
||
12313 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
||
12314 | }, |
||
12315 | { |
||
12316 | /* MOD_VEX_0F382C_PREFIX_2 */ |
||
12317 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, |
||
12318 | }, |
||
12319 | { |
||
12320 | /* MOD_VEX_0F382D_PREFIX_2 */ |
||
12321 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, |
||
12322 | }, |
||
12323 | { |
||
12324 | /* MOD_VEX_0F382E_PREFIX_2 */ |
||
12325 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, |
||
12326 | }, |
||
12327 | { |
||
12328 | /* MOD_VEX_0F382F_PREFIX_2 */ |
||
12329 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, |
||
12330 | }, |
||
12331 | { |
||
12332 | /* MOD_VEX_0F385A_PREFIX_2 */ |
||
12333 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, |
||
12334 | }, |
||
12335 | { |
||
12336 | /* MOD_VEX_0F388C_PREFIX_2 */ |
||
6324 | serge | 12337 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
5221 | serge | 12338 | }, |
12339 | { |
||
12340 | /* MOD_VEX_0F388E_PREFIX_2 */ |
||
6324 | serge | 12341 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
5221 | serge | 12342 | }, |
6324 | serge | 12343 | { |
12344 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ |
||
12345 | { Bad_Opcode }, |
||
12346 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, |
||
12347 | }, |
||
12348 | { |
||
12349 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ |
||
12350 | { Bad_Opcode }, |
||
12351 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, |
||
12352 | }, |
||
12353 | { |
||
12354 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ |
||
12355 | { Bad_Opcode }, |
||
12356 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, |
||
12357 | }, |
||
12358 | { |
||
12359 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ |
||
12360 | { Bad_Opcode }, |
||
12361 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, |
||
12362 | }, |
||
12363 | { |
||
12364 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ |
||
12365 | { Bad_Opcode }, |
||
12366 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, |
||
12367 | }, |
||
12368 | { |
||
12369 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ |
||
12370 | { Bad_Opcode }, |
||
12371 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, |
||
12372 | }, |
||
12373 | { |
||
12374 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ |
||
12375 | { Bad_Opcode }, |
||
12376 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, |
||
12377 | }, |
||
12378 | { |
||
12379 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ |
||
12380 | { Bad_Opcode }, |
||
12381 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, |
||
12382 | }, |
||
5221 | serge | 12383 | #define NEED_MOD_TABLE |
12384 | #include "i386-dis-evex.h" |
||
12385 | #undef NEED_MOD_TABLE |
||
12386 | }; |
||
12387 | |||
12388 | static const struct dis386 rm_table[][8] = { |
||
12389 | { |
||
12390 | /* RM_C6_REG_7 */ |
||
6324 | serge | 12391 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
5221 | serge | 12392 | }, |
12393 | { |
||
12394 | /* RM_C7_REG_7 */ |
||
6324 | serge | 12395 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
5221 | serge | 12396 | }, |
12397 | { |
||
12398 | /* RM_0F01_REG_0 */ |
||
12399 | { Bad_Opcode }, |
||
6324 | serge | 12400 | { "vmcall", { Skip_MODRM }, 0 }, |
12401 | { "vmlaunch", { Skip_MODRM }, 0 }, |
||
12402 | { "vmresume", { Skip_MODRM }, 0 }, |
||
12403 | { "vmxoff", { Skip_MODRM }, 0 }, |
||
5221 | serge | 12404 | }, |
12405 | { |
||
12406 | /* RM_0F01_REG_1 */ |
||
6324 | serge | 12407 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12408 | { "mwait", { { OP_Mwait, 0 } }, 0 }, |
||
12409 | { "clac", { Skip_MODRM }, 0 }, |
||
12410 | { "stac", { Skip_MODRM }, 0 }, |
||
12411 | { Bad_Opcode }, |
||
12412 | { Bad_Opcode }, |
||
12413 | { Bad_Opcode }, |
||
12414 | { "encls", { Skip_MODRM }, 0 }, |
||
5221 | serge | 12415 | }, |
12416 | { |
||
12417 | /* RM_0F01_REG_2 */ |
||
6324 | serge | 12418 | { "xgetbv", { Skip_MODRM }, 0 }, |
12419 | { "xsetbv", { Skip_MODRM }, 0 }, |
||
5221 | serge | 12420 | { Bad_Opcode }, |
12421 | { Bad_Opcode }, |
||
6324 | serge | 12422 | { "vmfunc", { Skip_MODRM }, 0 }, |
12423 | { "xend", { Skip_MODRM }, 0 }, |
||
12424 | { "xtest", { Skip_MODRM }, 0 }, |
||
12425 | { "enclu", { Skip_MODRM }, 0 }, |
||
5221 | serge | 12426 | }, |
12427 | { |
||
12428 | /* RM_0F01_REG_3 */ |
||
6324 | serge | 12429 | { "vmrun", { Skip_MODRM }, 0 }, |
12430 | { "vmmcall", { Skip_MODRM }, 0 }, |
||
12431 | { "vmload", { Skip_MODRM }, 0 }, |
||
12432 | { "vmsave", { Skip_MODRM }, 0 }, |
||
12433 | { "stgi", { Skip_MODRM }, 0 }, |
||
12434 | { "clgi", { Skip_MODRM }, 0 }, |
||
12435 | { "skinit", { Skip_MODRM }, 0 }, |
||
12436 | { "invlpga", { Skip_MODRM }, 0 }, |
||
5221 | serge | 12437 | }, |
12438 | { |
||
6324 | serge | 12439 | /* RM_0F01_REG_5 */ |
12440 | { Bad_Opcode }, |
||
12441 | { Bad_Opcode }, |
||
12442 | { Bad_Opcode }, |
||
12443 | { Bad_Opcode }, |
||
12444 | { Bad_Opcode }, |
||
12445 | { Bad_Opcode }, |
||
12446 | { "rdpkru", { Skip_MODRM }, 0 }, |
||
12447 | { "wrpkru", { Skip_MODRM }, 0 }, |
||
12448 | }, |
||
12449 | { |
||
5221 | serge | 12450 | /* RM_0F01_REG_7 */ |
6324 | serge | 12451 | { "swapgs", { Skip_MODRM }, 0 }, |
12452 | { "rdtscp", { Skip_MODRM }, 0 }, |
||
12453 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
||
12454 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, |
||
12455 | { "clzero", { Skip_MODRM }, 0 }, |
||
5221 | serge | 12456 | }, |
12457 | { |
||
12458 | /* RM_0FAE_REG_5 */ |
||
6324 | serge | 12459 | { "lfence", { Skip_MODRM }, 0 }, |
5221 | serge | 12460 | }, |
12461 | { |
||
12462 | /* RM_0FAE_REG_6 */ |
||
6324 | serge | 12463 | { "mfence", { Skip_MODRM }, 0 }, |
5221 | serge | 12464 | }, |
12465 | { |
||
12466 | /* RM_0FAE_REG_7 */ |
||
6324 | serge | 12467 | { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, |
5221 | serge | 12468 | }, |
12469 | }; |
||
12470 | |||
12471 | #define INTERNAL_DISASSEMBLER_ERROR _(" |
||
12472 | |||
12473 | /* We use the high bit to indicate different name for the same |
||
12474 | prefix. */ |
||
12475 | #define REP_PREFIX (0xf3 | 0x100) |
||
12476 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
||
12477 | #define XRELEASE_PREFIX (0xf3 | 0x400) |
||
12478 | #define BND_PREFIX (0xf2 | 0x400) |
||
12479 | |||
12480 | static int |
||
12481 | ckprefix (void) |
||
12482 | { |
||
12483 | int newrex, i, length; |
||
12484 | rex = 0; |
||
12485 | rex_ignored = 0; |
||
12486 | prefixes = 0; |
||
12487 | used_prefixes = 0; |
||
12488 | rex_used = 0; |
||
12489 | last_lock_prefix = -1; |
||
12490 | last_repz_prefix = -1; |
||
12491 | last_repnz_prefix = -1; |
||
12492 | last_data_prefix = -1; |
||
12493 | last_addr_prefix = -1; |
||
12494 | last_rex_prefix = -1; |
||
12495 | last_seg_prefix = -1; |
||
6324 | serge | 12496 | fwait_prefix = -1; |
12497 | active_seg_prefix = 0; |
||
5221 | serge | 12498 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12499 | all_prefixes[i] = 0; |
||
12500 | i = 0; |
||
12501 | length = 0; |
||
12502 | /* The maximum instruction length is 15bytes. */ |
||
12503 | while (length < MAX_CODE_LENGTH - 1) |
||
12504 | { |
||
12505 | FETCH_DATA (the_info, codep + 1); |
||
12506 | newrex = 0; |
||
12507 | switch (*codep) |
||
12508 | { |
||
12509 | /* REX prefixes family. */ |
||
12510 | case 0x40: |
||
12511 | case 0x41: |
||
12512 | case 0x42: |
||
12513 | case 0x43: |
||
12514 | case 0x44: |
||
12515 | case 0x45: |
||
12516 | case 0x46: |
||
12517 | case 0x47: |
||
12518 | case 0x48: |
||
12519 | case 0x49: |
||
12520 | case 0x4a: |
||
12521 | case 0x4b: |
||
12522 | case 0x4c: |
||
12523 | case 0x4d: |
||
12524 | case 0x4e: |
||
12525 | case 0x4f: |
||
12526 | if (address_mode == mode_64bit) |
||
12527 | newrex = *codep; |
||
12528 | else |
||
12529 | return 1; |
||
12530 | last_rex_prefix = i; |
||
12531 | break; |
||
12532 | case 0xf3: |
||
12533 | prefixes |= PREFIX_REPZ; |
||
12534 | last_repz_prefix = i; |
||
12535 | break; |
||
12536 | case 0xf2: |
||
12537 | prefixes |= PREFIX_REPNZ; |
||
12538 | last_repnz_prefix = i; |
||
12539 | break; |
||
12540 | case 0xf0: |
||
12541 | prefixes |= PREFIX_LOCK; |
||
12542 | last_lock_prefix = i; |
||
12543 | break; |
||
12544 | case 0x2e: |
||
12545 | prefixes |= PREFIX_CS; |
||
12546 | last_seg_prefix = i; |
||
6324 | serge | 12547 | active_seg_prefix = PREFIX_CS; |
5221 | serge | 12548 | break; |
12549 | case 0x36: |
||
12550 | prefixes |= PREFIX_SS; |
||
12551 | last_seg_prefix = i; |
||
6324 | serge | 12552 | active_seg_prefix = PREFIX_SS; |
5221 | serge | 12553 | break; |
12554 | case 0x3e: |
||
12555 | prefixes |= PREFIX_DS; |
||
12556 | last_seg_prefix = i; |
||
6324 | serge | 12557 | active_seg_prefix = PREFIX_DS; |
5221 | serge | 12558 | break; |
12559 | case 0x26: |
||
12560 | prefixes |= PREFIX_ES; |
||
12561 | last_seg_prefix = i; |
||
6324 | serge | 12562 | active_seg_prefix = PREFIX_ES; |
5221 | serge | 12563 | break; |
12564 | case 0x64: |
||
12565 | prefixes |= PREFIX_FS; |
||
12566 | last_seg_prefix = i; |
||
6324 | serge | 12567 | active_seg_prefix = PREFIX_FS; |
5221 | serge | 12568 | break; |
12569 | case 0x65: |
||
12570 | prefixes |= PREFIX_GS; |
||
12571 | last_seg_prefix = i; |
||
6324 | serge | 12572 | active_seg_prefix = PREFIX_GS; |
5221 | serge | 12573 | break; |
12574 | case 0x66: |
||
12575 | prefixes |= PREFIX_DATA; |
||
12576 | last_data_prefix = i; |
||
12577 | break; |
||
12578 | case 0x67: |
||
12579 | prefixes |= PREFIX_ADDR; |
||
12580 | last_addr_prefix = i; |
||
12581 | break; |
||
12582 | case FWAIT_OPCODE: |
||
12583 | /* fwait is really an instruction. If there are prefixes |
||
12584 | before the fwait, they belong to the fwait, *not* to the |
||
12585 | following instruction. */ |
||
6324 | serge | 12586 | fwait_prefix = i; |
5221 | serge | 12587 | if (prefixes || rex) |
12588 | { |
||
12589 | prefixes |= PREFIX_FWAIT; |
||
12590 | codep++; |
||
12591 | /* This ensures that the previous REX prefixes are noticed |
||
12592 | as unused prefixes, as in the return case below. */ |
||
12593 | rex_used = rex; |
||
12594 | return 1; |
||
12595 | } |
||
12596 | prefixes = PREFIX_FWAIT; |
||
12597 | break; |
||
12598 | default: |
||
12599 | return 1; |
||
12600 | } |
||
12601 | /* Rex is ignored when followed by another prefix. */ |
||
12602 | if (rex) |
||
12603 | { |
||
12604 | rex_used = rex; |
||
12605 | return 1; |
||
12606 | } |
||
12607 | if (*codep != FWAIT_OPCODE) |
||
12608 | all_prefixes[i++] = *codep; |
||
12609 | rex = newrex; |
||
12610 | codep++; |
||
12611 | length++; |
||
12612 | } |
||
12613 | return 0; |
||
12614 | } |
||
12615 | |||
12616 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
||
12617 | prefix byte. */ |
||
12618 | |||
12619 | static const char * |
||
12620 | prefix_name (int pref, int sizeflag) |
||
12621 | { |
||
12622 | static const char *rexes [16] = |
||
12623 | { |
||
12624 | "rex", /* 0x40 */ |
||
12625 | "rex.B", /* 0x41 */ |
||
12626 | "rex.X", /* 0x42 */ |
||
12627 | "rex.XB", /* 0x43 */ |
||
12628 | "rex.R", /* 0x44 */ |
||
12629 | "rex.RB", /* 0x45 */ |
||
12630 | "rex.RX", /* 0x46 */ |
||
12631 | "rex.RXB", /* 0x47 */ |
||
12632 | "rex.W", /* 0x48 */ |
||
12633 | "rex.WB", /* 0x49 */ |
||
12634 | "rex.WX", /* 0x4a */ |
||
12635 | "rex.WXB", /* 0x4b */ |
||
12636 | "rex.WR", /* 0x4c */ |
||
12637 | "rex.WRB", /* 0x4d */ |
||
12638 | "rex.WRX", /* 0x4e */ |
||
12639 | "rex.WRXB", /* 0x4f */ |
||
12640 | }; |
||
12641 | |||
12642 | switch (pref) |
||
12643 | { |
||
12644 | /* REX prefixes family. */ |
||
12645 | case 0x40: |
||
12646 | case 0x41: |
||
12647 | case 0x42: |
||
12648 | case 0x43: |
||
12649 | case 0x44: |
||
12650 | case 0x45: |
||
12651 | case 0x46: |
||
12652 | case 0x47: |
||
12653 | case 0x48: |
||
12654 | case 0x49: |
||
12655 | case 0x4a: |
||
12656 | case 0x4b: |
||
12657 | case 0x4c: |
||
12658 | case 0x4d: |
||
12659 | case 0x4e: |
||
12660 | case 0x4f: |
||
12661 | return rexes [pref - 0x40]; |
||
12662 | case 0xf3: |
||
12663 | return "repz"; |
||
12664 | case 0xf2: |
||
12665 | return "repnz"; |
||
12666 | case 0xf0: |
||
12667 | return "lock"; |
||
12668 | case 0x2e: |
||
12669 | return "cs"; |
||
12670 | case 0x36: |
||
12671 | return "ss"; |
||
12672 | case 0x3e: |
||
12673 | return "ds"; |
||
12674 | case 0x26: |
||
12675 | return "es"; |
||
12676 | case 0x64: |
||
12677 | return "fs"; |
||
12678 | case 0x65: |
||
12679 | return "gs"; |
||
12680 | case 0x66: |
||
12681 | return (sizeflag & DFLAG) ? "data16" : "data32"; |
||
12682 | case 0x67: |
||
12683 | if (address_mode == mode_64bit) |
||
12684 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
||
12685 | else |
||
12686 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
||
12687 | case FWAIT_OPCODE: |
||
12688 | return "fwait"; |
||
12689 | case REP_PREFIX: |
||
12690 | return "rep"; |
||
12691 | case XACQUIRE_PREFIX: |
||
12692 | return "xacquire"; |
||
12693 | case XRELEASE_PREFIX: |
||
12694 | return "xrelease"; |
||
12695 | case BND_PREFIX: |
||
12696 | return "bnd"; |
||
12697 | default: |
||
12698 | return NULL; |
||
12699 | } |
||
12700 | } |
||
12701 | |||
12702 | static char op_out[MAX_OPERANDS][100]; |
||
12703 | static int op_ad, op_index[MAX_OPERANDS]; |
||
12704 | static int two_source_ops; |
||
12705 | static bfd_vma op_address[MAX_OPERANDS]; |
||
12706 | static bfd_vma op_riprel[MAX_OPERANDS]; |
||
12707 | static bfd_vma start_pc; |
||
12708 | |||
12709 | /* |
||
12710 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. |
||
12711 | * (see topic "Redundant prefixes" in the "Differences from 8086" |
||
12712 | * section of the "Virtual 8086 Mode" chapter.) |
||
12713 | * 'pc' should be the address of this instruction, it will |
||
12714 | * be used to print the target address if this is a relative jump or call |
||
12715 | * The function returns the length of this instruction in bytes. |
||
12716 | */ |
||
12717 | |||
12718 | static char intel_syntax; |
||
12719 | static char intel_mnemonic = !SYSV386_COMPAT; |
||
12720 | static char open_char; |
||
12721 | static char close_char; |
||
12722 | static char separator_char; |
||
12723 | static char scale_char; |
||
12724 | |||
6324 | serge | 12725 | enum x86_64_isa |
12726 | { |
||
12727 | amd64 = 0, |
||
12728 | intel64 |
||
12729 | }; |
||
12730 | |||
12731 | static enum x86_64_isa isa64; |
||
12732 | |||
5221 | serge | 12733 | /* Here for backwards compatibility. When gdb stops using |
12734 | print_insn_i386_att and print_insn_i386_intel these functions can |
||
12735 | disappear, and print_insn_i386 be merged into print_insn. */ |
||
12736 | int |
||
12737 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
||
12738 | { |
||
12739 | intel_syntax = 0; |
||
12740 | |||
12741 | return print_insn (pc, info); |
||
12742 | } |
||
12743 | |||
12744 | int |
||
12745 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
||
12746 | { |
||
12747 | intel_syntax = 1; |
||
12748 | |||
12749 | return print_insn (pc, info); |
||
12750 | } |
||
12751 | |||
12752 | int |
||
12753 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
||
12754 | { |
||
12755 | intel_syntax = -1; |
||
12756 | |||
12757 | return print_insn (pc, info); |
||
12758 | } |
||
12759 | |||
12760 | void |
||
12761 | print_i386_disassembler_options (FILE *stream) |
||
12762 | { |
||
12763 | fprintf (stream, _("\n\ |
||
12764 | The following i386/x86-64 specific disassembler options are supported for use\n\ |
||
12765 | with the -M switch (multiple options should be separated by commas):\n")); |
||
12766 | |||
12767 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); |
||
12768 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); |
||
12769 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); |
||
12770 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); |
||
12771 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); |
||
12772 | fprintf (stream, _(" att-mnemonic\n" |
||
12773 | " Display instruction in AT&T mnemonic\n")); |
||
12774 | fprintf (stream, _(" intel-mnemonic\n" |
||
12775 | " Display instruction in Intel mnemonic\n")); |
||
12776 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
||
12777 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); |
||
12778 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); |
||
12779 | fprintf (stream, _(" data32 Assume 32bit data size\n")); |
||
12780 | fprintf (stream, _(" data16 Assume 16bit data size\n")); |
||
12781 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); |
||
6324 | serge | 12782 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12783 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); |
||
5221 | serge | 12784 | } |
12785 | |||
12786 | /* Bad opcode. */ |
||
6324 | serge | 12787 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
5221 | serge | 12788 | |
12789 | /* Get a pointer to struct dis386 with a valid name. */ |
||
12790 | |||
12791 | static const struct dis386 * |
||
12792 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
||
12793 | { |
||
12794 | int vindex, vex_table_index; |
||
12795 | |||
12796 | if (dp->name != NULL) |
||
12797 | return dp; |
||
12798 | |||
12799 | switch (dp->op[0].bytemode) |
||
12800 | { |
||
12801 | case USE_REG_TABLE: |
||
12802 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; |
||
12803 | break; |
||
12804 | |||
12805 | case USE_MOD_TABLE: |
||
12806 | vindex = modrm.mod == 0x3 ? 1 : 0; |
||
12807 | dp = &mod_table[dp->op[1].bytemode][vindex]; |
||
12808 | break; |
||
12809 | |||
12810 | case USE_RM_TABLE: |
||
12811 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; |
||
12812 | break; |
||
12813 | |||
12814 | case USE_PREFIX_TABLE: |
||
12815 | if (need_vex) |
||
12816 | { |
||
12817 | /* The prefix in VEX is implicit. */ |
||
12818 | switch (vex.prefix) |
||
12819 | { |
||
12820 | case 0: |
||
12821 | vindex = 0; |
||
12822 | break; |
||
12823 | case REPE_PREFIX_OPCODE: |
||
12824 | vindex = 1; |
||
12825 | break; |
||
12826 | case DATA_PREFIX_OPCODE: |
||
12827 | vindex = 2; |
||
12828 | break; |
||
12829 | case REPNE_PREFIX_OPCODE: |
||
12830 | vindex = 3; |
||
12831 | break; |
||
12832 | default: |
||
12833 | abort (); |
||
12834 | break; |
||
12835 | } |
||
12836 | } |
||
12837 | else |
||
12838 | { |
||
6324 | serge | 12839 | int last_prefix = -1; |
12840 | int prefix = 0; |
||
5221 | serge | 12841 | vindex = 0; |
6324 | serge | 12842 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12843 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the |
||
12844 | last one wins. */ |
||
12845 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) |
||
5221 | serge | 12846 | { |
6324 | serge | 12847 | if (last_repz_prefix > last_repnz_prefix) |
5221 | serge | 12848 | { |
6324 | serge | 12849 | vindex = 1; |
12850 | prefix = PREFIX_REPZ; |
||
12851 | last_prefix = last_repz_prefix; |
||
5221 | serge | 12852 | } |
12853 | else |
||
12854 | { |
||
6324 | serge | 12855 | vindex = 3; |
12856 | prefix = PREFIX_REPNZ; |
||
12857 | last_prefix = last_repnz_prefix; |
||
5221 | serge | 12858 | } |
6324 | serge | 12859 | |
12860 | /* Check if prefix should be ignored. */ |
||
12861 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement |
||
12862 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) |
||
12863 | & prefix) != 0) |
||
12864 | vindex = 0; |
||
5221 | serge | 12865 | } |
6324 | serge | 12866 | |
12867 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) |
||
12868 | { |
||
12869 | vindex = 2; |
||
12870 | prefix = PREFIX_DATA; |
||
12871 | last_prefix = last_data_prefix; |
||
12872 | } |
||
12873 | |||
12874 | if (vindex != 0) |
||
12875 | { |
||
12876 | used_prefixes |= prefix; |
||
12877 | all_prefixes[last_prefix] = 0; |
||
12878 | } |
||
5221 | serge | 12879 | } |
12880 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
||
12881 | break; |
||
12882 | |||
12883 | case USE_X86_64_TABLE: |
||
12884 | vindex = address_mode == mode_64bit ? 1 : 0; |
||
12885 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; |
||
12886 | break; |
||
12887 | |||
12888 | case USE_3BYTE_TABLE: |
||
12889 | FETCH_DATA (info, codep + 2); |
||
12890 | vindex = *codep++; |
||
12891 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
||
6324 | serge | 12892 | end_codep = codep; |
5221 | serge | 12893 | modrm.mod = (*codep >> 6) & 3; |
12894 | modrm.reg = (*codep >> 3) & 7; |
||
12895 | modrm.rm = *codep & 7; |
||
12896 | break; |
||
12897 | |||
12898 | case USE_VEX_LEN_TABLE: |
||
12899 | if (!need_vex) |
||
12900 | abort (); |
||
12901 | |||
12902 | switch (vex.length) |
||
12903 | { |
||
12904 | case 128: |
||
12905 | vindex = 0; |
||
12906 | break; |
||
12907 | case 256: |
||
12908 | vindex = 1; |
||
12909 | break; |
||
12910 | default: |
||
12911 | abort (); |
||
12912 | break; |
||
12913 | } |
||
12914 | |||
12915 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
||
12916 | break; |
||
12917 | |||
12918 | case USE_XOP_8F_TABLE: |
||
12919 | FETCH_DATA (info, codep + 3); |
||
12920 | /* All bits in the REX prefix are ignored. */ |
||
12921 | rex_ignored = rex; |
||
12922 | rex = ~(*codep >> 5) & 0x7; |
||
12923 | |||
12924 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ |
||
12925 | switch ((*codep & 0x1f)) |
||
12926 | { |
||
12927 | default: |
||
12928 | dp = &bad_opcode; |
||
12929 | return dp; |
||
12930 | case 0x8: |
||
12931 | vex_table_index = XOP_08; |
||
12932 | break; |
||
12933 | case 0x9: |
||
12934 | vex_table_index = XOP_09; |
||
12935 | break; |
||
12936 | case 0xa: |
||
12937 | vex_table_index = XOP_0A; |
||
12938 | break; |
||
12939 | } |
||
12940 | codep++; |
||
12941 | vex.w = *codep & 0x80; |
||
12942 | if (vex.w && address_mode == mode_64bit) |
||
12943 | rex |= REX_W; |
||
12944 | |||
12945 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
||
12946 | if (address_mode != mode_64bit |
||
12947 | && vex.register_specifier > 0x7) |
||
12948 | { |
||
12949 | dp = &bad_opcode; |
||
12950 | return dp; |
||
12951 | } |
||
12952 | |||
12953 | vex.length = (*codep & 0x4) ? 256 : 128; |
||
12954 | switch ((*codep & 0x3)) |
||
12955 | { |
||
12956 | case 0: |
||
12957 | vex.prefix = 0; |
||
12958 | break; |
||
12959 | case 1: |
||
12960 | vex.prefix = DATA_PREFIX_OPCODE; |
||
12961 | break; |
||
12962 | case 2: |
||
12963 | vex.prefix = REPE_PREFIX_OPCODE; |
||
12964 | break; |
||
12965 | case 3: |
||
12966 | vex.prefix = REPNE_PREFIX_OPCODE; |
||
12967 | break; |
||
12968 | } |
||
12969 | need_vex = 1; |
||
12970 | need_vex_reg = 1; |
||
12971 | codep++; |
||
12972 | vindex = *codep++; |
||
12973 | dp = &xop_table[vex_table_index][vindex]; |
||
12974 | |||
6324 | serge | 12975 | end_codep = codep; |
5221 | serge | 12976 | FETCH_DATA (info, codep + 1); |
12977 | modrm.mod = (*codep >> 6) & 3; |
||
12978 | modrm.reg = (*codep >> 3) & 7; |
||
12979 | modrm.rm = *codep & 7; |
||
12980 | break; |
||
12981 | |||
12982 | case USE_VEX_C4_TABLE: |
||
12983 | /* VEX prefix. */ |
||
12984 | FETCH_DATA (info, codep + 3); |
||
12985 | /* All bits in the REX prefix are ignored. */ |
||
12986 | rex_ignored = rex; |
||
12987 | rex = ~(*codep >> 5) & 0x7; |
||
12988 | switch ((*codep & 0x1f)) |
||
12989 | { |
||
12990 | default: |
||
12991 | dp = &bad_opcode; |
||
12992 | return dp; |
||
12993 | case 0x1: |
||
12994 | vex_table_index = VEX_0F; |
||
12995 | break; |
||
12996 | case 0x2: |
||
12997 | vex_table_index = VEX_0F38; |
||
12998 | break; |
||
12999 | case 0x3: |
||
13000 | vex_table_index = VEX_0F3A; |
||
13001 | break; |
||
13002 | } |
||
13003 | codep++; |
||
13004 | vex.w = *codep & 0x80; |
||
13005 | if (vex.w && address_mode == mode_64bit) |
||
13006 | rex |= REX_W; |
||
13007 | |||
13008 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
||
13009 | if (address_mode != mode_64bit |
||
13010 | && vex.register_specifier > 0x7) |
||
13011 | { |
||
13012 | dp = &bad_opcode; |
||
13013 | return dp; |
||
13014 | } |
||
13015 | |||
13016 | vex.length = (*codep & 0x4) ? 256 : 128; |
||
13017 | switch ((*codep & 0x3)) |
||
13018 | { |
||
13019 | case 0: |
||
13020 | vex.prefix = 0; |
||
13021 | break; |
||
13022 | case 1: |
||
13023 | vex.prefix = DATA_PREFIX_OPCODE; |
||
13024 | break; |
||
13025 | case 2: |
||
13026 | vex.prefix = REPE_PREFIX_OPCODE; |
||
13027 | break; |
||
13028 | case 3: |
||
13029 | vex.prefix = REPNE_PREFIX_OPCODE; |
||
13030 | break; |
||
13031 | } |
||
13032 | need_vex = 1; |
||
13033 | need_vex_reg = 1; |
||
13034 | codep++; |
||
13035 | vindex = *codep++; |
||
13036 | dp = &vex_table[vex_table_index][vindex]; |
||
6324 | serge | 13037 | end_codep = codep; |
5221 | serge | 13038 | /* There is no MODRM byte for VEX [82|77]. */ |
13039 | if (vindex != 0x77 && vindex != 0x82) |
||
13040 | { |
||
13041 | FETCH_DATA (info, codep + 1); |
||
13042 | modrm.mod = (*codep >> 6) & 3; |
||
13043 | modrm.reg = (*codep >> 3) & 7; |
||
13044 | modrm.rm = *codep & 7; |
||
13045 | } |
||
13046 | break; |
||
13047 | |||
13048 | case USE_VEX_C5_TABLE: |
||
13049 | /* VEX prefix. */ |
||
13050 | FETCH_DATA (info, codep + 2); |
||
13051 | /* All bits in the REX prefix are ignored. */ |
||
13052 | rex_ignored = rex; |
||
13053 | rex = (*codep & 0x80) ? 0 : REX_R; |
||
13054 | |||
13055 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
||
13056 | if (address_mode != mode_64bit |
||
13057 | && vex.register_specifier > 0x7) |
||
13058 | { |
||
13059 | dp = &bad_opcode; |
||
13060 | return dp; |
||
13061 | } |
||
13062 | |||
13063 | vex.w = 0; |
||
13064 | |||
13065 | vex.length = (*codep & 0x4) ? 256 : 128; |
||
13066 | switch ((*codep & 0x3)) |
||
13067 | { |
||
13068 | case 0: |
||
13069 | vex.prefix = 0; |
||
13070 | break; |
||
13071 | case 1: |
||
13072 | vex.prefix = DATA_PREFIX_OPCODE; |
||
13073 | break; |
||
13074 | case 2: |
||
13075 | vex.prefix = REPE_PREFIX_OPCODE; |
||
13076 | break; |
||
13077 | case 3: |
||
13078 | vex.prefix = REPNE_PREFIX_OPCODE; |
||
13079 | break; |
||
13080 | } |
||
13081 | need_vex = 1; |
||
13082 | need_vex_reg = 1; |
||
13083 | codep++; |
||
13084 | vindex = *codep++; |
||
13085 | dp = &vex_table[dp->op[1].bytemode][vindex]; |
||
6324 | serge | 13086 | end_codep = codep; |
5221 | serge | 13087 | /* There is no MODRM byte for VEX [82|77]. */ |
13088 | if (vindex != 0x77 && vindex != 0x82) |
||
13089 | { |
||
13090 | FETCH_DATA (info, codep + 1); |
||
13091 | modrm.mod = (*codep >> 6) & 3; |
||
13092 | modrm.reg = (*codep >> 3) & 7; |
||
13093 | modrm.rm = *codep & 7; |
||
13094 | } |
||
13095 | break; |
||
13096 | |||
13097 | case USE_VEX_W_TABLE: |
||
13098 | if (!need_vex) |
||
13099 | abort (); |
||
13100 | |||
13101 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; |
||
13102 | break; |
||
13103 | |||
13104 | case USE_EVEX_TABLE: |
||
13105 | two_source_ops = 0; |
||
13106 | /* EVEX prefix. */ |
||
13107 | vex.evex = 1; |
||
13108 | FETCH_DATA (info, codep + 4); |
||
13109 | /* All bits in the REX prefix are ignored. */ |
||
13110 | rex_ignored = rex; |
||
13111 | /* The first byte after 0x62. */ |
||
13112 | rex = ~(*codep >> 5) & 0x7; |
||
13113 | vex.r = *codep & 0x10; |
||
13114 | switch ((*codep & 0xf)) |
||
13115 | { |
||
13116 | default: |
||
13117 | return &bad_opcode; |
||
13118 | case 0x1: |
||
13119 | vex_table_index = EVEX_0F; |
||
13120 | break; |
||
13121 | case 0x2: |
||
13122 | vex_table_index = EVEX_0F38; |
||
13123 | break; |
||
13124 | case 0x3: |
||
13125 | vex_table_index = EVEX_0F3A; |
||
13126 | break; |
||
13127 | } |
||
13128 | |||
13129 | /* The second byte after 0x62. */ |
||
13130 | codep++; |
||
13131 | vex.w = *codep & 0x80; |
||
13132 | if (vex.w && address_mode == mode_64bit) |
||
13133 | rex |= REX_W; |
||
13134 | |||
13135 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
||
13136 | if (address_mode != mode_64bit) |
||
13137 | { |
||
13138 | /* In 16/32-bit mode silently ignore following bits. */ |
||
13139 | rex &= ~REX_B; |
||
13140 | vex.r = 1; |
||
13141 | vex.v = 1; |
||
13142 | vex.register_specifier &= 0x7; |
||
13143 | } |
||
13144 | |||
13145 | /* The U bit. */ |
||
13146 | if (!(*codep & 0x4)) |
||
13147 | return &bad_opcode; |
||
13148 | |||
13149 | switch ((*codep & 0x3)) |
||
13150 | { |
||
13151 | case 0: |
||
13152 | vex.prefix = 0; |
||
13153 | break; |
||
13154 | case 1: |
||
13155 | vex.prefix = DATA_PREFIX_OPCODE; |
||
13156 | break; |
||
13157 | case 2: |
||
13158 | vex.prefix = REPE_PREFIX_OPCODE; |
||
13159 | break; |
||
13160 | case 3: |
||
13161 | vex.prefix = REPNE_PREFIX_OPCODE; |
||
13162 | break; |
||
13163 | } |
||
13164 | |||
13165 | /* The third byte after 0x62. */ |
||
13166 | codep++; |
||
13167 | |||
13168 | /* Remember the static rounding bits. */ |
||
13169 | vex.ll = (*codep >> 5) & 3; |
||
13170 | vex.b = (*codep & 0x10) != 0; |
||
13171 | |||
13172 | vex.v = *codep & 0x8; |
||
13173 | vex.mask_register_specifier = *codep & 0x7; |
||
13174 | vex.zeroing = *codep & 0x80; |
||
13175 | |||
13176 | need_vex = 1; |
||
13177 | need_vex_reg = 1; |
||
13178 | codep++; |
||
13179 | vindex = *codep++; |
||
13180 | dp = &evex_table[vex_table_index][vindex]; |
||
6324 | serge | 13181 | end_codep = codep; |
5221 | serge | 13182 | FETCH_DATA (info, codep + 1); |
13183 | modrm.mod = (*codep >> 6) & 3; |
||
13184 | modrm.reg = (*codep >> 3) & 7; |
||
13185 | modrm.rm = *codep & 7; |
||
13186 | |||
13187 | /* Set vector length. */ |
||
13188 | if (modrm.mod == 3 && vex.b) |
||
13189 | vex.length = 512; |
||
13190 | else |
||
13191 | { |
||
13192 | switch (vex.ll) |
||
13193 | { |
||
13194 | case 0x0: |
||
13195 | vex.length = 128; |
||
13196 | break; |
||
13197 | case 0x1: |
||
13198 | vex.length = 256; |
||
13199 | break; |
||
13200 | case 0x2: |
||
13201 | vex.length = 512; |
||
13202 | break; |
||
13203 | default: |
||
13204 | return &bad_opcode; |
||
13205 | } |
||
13206 | } |
||
13207 | break; |
||
13208 | |||
13209 | case 0: |
||
13210 | dp = &bad_opcode; |
||
13211 | break; |
||
13212 | |||
13213 | default: |
||
13214 | abort (); |
||
13215 | } |
||
13216 | |||
13217 | if (dp->name != NULL) |
||
13218 | return dp; |
||
13219 | else |
||
13220 | return get_valid_dis386 (dp, info); |
||
13221 | } |
||
13222 | |||
13223 | static void |
||
13224 | get_sib (disassemble_info *info, int sizeflag) |
||
13225 | { |
||
13226 | /* If modrm.mod == 3, operand must be register. */ |
||
13227 | if (need_modrm |
||
13228 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
||
13229 | && modrm.mod != 3 |
||
13230 | && modrm.rm == 4) |
||
13231 | { |
||
13232 | FETCH_DATA (info, codep + 2); |
||
13233 | sib.index = (codep [1] >> 3) & 7; |
||
13234 | sib.scale = (codep [1] >> 6) & 3; |
||
13235 | sib.base = codep [1] & 7; |
||
13236 | } |
||
13237 | } |
||
13238 | |||
13239 | static int |
||
13240 | print_insn (bfd_vma pc, disassemble_info *info) |
||
13241 | { |
||
13242 | const struct dis386 *dp; |
||
13243 | int i; |
||
13244 | char *op_txt[MAX_OPERANDS]; |
||
13245 | int needcomma; |
||
6324 | serge | 13246 | int sizeflag, orig_sizeflag; |
5221 | serge | 13247 | const char *p; |
13248 | struct dis_private priv; |
||
13249 | int prefix_length; |
||
13250 | |||
13251 | priv.orig_sizeflag = AFLAG | DFLAG; |
||
13252 | if ((info->mach & bfd_mach_i386_i386) != 0) |
||
13253 | address_mode = mode_32bit; |
||
13254 | else if (info->mach == bfd_mach_i386_i8086) |
||
13255 | { |
||
13256 | address_mode = mode_16bit; |
||
13257 | priv.orig_sizeflag = 0; |
||
13258 | } |
||
13259 | else |
||
13260 | address_mode = mode_64bit; |
||
13261 | |||
13262 | if (intel_syntax == (char) -1) |
||
13263 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; |
||
13264 | |||
13265 | for (p = info->disassembler_options; p != NULL; ) |
||
13266 | { |
||
6324 | serge | 13267 | if (CONST_STRNEQ (p, "amd64")) |
13268 | isa64 = amd64; |
||
13269 | else if (CONST_STRNEQ (p, "intel64")) |
||
13270 | isa64 = intel64; |
||
13271 | else if (CONST_STRNEQ (p, "x86-64")) |
||
5221 | serge | 13272 | { |
13273 | address_mode = mode_64bit; |
||
13274 | priv.orig_sizeflag = AFLAG | DFLAG; |
||
13275 | } |
||
13276 | else if (CONST_STRNEQ (p, "i386")) |
||
13277 | { |
||
13278 | address_mode = mode_32bit; |
||
13279 | priv.orig_sizeflag = AFLAG | DFLAG; |
||
13280 | } |
||
13281 | else if (CONST_STRNEQ (p, "i8086")) |
||
13282 | { |
||
13283 | address_mode = mode_16bit; |
||
13284 | priv.orig_sizeflag = 0; |
||
13285 | } |
||
13286 | else if (CONST_STRNEQ (p, "intel")) |
||
13287 | { |
||
13288 | intel_syntax = 1; |
||
13289 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
||
13290 | intel_mnemonic = 1; |
||
13291 | } |
||
13292 | else if (CONST_STRNEQ (p, "att")) |
||
13293 | { |
||
13294 | intel_syntax = 0; |
||
13295 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
||
13296 | intel_mnemonic = 0; |
||
13297 | } |
||
13298 | else if (CONST_STRNEQ (p, "addr")) |
||
13299 | { |
||
13300 | if (address_mode == mode_64bit) |
||
13301 | { |
||
13302 | if (p[4] == '3' && p[5] == '2') |
||
13303 | priv.orig_sizeflag &= ~AFLAG; |
||
13304 | else if (p[4] == '6' && p[5] == '4') |
||
13305 | priv.orig_sizeflag |= AFLAG; |
||
13306 | } |
||
13307 | else |
||
13308 | { |
||
13309 | if (p[4] == '1' && p[5] == '6') |
||
13310 | priv.orig_sizeflag &= ~AFLAG; |
||
13311 | else if (p[4] == '3' && p[5] == '2') |
||
13312 | priv.orig_sizeflag |= AFLAG; |
||
13313 | } |
||
13314 | } |
||
13315 | else if (CONST_STRNEQ (p, "data")) |
||
13316 | { |
||
13317 | if (p[4] == '1' && p[5] == '6') |
||
13318 | priv.orig_sizeflag &= ~DFLAG; |
||
13319 | else if (p[4] == '3' && p[5] == '2') |
||
13320 | priv.orig_sizeflag |= DFLAG; |
||
13321 | } |
||
13322 | else if (CONST_STRNEQ (p, "suffix")) |
||
13323 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
||
13324 | |||
13325 | p = strchr (p, ','); |
||
13326 | if (p != NULL) |
||
13327 | p++; |
||
13328 | } |
||
13329 | |||
13330 | if (intel_syntax) |
||
13331 | { |
||
13332 | names64 = intel_names64; |
||
13333 | names32 = intel_names32; |
||
13334 | names16 = intel_names16; |
||
13335 | names8 = intel_names8; |
||
13336 | names8rex = intel_names8rex; |
||
13337 | names_seg = intel_names_seg; |
||
13338 | names_mm = intel_names_mm; |
||
13339 | names_bnd = intel_names_bnd; |
||
13340 | names_xmm = intel_names_xmm; |
||
13341 | names_ymm = intel_names_ymm; |
||
13342 | names_zmm = intel_names_zmm; |
||
13343 | index64 = intel_index64; |
||
13344 | index32 = intel_index32; |
||
13345 | names_mask = intel_names_mask; |
||
13346 | index16 = intel_index16; |
||
13347 | open_char = '['; |
||
13348 | close_char = ']'; |
||
13349 | separator_char = '+'; |
||
13350 | scale_char = '*'; |
||
13351 | } |
||
13352 | else |
||
13353 | { |
||
13354 | names64 = att_names64; |
||
13355 | names32 = att_names32; |
||
13356 | names16 = att_names16; |
||
13357 | names8 = att_names8; |
||
13358 | names8rex = att_names8rex; |
||
13359 | names_seg = att_names_seg; |
||
13360 | names_mm = att_names_mm; |
||
13361 | names_bnd = att_names_bnd; |
||
13362 | names_xmm = att_names_xmm; |
||
13363 | names_ymm = att_names_ymm; |
||
13364 | names_zmm = att_names_zmm; |
||
13365 | index64 = att_index64; |
||
13366 | index32 = att_index32; |
||
13367 | names_mask = att_names_mask; |
||
13368 | index16 = att_index16; |
||
13369 | open_char = '('; |
||
13370 | close_char = ')'; |
||
13371 | separator_char = ','; |
||
13372 | scale_char = ','; |
||
13373 | } |
||
13374 | |||
13375 | /* The output looks better if we put 7 bytes on a line, since that |
||
13376 | puts most long word instructions on a single line. Use 8 bytes |
||
13377 | for Intel L1OM. */ |
||
13378 | if ((info->mach & bfd_mach_l1om) != 0) |
||
13379 | info->bytes_per_line = 8; |
||
13380 | else |
||
13381 | info->bytes_per_line = 7; |
||
13382 | |||
13383 | info->private_data = &priv; |
||
13384 | priv.max_fetched = priv.the_buffer; |
||
13385 | priv.insn_start = pc; |
||
13386 | |||
13387 | obuf[0] = 0; |
||
13388 | for (i = 0; i < MAX_OPERANDS; ++i) |
||
13389 | { |
||
13390 | op_out[i][0] = 0; |
||
13391 | op_index[i] = -1; |
||
13392 | } |
||
13393 | |||
13394 | the_info = info; |
||
13395 | start_pc = pc; |
||
13396 | start_codep = priv.the_buffer; |
||
13397 | codep = priv.the_buffer; |
||
13398 | |||
6324 | serge | 13399 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5221 | serge | 13400 | { |
13401 | const char *name; |
||
13402 | |||
13403 | /* Getting here means we tried for data but didn't get it. That |
||
13404 | means we have an incomplete instruction of some sort. Just |
||
13405 | print the first byte as a prefix or a .byte pseudo-op. */ |
||
13406 | if (codep > priv.the_buffer) |
||
13407 | { |
||
13408 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
||
13409 | if (name != NULL) |
||
13410 | (*info->fprintf_func) (info->stream, "%s", name); |
||
13411 | else |
||
13412 | { |
||
13413 | /* Just print the first byte as a .byte instruction. */ |
||
13414 | (*info->fprintf_func) (info->stream, ".byte 0x%x", |
||
13415 | (unsigned int) priv.the_buffer[0]); |
||
13416 | } |
||
13417 | |||
13418 | return 1; |
||
13419 | } |
||
13420 | |||
13421 | return -1; |
||
13422 | } |
||
13423 | |||
13424 | obufp = obuf; |
||
13425 | sizeflag = priv.orig_sizeflag; |
||
13426 | |||
13427 | if (!ckprefix () || rex_used) |
||
13428 | { |
||
13429 | /* Too many prefixes or unused REX prefixes. */ |
||
13430 | for (i = 0; |
||
13431 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
||
13432 | i++) |
||
13433 | (*info->fprintf_func) (info->stream, "%s%s", |
||
13434 | i == 0 ? "" : " ", |
||
13435 | prefix_name (all_prefixes[i], sizeflag)); |
||
13436 | return i; |
||
13437 | } |
||
13438 | |||
13439 | insn_codep = codep; |
||
13440 | |||
13441 | FETCH_DATA (info, codep + 1); |
||
13442 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); |
||
13443 | |||
13444 | if (((prefixes & PREFIX_FWAIT) |
||
13445 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
||
13446 | { |
||
6324 | serge | 13447 | /* Handle prefixes before fwait. */ |
13448 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
||
13449 | i++) |
||
13450 | (*info->fprintf_func) (info->stream, "%s ", |
||
13451 | prefix_name (all_prefixes[i], sizeflag)); |
||
5221 | serge | 13452 | (*info->fprintf_func) (info->stream, "fwait"); |
6324 | serge | 13453 | return i + 1; |
5221 | serge | 13454 | } |
13455 | |||
13456 | if (*codep == 0x0f) |
||
13457 | { |
||
13458 | unsigned char threebyte; |
||
6324 | serge | 13459 | |
13460 | codep++; |
||
13461 | FETCH_DATA (info, codep + 1); |
||
13462 | threebyte = *codep; |
||
5221 | serge | 13463 | dp = &dis386_twobyte[threebyte]; |
13464 | need_modrm = twobyte_has_modrm[*codep]; |
||
13465 | codep++; |
||
13466 | } |
||
13467 | else |
||
13468 | { |
||
13469 | dp = &dis386[*codep]; |
||
13470 | need_modrm = onebyte_has_modrm[*codep]; |
||
13471 | codep++; |
||
13472 | } |
||
13473 | |||
6324 | serge | 13474 | /* Save sizeflag for printing the extra prefixes later before updating |
13475 | it for mnemonic and operand processing. The prefix names depend |
||
13476 | only on the address mode. */ |
||
13477 | orig_sizeflag = sizeflag; |
||
5221 | serge | 13478 | if (prefixes & PREFIX_ADDR) |
6324 | serge | 13479 | sizeflag ^= AFLAG; |
5221 | serge | 13480 | if ((prefixes & PREFIX_DATA)) |
6324 | serge | 13481 | sizeflag ^= DFLAG; |
5221 | serge | 13482 | |
6324 | serge | 13483 | end_codep = codep; |
5221 | serge | 13484 | if (need_modrm) |
13485 | { |
||
13486 | FETCH_DATA (info, codep + 1); |
||
13487 | modrm.mod = (*codep >> 6) & 3; |
||
13488 | modrm.reg = (*codep >> 3) & 7; |
||
13489 | modrm.rm = *codep & 7; |
||
13490 | } |
||
13491 | |||
13492 | need_vex = 0; |
||
13493 | need_vex_reg = 0; |
||
13494 | vex_w_done = 0; |
||
13495 | vex.evex = 0; |
||
13496 | |||
13497 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
||
13498 | { |
||
13499 | get_sib (info, sizeflag); |
||
13500 | dofloat (sizeflag); |
||
13501 | } |
||
13502 | else |
||
13503 | { |
||
13504 | dp = get_valid_dis386 (dp, info); |
||
13505 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
||
13506 | { |
||
13507 | get_sib (info, sizeflag); |
||
13508 | for (i = 0; i < MAX_OPERANDS; ++i) |
||
13509 | { |
||
13510 | obufp = op_out[i]; |
||
13511 | op_ad = MAX_OPERANDS - 1 - i; |
||
13512 | if (dp->op[i].rtn) |
||
13513 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); |
||
13514 | /* For EVEX instruction after the last operand masking |
||
13515 | should be printed. */ |
||
13516 | if (i == 0 && vex.evex) |
||
13517 | { |
||
13518 | /* Don't print {%k0}. */ |
||
13519 | if (vex.mask_register_specifier) |
||
13520 | { |
||
13521 | oappend ("{"); |
||
13522 | oappend (names_mask[vex.mask_register_specifier]); |
||
13523 | oappend ("}"); |
||
13524 | } |
||
13525 | if (vex.zeroing) |
||
13526 | oappend ("{z}"); |
||
13527 | } |
||
13528 | } |
||
13529 | } |
||
13530 | } |
||
13531 | |||
13532 | /* Check if the REX prefix is used. */ |
||
6324 | serge | 13533 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
5221 | serge | 13534 | all_prefixes[last_rex_prefix] = 0; |
13535 | |||
13536 | /* Check if the SEG prefix is used. */ |
||
13537 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
||
13538 | | PREFIX_FS | PREFIX_GS)) != 0 |
||
6324 | serge | 13539 | && (used_prefixes & active_seg_prefix) != 0) |
5221 | serge | 13540 | all_prefixes[last_seg_prefix] = 0; |
13541 | |||
13542 | /* Check if the ADDR prefix is used. */ |
||
13543 | if ((prefixes & PREFIX_ADDR) != 0 |
||
13544 | && (used_prefixes & PREFIX_ADDR) != 0) |
||
13545 | all_prefixes[last_addr_prefix] = 0; |
||
13546 | |||
13547 | /* Check if the DATA prefix is used. */ |
||
13548 | if ((prefixes & PREFIX_DATA) != 0 |
||
13549 | && (used_prefixes & PREFIX_DATA) != 0) |
||
13550 | all_prefixes[last_data_prefix] = 0; |
||
13551 | |||
6324 | serge | 13552 | /* Print the extra prefixes. */ |
5221 | serge | 13553 | prefix_length = 0; |
13554 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
||
13555 | if (all_prefixes[i]) |
||
13556 | { |
||
13557 | const char *name; |
||
6324 | serge | 13558 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
5221 | serge | 13559 | if (name == NULL) |
13560 | abort (); |
||
13561 | prefix_length += strlen (name) + 1; |
||
13562 | (*info->fprintf_func) (info->stream, "%s ", name); |
||
13563 | } |
||
13564 | |||
6324 | serge | 13565 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13566 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be |
||
13567 | used by putop and MMX/SSE operand and may be overriden by the |
||
13568 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix |
||
13569 | separately. */ |
||
13570 | if (dp->prefix_requirement == PREFIX_OPCODE |
||
13571 | && dp != &bad_opcode |
||
13572 | && (((prefixes |
||
13573 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 |
||
13574 | && (used_prefixes |
||
13575 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) |
||
13576 | || ((((prefixes |
||
13577 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) |
||
13578 | == PREFIX_DATA) |
||
13579 | && (used_prefixes & PREFIX_DATA) == 0)))) |
||
13580 | { |
||
13581 | (*info->fprintf_func) (info->stream, "(bad)"); |
||
13582 | return end_codep - priv.the_buffer; |
||
13583 | } |
||
13584 | |||
5221 | serge | 13585 | /* Check maximum code length. */ |
13586 | if ((codep - start_codep) > MAX_CODE_LENGTH) |
||
13587 | { |
||
13588 | (*info->fprintf_func) (info->stream, "(bad)"); |
||
13589 | return MAX_CODE_LENGTH; |
||
13590 | } |
||
13591 | |||
13592 | obufp = mnemonicendp; |
||
13593 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
||
13594 | oappend (" "); |
||
13595 | oappend (" "); |
||
13596 | (*info->fprintf_func) (info->stream, "%s", obuf); |
||
13597 | |||
13598 | /* The enter and bound instructions are printed with operands in the same |
||
13599 | order as the intel book; everything else is printed in reverse order. */ |
||
13600 | if (intel_syntax || two_source_ops) |
||
13601 | { |
||
13602 | bfd_vma riprel; |
||
13603 | |||
13604 | for (i = 0; i < MAX_OPERANDS; ++i) |
||
13605 | op_txt[i] = op_out[i]; |
||
13606 | |||
6324 | serge | 13607 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13608 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) |
||
13609 | { |
||
13610 | op_txt[2] = op_out[3]; |
||
13611 | op_txt[3] = op_out[2]; |
||
13612 | } |
||
13613 | |||
5221 | serge | 13614 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13615 | { |
||
13616 | op_ad = op_index[i]; |
||
13617 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; |
||
13618 | op_index[MAX_OPERANDS - 1 - i] = op_ad; |
||
13619 | riprel = op_riprel[i]; |
||
13620 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; |
||
13621 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; |
||
13622 | } |
||
13623 | } |
||
13624 | else |
||
13625 | { |
||
13626 | for (i = 0; i < MAX_OPERANDS; ++i) |
||
13627 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
||
13628 | } |
||
13629 | |||
13630 | needcomma = 0; |
||
13631 | for (i = 0; i < MAX_OPERANDS; ++i) |
||
13632 | if (*op_txt[i]) |
||
13633 | { |
||
13634 | if (needcomma) |
||
13635 | (*info->fprintf_func) (info->stream, ","); |
||
13636 | if (op_index[i] != -1 && !op_riprel[i]) |
||
13637 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); |
||
13638 | else |
||
13639 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); |
||
13640 | needcomma = 1; |
||
13641 | } |
||
13642 | |||
13643 | for (i = 0; i < MAX_OPERANDS; i++) |
||
13644 | if (op_index[i] != -1 && op_riprel[i]) |
||
13645 | { |
||
13646 | (*info->fprintf_func) (info->stream, " # "); |
||
13647 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep |
||
13648 | + op_address[op_index[i]]), info); |
||
13649 | break; |
||
13650 | } |
||
13651 | return codep - priv.the_buffer; |
||
13652 | } |
||
13653 | |||
13654 | static const char *float_mem[] = { |
||
13655 | /* d8 */ |
||
13656 | "fadd{s|}", |
||
13657 | "fmul{s|}", |
||
13658 | "fcom{s|}", |
||
13659 | "fcomp{s|}", |
||
13660 | "fsub{s|}", |
||
13661 | "fsubr{s|}", |
||
13662 | "fdiv{s|}", |
||
13663 | "fdivr{s|}", |
||
13664 | /* d9 */ |
||
13665 | "fld{s|}", |
||
13666 | "(bad)", |
||
13667 | "fst{s|}", |
||
13668 | "fstp{s|}", |
||
13669 | "fldenvIC", |
||
13670 | "fldcw", |
||
13671 | "fNstenvIC", |
||
13672 | "fNstcw", |
||
13673 | /* da */ |
||
13674 | "fiadd{l|}", |
||
13675 | "fimul{l|}", |
||
13676 | "ficom{l|}", |
||
13677 | "ficomp{l|}", |
||
13678 | "fisub{l|}", |
||
13679 | "fisubr{l|}", |
||
13680 | "fidiv{l|}", |
||
13681 | "fidivr{l|}", |
||
13682 | /* db */ |
||
13683 | "fild{l|}", |
||
13684 | "fisttp{l|}", |
||
13685 | "fist{l|}", |
||
13686 | "fistp{l|}", |
||
13687 | "(bad)", |
||
13688 | "fld{t||t|}", |
||
13689 | "(bad)", |
||
13690 | "fstp{t||t|}", |
||
13691 | /* dc */ |
||
13692 | "fadd{l|}", |
||
13693 | "fmul{l|}", |
||
13694 | "fcom{l|}", |
||
13695 | "fcomp{l|}", |
||
13696 | "fsub{l|}", |
||
13697 | "fsubr{l|}", |
||
13698 | "fdiv{l|}", |
||
13699 | "fdivr{l|}", |
||
13700 | /* dd */ |
||
13701 | "fld{l|}", |
||
13702 | "fisttp{ll|}", |
||
13703 | "fst{l||}", |
||
13704 | "fstp{l|}", |
||
13705 | "frstorIC", |
||
13706 | "(bad)", |
||
13707 | "fNsaveIC", |
||
13708 | "fNstsw", |
||
13709 | /* de */ |
||
13710 | "fiadd", |
||
13711 | "fimul", |
||
13712 | "ficom", |
||
13713 | "ficomp", |
||
13714 | "fisub", |
||
13715 | "fisubr", |
||
13716 | "fidiv", |
||
13717 | "fidivr", |
||
13718 | /* df */ |
||
13719 | "fild", |
||
13720 | "fisttp", |
||
13721 | "fist", |
||
13722 | "fistp", |
||
13723 | "fbld", |
||
13724 | "fild{ll|}", |
||
13725 | "fbstp", |
||
13726 | "fistp{ll|}", |
||
13727 | }; |
||
13728 | |||
13729 | static const unsigned char float_mem_mode[] = { |
||
13730 | /* d8 */ |
||
13731 | d_mode, |
||
13732 | d_mode, |
||
13733 | d_mode, |
||
13734 | d_mode, |
||
13735 | d_mode, |
||
13736 | d_mode, |
||
13737 | d_mode, |
||
13738 | d_mode, |
||
13739 | /* d9 */ |
||
13740 | d_mode, |
||
13741 | 0, |
||
13742 | d_mode, |
||
13743 | d_mode, |
||
13744 | 0, |
||
13745 | w_mode, |
||
13746 | 0, |
||
13747 | w_mode, |
||
13748 | /* da */ |
||
13749 | d_mode, |
||
13750 | d_mode, |
||
13751 | d_mode, |
||
13752 | d_mode, |
||
13753 | d_mode, |
||
13754 | d_mode, |
||
13755 | d_mode, |
||
13756 | d_mode, |
||
13757 | /* db */ |
||
13758 | d_mode, |
||
13759 | d_mode, |
||
13760 | d_mode, |
||
13761 | d_mode, |
||
13762 | 0, |
||
13763 | t_mode, |
||
13764 | 0, |
||
13765 | t_mode, |
||
13766 | /* dc */ |
||
13767 | q_mode, |
||
13768 | q_mode, |
||
13769 | q_mode, |
||
13770 | q_mode, |
||
13771 | q_mode, |
||
13772 | q_mode, |
||
13773 | q_mode, |
||
13774 | q_mode, |
||
13775 | /* dd */ |
||
13776 | q_mode, |
||
13777 | q_mode, |
||
13778 | q_mode, |
||
13779 | q_mode, |
||
13780 | 0, |
||
13781 | 0, |
||
13782 | 0, |
||
13783 | w_mode, |
||
13784 | /* de */ |
||
13785 | w_mode, |
||
13786 | w_mode, |
||
13787 | w_mode, |
||
13788 | w_mode, |
||
13789 | w_mode, |
||
13790 | w_mode, |
||
13791 | w_mode, |
||
13792 | w_mode, |
||
13793 | /* df */ |
||
13794 | w_mode, |
||
13795 | w_mode, |
||
13796 | w_mode, |
||
13797 | w_mode, |
||
13798 | t_mode, |
||
13799 | q_mode, |
||
13800 | t_mode, |
||
13801 | q_mode |
||
13802 | }; |
||
13803 | |||
13804 | #define ST { OP_ST, 0 } |
||
13805 | #define STi { OP_STi, 0 } |
||
13806 | |||
6324 | serge | 13807 | #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 |
13808 | #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 |
||
13809 | #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 |
||
13810 | #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 |
||
13811 | #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 |
||
13812 | #define FGRPda_5 NULL, { { NULL, 5 } }, 0 |
||
13813 | #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 |
||
13814 | #define FGRPde_3 NULL, { { NULL, 7 } }, 0 |
||
13815 | #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 |
||
5221 | serge | 13816 | |
13817 | static const struct dis386 float_reg[][8] = { |
||
13818 | /* d8 */ |
||
13819 | { |
||
6324 | serge | 13820 | { "fadd", { ST, STi }, 0 }, |
13821 | { "fmul", { ST, STi }, 0 }, |
||
13822 | { "fcom", { STi }, 0 }, |
||
13823 | { "fcomp", { STi }, 0 }, |
||
13824 | { "fsub", { ST, STi }, 0 }, |
||
13825 | { "fsubr", { ST, STi }, 0 }, |
||
13826 | { "fdiv", { ST, STi }, 0 }, |
||
13827 | { "fdivr", { ST, STi }, 0 }, |
||
5221 | serge | 13828 | }, |
13829 | /* d9 */ |
||
13830 | { |
||
6324 | serge | 13831 | { "fld", { STi }, 0 }, |
13832 | { "fxch", { STi }, 0 }, |
||
5221 | serge | 13833 | { FGRPd9_2 }, |
13834 | { Bad_Opcode }, |
||
13835 | { FGRPd9_4 }, |
||
13836 | { FGRPd9_5 }, |
||
13837 | { FGRPd9_6 }, |
||
13838 | { FGRPd9_7 }, |
||
13839 | }, |
||
13840 | /* da */ |
||
13841 | { |
||
6324 | serge | 13842 | { "fcmovb", { ST, STi }, 0 }, |
13843 | { "fcmove", { ST, STi }, 0 }, |
||
13844 | { "fcmovbe",{ ST, STi }, 0 }, |
||
13845 | { "fcmovu", { ST, STi }, 0 }, |
||
5221 | serge | 13846 | { Bad_Opcode }, |
13847 | { FGRPda_5 }, |
||
13848 | { Bad_Opcode }, |
||
13849 | { Bad_Opcode }, |
||
13850 | }, |
||
13851 | /* db */ |
||
13852 | { |
||
6324 | serge | 13853 | { "fcmovnb",{ ST, STi }, 0 }, |
13854 | { "fcmovne",{ ST, STi }, 0 }, |
||
13855 | { "fcmovnbe",{ ST, STi }, 0 }, |
||
13856 | { "fcmovnu",{ ST, STi }, 0 }, |
||
5221 | serge | 13857 | { FGRPdb_4 }, |
6324 | serge | 13858 | { "fucomi", { ST, STi }, 0 }, |
13859 | { "fcomi", { ST, STi }, 0 }, |
||
5221 | serge | 13860 | { Bad_Opcode }, |
13861 | }, |
||
13862 | /* dc */ |
||
13863 | { |
||
6324 | serge | 13864 | { "fadd", { STi, ST }, 0 }, |
13865 | { "fmul", { STi, ST }, 0 }, |
||
5221 | serge | 13866 | { Bad_Opcode }, |
13867 | { Bad_Opcode }, |
||
6324 | serge | 13868 | { "fsub!M", { STi, ST }, 0 }, |
13869 | { "fsubM", { STi, ST }, 0 }, |
||
13870 | { "fdiv!M", { STi, ST }, 0 }, |
||
13871 | { "fdivM", { STi, ST }, 0 }, |
||
5221 | serge | 13872 | }, |
13873 | /* dd */ |
||
13874 | { |
||
6324 | serge | 13875 | { "ffree", { STi }, 0 }, |
5221 | serge | 13876 | { Bad_Opcode }, |
6324 | serge | 13877 | { "fst", { STi }, 0 }, |
13878 | { "fstp", { STi }, 0 }, |
||
13879 | { "fucom", { STi }, 0 }, |
||
13880 | { "fucomp", { STi }, 0 }, |
||
5221 | serge | 13881 | { Bad_Opcode }, |
13882 | { Bad_Opcode }, |
||
13883 | }, |
||
13884 | /* de */ |
||
13885 | { |
||
6324 | serge | 13886 | { "faddp", { STi, ST }, 0 }, |
13887 | { "fmulp", { STi, ST }, 0 }, |
||
5221 | serge | 13888 | { Bad_Opcode }, |
13889 | { FGRPde_3 }, |
||
6324 | serge | 13890 | { "fsub!Mp", { STi, ST }, 0 }, |
13891 | { "fsubMp", { STi, ST }, 0 }, |
||
13892 | { "fdiv!Mp", { STi, ST }, 0 }, |
||
13893 | { "fdivMp", { STi, ST }, 0 }, |
||
5221 | serge | 13894 | }, |
13895 | /* df */ |
||
13896 | { |
||
6324 | serge | 13897 | { "ffreep", { STi }, 0 }, |
5221 | serge | 13898 | { Bad_Opcode }, |
13899 | { Bad_Opcode }, |
||
13900 | { Bad_Opcode }, |
||
13901 | { FGRPdf_4 }, |
||
6324 | serge | 13902 | { "fucomip", { ST, STi }, 0 }, |
13903 | { "fcomip", { ST, STi }, 0 }, |
||
5221 | serge | 13904 | { Bad_Opcode }, |
13905 | }, |
||
13906 | }; |
||
13907 | |||
13908 | static char *fgrps[][8] = { |
||
13909 | /* d9_2 0 */ |
||
13910 | { |
||
13911 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
||
13912 | }, |
||
13913 | |||
13914 | /* d9_4 1 */ |
||
13915 | { |
||
13916 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", |
||
13917 | }, |
||
13918 | |||
13919 | /* d9_5 2 */ |
||
13920 | { |
||
13921 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", |
||
13922 | }, |
||
13923 | |||
13924 | /* d9_6 3 */ |
||
13925 | { |
||
13926 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", |
||
13927 | }, |
||
13928 | |||
13929 | /* d9_7 4 */ |
||
13930 | { |
||
13931 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", |
||
13932 | }, |
||
13933 | |||
13934 | /* da_5 5 */ |
||
13935 | { |
||
13936 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
||
13937 | }, |
||
13938 | |||
13939 | /* db_4 6 */ |
||
13940 | { |
||
13941 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
||
13942 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", |
||
13943 | }, |
||
13944 | |||
13945 | /* de_3 7 */ |
||
13946 | { |
||
13947 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
||
13948 | }, |
||
13949 | |||
13950 | /* df_4 8 */ |
||
13951 | { |
||
13952 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
||
13953 | }, |
||
13954 | }; |
||
13955 | |||
13956 | static void |
||
13957 | swap_operand (void) |
||
13958 | { |
||
13959 | mnemonicendp[0] = '.'; |
||
13960 | mnemonicendp[1] = 's'; |
||
13961 | mnemonicendp += 2; |
||
13962 | } |
||
13963 | |||
13964 | static void |
||
13965 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, |
||
13966 | int sizeflag ATTRIBUTE_UNUSED) |
||
13967 | { |
||
13968 | /* Skip mod/rm byte. */ |
||
13969 | MODRM_CHECK; |
||
13970 | codep++; |
||
13971 | } |
||
13972 | |||
13973 | static void |
||
13974 | dofloat (int sizeflag) |
||
13975 | { |
||
13976 | const struct dis386 *dp; |
||
13977 | unsigned char floatop; |
||
13978 | |||
13979 | floatop = codep[-1]; |
||
13980 | |||
13981 | if (modrm.mod != 3) |
||
13982 | { |
||
13983 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
||
13984 | |||
13985 | putop (float_mem[fp_indx], sizeflag); |
||
13986 | obufp = op_out[0]; |
||
13987 | op_ad = 2; |
||
13988 | OP_E (float_mem_mode[fp_indx], sizeflag); |
||
13989 | return; |
||
13990 | } |
||
13991 | /* Skip mod/rm byte. */ |
||
13992 | MODRM_CHECK; |
||
13993 | codep++; |
||
13994 | |||
13995 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
||
13996 | if (dp->name == NULL) |
||
13997 | { |
||
13998 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
||
13999 | |||
14000 | /* Instruction fnstsw is only one with strange arg. */ |
||
14001 | if (floatop == 0xdf && codep[-1] == 0xe0) |
||
14002 | strcpy (op_out[0], names16[0]); |
||
14003 | } |
||
14004 | else |
||
14005 | { |
||
14006 | putop (dp->name, sizeflag); |
||
14007 | |||
14008 | obufp = op_out[0]; |
||
14009 | op_ad = 2; |
||
14010 | if (dp->op[0].rtn) |
||
14011 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); |
||
14012 | |||
14013 | obufp = op_out[1]; |
||
14014 | op_ad = 1; |
||
14015 | if (dp->op[1].rtn) |
||
14016 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); |
||
14017 | } |
||
14018 | } |
||
14019 | |||
14020 | /* Like oappend (below), but S is a string starting with '%'. |
||
14021 | In Intel syntax, the '%' is elided. */ |
||
14022 | static void |
||
14023 | oappend_maybe_intel (const char *s) |
||
14024 | { |
||
14025 | oappend (s + intel_syntax); |
||
14026 | } |
||
14027 | |||
14028 | static void |
||
14029 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
14030 | { |
||
14031 | oappend_maybe_intel ("%st"); |
||
14032 | } |
||
14033 | |||
14034 | static void |
||
14035 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
14036 | { |
||
14037 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
||
14038 | oappend_maybe_intel (scratchbuf); |
||
14039 | } |
||
14040 | |||
14041 | /* Capital letters in template are macros. */ |
||
14042 | static int |
||
14043 | putop (const char *in_template, int sizeflag) |
||
14044 | { |
||
14045 | const char *p; |
||
14046 | int alt = 0; |
||
14047 | int cond = 1; |
||
14048 | unsigned int l = 0, len = 1; |
||
14049 | char last[4]; |
||
14050 | |||
14051 | #define SAVE_LAST(c) \ |
||
14052 | if (l < len && l < sizeof (last)) \ |
||
14053 | last[l++] = c; \ |
||
14054 | else \ |
||
14055 | abort (); |
||
14056 | |||
14057 | for (p = in_template; *p; p++) |
||
14058 | { |
||
14059 | switch (*p) |
||
14060 | { |
||
14061 | default: |
||
14062 | *obufp++ = *p; |
||
14063 | break; |
||
14064 | case '%': |
||
14065 | len++; |
||
14066 | break; |
||
14067 | case '!': |
||
14068 | cond = 0; |
||
14069 | break; |
||
14070 | case '{': |
||
14071 | alt = 0; |
||
14072 | if (intel_syntax) |
||
14073 | { |
||
14074 | while (*++p != '|') |
||
14075 | if (*p == '}' || *p == '\0') |
||
14076 | abort (); |
||
14077 | } |
||
14078 | /* Fall through. */ |
||
14079 | case 'I': |
||
14080 | alt = 1; |
||
14081 | continue; |
||
14082 | case '|': |
||
14083 | while (*++p != '}') |
||
14084 | { |
||
14085 | if (*p == '\0') |
||
14086 | abort (); |
||
14087 | } |
||
14088 | break; |
||
14089 | case '}': |
||
14090 | break; |
||
14091 | case 'A': |
||
14092 | if (intel_syntax) |
||
14093 | break; |
||
14094 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
||
14095 | *obufp++ = 'b'; |
||
14096 | break; |
||
14097 | case 'B': |
||
14098 | if (l == 0 && len == 1) |
||
14099 | { |
||
14100 | case_B: |
||
14101 | if (intel_syntax) |
||
14102 | break; |
||
14103 | if (sizeflag & SUFFIX_ALWAYS) |
||
14104 | *obufp++ = 'b'; |
||
14105 | } |
||
14106 | else |
||
14107 | { |
||
14108 | if (l != 1 |
||
14109 | || len != 2 |
||
14110 | || last[0] != 'L') |
||
14111 | { |
||
14112 | SAVE_LAST (*p); |
||
14113 | break; |
||
14114 | } |
||
14115 | |||
14116 | if (address_mode == mode_64bit |
||
14117 | && !(prefixes & PREFIX_ADDR)) |
||
14118 | { |
||
14119 | *obufp++ = 'a'; |
||
14120 | *obufp++ = 'b'; |
||
14121 | *obufp++ = 's'; |
||
14122 | } |
||
14123 | |||
14124 | goto case_B; |
||
14125 | } |
||
14126 | break; |
||
14127 | case 'C': |
||
14128 | if (intel_syntax && !alt) |
||
14129 | break; |
||
14130 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
||
14131 | { |
||
14132 | if (sizeflag & DFLAG) |
||
14133 | *obufp++ = intel_syntax ? 'd' : 'l'; |
||
14134 | else |
||
14135 | *obufp++ = intel_syntax ? 'w' : 's'; |
||
14136 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14137 | } |
||
14138 | break; |
||
14139 | case 'D': |
||
14140 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
||
14141 | break; |
||
14142 | USED_REX (REX_W); |
||
14143 | if (modrm.mod == 3) |
||
14144 | { |
||
14145 | if (rex & REX_W) |
||
14146 | *obufp++ = 'q'; |
||
14147 | else |
||
14148 | { |
||
14149 | if (sizeflag & DFLAG) |
||
14150 | *obufp++ = intel_syntax ? 'd' : 'l'; |
||
14151 | else |
||
14152 | *obufp++ = 'w'; |
||
14153 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14154 | } |
||
14155 | } |
||
14156 | else |
||
14157 | *obufp++ = 'w'; |
||
14158 | break; |
||
14159 | case 'E': /* For jcxz/jecxz */ |
||
14160 | if (address_mode == mode_64bit) |
||
14161 | { |
||
14162 | if (sizeflag & AFLAG) |
||
14163 | *obufp++ = 'r'; |
||
14164 | else |
||
14165 | *obufp++ = 'e'; |
||
14166 | } |
||
14167 | else |
||
14168 | if (sizeflag & AFLAG) |
||
14169 | *obufp++ = 'e'; |
||
14170 | used_prefixes |= (prefixes & PREFIX_ADDR); |
||
14171 | break; |
||
14172 | case 'F': |
||
14173 | if (intel_syntax) |
||
14174 | break; |
||
14175 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
||
14176 | { |
||
14177 | if (sizeflag & AFLAG) |
||
14178 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
||
14179 | else |
||
14180 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
||
14181 | used_prefixes |= (prefixes & PREFIX_ADDR); |
||
14182 | } |
||
14183 | break; |
||
14184 | case 'G': |
||
14185 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) |
||
14186 | break; |
||
14187 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
||
14188 | *obufp++ = 'l'; |
||
14189 | else |
||
14190 | *obufp++ = 'w'; |
||
14191 | if (!(rex & REX_W)) |
||
14192 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14193 | break; |
||
14194 | case 'H': |
||
14195 | if (intel_syntax) |
||
14196 | break; |
||
14197 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
||
14198 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) |
||
14199 | { |
||
14200 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); |
||
14201 | *obufp++ = ','; |
||
14202 | *obufp++ = 'p'; |
||
14203 | if (prefixes & PREFIX_DS) |
||
14204 | *obufp++ = 't'; |
||
14205 | else |
||
14206 | *obufp++ = 'n'; |
||
14207 | } |
||
14208 | break; |
||
14209 | case 'J': |
||
14210 | if (intel_syntax) |
||
14211 | break; |
||
14212 | *obufp++ = 'l'; |
||
14213 | break; |
||
14214 | case 'K': |
||
14215 | USED_REX (REX_W); |
||
14216 | if (rex & REX_W) |
||
14217 | *obufp++ = 'q'; |
||
14218 | else |
||
14219 | *obufp++ = 'd'; |
||
14220 | break; |
||
14221 | case 'Z': |
||
6324 | serge | 14222 | if (l != 0 || len != 1) |
14223 | { |
||
14224 | if (l != 1 || len != 2 || last[0] != 'X') |
||
14225 | { |
||
14226 | SAVE_LAST (*p); |
||
14227 | break; |
||
14228 | } |
||
14229 | if (!need_vex || !vex.evex) |
||
14230 | abort (); |
||
14231 | if (intel_syntax |
||
14232 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
||
14233 | break; |
||
14234 | switch (vex.length) |
||
14235 | { |
||
14236 | case 128: |
||
14237 | *obufp++ = 'x'; |
||
14238 | break; |
||
14239 | case 256: |
||
14240 | *obufp++ = 'y'; |
||
14241 | break; |
||
14242 | case 512: |
||
14243 | *obufp++ = 'z'; |
||
14244 | break; |
||
14245 | default: |
||
14246 | abort (); |
||
14247 | } |
||
14248 | break; |
||
14249 | } |
||
5221 | serge | 14250 | if (intel_syntax) |
14251 | break; |
||
14252 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) |
||
14253 | { |
||
14254 | *obufp++ = 'q'; |
||
14255 | break; |
||
14256 | } |
||
14257 | /* Fall through. */ |
||
14258 | goto case_L; |
||
14259 | case 'L': |
||
14260 | if (l != 0 || len != 1) |
||
14261 | { |
||
14262 | SAVE_LAST (*p); |
||
14263 | break; |
||
14264 | } |
||
14265 | case_L: |
||
14266 | if (intel_syntax) |
||
14267 | break; |
||
14268 | if (sizeflag & SUFFIX_ALWAYS) |
||
14269 | *obufp++ = 'l'; |
||
14270 | break; |
||
14271 | case 'M': |
||
14272 | if (intel_mnemonic != cond) |
||
14273 | *obufp++ = 'r'; |
||
14274 | break; |
||
14275 | case 'N': |
||
14276 | if ((prefixes & PREFIX_FWAIT) == 0) |
||
14277 | *obufp++ = 'n'; |
||
14278 | else |
||
14279 | used_prefixes |= PREFIX_FWAIT; |
||
14280 | break; |
||
14281 | case 'O': |
||
14282 | USED_REX (REX_W); |
||
14283 | if (rex & REX_W) |
||
14284 | *obufp++ = 'o'; |
||
14285 | else if (intel_syntax && (sizeflag & DFLAG)) |
||
14286 | *obufp++ = 'q'; |
||
14287 | else |
||
14288 | *obufp++ = 'd'; |
||
14289 | if (!(rex & REX_W)) |
||
14290 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14291 | break; |
||
14292 | case 'T': |
||
14293 | if (!intel_syntax |
||
14294 | && address_mode == mode_64bit |
||
14295 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
||
14296 | { |
||
14297 | *obufp++ = 'q'; |
||
14298 | break; |
||
14299 | } |
||
14300 | /* Fall through. */ |
||
6324 | serge | 14301 | goto case_P; |
5221 | serge | 14302 | case 'P': |
6324 | serge | 14303 | if (l == 0 && len == 1) |
5221 | serge | 14304 | { |
6324 | serge | 14305 | case_P: |
14306 | if (intel_syntax) |
||
5221 | serge | 14307 | { |
6324 | serge | 14308 | if ((rex & REX_W) == 0 |
14309 | && (prefixes & PREFIX_DATA)) |
||
14310 | { |
||
14311 | if ((sizeflag & DFLAG) == 0) |
||
14312 | *obufp++ = 'w'; |
||
14313 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14314 | } |
||
14315 | break; |
||
5221 | serge | 14316 | } |
6324 | serge | 14317 | if ((prefixes & PREFIX_DATA) |
14318 | || (rex & REX_W) |
||
14319 | || (sizeflag & SUFFIX_ALWAYS)) |
||
14320 | { |
||
14321 | USED_REX (REX_W); |
||
14322 | if (rex & REX_W) |
||
14323 | *obufp++ = 'q'; |
||
14324 | else |
||
14325 | { |
||
14326 | if (sizeflag & DFLAG) |
||
14327 | *obufp++ = 'l'; |
||
14328 | else |
||
14329 | *obufp++ = 'w'; |
||
14330 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14331 | } |
||
14332 | } |
||
5221 | serge | 14333 | } |
6324 | serge | 14334 | else |
5221 | serge | 14335 | { |
6324 | serge | 14336 | if (l != 1 || len != 2 || last[0] != 'L') |
5221 | serge | 14337 | { |
6324 | serge | 14338 | SAVE_LAST (*p); |
14339 | break; |
||
5221 | serge | 14340 | } |
6324 | serge | 14341 | |
14342 | if ((prefixes & PREFIX_DATA) |
||
14343 | || (rex & REX_W) |
||
14344 | || (sizeflag & SUFFIX_ALWAYS)) |
||
14345 | { |
||
14346 | USED_REX (REX_W); |
||
14347 | if (rex & REX_W) |
||
14348 | *obufp++ = 'q'; |
||
14349 | else |
||
14350 | { |
||
14351 | if (sizeflag & DFLAG) |
||
14352 | *obufp++ = intel_syntax ? 'd' : 'l'; |
||
14353 | else |
||
14354 | *obufp++ = 'w'; |
||
14355 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14356 | } |
||
14357 | } |
||
5221 | serge | 14358 | } |
14359 | break; |
||
14360 | case 'U': |
||
14361 | if (intel_syntax) |
||
14362 | break; |
||
14363 | if (address_mode == mode_64bit |
||
14364 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
||
14365 | { |
||
14366 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
||
14367 | *obufp++ = 'q'; |
||
14368 | break; |
||
14369 | } |
||
14370 | /* Fall through. */ |
||
14371 | goto case_Q; |
||
14372 | case 'Q': |
||
14373 | if (l == 0 && len == 1) |
||
14374 | { |
||
14375 | case_Q: |
||
14376 | if (intel_syntax && !alt) |
||
14377 | break; |
||
14378 | USED_REX (REX_W); |
||
14379 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
||
14380 | { |
||
14381 | if (rex & REX_W) |
||
14382 | *obufp++ = 'q'; |
||
14383 | else |
||
14384 | { |
||
14385 | if (sizeflag & DFLAG) |
||
14386 | *obufp++ = intel_syntax ? 'd' : 'l'; |
||
14387 | else |
||
14388 | *obufp++ = 'w'; |
||
14389 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14390 | } |
||
14391 | } |
||
14392 | } |
||
14393 | else |
||
14394 | { |
||
14395 | if (l != 1 || len != 2 || last[0] != 'L') |
||
14396 | { |
||
14397 | SAVE_LAST (*p); |
||
14398 | break; |
||
14399 | } |
||
14400 | if (intel_syntax |
||
14401 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
||
14402 | break; |
||
14403 | if ((rex & REX_W)) |
||
14404 | { |
||
14405 | USED_REX (REX_W); |
||
14406 | *obufp++ = 'q'; |
||
14407 | } |
||
14408 | else |
||
14409 | *obufp++ = 'l'; |
||
14410 | } |
||
14411 | break; |
||
14412 | case 'R': |
||
14413 | USED_REX (REX_W); |
||
14414 | if (rex & REX_W) |
||
14415 | *obufp++ = 'q'; |
||
14416 | else if (sizeflag & DFLAG) |
||
14417 | { |
||
14418 | if (intel_syntax) |
||
14419 | *obufp++ = 'd'; |
||
14420 | else |
||
14421 | *obufp++ = 'l'; |
||
14422 | } |
||
14423 | else |
||
14424 | *obufp++ = 'w'; |
||
14425 | if (intel_syntax && !p[1] |
||
14426 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
||
14427 | *obufp++ = 'e'; |
||
14428 | if (!(rex & REX_W)) |
||
14429 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14430 | break; |
||
14431 | case 'V': |
||
14432 | if (l == 0 && len == 1) |
||
14433 | { |
||
14434 | if (intel_syntax) |
||
14435 | break; |
||
14436 | if (address_mode == mode_64bit |
||
14437 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
||
14438 | { |
||
14439 | if (sizeflag & SUFFIX_ALWAYS) |
||
14440 | *obufp++ = 'q'; |
||
14441 | break; |
||
14442 | } |
||
14443 | } |
||
14444 | else |
||
14445 | { |
||
14446 | if (l != 1 |
||
14447 | || len != 2 |
||
14448 | || last[0] != 'L') |
||
14449 | { |
||
14450 | SAVE_LAST (*p); |
||
14451 | break; |
||
14452 | } |
||
14453 | |||
14454 | if (rex & REX_W) |
||
14455 | { |
||
14456 | *obufp++ = 'a'; |
||
14457 | *obufp++ = 'b'; |
||
14458 | *obufp++ = 's'; |
||
14459 | } |
||
14460 | } |
||
14461 | /* Fall through. */ |
||
14462 | goto case_S; |
||
14463 | case 'S': |
||
14464 | if (l == 0 && len == 1) |
||
14465 | { |
||
14466 | case_S: |
||
14467 | if (intel_syntax) |
||
14468 | break; |
||
14469 | if (sizeflag & SUFFIX_ALWAYS) |
||
14470 | { |
||
14471 | if (rex & REX_W) |
||
14472 | *obufp++ = 'q'; |
||
14473 | else |
||
14474 | { |
||
14475 | if (sizeflag & DFLAG) |
||
14476 | *obufp++ = 'l'; |
||
14477 | else |
||
14478 | *obufp++ = 'w'; |
||
14479 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14480 | } |
||
14481 | } |
||
14482 | } |
||
14483 | else |
||
14484 | { |
||
14485 | if (l != 1 |
||
14486 | || len != 2 |
||
14487 | || last[0] != 'L') |
||
14488 | { |
||
14489 | SAVE_LAST (*p); |
||
14490 | break; |
||
14491 | } |
||
14492 | |||
14493 | if (address_mode == mode_64bit |
||
14494 | && !(prefixes & PREFIX_ADDR)) |
||
14495 | { |
||
14496 | *obufp++ = 'a'; |
||
14497 | *obufp++ = 'b'; |
||
14498 | *obufp++ = 's'; |
||
14499 | } |
||
14500 | |||
14501 | goto case_S; |
||
14502 | } |
||
14503 | break; |
||
14504 | case 'X': |
||
14505 | if (l != 0 || len != 1) |
||
14506 | { |
||
14507 | SAVE_LAST (*p); |
||
14508 | break; |
||
14509 | } |
||
14510 | if (need_vex && vex.prefix) |
||
14511 | { |
||
14512 | if (vex.prefix == DATA_PREFIX_OPCODE) |
||
14513 | *obufp++ = 'd'; |
||
14514 | else |
||
14515 | *obufp++ = 's'; |
||
14516 | } |
||
14517 | else |
||
14518 | { |
||
14519 | if (prefixes & PREFIX_DATA) |
||
14520 | *obufp++ = 'd'; |
||
14521 | else |
||
14522 | *obufp++ = 's'; |
||
14523 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14524 | } |
||
14525 | break; |
||
14526 | case 'Y': |
||
14527 | if (l == 0 && len == 1) |
||
14528 | { |
||
14529 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
||
14530 | break; |
||
14531 | if (rex & REX_W) |
||
14532 | { |
||
14533 | USED_REX (REX_W); |
||
14534 | *obufp++ = 'q'; |
||
14535 | } |
||
14536 | break; |
||
14537 | } |
||
14538 | else |
||
14539 | { |
||
14540 | if (l != 1 || len != 2 || last[0] != 'X') |
||
14541 | { |
||
14542 | SAVE_LAST (*p); |
||
14543 | break; |
||
14544 | } |
||
14545 | if (!need_vex) |
||
14546 | abort (); |
||
14547 | if (intel_syntax |
||
6324 | serge | 14548 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
5221 | serge | 14549 | break; |
14550 | switch (vex.length) |
||
14551 | { |
||
14552 | case 128: |
||
14553 | *obufp++ = 'x'; |
||
14554 | break; |
||
14555 | case 256: |
||
14556 | *obufp++ = 'y'; |
||
14557 | break; |
||
6324 | serge | 14558 | case 512: |
14559 | if (!vex.evex) |
||
5221 | serge | 14560 | default: |
6324 | serge | 14561 | abort (); |
5221 | serge | 14562 | } |
14563 | } |
||
14564 | break; |
||
14565 | case 'W': |
||
14566 | if (l == 0 && len == 1) |
||
14567 | { |
||
14568 | /* operand size flag for cwtl, cbtw */ |
||
14569 | USED_REX (REX_W); |
||
14570 | if (rex & REX_W) |
||
14571 | { |
||
14572 | if (intel_syntax) |
||
14573 | *obufp++ = 'd'; |
||
14574 | else |
||
14575 | *obufp++ = 'l'; |
||
14576 | } |
||
14577 | else if (sizeflag & DFLAG) |
||
14578 | *obufp++ = 'w'; |
||
14579 | else |
||
14580 | *obufp++ = 'b'; |
||
14581 | if (!(rex & REX_W)) |
||
14582 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14583 | } |
||
14584 | else |
||
14585 | { |
||
14586 | if (l != 1 |
||
14587 | || len != 2 |
||
14588 | || (last[0] != 'X' |
||
14589 | && last[0] != 'L')) |
||
14590 | { |
||
14591 | SAVE_LAST (*p); |
||
14592 | break; |
||
14593 | } |
||
14594 | if (!need_vex) |
||
14595 | abort (); |
||
14596 | if (last[0] == 'X') |
||
14597 | *obufp++ = vex.w ? 'd': 's'; |
||
14598 | else |
||
14599 | *obufp++ = vex.w ? 'q': 'd'; |
||
14600 | } |
||
14601 | break; |
||
6324 | serge | 14602 | case '^': |
14603 | if (intel_syntax) |
||
14604 | break; |
||
14605 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
||
14606 | { |
||
14607 | if (sizeflag & DFLAG) |
||
14608 | *obufp++ = 'l'; |
||
14609 | else |
||
14610 | *obufp++ = 'w'; |
||
14611 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14612 | } |
||
14613 | break; |
||
14614 | case '@': |
||
14615 | if (intel_syntax) |
||
14616 | break; |
||
14617 | if (address_mode == mode_64bit |
||
14618 | && (isa64 == intel64 |
||
14619 | || ((sizeflag & DFLAG) || (rex & REX_W)))) |
||
14620 | *obufp++ = 'q'; |
||
14621 | else if ((prefixes & PREFIX_DATA)) |
||
14622 | { |
||
14623 | if (!(sizeflag & DFLAG)) |
||
14624 | *obufp++ = 'w'; |
||
14625 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14626 | } |
||
14627 | break; |
||
5221 | serge | 14628 | } |
14629 | alt = 0; |
||
14630 | } |
||
14631 | *obufp = 0; |
||
14632 | mnemonicendp = obufp; |
||
14633 | return 0; |
||
14634 | } |
||
14635 | |||
14636 | static void |
||
14637 | oappend (const char *s) |
||
14638 | { |
||
14639 | obufp = stpcpy (obufp, s); |
||
14640 | } |
||
14641 | |||
14642 | static void |
||
14643 | append_seg (void) |
||
14644 | { |
||
6324 | serge | 14645 | /* Only print the active segment register. */ |
14646 | if (!active_seg_prefix) |
||
14647 | return; |
||
14648 | |||
14649 | used_prefixes |= active_seg_prefix; |
||
14650 | switch (active_seg_prefix) |
||
5221 | serge | 14651 | { |
6324 | serge | 14652 | case PREFIX_CS: |
5221 | serge | 14653 | oappend_maybe_intel ("%cs:"); |
6324 | serge | 14654 | break; |
14655 | case PREFIX_DS: |
||
5221 | serge | 14656 | oappend_maybe_intel ("%ds:"); |
6324 | serge | 14657 | break; |
14658 | case PREFIX_SS: |
||
5221 | serge | 14659 | oappend_maybe_intel ("%ss:"); |
6324 | serge | 14660 | break; |
14661 | case PREFIX_ES: |
||
5221 | serge | 14662 | oappend_maybe_intel ("%es:"); |
6324 | serge | 14663 | break; |
14664 | case PREFIX_FS: |
||
5221 | serge | 14665 | oappend_maybe_intel ("%fs:"); |
6324 | serge | 14666 | break; |
14667 | case PREFIX_GS: |
||
5221 | serge | 14668 | oappend_maybe_intel ("%gs:"); |
6324 | serge | 14669 | break; |
14670 | default: |
||
14671 | break; |
||
5221 | serge | 14672 | } |
14673 | } |
||
14674 | |||
14675 | static void |
||
14676 | OP_indirE (int bytemode, int sizeflag) |
||
14677 | { |
||
14678 | if (!intel_syntax) |
||
14679 | oappend ("*"); |
||
14680 | OP_E (bytemode, sizeflag); |
||
14681 | } |
||
14682 | |||
14683 | static void |
||
14684 | print_operand_value (char *buf, int hex, bfd_vma disp) |
||
14685 | { |
||
14686 | if (address_mode == mode_64bit) |
||
14687 | { |
||
14688 | if (hex) |
||
14689 | { |
||
14690 | char tmp[30]; |
||
14691 | int i; |
||
14692 | buf[0] = '0'; |
||
14693 | buf[1] = 'x'; |
||
14694 | sprintf_vma (tmp, disp); |
||
14695 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
||
14696 | strcpy (buf + 2, tmp + i); |
||
14697 | } |
||
14698 | else |
||
14699 | { |
||
14700 | bfd_signed_vma v = disp; |
||
14701 | char tmp[30]; |
||
14702 | int i; |
||
14703 | if (v < 0) |
||
14704 | { |
||
14705 | *(buf++) = '-'; |
||
14706 | v = -disp; |
||
14707 | /* Check for possible overflow on 0x8000000000000000. */ |
||
14708 | if (v < 0) |
||
14709 | { |
||
14710 | strcpy (buf, "9223372036854775808"); |
||
14711 | return; |
||
14712 | } |
||
14713 | } |
||
14714 | if (!v) |
||
14715 | { |
||
14716 | strcpy (buf, "0"); |
||
14717 | return; |
||
14718 | } |
||
14719 | |||
14720 | i = 0; |
||
14721 | tmp[29] = 0; |
||
14722 | while (v) |
||
14723 | { |
||
14724 | tmp[28 - i] = (v % 10) + '0'; |
||
14725 | v /= 10; |
||
14726 | i++; |
||
14727 | } |
||
14728 | strcpy (buf, tmp + 29 - i); |
||
14729 | } |
||
14730 | } |
||
14731 | else |
||
14732 | { |
||
14733 | if (hex) |
||
14734 | sprintf (buf, "0x%x", (unsigned int) disp); |
||
14735 | else |
||
14736 | sprintf (buf, "%d", (int) disp); |
||
14737 | } |
||
14738 | } |
||
14739 | |||
14740 | /* Put DISP in BUF as signed hex number. */ |
||
14741 | |||
14742 | static void |
||
14743 | print_displacement (char *buf, bfd_vma disp) |
||
14744 | { |
||
14745 | bfd_signed_vma val = disp; |
||
14746 | char tmp[30]; |
||
14747 | int i, j = 0; |
||
14748 | |||
14749 | if (val < 0) |
||
14750 | { |
||
14751 | buf[j++] = '-'; |
||
14752 | val = -disp; |
||
14753 | |||
14754 | /* Check for possible overflow. */ |
||
14755 | if (val < 0) |
||
14756 | { |
||
14757 | switch (address_mode) |
||
14758 | { |
||
14759 | case mode_64bit: |
||
14760 | strcpy (buf + j, "0x8000000000000000"); |
||
14761 | break; |
||
14762 | case mode_32bit: |
||
14763 | strcpy (buf + j, "0x80000000"); |
||
14764 | break; |
||
14765 | case mode_16bit: |
||
14766 | strcpy (buf + j, "0x8000"); |
||
14767 | break; |
||
14768 | } |
||
14769 | return; |
||
14770 | } |
||
14771 | } |
||
14772 | |||
14773 | buf[j++] = '0'; |
||
14774 | buf[j++] = 'x'; |
||
14775 | |||
14776 | sprintf_vma (tmp, (bfd_vma) val); |
||
14777 | for (i = 0; tmp[i] == '0'; i++) |
||
14778 | continue; |
||
14779 | if (tmp[i] == '\0') |
||
14780 | i--; |
||
14781 | strcpy (buf + j, tmp + i); |
||
14782 | } |
||
14783 | |||
14784 | static void |
||
14785 | intel_operand_size (int bytemode, int sizeflag) |
||
14786 | { |
||
14787 | if (vex.evex |
||
14788 | && vex.b |
||
14789 | && (bytemode == x_mode |
||
14790 | || bytemode == evex_half_bcst_xmmq_mode)) |
||
14791 | { |
||
14792 | if (vex.w) |
||
14793 | oappend ("QWORD PTR "); |
||
14794 | else |
||
14795 | oappend ("DWORD PTR "); |
||
14796 | return; |
||
14797 | } |
||
14798 | switch (bytemode) |
||
14799 | { |
||
14800 | case b_mode: |
||
14801 | case b_swap_mode: |
||
14802 | case dqb_mode: |
||
6324 | serge | 14803 | case db_mode: |
5221 | serge | 14804 | oappend ("BYTE PTR "); |
14805 | break; |
||
14806 | case w_mode: |
||
6324 | serge | 14807 | case dw_mode: |
5221 | serge | 14808 | case dqw_mode: |
6324 | serge | 14809 | case dqw_swap_mode: |
5221 | serge | 14810 | oappend ("WORD PTR "); |
14811 | break; |
||
14812 | case stack_v_mode: |
||
14813 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
||
14814 | { |
||
14815 | oappend ("QWORD PTR "); |
||
14816 | break; |
||
14817 | } |
||
14818 | /* FALLTHRU */ |
||
14819 | case v_mode: |
||
14820 | case v_swap_mode: |
||
14821 | case dq_mode: |
||
14822 | USED_REX (REX_W); |
||
14823 | if (rex & REX_W) |
||
14824 | oappend ("QWORD PTR "); |
||
14825 | else |
||
14826 | { |
||
14827 | if ((sizeflag & DFLAG) || bytemode == dq_mode) |
||
14828 | oappend ("DWORD PTR "); |
||
14829 | else |
||
14830 | oappend ("WORD PTR "); |
||
14831 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14832 | } |
||
14833 | break; |
||
14834 | case z_mode: |
||
14835 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
||
14836 | *obufp++ = 'D'; |
||
14837 | oappend ("WORD PTR "); |
||
14838 | if (!(rex & REX_W)) |
||
14839 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14840 | break; |
||
14841 | case a_mode: |
||
14842 | if (sizeflag & DFLAG) |
||
14843 | oappend ("QWORD PTR "); |
||
14844 | else |
||
14845 | oappend ("DWORD PTR "); |
||
14846 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14847 | break; |
||
14848 | case d_mode: |
||
14849 | case d_scalar_mode: |
||
14850 | case d_scalar_swap_mode: |
||
14851 | case d_swap_mode: |
||
14852 | case dqd_mode: |
||
14853 | oappend ("DWORD PTR "); |
||
14854 | break; |
||
14855 | case q_mode: |
||
14856 | case q_scalar_mode: |
||
14857 | case q_scalar_swap_mode: |
||
14858 | case q_swap_mode: |
||
14859 | oappend ("QWORD PTR "); |
||
14860 | break; |
||
14861 | case m_mode: |
||
14862 | if (address_mode == mode_64bit) |
||
14863 | oappend ("QWORD PTR "); |
||
14864 | else |
||
14865 | oappend ("DWORD PTR "); |
||
14866 | break; |
||
14867 | case f_mode: |
||
14868 | if (sizeflag & DFLAG) |
||
14869 | oappend ("FWORD PTR "); |
||
14870 | else |
||
14871 | oappend ("DWORD PTR "); |
||
14872 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
14873 | break; |
||
14874 | case t_mode: |
||
14875 | oappend ("TBYTE PTR "); |
||
14876 | break; |
||
14877 | case x_mode: |
||
14878 | case x_swap_mode: |
||
14879 | case evex_x_gscat_mode: |
||
14880 | case evex_x_nobcst_mode: |
||
14881 | if (need_vex) |
||
14882 | { |
||
14883 | switch (vex.length) |
||
14884 | { |
||
14885 | case 128: |
||
14886 | oappend ("XMMWORD PTR "); |
||
14887 | break; |
||
14888 | case 256: |
||
14889 | oappend ("YMMWORD PTR "); |
||
14890 | break; |
||
14891 | case 512: |
||
14892 | oappend ("ZMMWORD PTR "); |
||
14893 | break; |
||
14894 | default: |
||
14895 | abort (); |
||
14896 | } |
||
14897 | } |
||
14898 | else |
||
14899 | oappend ("XMMWORD PTR "); |
||
14900 | break; |
||
14901 | case xmm_mode: |
||
14902 | oappend ("XMMWORD PTR "); |
||
14903 | break; |
||
14904 | case ymm_mode: |
||
14905 | oappend ("YMMWORD PTR "); |
||
14906 | break; |
||
14907 | case xmmq_mode: |
||
14908 | case evex_half_bcst_xmmq_mode: |
||
14909 | if (!need_vex) |
||
14910 | abort (); |
||
14911 | |||
14912 | switch (vex.length) |
||
14913 | { |
||
14914 | case 128: |
||
14915 | oappend ("QWORD PTR "); |
||
14916 | break; |
||
14917 | case 256: |
||
14918 | oappend ("XMMWORD PTR "); |
||
14919 | break; |
||
14920 | case 512: |
||
14921 | oappend ("YMMWORD PTR "); |
||
14922 | break; |
||
14923 | default: |
||
14924 | abort (); |
||
14925 | } |
||
14926 | break; |
||
14927 | case xmm_mb_mode: |
||
14928 | if (!need_vex) |
||
14929 | abort (); |
||
14930 | |||
14931 | switch (vex.length) |
||
14932 | { |
||
14933 | case 128: |
||
14934 | case 256: |
||
14935 | case 512: |
||
14936 | oappend ("BYTE PTR "); |
||
14937 | break; |
||
14938 | default: |
||
14939 | abort (); |
||
14940 | } |
||
14941 | break; |
||
14942 | case xmm_mw_mode: |
||
14943 | if (!need_vex) |
||
14944 | abort (); |
||
14945 | |||
14946 | switch (vex.length) |
||
14947 | { |
||
14948 | case 128: |
||
14949 | case 256: |
||
14950 | case 512: |
||
14951 | oappend ("WORD PTR "); |
||
14952 | break; |
||
14953 | default: |
||
14954 | abort (); |
||
14955 | } |
||
14956 | break; |
||
14957 | case xmm_md_mode: |
||
14958 | if (!need_vex) |
||
14959 | abort (); |
||
14960 | |||
14961 | switch (vex.length) |
||
14962 | { |
||
14963 | case 128: |
||
14964 | case 256: |
||
14965 | case 512: |
||
14966 | oappend ("DWORD PTR "); |
||
14967 | break; |
||
14968 | default: |
||
14969 | abort (); |
||
14970 | } |
||
14971 | break; |
||
14972 | case xmm_mq_mode: |
||
14973 | if (!need_vex) |
||
14974 | abort (); |
||
14975 | |||
14976 | switch (vex.length) |
||
14977 | { |
||
14978 | case 128: |
||
14979 | case 256: |
||
14980 | case 512: |
||
14981 | oappend ("QWORD PTR "); |
||
14982 | break; |
||
14983 | default: |
||
14984 | abort (); |
||
14985 | } |
||
14986 | break; |
||
14987 | case xmmdw_mode: |
||
14988 | if (!need_vex) |
||
14989 | abort (); |
||
14990 | |||
14991 | switch (vex.length) |
||
14992 | { |
||
14993 | case 128: |
||
14994 | oappend ("WORD PTR "); |
||
14995 | break; |
||
14996 | case 256: |
||
14997 | oappend ("DWORD PTR "); |
||
14998 | break; |
||
14999 | case 512: |
||
15000 | oappend ("QWORD PTR "); |
||
15001 | break; |
||
15002 | default: |
||
15003 | abort (); |
||
15004 | } |
||
15005 | break; |
||
15006 | case xmmqd_mode: |
||
15007 | if (!need_vex) |
||
15008 | abort (); |
||
15009 | |||
15010 | switch (vex.length) |
||
15011 | { |
||
15012 | case 128: |
||
15013 | oappend ("DWORD PTR "); |
||
15014 | break; |
||
15015 | case 256: |
||
15016 | oappend ("QWORD PTR "); |
||
15017 | break; |
||
15018 | case 512: |
||
15019 | oappend ("XMMWORD PTR "); |
||
15020 | break; |
||
15021 | default: |
||
15022 | abort (); |
||
15023 | } |
||
15024 | break; |
||
15025 | case ymmq_mode: |
||
15026 | if (!need_vex) |
||
15027 | abort (); |
||
15028 | |||
15029 | switch (vex.length) |
||
15030 | { |
||
15031 | case 128: |
||
15032 | oappend ("QWORD PTR "); |
||
15033 | break; |
||
15034 | case 256: |
||
15035 | oappend ("YMMWORD PTR "); |
||
15036 | break; |
||
15037 | case 512: |
||
15038 | oappend ("ZMMWORD PTR "); |
||
15039 | break; |
||
15040 | default: |
||
15041 | abort (); |
||
15042 | } |
||
15043 | break; |
||
15044 | case ymmxmm_mode: |
||
15045 | if (!need_vex) |
||
15046 | abort (); |
||
15047 | |||
15048 | switch (vex.length) |
||
15049 | { |
||
15050 | case 128: |
||
15051 | case 256: |
||
15052 | oappend ("XMMWORD PTR "); |
||
15053 | break; |
||
15054 | default: |
||
15055 | abort (); |
||
15056 | } |
||
15057 | break; |
||
15058 | case o_mode: |
||
15059 | oappend ("OWORD PTR "); |
||
15060 | break; |
||
15061 | case xmm_mdq_mode: |
||
15062 | case vex_w_dq_mode: |
||
15063 | case vex_scalar_w_dq_mode: |
||
15064 | if (!need_vex) |
||
15065 | abort (); |
||
15066 | |||
15067 | if (vex.w) |
||
15068 | oappend ("QWORD PTR "); |
||
15069 | else |
||
15070 | oappend ("DWORD PTR "); |
||
15071 | break; |
||
15072 | case vex_vsib_d_w_dq_mode: |
||
15073 | case vex_vsib_q_w_dq_mode: |
||
15074 | if (!need_vex) |
||
15075 | abort (); |
||
15076 | |||
15077 | if (!vex.evex) |
||
15078 | { |
||
15079 | if (vex.w) |
||
15080 | oappend ("QWORD PTR "); |
||
15081 | else |
||
15082 | oappend ("DWORD PTR "); |
||
15083 | } |
||
15084 | else |
||
15085 | { |
||
6324 | serge | 15086 | switch (vex.length) |
15087 | { |
||
15088 | case 128: |
||
15089 | oappend ("XMMWORD PTR "); |
||
15090 | break; |
||
15091 | case 256: |
||
15092 | oappend ("YMMWORD PTR "); |
||
15093 | break; |
||
15094 | case 512: |
||
15095 | oappend ("ZMMWORD PTR "); |
||
15096 | break; |
||
15097 | default: |
||
15098 | abort (); |
||
15099 | } |
||
5221 | serge | 15100 | } |
15101 | break; |
||
6324 | serge | 15102 | case vex_vsib_q_w_d_mode: |
15103 | case vex_vsib_d_w_d_mode: |
||
15104 | if (!need_vex || !vex.evex) |
||
15105 | abort (); |
||
15106 | |||
15107 | switch (vex.length) |
||
15108 | { |
||
15109 | case 128: |
||
15110 | oappend ("QWORD PTR "); |
||
15111 | break; |
||
15112 | case 256: |
||
15113 | oappend ("XMMWORD PTR "); |
||
15114 | break; |
||
15115 | case 512: |
||
15116 | oappend ("YMMWORD PTR "); |
||
15117 | break; |
||
15118 | default: |
||
15119 | abort (); |
||
15120 | } |
||
15121 | |||
15122 | break; |
||
15123 | case mask_bd_mode: |
||
15124 | if (!need_vex || vex.length != 128) |
||
15125 | abort (); |
||
15126 | if (vex.w) |
||
15127 | oappend ("DWORD PTR "); |
||
15128 | else |
||
15129 | oappend ("BYTE PTR "); |
||
15130 | break; |
||
5221 | serge | 15131 | case mask_mode: |
15132 | if (!need_vex) |
||
15133 | abort (); |
||
6324 | serge | 15134 | if (vex.w) |
15135 | oappend ("QWORD PTR "); |
||
15136 | else |
||
15137 | oappend ("WORD PTR "); |
||
5221 | serge | 15138 | break; |
15139 | case v_bnd_mode: |
||
15140 | default: |
||
15141 | break; |
||
15142 | } |
||
15143 | } |
||
15144 | |||
15145 | static void |
||
15146 | OP_E_register (int bytemode, int sizeflag) |
||
15147 | { |
||
15148 | int reg = modrm.rm; |
||
15149 | const char **names; |
||
15150 | |||
15151 | USED_REX (REX_B); |
||
15152 | if ((rex & REX_B)) |
||
15153 | reg += 8; |
||
15154 | |||
15155 | if ((sizeflag & SUFFIX_ALWAYS) |
||
6324 | serge | 15156 | && (bytemode == b_swap_mode |
15157 | || bytemode == v_swap_mode |
||
15158 | || bytemode == dqw_swap_mode)) |
||
5221 | serge | 15159 | swap_operand (); |
15160 | |||
15161 | switch (bytemode) |
||
15162 | { |
||
15163 | case b_mode: |
||
15164 | case b_swap_mode: |
||
15165 | USED_REX (0); |
||
15166 | if (rex) |
||
15167 | names = names8rex; |
||
15168 | else |
||
15169 | names = names8; |
||
15170 | break; |
||
15171 | case w_mode: |
||
15172 | names = names16; |
||
15173 | break; |
||
15174 | case d_mode: |
||
6324 | serge | 15175 | case dw_mode: |
15176 | case db_mode: |
||
5221 | serge | 15177 | names = names32; |
15178 | break; |
||
15179 | case q_mode: |
||
15180 | names = names64; |
||
15181 | break; |
||
15182 | case m_mode: |
||
15183 | case v_bnd_mode: |
||
15184 | names = address_mode == mode_64bit ? names64 : names32; |
||
15185 | break; |
||
15186 | case bnd_mode: |
||
15187 | names = names_bnd; |
||
15188 | break; |
||
15189 | case stack_v_mode: |
||
15190 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
||
15191 | { |
||
15192 | names = names64; |
||
15193 | break; |
||
15194 | } |
||
15195 | bytemode = v_mode; |
||
15196 | /* FALLTHRU */ |
||
15197 | case v_mode: |
||
15198 | case v_swap_mode: |
||
15199 | case dq_mode: |
||
15200 | case dqb_mode: |
||
15201 | case dqd_mode: |
||
15202 | case dqw_mode: |
||
6324 | serge | 15203 | case dqw_swap_mode: |
5221 | serge | 15204 | USED_REX (REX_W); |
15205 | if (rex & REX_W) |
||
15206 | names = names64; |
||
15207 | else |
||
15208 | { |
||
15209 | if ((sizeflag & DFLAG) |
||
15210 | || (bytemode != v_mode |
||
15211 | && bytemode != v_swap_mode)) |
||
15212 | names = names32; |
||
15213 | else |
||
15214 | names = names16; |
||
15215 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
15216 | } |
||
15217 | break; |
||
6324 | serge | 15218 | case mask_bd_mode: |
5221 | serge | 15219 | case mask_mode: |
15220 | names = names_mask; |
||
15221 | break; |
||
15222 | case 0: |
||
15223 | return; |
||
15224 | default: |
||
15225 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
15226 | return; |
||
15227 | } |
||
15228 | oappend (names[reg]); |
||
15229 | } |
||
15230 | |||
15231 | static void |
||
15232 | OP_E_memory (int bytemode, int sizeflag) |
||
15233 | { |
||
15234 | bfd_vma disp = 0; |
||
15235 | int add = (rex & REX_B) ? 8 : 0; |
||
15236 | int riprel = 0; |
||
15237 | int shift; |
||
15238 | |||
15239 | if (vex.evex) |
||
15240 | { |
||
15241 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ |
||
15242 | if (vex.b |
||
15243 | && bytemode != x_mode |
||
6324 | serge | 15244 | && bytemode != xmmq_mode |
5221 | serge | 15245 | && bytemode != evex_half_bcst_xmmq_mode) |
15246 | { |
||
15247 | BadOp (); |
||
15248 | return; |
||
15249 | } |
||
15250 | switch (bytemode) |
||
15251 | { |
||
6324 | serge | 15252 | case dqw_mode: |
15253 | case dw_mode: |
||
15254 | case dqw_swap_mode: |
||
15255 | shift = 1; |
||
15256 | break; |
||
15257 | case dqb_mode: |
||
15258 | case db_mode: |
||
15259 | shift = 0; |
||
15260 | break; |
||
5221 | serge | 15261 | case vex_vsib_d_w_dq_mode: |
6324 | serge | 15262 | case vex_vsib_d_w_d_mode: |
15263 | case vex_vsib_q_w_dq_mode: |
||
15264 | case vex_vsib_q_w_d_mode: |
||
5221 | serge | 15265 | case evex_x_gscat_mode: |
15266 | case xmm_mdq_mode: |
||
15267 | shift = vex.w ? 3 : 2; |
||
15268 | break; |
||
15269 | case x_mode: |
||
15270 | case evex_half_bcst_xmmq_mode: |
||
6324 | serge | 15271 | case xmmq_mode: |
5221 | serge | 15272 | if (vex.b) |
15273 | { |
||
15274 | shift = vex.w ? 3 : 2; |
||
15275 | break; |
||
15276 | } |
||
15277 | /* Fall through if vex.b == 0. */ |
||
15278 | case xmmqd_mode: |
||
15279 | case xmmdw_mode: |
||
15280 | case ymmq_mode: |
||
15281 | case evex_x_nobcst_mode: |
||
15282 | case x_swap_mode: |
||
15283 | switch (vex.length) |
||
15284 | { |
||
15285 | case 128: |
||
15286 | shift = 4; |
||
15287 | break; |
||
15288 | case 256: |
||
15289 | shift = 5; |
||
15290 | break; |
||
15291 | case 512: |
||
15292 | shift = 6; |
||
15293 | break; |
||
15294 | default: |
||
15295 | abort (); |
||
15296 | } |
||
15297 | break; |
||
15298 | case ymm_mode: |
||
15299 | shift = 5; |
||
15300 | break; |
||
15301 | case xmm_mode: |
||
15302 | shift = 4; |
||
15303 | break; |
||
15304 | case xmm_mq_mode: |
||
15305 | case q_mode: |
||
15306 | case q_scalar_mode: |
||
15307 | case q_swap_mode: |
||
15308 | case q_scalar_swap_mode: |
||
15309 | shift = 3; |
||
15310 | break; |
||
15311 | case dqd_mode: |
||
15312 | case xmm_md_mode: |
||
15313 | case d_mode: |
||
15314 | case d_scalar_mode: |
||
15315 | case d_swap_mode: |
||
15316 | case d_scalar_swap_mode: |
||
15317 | shift = 2; |
||
15318 | break; |
||
15319 | case xmm_mw_mode: |
||
15320 | shift = 1; |
||
15321 | break; |
||
15322 | case xmm_mb_mode: |
||
15323 | shift = 0; |
||
15324 | break; |
||
15325 | default: |
||
15326 | abort (); |
||
15327 | } |
||
15328 | /* Make necessary corrections to shift for modes that need it. |
||
15329 | For these modes we currently have shift 4, 5 or 6 depending on |
||
15330 | vex.length (it corresponds to xmmword, ymmword or zmmword |
||
15331 | operand). We might want to make it 3, 4 or 5 (e.g. for |
||
15332 | xmmq_mode). In case of broadcast enabled the corrections |
||
15333 | aren't needed, as element size is always 32 or 64 bits. */ |
||
6324 | serge | 15334 | if (!vex.b |
15335 | && (bytemode == xmmq_mode |
||
15336 | || bytemode == evex_half_bcst_xmmq_mode)) |
||
5221 | serge | 15337 | shift -= 1; |
15338 | else if (bytemode == xmmqd_mode) |
||
15339 | shift -= 2; |
||
15340 | else if (bytemode == xmmdw_mode) |
||
15341 | shift -= 3; |
||
6324 | serge | 15342 | else if (bytemode == ymmq_mode && vex.length == 128) |
15343 | shift -= 1; |
||
5221 | serge | 15344 | } |
15345 | else |
||
15346 | shift = 0; |
||
15347 | |||
15348 | USED_REX (REX_B); |
||
15349 | if (intel_syntax) |
||
15350 | intel_operand_size (bytemode, sizeflag); |
||
15351 | append_seg (); |
||
15352 | |||
15353 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
||
15354 | { |
||
15355 | /* 32/64 bit address mode */ |
||
15356 | int havedisp; |
||
15357 | int havesib; |
||
15358 | int havebase; |
||
15359 | int haveindex; |
||
15360 | int needindex; |
||
15361 | int base, rbase; |
||
15362 | int vindex = 0; |
||
15363 | int scale = 0; |
||
15364 | int addr32flag = !((sizeflag & AFLAG) |
||
15365 | || bytemode == v_bnd_mode |
||
15366 | || bytemode == bnd_mode); |
||
15367 | const char **indexes64 = names64; |
||
15368 | const char **indexes32 = names32; |
||
15369 | |||
15370 | havesib = 0; |
||
15371 | havebase = 1; |
||
15372 | haveindex = 0; |
||
15373 | base = modrm.rm; |
||
15374 | |||
15375 | if (base == 4) |
||
15376 | { |
||
15377 | havesib = 1; |
||
15378 | vindex = sib.index; |
||
15379 | USED_REX (REX_X); |
||
15380 | if (rex & REX_X) |
||
15381 | vindex += 8; |
||
15382 | switch (bytemode) |
||
15383 | { |
||
15384 | case vex_vsib_d_w_dq_mode: |
||
6324 | serge | 15385 | case vex_vsib_d_w_d_mode: |
5221 | serge | 15386 | case vex_vsib_q_w_dq_mode: |
6324 | serge | 15387 | case vex_vsib_q_w_d_mode: |
5221 | serge | 15388 | if (!need_vex) |
15389 | abort (); |
||
15390 | if (vex.evex) |
||
15391 | { |
||
15392 | if (!vex.v) |
||
15393 | vindex += 16; |
||
15394 | } |
||
15395 | |||
15396 | haveindex = 1; |
||
15397 | switch (vex.length) |
||
15398 | { |
||
15399 | case 128: |
||
15400 | indexes64 = indexes32 = names_xmm; |
||
15401 | break; |
||
15402 | case 256: |
||
6324 | serge | 15403 | if (!vex.w |
15404 | || bytemode == vex_vsib_q_w_dq_mode |
||
15405 | || bytemode == vex_vsib_q_w_d_mode) |
||
5221 | serge | 15406 | indexes64 = indexes32 = names_ymm; |
15407 | else |
||
15408 | indexes64 = indexes32 = names_xmm; |
||
15409 | break; |
||
15410 | case 512: |
||
6324 | serge | 15411 | if (!vex.w |
15412 | || bytemode == vex_vsib_q_w_dq_mode |
||
15413 | || bytemode == vex_vsib_q_w_d_mode) |
||
5221 | serge | 15414 | indexes64 = indexes32 = names_zmm; |
15415 | else |
||
15416 | indexes64 = indexes32 = names_ymm; |
||
15417 | break; |
||
15418 | default: |
||
15419 | abort (); |
||
15420 | } |
||
15421 | break; |
||
15422 | default: |
||
15423 | haveindex = vindex != 4; |
||
15424 | break; |
||
15425 | } |
||
15426 | scale = sib.scale; |
||
15427 | base = sib.base; |
||
15428 | codep++; |
||
15429 | } |
||
15430 | rbase = base + add; |
||
15431 | |||
15432 | switch (modrm.mod) |
||
15433 | { |
||
15434 | case 0: |
||
15435 | if (base == 5) |
||
15436 | { |
||
15437 | havebase = 0; |
||
15438 | if (address_mode == mode_64bit && !havesib) |
||
15439 | riprel = 1; |
||
15440 | disp = get32s (); |
||
15441 | } |
||
15442 | break; |
||
15443 | case 1: |
||
15444 | FETCH_DATA (the_info, codep + 1); |
||
15445 | disp = *codep++; |
||
15446 | if ((disp & 0x80) != 0) |
||
15447 | disp -= 0x100; |
||
15448 | if (vex.evex && shift > 0) |
||
15449 | disp <<= shift; |
||
15450 | break; |
||
15451 | case 2: |
||
15452 | disp = get32s (); |
||
15453 | break; |
||
15454 | } |
||
15455 | |||
15456 | /* In 32bit mode, we need index register to tell [offset] from |
||
15457 | [eiz*1 + offset]. */ |
||
15458 | needindex = (havesib |
||
15459 | && !havebase |
||
15460 | && !haveindex |
||
15461 | && address_mode == mode_32bit); |
||
15462 | havedisp = (havebase |
||
15463 | || needindex |
||
15464 | || (havesib && (haveindex || scale != 0))); |
||
15465 | |||
15466 | if (!intel_syntax) |
||
15467 | if (modrm.mod != 0 || base == 5) |
||
15468 | { |
||
15469 | if (havedisp || riprel) |
||
15470 | print_displacement (scratchbuf, disp); |
||
15471 | else |
||
15472 | print_operand_value (scratchbuf, 1, disp); |
||
15473 | oappend (scratchbuf); |
||
15474 | if (riprel) |
||
15475 | { |
||
15476 | set_op (disp, 1); |
||
15477 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
||
15478 | } |
||
15479 | } |
||
15480 | |||
15481 | if ((havebase || haveindex || riprel) |
||
15482 | && (bytemode != v_bnd_mode) |
||
15483 | && (bytemode != bnd_mode)) |
||
15484 | used_prefixes |= PREFIX_ADDR; |
||
15485 | |||
15486 | if (havedisp || (intel_syntax && riprel)) |
||
15487 | { |
||
15488 | *obufp++ = open_char; |
||
15489 | if (intel_syntax && riprel) |
||
15490 | { |
||
15491 | set_op (disp, 1); |
||
15492 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
||
15493 | } |
||
15494 | *obufp = '\0'; |
||
15495 | if (havebase) |
||
15496 | oappend (address_mode == mode_64bit && !addr32flag |
||
15497 | ? names64[rbase] : names32[rbase]); |
||
15498 | if (havesib) |
||
15499 | { |
||
15500 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
||
15501 | print index to tell base + index from base. */ |
||
15502 | if (scale != 0 |
||
15503 | || needindex |
||
15504 | || haveindex |
||
15505 | || (havebase && base != ESP_REG_NUM)) |
||
15506 | { |
||
15507 | if (!intel_syntax || havebase) |
||
15508 | { |
||
15509 | *obufp++ = separator_char; |
||
15510 | *obufp = '\0'; |
||
15511 | } |
||
15512 | if (haveindex) |
||
15513 | oappend (address_mode == mode_64bit && !addr32flag |
||
15514 | ? indexes64[vindex] : indexes32[vindex]); |
||
15515 | else |
||
15516 | oappend (address_mode == mode_64bit && !addr32flag |
||
15517 | ? index64 : index32); |
||
15518 | |||
15519 | *obufp++ = scale_char; |
||
15520 | *obufp = '\0'; |
||
15521 | sprintf (scratchbuf, "%d", 1 << scale); |
||
15522 | oappend (scratchbuf); |
||
15523 | } |
||
15524 | } |
||
15525 | if (intel_syntax |
||
15526 | && (disp || modrm.mod != 0 || base == 5)) |
||
15527 | { |
||
15528 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
||
15529 | { |
||
15530 | *obufp++ = '+'; |
||
15531 | *obufp = '\0'; |
||
15532 | } |
||
15533 | else if (modrm.mod != 1 && disp != -disp) |
||
15534 | { |
||
15535 | *obufp++ = '-'; |
||
15536 | *obufp = '\0'; |
||
15537 | disp = - (bfd_signed_vma) disp; |
||
15538 | } |
||
15539 | |||
15540 | if (havedisp) |
||
15541 | print_displacement (scratchbuf, disp); |
||
15542 | else |
||
15543 | print_operand_value (scratchbuf, 1, disp); |
||
15544 | oappend (scratchbuf); |
||
15545 | } |
||
15546 | |||
15547 | *obufp++ = close_char; |
||
15548 | *obufp = '\0'; |
||
15549 | } |
||
15550 | else if (intel_syntax) |
||
15551 | { |
||
15552 | if (modrm.mod != 0 || base == 5) |
||
15553 | { |
||
6324 | serge | 15554 | if (!active_seg_prefix) |
5221 | serge | 15555 | { |
15556 | oappend (names_seg[ds_reg - es_reg]); |
||
15557 | oappend (":"); |
||
15558 | } |
||
15559 | print_operand_value (scratchbuf, 1, disp); |
||
15560 | oappend (scratchbuf); |
||
15561 | } |
||
15562 | } |
||
15563 | } |
||
15564 | else |
||
15565 | { |
||
15566 | /* 16 bit address mode */ |
||
15567 | used_prefixes |= prefixes & PREFIX_ADDR; |
||
15568 | switch (modrm.mod) |
||
15569 | { |
||
15570 | case 0: |
||
15571 | if (modrm.rm == 6) |
||
15572 | { |
||
15573 | disp = get16 (); |
||
15574 | if ((disp & 0x8000) != 0) |
||
15575 | disp -= 0x10000; |
||
15576 | } |
||
15577 | break; |
||
15578 | case 1: |
||
15579 | FETCH_DATA (the_info, codep + 1); |
||
15580 | disp = *codep++; |
||
15581 | if ((disp & 0x80) != 0) |
||
15582 | disp -= 0x100; |
||
15583 | break; |
||
15584 | case 2: |
||
15585 | disp = get16 (); |
||
15586 | if ((disp & 0x8000) != 0) |
||
15587 | disp -= 0x10000; |
||
15588 | break; |
||
15589 | } |
||
15590 | |||
15591 | if (!intel_syntax) |
||
15592 | if (modrm.mod != 0 || modrm.rm == 6) |
||
15593 | { |
||
15594 | print_displacement (scratchbuf, disp); |
||
15595 | oappend (scratchbuf); |
||
15596 | } |
||
15597 | |||
15598 | if (modrm.mod != 0 || modrm.rm != 6) |
||
15599 | { |
||
15600 | *obufp++ = open_char; |
||
15601 | *obufp = '\0'; |
||
15602 | oappend (index16[modrm.rm]); |
||
15603 | if (intel_syntax |
||
15604 | && (disp || modrm.mod != 0 || modrm.rm == 6)) |
||
15605 | { |
||
15606 | if ((bfd_signed_vma) disp >= 0) |
||
15607 | { |
||
15608 | *obufp++ = '+'; |
||
15609 | *obufp = '\0'; |
||
15610 | } |
||
15611 | else if (modrm.mod != 1) |
||
15612 | { |
||
15613 | *obufp++ = '-'; |
||
15614 | *obufp = '\0'; |
||
15615 | disp = - (bfd_signed_vma) disp; |
||
15616 | } |
||
15617 | |||
15618 | print_displacement (scratchbuf, disp); |
||
15619 | oappend (scratchbuf); |
||
15620 | } |
||
15621 | |||
15622 | *obufp++ = close_char; |
||
15623 | *obufp = '\0'; |
||
15624 | } |
||
15625 | else if (intel_syntax) |
||
15626 | { |
||
6324 | serge | 15627 | if (!active_seg_prefix) |
5221 | serge | 15628 | { |
15629 | oappend (names_seg[ds_reg - es_reg]); |
||
15630 | oappend (":"); |
||
15631 | } |
||
15632 | print_operand_value (scratchbuf, 1, disp & 0xffff); |
||
15633 | oappend (scratchbuf); |
||
15634 | } |
||
15635 | } |
||
15636 | if (vex.evex && vex.b |
||
15637 | && (bytemode == x_mode |
||
6324 | serge | 15638 | || bytemode == xmmq_mode |
5221 | serge | 15639 | || bytemode == evex_half_bcst_xmmq_mode)) |
15640 | { |
||
6324 | serge | 15641 | if (vex.w |
15642 | || bytemode == xmmq_mode |
||
15643 | || bytemode == evex_half_bcst_xmmq_mode) |
||
15644 | { |
||
15645 | switch (vex.length) |
||
15646 | { |
||
15647 | case 128: |
||
15648 | oappend ("{1to2}"); |
||
15649 | break; |
||
15650 | case 256: |
||
15651 | oappend ("{1to4}"); |
||
15652 | break; |
||
15653 | case 512: |
||
15654 | oappend ("{1to8}"); |
||
15655 | break; |
||
15656 | default: |
||
15657 | abort (); |
||
15658 | } |
||
15659 | } |
||
5221 | serge | 15660 | else |
6324 | serge | 15661 | { |
15662 | switch (vex.length) |
||
15663 | { |
||
15664 | case 128: |
||
15665 | oappend ("{1to4}"); |
||
15666 | break; |
||
15667 | case 256: |
||
15668 | oappend ("{1to8}"); |
||
15669 | break; |
||
15670 | case 512: |
||
15671 | oappend ("{1to16}"); |
||
15672 | break; |
||
15673 | default: |
||
15674 | abort (); |
||
15675 | } |
||
15676 | } |
||
5221 | serge | 15677 | } |
15678 | } |
||
15679 | |||
15680 | static void |
||
15681 | OP_E (int bytemode, int sizeflag) |
||
15682 | { |
||
15683 | /* Skip mod/rm byte. */ |
||
15684 | MODRM_CHECK; |
||
15685 | codep++; |
||
15686 | |||
15687 | if (modrm.mod == 3) |
||
15688 | OP_E_register (bytemode, sizeflag); |
||
15689 | else |
||
15690 | OP_E_memory (bytemode, sizeflag); |
||
15691 | } |
||
15692 | |||
15693 | static void |
||
15694 | OP_G (int bytemode, int sizeflag) |
||
15695 | { |
||
15696 | int add = 0; |
||
15697 | USED_REX (REX_R); |
||
15698 | if (rex & REX_R) |
||
15699 | add += 8; |
||
15700 | switch (bytemode) |
||
15701 | { |
||
15702 | case b_mode: |
||
15703 | USED_REX (0); |
||
15704 | if (rex) |
||
15705 | oappend (names8rex[modrm.reg + add]); |
||
15706 | else |
||
15707 | oappend (names8[modrm.reg + add]); |
||
15708 | break; |
||
15709 | case w_mode: |
||
15710 | oappend (names16[modrm.reg + add]); |
||
15711 | break; |
||
15712 | case d_mode: |
||
6324 | serge | 15713 | case db_mode: |
15714 | case dw_mode: |
||
5221 | serge | 15715 | oappend (names32[modrm.reg + add]); |
15716 | break; |
||
15717 | case q_mode: |
||
15718 | oappend (names64[modrm.reg + add]); |
||
15719 | break; |
||
15720 | case bnd_mode: |
||
15721 | oappend (names_bnd[modrm.reg]); |
||
15722 | break; |
||
15723 | case v_mode: |
||
15724 | case dq_mode: |
||
15725 | case dqb_mode: |
||
15726 | case dqd_mode: |
||
15727 | case dqw_mode: |
||
6324 | serge | 15728 | case dqw_swap_mode: |
5221 | serge | 15729 | USED_REX (REX_W); |
15730 | if (rex & REX_W) |
||
15731 | oappend (names64[modrm.reg + add]); |
||
15732 | else |
||
15733 | { |
||
15734 | if ((sizeflag & DFLAG) || bytemode != v_mode) |
||
15735 | oappend (names32[modrm.reg + add]); |
||
15736 | else |
||
15737 | oappend (names16[modrm.reg + add]); |
||
15738 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
15739 | } |
||
15740 | break; |
||
15741 | case m_mode: |
||
15742 | if (address_mode == mode_64bit) |
||
15743 | oappend (names64[modrm.reg + add]); |
||
15744 | else |
||
15745 | oappend (names32[modrm.reg + add]); |
||
15746 | break; |
||
6324 | serge | 15747 | case mask_bd_mode: |
5221 | serge | 15748 | case mask_mode: |
15749 | oappend (names_mask[modrm.reg + add]); |
||
15750 | break; |
||
15751 | default: |
||
15752 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
15753 | break; |
||
15754 | } |
||
15755 | } |
||
15756 | |||
15757 | static bfd_vma |
||
15758 | get64 (void) |
||
15759 | { |
||
15760 | bfd_vma x; |
||
15761 | #ifdef BFD64 |
||
15762 | unsigned int a; |
||
15763 | unsigned int b; |
||
15764 | |||
15765 | FETCH_DATA (the_info, codep + 8); |
||
15766 | a = *codep++ & 0xff; |
||
15767 | a |= (*codep++ & 0xff) << 8; |
||
15768 | a |= (*codep++ & 0xff) << 16; |
||
6324 | serge | 15769 | a |= (*codep++ & 0xffu) << 24; |
5221 | serge | 15770 | b = *codep++ & 0xff; |
15771 | b |= (*codep++ & 0xff) << 8; |
||
15772 | b |= (*codep++ & 0xff) << 16; |
||
6324 | serge | 15773 | b |= (*codep++ & 0xffu) << 24; |
5221 | serge | 15774 | x = a + ((bfd_vma) b << 32); |
15775 | #else |
||
15776 | abort (); |
||
15777 | x = 0; |
||
15778 | #endif |
||
15779 | return x; |
||
15780 | } |
||
15781 | |||
15782 | static bfd_signed_vma |
||
15783 | get32 (void) |
||
15784 | { |
||
15785 | bfd_signed_vma x = 0; |
||
15786 | |||
15787 | FETCH_DATA (the_info, codep + 4); |
||
15788 | x = *codep++ & (bfd_signed_vma) 0xff; |
||
15789 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
||
15790 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
||
15791 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
||
15792 | return x; |
||
15793 | } |
||
15794 | |||
15795 | static bfd_signed_vma |
||
15796 | get32s (void) |
||
15797 | { |
||
15798 | bfd_signed_vma x = 0; |
||
15799 | |||
15800 | FETCH_DATA (the_info, codep + 4); |
||
15801 | x = *codep++ & (bfd_signed_vma) 0xff; |
||
15802 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
||
15803 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
||
15804 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
||
15805 | |||
15806 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); |
||
15807 | |||
15808 | return x; |
||
15809 | } |
||
15810 | |||
15811 | static int |
||
15812 | get16 (void) |
||
15813 | { |
||
15814 | int x = 0; |
||
15815 | |||
15816 | FETCH_DATA (the_info, codep + 2); |
||
15817 | x = *codep++ & 0xff; |
||
15818 | x |= (*codep++ & 0xff) << 8; |
||
15819 | return x; |
||
15820 | } |
||
15821 | |||
15822 | static void |
||
15823 | set_op (bfd_vma op, int riprel) |
||
15824 | { |
||
15825 | op_index[op_ad] = op_ad; |
||
15826 | if (address_mode == mode_64bit) |
||
15827 | { |
||
15828 | op_address[op_ad] = op; |
||
15829 | op_riprel[op_ad] = riprel; |
||
15830 | } |
||
15831 | else |
||
15832 | { |
||
15833 | /* Mask to get a 32-bit address. */ |
||
15834 | op_address[op_ad] = op & 0xffffffff; |
||
15835 | op_riprel[op_ad] = riprel & 0xffffffff; |
||
15836 | } |
||
15837 | } |
||
15838 | |||
15839 | static void |
||
15840 | OP_REG (int code, int sizeflag) |
||
15841 | { |
||
15842 | const char *s; |
||
15843 | int add; |
||
15844 | |||
15845 | switch (code) |
||
15846 | { |
||
15847 | case es_reg: case ss_reg: case cs_reg: |
||
15848 | case ds_reg: case fs_reg: case gs_reg: |
||
15849 | oappend (names_seg[code - es_reg]); |
||
15850 | return; |
||
15851 | } |
||
15852 | |||
15853 | USED_REX (REX_B); |
||
15854 | if (rex & REX_B) |
||
15855 | add = 8; |
||
15856 | else |
||
15857 | add = 0; |
||
15858 | |||
15859 | switch (code) |
||
15860 | { |
||
15861 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
||
15862 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
||
15863 | s = names16[code - ax_reg + add]; |
||
15864 | break; |
||
15865 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
||
15866 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
||
15867 | USED_REX (0); |
||
15868 | if (rex) |
||
15869 | s = names8rex[code - al_reg + add]; |
||
15870 | else |
||
15871 | s = names8[code - al_reg]; |
||
15872 | break; |
||
15873 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
||
15874 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: |
||
15875 | if (address_mode == mode_64bit |
||
15876 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
||
15877 | { |
||
15878 | s = names64[code - rAX_reg + add]; |
||
15879 | break; |
||
15880 | } |
||
15881 | code += eAX_reg - rAX_reg; |
||
15882 | /* Fall through. */ |
||
15883 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
||
15884 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
||
15885 | USED_REX (REX_W); |
||
15886 | if (rex & REX_W) |
||
15887 | s = names64[code - eAX_reg + add]; |
||
15888 | else |
||
15889 | { |
||
15890 | if (sizeflag & DFLAG) |
||
15891 | s = names32[code - eAX_reg + add]; |
||
15892 | else |
||
15893 | s = names16[code - eAX_reg + add]; |
||
15894 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
15895 | } |
||
15896 | break; |
||
15897 | default: |
||
15898 | s = INTERNAL_DISASSEMBLER_ERROR; |
||
15899 | break; |
||
15900 | } |
||
15901 | oappend (s); |
||
15902 | } |
||
15903 | |||
15904 | static void |
||
15905 | OP_IMREG (int code, int sizeflag) |
||
15906 | { |
||
15907 | const char *s; |
||
15908 | |||
15909 | switch (code) |
||
15910 | { |
||
15911 | case indir_dx_reg: |
||
15912 | if (intel_syntax) |
||
15913 | s = "dx"; |
||
15914 | else |
||
15915 | s = "(%dx)"; |
||
15916 | break; |
||
15917 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
||
15918 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
||
15919 | s = names16[code - ax_reg]; |
||
15920 | break; |
||
15921 | case es_reg: case ss_reg: case cs_reg: |
||
15922 | case ds_reg: case fs_reg: case gs_reg: |
||
15923 | s = names_seg[code - es_reg]; |
||
15924 | break; |
||
15925 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
||
15926 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
||
15927 | USED_REX (0); |
||
15928 | if (rex) |
||
15929 | s = names8rex[code - al_reg]; |
||
15930 | else |
||
15931 | s = names8[code - al_reg]; |
||
15932 | break; |
||
15933 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
||
15934 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
||
15935 | USED_REX (REX_W); |
||
15936 | if (rex & REX_W) |
||
15937 | s = names64[code - eAX_reg]; |
||
15938 | else |
||
15939 | { |
||
15940 | if (sizeflag & DFLAG) |
||
15941 | s = names32[code - eAX_reg]; |
||
15942 | else |
||
15943 | s = names16[code - eAX_reg]; |
||
15944 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
15945 | } |
||
15946 | break; |
||
15947 | case z_mode_ax_reg: |
||
15948 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
||
15949 | s = *names32; |
||
15950 | else |
||
15951 | s = *names16; |
||
15952 | if (!(rex & REX_W)) |
||
15953 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
15954 | break; |
||
15955 | default: |
||
15956 | s = INTERNAL_DISASSEMBLER_ERROR; |
||
15957 | break; |
||
15958 | } |
||
15959 | oappend (s); |
||
15960 | } |
||
15961 | |||
15962 | static void |
||
15963 | OP_I (int bytemode, int sizeflag) |
||
15964 | { |
||
15965 | bfd_signed_vma op; |
||
15966 | bfd_signed_vma mask = -1; |
||
15967 | |||
15968 | switch (bytemode) |
||
15969 | { |
||
15970 | case b_mode: |
||
15971 | FETCH_DATA (the_info, codep + 1); |
||
15972 | op = *codep++; |
||
15973 | mask = 0xff; |
||
15974 | break; |
||
15975 | case q_mode: |
||
15976 | if (address_mode == mode_64bit) |
||
15977 | { |
||
15978 | op = get32s (); |
||
15979 | break; |
||
15980 | } |
||
15981 | /* Fall through. */ |
||
15982 | case v_mode: |
||
15983 | USED_REX (REX_W); |
||
15984 | if (rex & REX_W) |
||
15985 | op = get32s (); |
||
15986 | else |
||
15987 | { |
||
15988 | if (sizeflag & DFLAG) |
||
15989 | { |
||
15990 | op = get32 (); |
||
15991 | mask = 0xffffffff; |
||
15992 | } |
||
15993 | else |
||
15994 | { |
||
15995 | op = get16 (); |
||
15996 | mask = 0xfffff; |
||
15997 | } |
||
15998 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
15999 | } |
||
16000 | break; |
||
16001 | case w_mode: |
||
16002 | mask = 0xfffff; |
||
16003 | op = get16 (); |
||
16004 | break; |
||
16005 | case const_1_mode: |
||
16006 | if (intel_syntax) |
||
16007 | oappend ("1"); |
||
16008 | return; |
||
16009 | default: |
||
16010 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
16011 | return; |
||
16012 | } |
||
16013 | |||
16014 | op &= mask; |
||
16015 | scratchbuf[0] = '$'; |
||
16016 | print_operand_value (scratchbuf + 1, 1, op); |
||
16017 | oappend_maybe_intel (scratchbuf); |
||
16018 | scratchbuf[0] = '\0'; |
||
16019 | } |
||
16020 | |||
16021 | static void |
||
16022 | OP_I64 (int bytemode, int sizeflag) |
||
16023 | { |
||
16024 | bfd_signed_vma op; |
||
16025 | bfd_signed_vma mask = -1; |
||
16026 | |||
16027 | if (address_mode != mode_64bit) |
||
16028 | { |
||
16029 | OP_I (bytemode, sizeflag); |
||
16030 | return; |
||
16031 | } |
||
16032 | |||
16033 | switch (bytemode) |
||
16034 | { |
||
16035 | case b_mode: |
||
16036 | FETCH_DATA (the_info, codep + 1); |
||
16037 | op = *codep++; |
||
16038 | mask = 0xff; |
||
16039 | break; |
||
16040 | case v_mode: |
||
16041 | USED_REX (REX_W); |
||
16042 | if (rex & REX_W) |
||
16043 | op = get64 (); |
||
16044 | else |
||
16045 | { |
||
16046 | if (sizeflag & DFLAG) |
||
16047 | { |
||
16048 | op = get32 (); |
||
16049 | mask = 0xffffffff; |
||
16050 | } |
||
16051 | else |
||
16052 | { |
||
16053 | op = get16 (); |
||
16054 | mask = 0xfffff; |
||
16055 | } |
||
16056 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16057 | } |
||
16058 | break; |
||
16059 | case w_mode: |
||
16060 | mask = 0xfffff; |
||
16061 | op = get16 (); |
||
16062 | break; |
||
16063 | default: |
||
16064 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
16065 | return; |
||
16066 | } |
||
16067 | |||
16068 | op &= mask; |
||
16069 | scratchbuf[0] = '$'; |
||
16070 | print_operand_value (scratchbuf + 1, 1, op); |
||
16071 | oappend_maybe_intel (scratchbuf); |
||
16072 | scratchbuf[0] = '\0'; |
||
16073 | } |
||
16074 | |||
16075 | static void |
||
16076 | OP_sI (int bytemode, int sizeflag) |
||
16077 | { |
||
16078 | bfd_signed_vma op; |
||
16079 | |||
16080 | switch (bytemode) |
||
16081 | { |
||
16082 | case b_mode: |
||
16083 | case b_T_mode: |
||
16084 | FETCH_DATA (the_info, codep + 1); |
||
16085 | op = *codep++; |
||
16086 | if ((op & 0x80) != 0) |
||
16087 | op -= 0x100; |
||
16088 | if (bytemode == b_T_mode) |
||
16089 | { |
||
16090 | if (address_mode != mode_64bit |
||
16091 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
||
16092 | { |
||
16093 | /* The operand-size prefix is overridden by a REX prefix. */ |
||
16094 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
||
16095 | op &= 0xffffffff; |
||
16096 | else |
||
16097 | op &= 0xffff; |
||
16098 | } |
||
16099 | } |
||
16100 | else |
||
16101 | { |
||
16102 | if (!(rex & REX_W)) |
||
16103 | { |
||
16104 | if (sizeflag & DFLAG) |
||
16105 | op &= 0xffffffff; |
||
16106 | else |
||
16107 | op &= 0xffff; |
||
16108 | } |
||
16109 | } |
||
16110 | break; |
||
16111 | case v_mode: |
||
16112 | /* The operand-size prefix is overridden by a REX prefix. */ |
||
16113 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
||
16114 | op = get32s (); |
||
16115 | else |
||
16116 | op = get16 (); |
||
16117 | break; |
||
16118 | default: |
||
16119 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
16120 | return; |
||
16121 | } |
||
16122 | |||
16123 | scratchbuf[0] = '$'; |
||
16124 | print_operand_value (scratchbuf + 1, 1, op); |
||
16125 | oappend_maybe_intel (scratchbuf); |
||
16126 | } |
||
16127 | |||
16128 | static void |
||
16129 | OP_J (int bytemode, int sizeflag) |
||
16130 | { |
||
16131 | bfd_vma disp; |
||
16132 | bfd_vma mask = -1; |
||
16133 | bfd_vma segment = 0; |
||
16134 | |||
16135 | switch (bytemode) |
||
16136 | { |
||
16137 | case b_mode: |
||
16138 | FETCH_DATA (the_info, codep + 1); |
||
16139 | disp = *codep++; |
||
16140 | if ((disp & 0x80) != 0) |
||
16141 | disp -= 0x100; |
||
16142 | break; |
||
16143 | case v_mode: |
||
6324 | serge | 16144 | if (isa64 == amd64) |
16145 | USED_REX (REX_W); |
||
16146 | if ((sizeflag & DFLAG) |
||
16147 | || (address_mode == mode_64bit |
||
16148 | && (isa64 != amd64 || (rex & REX_W)))) |
||
5221 | serge | 16149 | disp = get32s (); |
16150 | else |
||
16151 | { |
||
16152 | disp = get16 (); |
||
16153 | if ((disp & 0x8000) != 0) |
||
16154 | disp -= 0x10000; |
||
16155 | /* In 16bit mode, address is wrapped around at 64k within |
||
16156 | the same segment. Otherwise, a data16 prefix on a jump |
||
16157 | instruction means that the pc is masked to 16 bits after |
||
16158 | the displacement is added! */ |
||
16159 | mask = 0xffff; |
||
16160 | if ((prefixes & PREFIX_DATA) == 0) |
||
16161 | segment = ((start_pc + codep - start_codep) |
||
16162 | & ~((bfd_vma) 0xffff)); |
||
16163 | } |
||
6324 | serge | 16164 | if (address_mode != mode_64bit |
16165 | || (isa64 == amd64 && !(rex & REX_W))) |
||
5221 | serge | 16166 | used_prefixes |= (prefixes & PREFIX_DATA); |
16167 | break; |
||
16168 | default: |
||
16169 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
16170 | return; |
||
16171 | } |
||
16172 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
||
16173 | set_op (disp, 0); |
||
16174 | print_operand_value (scratchbuf, 1, disp); |
||
16175 | oappend (scratchbuf); |
||
16176 | } |
||
16177 | |||
16178 | static void |
||
16179 | OP_SEG (int bytemode, int sizeflag) |
||
16180 | { |
||
16181 | if (bytemode == w_mode) |
||
16182 | oappend (names_seg[modrm.reg]); |
||
16183 | else |
||
16184 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
||
16185 | } |
||
16186 | |||
16187 | static void |
||
16188 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
||
16189 | { |
||
16190 | int seg, offset; |
||
16191 | |||
16192 | if (sizeflag & DFLAG) |
||
16193 | { |
||
16194 | offset = get32 (); |
||
16195 | seg = get16 (); |
||
16196 | } |
||
16197 | else |
||
16198 | { |
||
16199 | offset = get16 (); |
||
16200 | seg = get16 (); |
||
16201 | } |
||
16202 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16203 | if (intel_syntax) |
||
16204 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
||
16205 | else |
||
16206 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); |
||
16207 | oappend (scratchbuf); |
||
16208 | } |
||
16209 | |||
16210 | static void |
||
16211 | OP_OFF (int bytemode, int sizeflag) |
||
16212 | { |
||
16213 | bfd_vma off; |
||
16214 | |||
16215 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
||
16216 | intel_operand_size (bytemode, sizeflag); |
||
16217 | append_seg (); |
||
16218 | |||
16219 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
||
16220 | off = get32 (); |
||
16221 | else |
||
16222 | off = get16 (); |
||
16223 | |||
16224 | if (intel_syntax) |
||
16225 | { |
||
6324 | serge | 16226 | if (!active_seg_prefix) |
5221 | serge | 16227 | { |
16228 | oappend (names_seg[ds_reg - es_reg]); |
||
16229 | oappend (":"); |
||
16230 | } |
||
16231 | } |
||
16232 | print_operand_value (scratchbuf, 1, off); |
||
16233 | oappend (scratchbuf); |
||
16234 | } |
||
16235 | |||
16236 | static void |
||
16237 | OP_OFF64 (int bytemode, int sizeflag) |
||
16238 | { |
||
16239 | bfd_vma off; |
||
16240 | |||
16241 | if (address_mode != mode_64bit |
||
16242 | || (prefixes & PREFIX_ADDR)) |
||
16243 | { |
||
16244 | OP_OFF (bytemode, sizeflag); |
||
16245 | return; |
||
16246 | } |
||
16247 | |||
16248 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
||
16249 | intel_operand_size (bytemode, sizeflag); |
||
16250 | append_seg (); |
||
16251 | |||
16252 | off = get64 (); |
||
16253 | |||
16254 | if (intel_syntax) |
||
16255 | { |
||
6324 | serge | 16256 | if (!active_seg_prefix) |
5221 | serge | 16257 | { |
16258 | oappend (names_seg[ds_reg - es_reg]); |
||
16259 | oappend (":"); |
||
16260 | } |
||
16261 | } |
||
16262 | print_operand_value (scratchbuf, 1, off); |
||
16263 | oappend (scratchbuf); |
||
16264 | } |
||
16265 | |||
16266 | static void |
||
16267 | ptr_reg (int code, int sizeflag) |
||
16268 | { |
||
16269 | const char *s; |
||
16270 | |||
16271 | *obufp++ = open_char; |
||
16272 | used_prefixes |= (prefixes & PREFIX_ADDR); |
||
16273 | if (address_mode == mode_64bit) |
||
16274 | { |
||
16275 | if (!(sizeflag & AFLAG)) |
||
16276 | s = names32[code - eAX_reg]; |
||
16277 | else |
||
16278 | s = names64[code - eAX_reg]; |
||
16279 | } |
||
16280 | else if (sizeflag & AFLAG) |
||
16281 | s = names32[code - eAX_reg]; |
||
16282 | else |
||
16283 | s = names16[code - eAX_reg]; |
||
16284 | oappend (s); |
||
16285 | *obufp++ = close_char; |
||
16286 | *obufp = 0; |
||
16287 | } |
||
16288 | |||
16289 | static void |
||
16290 | OP_ESreg (int code, int sizeflag) |
||
16291 | { |
||
16292 | if (intel_syntax) |
||
16293 | { |
||
16294 | switch (codep[-1]) |
||
16295 | { |
||
16296 | case 0x6d: /* insw/insl */ |
||
16297 | intel_operand_size (z_mode, sizeflag); |
||
16298 | break; |
||
16299 | case 0xa5: /* movsw/movsl/movsq */ |
||
16300 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
||
16301 | case 0xab: /* stosw/stosl */ |
||
16302 | case 0xaf: /* scasw/scasl */ |
||
16303 | intel_operand_size (v_mode, sizeflag); |
||
16304 | break; |
||
16305 | default: |
||
16306 | intel_operand_size (b_mode, sizeflag); |
||
16307 | } |
||
16308 | } |
||
16309 | oappend_maybe_intel ("%es:"); |
||
16310 | ptr_reg (code, sizeflag); |
||
16311 | } |
||
16312 | |||
16313 | static void |
||
16314 | OP_DSreg (int code, int sizeflag) |
||
16315 | { |
||
16316 | if (intel_syntax) |
||
16317 | { |
||
16318 | switch (codep[-1]) |
||
16319 | { |
||
16320 | case 0x6f: /* outsw/outsl */ |
||
16321 | intel_operand_size (z_mode, sizeflag); |
||
16322 | break; |
||
16323 | case 0xa5: /* movsw/movsl/movsq */ |
||
16324 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
||
16325 | case 0xad: /* lodsw/lodsl/lodsq */ |
||
16326 | intel_operand_size (v_mode, sizeflag); |
||
16327 | break; |
||
16328 | default: |
||
16329 | intel_operand_size (b_mode, sizeflag); |
||
16330 | } |
||
16331 | } |
||
6324 | serge | 16332 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16333 | default segment register DS is printed. */ |
||
16334 | if (!active_seg_prefix) |
||
16335 | active_seg_prefix = PREFIX_DS; |
||
5221 | serge | 16336 | append_seg (); |
16337 | ptr_reg (code, sizeflag); |
||
16338 | } |
||
16339 | |||
16340 | static void |
||
16341 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16342 | { |
||
16343 | int add; |
||
16344 | if (rex & REX_R) |
||
16345 | { |
||
16346 | USED_REX (REX_R); |
||
16347 | add = 8; |
||
16348 | } |
||
16349 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
||
16350 | { |
||
16351 | all_prefixes[last_lock_prefix] = 0; |
||
16352 | used_prefixes |= PREFIX_LOCK; |
||
16353 | add = 8; |
||
16354 | } |
||
16355 | else |
||
16356 | add = 0; |
||
16357 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
||
16358 | oappend_maybe_intel (scratchbuf); |
||
16359 | } |
||
16360 | |||
16361 | static void |
||
16362 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16363 | { |
||
16364 | int add; |
||
16365 | USED_REX (REX_R); |
||
16366 | if (rex & REX_R) |
||
16367 | add = 8; |
||
16368 | else |
||
16369 | add = 0; |
||
16370 | if (intel_syntax) |
||
16371 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
||
16372 | else |
||
16373 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
||
16374 | oappend (scratchbuf); |
||
16375 | } |
||
16376 | |||
16377 | static void |
||
16378 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16379 | { |
||
16380 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
||
16381 | oappend_maybe_intel (scratchbuf); |
||
16382 | } |
||
16383 | |||
16384 | static void |
||
16385 | OP_R (int bytemode, int sizeflag) |
||
16386 | { |
||
6324 | serge | 16387 | /* Skip mod/rm byte. */ |
16388 | MODRM_CHECK; |
||
16389 | codep++; |
||
16390 | OP_E_register (bytemode, sizeflag); |
||
5221 | serge | 16391 | } |
16392 | |||
16393 | static void |
||
16394 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16395 | { |
||
16396 | int reg = modrm.reg; |
||
16397 | const char **names; |
||
16398 | |||
16399 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16400 | if (prefixes & PREFIX_DATA) |
||
16401 | { |
||
16402 | names = names_xmm; |
||
16403 | USED_REX (REX_R); |
||
16404 | if (rex & REX_R) |
||
16405 | reg += 8; |
||
16406 | } |
||
16407 | else |
||
16408 | names = names_mm; |
||
16409 | oappend (names[reg]); |
||
16410 | } |
||
16411 | |||
16412 | static void |
||
16413 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
||
16414 | { |
||
16415 | int reg = modrm.reg; |
||
16416 | const char **names; |
||
16417 | |||
16418 | USED_REX (REX_R); |
||
16419 | if (rex & REX_R) |
||
16420 | reg += 8; |
||
16421 | if (vex.evex) |
||
16422 | { |
||
16423 | if (!vex.r) |
||
16424 | reg += 16; |
||
16425 | } |
||
16426 | |||
16427 | if (need_vex |
||
16428 | && bytemode != xmm_mode |
||
16429 | && bytemode != xmmq_mode |
||
16430 | && bytemode != evex_half_bcst_xmmq_mode |
||
16431 | && bytemode != ymm_mode |
||
16432 | && bytemode != scalar_mode) |
||
16433 | { |
||
16434 | switch (vex.length) |
||
16435 | { |
||
16436 | case 128: |
||
16437 | names = names_xmm; |
||
16438 | break; |
||
16439 | case 256: |
||
6324 | serge | 16440 | if (vex.w |
16441 | || (bytemode != vex_vsib_q_w_dq_mode |
||
16442 | && bytemode != vex_vsib_q_w_d_mode)) |
||
5221 | serge | 16443 | names = names_ymm; |
16444 | else |
||
16445 | names = names_xmm; |
||
16446 | break; |
||
16447 | case 512: |
||
16448 | names = names_zmm; |
||
16449 | break; |
||
16450 | default: |
||
16451 | abort (); |
||
16452 | } |
||
16453 | } |
||
16454 | else if (bytemode == xmmq_mode |
||
16455 | || bytemode == evex_half_bcst_xmmq_mode) |
||
16456 | { |
||
16457 | switch (vex.length) |
||
16458 | { |
||
16459 | case 128: |
||
16460 | case 256: |
||
16461 | names = names_xmm; |
||
16462 | break; |
||
16463 | case 512: |
||
16464 | names = names_ymm; |
||
16465 | break; |
||
16466 | default: |
||
16467 | abort (); |
||
16468 | } |
||
16469 | } |
||
16470 | else if (bytemode == ymm_mode) |
||
16471 | names = names_ymm; |
||
16472 | else |
||
16473 | names = names_xmm; |
||
16474 | oappend (names[reg]); |
||
16475 | } |
||
16476 | |||
16477 | static void |
||
16478 | OP_EM (int bytemode, int sizeflag) |
||
16479 | { |
||
16480 | int reg; |
||
16481 | const char **names; |
||
16482 | |||
16483 | if (modrm.mod != 3) |
||
16484 | { |
||
16485 | if (intel_syntax |
||
16486 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
||
16487 | { |
||
16488 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
||
16489 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16490 | } |
||
16491 | OP_E (bytemode, sizeflag); |
||
16492 | return; |
||
16493 | } |
||
16494 | |||
16495 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
||
16496 | swap_operand (); |
||
16497 | |||
16498 | /* Skip mod/rm byte. */ |
||
16499 | MODRM_CHECK; |
||
16500 | codep++; |
||
16501 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16502 | reg = modrm.rm; |
||
16503 | if (prefixes & PREFIX_DATA) |
||
16504 | { |
||
16505 | names = names_xmm; |
||
16506 | USED_REX (REX_B); |
||
16507 | if (rex & REX_B) |
||
16508 | reg += 8; |
||
16509 | } |
||
16510 | else |
||
16511 | names = names_mm; |
||
16512 | oappend (names[reg]); |
||
16513 | } |
||
16514 | |||
16515 | /* cvt* are the only instructions in sse2 which have |
||
16516 | both SSE and MMX operands and also have 0x66 prefix |
||
16517 | in their opcode. 0x66 was originally used to differentiate |
||
16518 | between SSE and MMX instruction(operands). So we have to handle the |
||
16519 | cvt* separately using OP_EMC and OP_MXC */ |
||
16520 | static void |
||
16521 | OP_EMC (int bytemode, int sizeflag) |
||
16522 | { |
||
16523 | if (modrm.mod != 3) |
||
16524 | { |
||
16525 | if (intel_syntax && bytemode == v_mode) |
||
16526 | { |
||
16527 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
||
16528 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16529 | } |
||
16530 | OP_E (bytemode, sizeflag); |
||
16531 | return; |
||
16532 | } |
||
16533 | |||
16534 | /* Skip mod/rm byte. */ |
||
16535 | MODRM_CHECK; |
||
16536 | codep++; |
||
16537 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16538 | oappend (names_mm[modrm.rm]); |
||
16539 | } |
||
16540 | |||
16541 | static void |
||
16542 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16543 | { |
||
16544 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
16545 | oappend (names_mm[modrm.reg]); |
||
16546 | } |
||
16547 | |||
16548 | static void |
||
16549 | OP_EX (int bytemode, int sizeflag) |
||
16550 | { |
||
16551 | int reg; |
||
16552 | const char **names; |
||
16553 | |||
16554 | /* Skip mod/rm byte. */ |
||
16555 | MODRM_CHECK; |
||
16556 | codep++; |
||
16557 | |||
16558 | if (modrm.mod != 3) |
||
16559 | { |
||
16560 | OP_E_memory (bytemode, sizeflag); |
||
16561 | return; |
||
16562 | } |
||
16563 | |||
16564 | reg = modrm.rm; |
||
16565 | USED_REX (REX_B); |
||
16566 | if (rex & REX_B) |
||
16567 | reg += 8; |
||
16568 | if (vex.evex) |
||
16569 | { |
||
16570 | USED_REX (REX_X); |
||
16571 | if ((rex & REX_X)) |
||
16572 | reg += 16; |
||
16573 | } |
||
16574 | |||
16575 | if ((sizeflag & SUFFIX_ALWAYS) |
||
16576 | && (bytemode == x_swap_mode |
||
16577 | || bytemode == d_swap_mode |
||
6324 | serge | 16578 | || bytemode == dqw_swap_mode |
5221 | serge | 16579 | || bytemode == d_scalar_swap_mode |
16580 | || bytemode == q_swap_mode |
||
16581 | || bytemode == q_scalar_swap_mode)) |
||
16582 | swap_operand (); |
||
16583 | |||
16584 | if (need_vex |
||
16585 | && bytemode != xmm_mode |
||
16586 | && bytemode != xmmdw_mode |
||
16587 | && bytemode != xmmqd_mode |
||
16588 | && bytemode != xmm_mb_mode |
||
16589 | && bytemode != xmm_mw_mode |
||
16590 | && bytemode != xmm_md_mode |
||
16591 | && bytemode != xmm_mq_mode |
||
16592 | && bytemode != xmm_mdq_mode |
||
16593 | && bytemode != xmmq_mode |
||
16594 | && bytemode != evex_half_bcst_xmmq_mode |
||
16595 | && bytemode != ymm_mode |
||
16596 | && bytemode != d_scalar_mode |
||
16597 | && bytemode != d_scalar_swap_mode |
||
16598 | && bytemode != q_scalar_mode |
||
16599 | && bytemode != q_scalar_swap_mode |
||
16600 | && bytemode != vex_scalar_w_dq_mode) |
||
16601 | { |
||
16602 | switch (vex.length) |
||
16603 | { |
||
16604 | case 128: |
||
16605 | names = names_xmm; |
||
16606 | break; |
||
16607 | case 256: |
||
16608 | names = names_ymm; |
||
16609 | break; |
||
16610 | case 512: |
||
16611 | names = names_zmm; |
||
16612 | break; |
||
16613 | default: |
||
16614 | abort (); |
||
16615 | } |
||
16616 | } |
||
16617 | else if (bytemode == xmmq_mode |
||
16618 | || bytemode == evex_half_bcst_xmmq_mode) |
||
16619 | { |
||
16620 | switch (vex.length) |
||
16621 | { |
||
16622 | case 128: |
||
16623 | case 256: |
||
16624 | names = names_xmm; |
||
16625 | break; |
||
16626 | case 512: |
||
16627 | names = names_ymm; |
||
16628 | break; |
||
16629 | default: |
||
16630 | abort (); |
||
16631 | } |
||
16632 | } |
||
16633 | else if (bytemode == ymm_mode) |
||
16634 | names = names_ymm; |
||
16635 | else |
||
16636 | names = names_xmm; |
||
16637 | oappend (names[reg]); |
||
16638 | } |
||
16639 | |||
16640 | static void |
||
16641 | OP_MS (int bytemode, int sizeflag) |
||
16642 | { |
||
16643 | if (modrm.mod == 3) |
||
16644 | OP_EM (bytemode, sizeflag); |
||
16645 | else |
||
16646 | BadOp (); |
||
16647 | } |
||
16648 | |||
16649 | static void |
||
16650 | OP_XS (int bytemode, int sizeflag) |
||
16651 | { |
||
16652 | if (modrm.mod == 3) |
||
16653 | OP_EX (bytemode, sizeflag); |
||
16654 | else |
||
16655 | BadOp (); |
||
16656 | } |
||
16657 | |||
16658 | static void |
||
16659 | OP_M (int bytemode, int sizeflag) |
||
16660 | { |
||
16661 | if (modrm.mod == 3) |
||
16662 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
||
16663 | BadOp (); |
||
16664 | else |
||
16665 | OP_E (bytemode, sizeflag); |
||
16666 | } |
||
16667 | |||
16668 | static void |
||
16669 | OP_0f07 (int bytemode, int sizeflag) |
||
16670 | { |
||
16671 | if (modrm.mod != 3 || modrm.rm != 0) |
||
16672 | BadOp (); |
||
16673 | else |
||
16674 | OP_E (bytemode, sizeflag); |
||
16675 | } |
||
16676 | |||
16677 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
||
16678 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
||
16679 | |||
16680 | static void |
||
16681 | NOP_Fixup1 (int bytemode, int sizeflag) |
||
16682 | { |
||
16683 | if ((prefixes & PREFIX_DATA) != 0 |
||
16684 | || (rex != 0 |
||
16685 | && rex != 0x48 |
||
16686 | && address_mode == mode_64bit)) |
||
16687 | OP_REG (bytemode, sizeflag); |
||
16688 | else |
||
16689 | strcpy (obuf, "nop"); |
||
16690 | } |
||
16691 | |||
16692 | static void |
||
16693 | NOP_Fixup2 (int bytemode, int sizeflag) |
||
16694 | { |
||
16695 | if ((prefixes & PREFIX_DATA) != 0 |
||
16696 | || (rex != 0 |
||
16697 | && rex != 0x48 |
||
16698 | && address_mode == mode_64bit)) |
||
16699 | OP_IMREG (bytemode, sizeflag); |
||
16700 | } |
||
16701 | |||
16702 | static const char *const Suffix3DNow[] = { |
||
16703 | /* 00 */ NULL, NULL, NULL, NULL, |
||
16704 | /* 04 */ NULL, NULL, NULL, NULL, |
||
16705 | /* 08 */ NULL, NULL, NULL, NULL, |
||
16706 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
||
16707 | /* 10 */ NULL, NULL, NULL, NULL, |
||
16708 | /* 14 */ NULL, NULL, NULL, NULL, |
||
16709 | /* 18 */ NULL, NULL, NULL, NULL, |
||
16710 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
||
16711 | /* 20 */ NULL, NULL, NULL, NULL, |
||
16712 | /* 24 */ NULL, NULL, NULL, NULL, |
||
16713 | /* 28 */ NULL, NULL, NULL, NULL, |
||
16714 | /* 2C */ NULL, NULL, NULL, NULL, |
||
16715 | /* 30 */ NULL, NULL, NULL, NULL, |
||
16716 | /* 34 */ NULL, NULL, NULL, NULL, |
||
16717 | /* 38 */ NULL, NULL, NULL, NULL, |
||
16718 | /* 3C */ NULL, NULL, NULL, NULL, |
||
16719 | /* 40 */ NULL, NULL, NULL, NULL, |
||
16720 | /* 44 */ NULL, NULL, NULL, NULL, |
||
16721 | /* 48 */ NULL, NULL, NULL, NULL, |
||
16722 | /* 4C */ NULL, NULL, NULL, NULL, |
||
16723 | /* 50 */ NULL, NULL, NULL, NULL, |
||
16724 | /* 54 */ NULL, NULL, NULL, NULL, |
||
16725 | /* 58 */ NULL, NULL, NULL, NULL, |
||
16726 | /* 5C */ NULL, NULL, NULL, NULL, |
||
16727 | /* 60 */ NULL, NULL, NULL, NULL, |
||
16728 | /* 64 */ NULL, NULL, NULL, NULL, |
||
16729 | /* 68 */ NULL, NULL, NULL, NULL, |
||
16730 | /* 6C */ NULL, NULL, NULL, NULL, |
||
16731 | /* 70 */ NULL, NULL, NULL, NULL, |
||
16732 | /* 74 */ NULL, NULL, NULL, NULL, |
||
16733 | /* 78 */ NULL, NULL, NULL, NULL, |
||
16734 | /* 7C */ NULL, NULL, NULL, NULL, |
||
16735 | /* 80 */ NULL, NULL, NULL, NULL, |
||
16736 | /* 84 */ NULL, NULL, NULL, NULL, |
||
16737 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
||
16738 | /* 8C */ NULL, NULL, "pfpnacc", NULL, |
||
16739 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
||
16740 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", |
||
16741 | /* 98 */ NULL, NULL, "pfsub", NULL, |
||
16742 | /* 9C */ NULL, NULL, "pfadd", NULL, |
||
16743 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, |
||
16744 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", |
||
16745 | /* A8 */ NULL, NULL, "pfsubr", NULL, |
||
16746 | /* AC */ NULL, NULL, "pfacc", NULL, |
||
16747 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, |
||
16748 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
||
16749 | /* B8 */ NULL, NULL, NULL, "pswapd", |
||
16750 | /* BC */ NULL, NULL, NULL, "pavgusb", |
||
16751 | /* C0 */ NULL, NULL, NULL, NULL, |
||
16752 | /* C4 */ NULL, NULL, NULL, NULL, |
||
16753 | /* C8 */ NULL, NULL, NULL, NULL, |
||
16754 | /* CC */ NULL, NULL, NULL, NULL, |
||
16755 | /* D0 */ NULL, NULL, NULL, NULL, |
||
16756 | /* D4 */ NULL, NULL, NULL, NULL, |
||
16757 | /* D8 */ NULL, NULL, NULL, NULL, |
||
16758 | /* DC */ NULL, NULL, NULL, NULL, |
||
16759 | /* E0 */ NULL, NULL, NULL, NULL, |
||
16760 | /* E4 */ NULL, NULL, NULL, NULL, |
||
16761 | /* E8 */ NULL, NULL, NULL, NULL, |
||
16762 | /* EC */ NULL, NULL, NULL, NULL, |
||
16763 | /* F0 */ NULL, NULL, NULL, NULL, |
||
16764 | /* F4 */ NULL, NULL, NULL, NULL, |
||
16765 | /* F8 */ NULL, NULL, NULL, NULL, |
||
16766 | /* FC */ NULL, NULL, NULL, NULL, |
||
16767 | }; |
||
16768 | |||
16769 | static void |
||
16770 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16771 | { |
||
16772 | const char *mnemonic; |
||
16773 | |||
16774 | FETCH_DATA (the_info, codep + 1); |
||
16775 | /* AMD 3DNow! instructions are specified by an opcode suffix in the |
||
16776 | place where an 8-bit immediate would normally go. ie. the last |
||
16777 | byte of the instruction. */ |
||
16778 | obufp = mnemonicendp; |
||
16779 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
||
16780 | if (mnemonic) |
||
16781 | oappend (mnemonic); |
||
16782 | else |
||
16783 | { |
||
16784 | /* Since a variable sized modrm/sib chunk is between the start |
||
16785 | of the opcode (0x0f0f) and the opcode suffix, we need to do |
||
16786 | all the modrm processing first, and don't know until now that |
||
16787 | we have a bad opcode. This necessitates some cleaning up. */ |
||
16788 | op_out[0][0] = '\0'; |
||
16789 | op_out[1][0] = '\0'; |
||
16790 | BadOp (); |
||
16791 | } |
||
16792 | mnemonicendp = obufp; |
||
16793 | } |
||
16794 | |||
16795 | static struct op simd_cmp_op[] = |
||
16796 | { |
||
16797 | { STRING_COMMA_LEN ("eq") }, |
||
16798 | { STRING_COMMA_LEN ("lt") }, |
||
16799 | { STRING_COMMA_LEN ("le") }, |
||
16800 | { STRING_COMMA_LEN ("unord") }, |
||
16801 | { STRING_COMMA_LEN ("neq") }, |
||
16802 | { STRING_COMMA_LEN ("nlt") }, |
||
16803 | { STRING_COMMA_LEN ("nle") }, |
||
16804 | { STRING_COMMA_LEN ("ord") } |
||
16805 | }; |
||
16806 | |||
16807 | static void |
||
16808 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16809 | { |
||
16810 | unsigned int cmp_type; |
||
16811 | |||
16812 | FETCH_DATA (the_info, codep + 1); |
||
16813 | cmp_type = *codep++ & 0xff; |
||
16814 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
||
16815 | { |
||
16816 | char suffix [3]; |
||
16817 | char *p = mnemonicendp - 2; |
||
16818 | suffix[0] = p[0]; |
||
16819 | suffix[1] = p[1]; |
||
16820 | suffix[2] = '\0'; |
||
16821 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
||
16822 | mnemonicendp += simd_cmp_op[cmp_type].len; |
||
16823 | } |
||
16824 | else |
||
16825 | { |
||
16826 | /* We have a reserved extension byte. Output it directly. */ |
||
16827 | scratchbuf[0] = '$'; |
||
16828 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
||
16829 | oappend_maybe_intel (scratchbuf); |
||
16830 | scratchbuf[0] = '\0'; |
||
16831 | } |
||
16832 | } |
||
16833 | |||
16834 | static void |
||
6324 | serge | 16835 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, |
16836 | int sizeflag ATTRIBUTE_UNUSED) |
||
16837 | { |
||
16838 | /* mwaitx %eax,%ecx,%ebx */ |
||
16839 | if (!intel_syntax) |
||
16840 | { |
||
16841 | const char **names = (address_mode == mode_64bit |
||
16842 | ? names64 : names32); |
||
16843 | strcpy (op_out[0], names[0]); |
||
16844 | strcpy (op_out[1], names[1]); |
||
16845 | strcpy (op_out[2], names[3]); |
||
16846 | two_source_ops = 1; |
||
16847 | } |
||
16848 | /* Skip mod/rm byte. */ |
||
16849 | MODRM_CHECK; |
||
16850 | codep++; |
||
16851 | } |
||
16852 | |||
16853 | static void |
||
5221 | serge | 16854 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16855 | int sizeflag ATTRIBUTE_UNUSED) |
||
16856 | { |
||
16857 | /* mwait %eax,%ecx */ |
||
16858 | if (!intel_syntax) |
||
16859 | { |
||
16860 | const char **names = (address_mode == mode_64bit |
||
16861 | ? names64 : names32); |
||
16862 | strcpy (op_out[0], names[0]); |
||
16863 | strcpy (op_out[1], names[1]); |
||
16864 | two_source_ops = 1; |
||
16865 | } |
||
16866 | /* Skip mod/rm byte. */ |
||
16867 | MODRM_CHECK; |
||
16868 | codep++; |
||
16869 | } |
||
16870 | |||
16871 | static void |
||
16872 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, |
||
16873 | int sizeflag ATTRIBUTE_UNUSED) |
||
16874 | { |
||
16875 | /* monitor %eax,%ecx,%edx" */ |
||
16876 | if (!intel_syntax) |
||
16877 | { |
||
16878 | const char **op1_names; |
||
16879 | const char **names = (address_mode == mode_64bit |
||
16880 | ? names64 : names32); |
||
16881 | |||
16882 | if (!(prefixes & PREFIX_ADDR)) |
||
16883 | op1_names = (address_mode == mode_16bit |
||
16884 | ? names16 : names); |
||
16885 | else |
||
16886 | { |
||
16887 | /* Remove "addr16/addr32". */ |
||
16888 | all_prefixes[last_addr_prefix] = 0; |
||
16889 | op1_names = (address_mode != mode_32bit |
||
16890 | ? names32 : names16); |
||
16891 | used_prefixes |= PREFIX_ADDR; |
||
16892 | } |
||
16893 | strcpy (op_out[0], op1_names[0]); |
||
16894 | strcpy (op_out[1], names[1]); |
||
16895 | strcpy (op_out[2], names[2]); |
||
16896 | two_source_ops = 1; |
||
16897 | } |
||
16898 | /* Skip mod/rm byte. */ |
||
16899 | MODRM_CHECK; |
||
16900 | codep++; |
||
16901 | } |
||
16902 | |||
16903 | static void |
||
16904 | BadOp (void) |
||
16905 | { |
||
16906 | /* Throw away prefixes and 1st. opcode byte. */ |
||
16907 | codep = insn_codep + 1; |
||
16908 | oappend ("(bad)"); |
||
16909 | } |
||
16910 | |||
16911 | static void |
||
16912 | REP_Fixup (int bytemode, int sizeflag) |
||
16913 | { |
||
16914 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, |
||
16915 | lods and stos. */ |
||
16916 | if (prefixes & PREFIX_REPZ) |
||
16917 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
||
16918 | |||
16919 | switch (bytemode) |
||
16920 | { |
||
16921 | case al_reg: |
||
16922 | case eAX_reg: |
||
16923 | case indir_dx_reg: |
||
16924 | OP_IMREG (bytemode, sizeflag); |
||
16925 | break; |
||
16926 | case eDI_reg: |
||
16927 | OP_ESreg (bytemode, sizeflag); |
||
16928 | break; |
||
16929 | case eSI_reg: |
||
16930 | OP_DSreg (bytemode, sizeflag); |
||
16931 | break; |
||
16932 | default: |
||
16933 | abort (); |
||
16934 | break; |
||
16935 | } |
||
16936 | } |
||
16937 | |||
16938 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
||
16939 | "bnd". */ |
||
16940 | |||
16941 | static void |
||
16942 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
16943 | { |
||
16944 | if (prefixes & PREFIX_REPNZ) |
||
16945 | all_prefixes[last_repnz_prefix] = BND_PREFIX; |
||
16946 | } |
||
16947 | |||
16948 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
||
16949 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. |
||
16950 | */ |
||
16951 | |||
16952 | static void |
||
16953 | HLE_Fixup1 (int bytemode, int sizeflag) |
||
16954 | { |
||
16955 | if (modrm.mod != 3 |
||
16956 | && (prefixes & PREFIX_LOCK) != 0) |
||
16957 | { |
||
16958 | if (prefixes & PREFIX_REPZ) |
||
16959 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
||
16960 | if (prefixes & PREFIX_REPNZ) |
||
16961 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
||
16962 | } |
||
16963 | |||
16964 | OP_E (bytemode, sizeflag); |
||
16965 | } |
||
16966 | |||
16967 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
||
16968 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. |
||
16969 | */ |
||
16970 | |||
16971 | static void |
||
16972 | HLE_Fixup2 (int bytemode, int sizeflag) |
||
16973 | { |
||
16974 | if (modrm.mod != 3) |
||
16975 | { |
||
16976 | if (prefixes & PREFIX_REPZ) |
||
16977 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
||
16978 | if (prefixes & PREFIX_REPNZ) |
||
16979 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
||
16980 | } |
||
16981 | |||
16982 | OP_E (bytemode, sizeflag); |
||
16983 | } |
||
16984 | |||
16985 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as |
||
16986 | "xrelease" for memory operand. No check for LOCK prefix. */ |
||
16987 | |||
16988 | static void |
||
16989 | HLE_Fixup3 (int bytemode, int sizeflag) |
||
16990 | { |
||
16991 | if (modrm.mod != 3 |
||
16992 | && last_repz_prefix > last_repnz_prefix |
||
16993 | && (prefixes & PREFIX_REPZ) != 0) |
||
16994 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
||
16995 | |||
16996 | OP_E (bytemode, sizeflag); |
||
16997 | } |
||
16998 | |||
16999 | static void |
||
17000 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) |
||
17001 | { |
||
17002 | USED_REX (REX_W); |
||
17003 | if (rex & REX_W) |
||
17004 | { |
||
17005 | /* Change cmpxchg8b to cmpxchg16b. */ |
||
17006 | char *p = mnemonicendp - 2; |
||
17007 | mnemonicendp = stpcpy (p, "16b"); |
||
17008 | bytemode = o_mode; |
||
17009 | } |
||
17010 | else if ((prefixes & PREFIX_LOCK) != 0) |
||
17011 | { |
||
17012 | if (prefixes & PREFIX_REPZ) |
||
17013 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
||
17014 | if (prefixes & PREFIX_REPNZ) |
||
17015 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
||
17016 | } |
||
17017 | |||
17018 | OP_M (bytemode, sizeflag); |
||
17019 | } |
||
17020 | |||
17021 | static void |
||
17022 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) |
||
17023 | { |
||
17024 | const char **names; |
||
17025 | |||
17026 | if (need_vex) |
||
17027 | { |
||
17028 | switch (vex.length) |
||
17029 | { |
||
17030 | case 128: |
||
17031 | names = names_xmm; |
||
17032 | break; |
||
17033 | case 256: |
||
17034 | names = names_ymm; |
||
17035 | break; |
||
17036 | default: |
||
17037 | abort (); |
||
17038 | } |
||
17039 | } |
||
17040 | else |
||
17041 | names = names_xmm; |
||
17042 | oappend (names[reg]); |
||
17043 | } |
||
17044 | |||
17045 | static void |
||
17046 | CRC32_Fixup (int bytemode, int sizeflag) |
||
17047 | { |
||
17048 | /* Add proper suffix to "crc32". */ |
||
17049 | char *p = mnemonicendp; |
||
17050 | |||
17051 | switch (bytemode) |
||
17052 | { |
||
17053 | case b_mode: |
||
17054 | if (intel_syntax) |
||
17055 | goto skip; |
||
17056 | |||
17057 | *p++ = 'b'; |
||
17058 | break; |
||
17059 | case v_mode: |
||
17060 | if (intel_syntax) |
||
17061 | goto skip; |
||
17062 | |||
17063 | USED_REX (REX_W); |
||
17064 | if (rex & REX_W) |
||
17065 | *p++ = 'q'; |
||
17066 | else |
||
17067 | { |
||
17068 | if (sizeflag & DFLAG) |
||
17069 | *p++ = 'l'; |
||
17070 | else |
||
17071 | *p++ = 'w'; |
||
17072 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
17073 | } |
||
17074 | break; |
||
17075 | default: |
||
17076 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
17077 | break; |
||
17078 | } |
||
17079 | mnemonicendp = p; |
||
17080 | *p = '\0'; |
||
17081 | |||
17082 | skip: |
||
17083 | if (modrm.mod == 3) |
||
17084 | { |
||
17085 | int add; |
||
17086 | |||
17087 | /* Skip mod/rm byte. */ |
||
17088 | MODRM_CHECK; |
||
17089 | codep++; |
||
17090 | |||
17091 | USED_REX (REX_B); |
||
17092 | add = (rex & REX_B) ? 8 : 0; |
||
17093 | if (bytemode == b_mode) |
||
17094 | { |
||
17095 | USED_REX (0); |
||
17096 | if (rex) |
||
17097 | oappend (names8rex[modrm.rm + add]); |
||
17098 | else |
||
17099 | oappend (names8[modrm.rm + add]); |
||
17100 | } |
||
17101 | else |
||
17102 | { |
||
17103 | USED_REX (REX_W); |
||
17104 | if (rex & REX_W) |
||
17105 | oappend (names64[modrm.rm + add]); |
||
17106 | else if ((prefixes & PREFIX_DATA)) |
||
17107 | oappend (names16[modrm.rm + add]); |
||
17108 | else |
||
17109 | oappend (names32[modrm.rm + add]); |
||
17110 | } |
||
17111 | } |
||
17112 | else |
||
17113 | OP_E (bytemode, sizeflag); |
||
17114 | } |
||
17115 | |||
17116 | static void |
||
17117 | FXSAVE_Fixup (int bytemode, int sizeflag) |
||
17118 | { |
||
17119 | /* Add proper suffix to "fxsave" and "fxrstor". */ |
||
17120 | USED_REX (REX_W); |
||
17121 | if (rex & REX_W) |
||
17122 | { |
||
17123 | char *p = mnemonicendp; |
||
17124 | *p++ = '6'; |
||
17125 | *p++ = '4'; |
||
17126 | *p = '\0'; |
||
17127 | mnemonicendp = p; |
||
17128 | } |
||
17129 | OP_M (bytemode, sizeflag); |
||
17130 | } |
||
17131 | |||
17132 | /* Display the destination register operand for instructions with |
||
17133 | VEX. */ |
||
17134 | |||
17135 | static void |
||
17136 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
||
17137 | { |
||
17138 | int reg; |
||
17139 | const char **names; |
||
17140 | |||
17141 | if (!need_vex) |
||
17142 | abort (); |
||
17143 | |||
17144 | if (!need_vex_reg) |
||
17145 | return; |
||
17146 | |||
17147 | reg = vex.register_specifier; |
||
17148 | if (vex.evex) |
||
17149 | { |
||
17150 | if (!vex.v) |
||
17151 | reg += 16; |
||
17152 | } |
||
17153 | |||
17154 | if (bytemode == vex_scalar_mode) |
||
17155 | { |
||
17156 | oappend (names_xmm[reg]); |
||
17157 | return; |
||
17158 | } |
||
17159 | |||
17160 | switch (vex.length) |
||
17161 | { |
||
17162 | case 128: |
||
17163 | switch (bytemode) |
||
17164 | { |
||
17165 | case vex_mode: |
||
17166 | case vex128_mode: |
||
17167 | case vex_vsib_q_w_dq_mode: |
||
6324 | serge | 17168 | case vex_vsib_q_w_d_mode: |
5221 | serge | 17169 | names = names_xmm; |
17170 | break; |
||
17171 | case dq_mode: |
||
17172 | if (vex.w) |
||
17173 | names = names64; |
||
17174 | else |
||
17175 | names = names32; |
||
17176 | break; |
||
6324 | serge | 17177 | case mask_bd_mode: |
5221 | serge | 17178 | case mask_mode: |
17179 | names = names_mask; |
||
17180 | break; |
||
17181 | default: |
||
17182 | abort (); |
||
17183 | return; |
||
17184 | } |
||
17185 | break; |
||
17186 | case 256: |
||
17187 | switch (bytemode) |
||
17188 | { |
||
17189 | case vex_mode: |
||
17190 | case vex256_mode: |
||
17191 | names = names_ymm; |
||
17192 | break; |
||
17193 | case vex_vsib_q_w_dq_mode: |
||
6324 | serge | 17194 | case vex_vsib_q_w_d_mode: |
5221 | serge | 17195 | names = vex.w ? names_ymm : names_xmm; |
17196 | break; |
||
6324 | serge | 17197 | case mask_bd_mode: |
5221 | serge | 17198 | case mask_mode: |
17199 | names = names_mask; |
||
17200 | break; |
||
17201 | default: |
||
17202 | abort (); |
||
17203 | return; |
||
17204 | } |
||
17205 | break; |
||
17206 | case 512: |
||
17207 | names = names_zmm; |
||
17208 | break; |
||
17209 | default: |
||
17210 | abort (); |
||
17211 | break; |
||
17212 | } |
||
17213 | oappend (names[reg]); |
||
17214 | } |
||
17215 | |||
17216 | /* Get the VEX immediate byte without moving codep. */ |
||
17217 | |||
17218 | static unsigned char |
||
17219 | get_vex_imm8 (int sizeflag, int opnum) |
||
17220 | { |
||
17221 | int bytes_before_imm = 0; |
||
17222 | |||
17223 | if (modrm.mod != 3) |
||
17224 | { |
||
17225 | /* There are SIB/displacement bytes. */ |
||
17226 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
||
17227 | { |
||
17228 | /* 32/64 bit address mode */ |
||
17229 | int base = modrm.rm; |
||
17230 | |||
17231 | /* Check SIB byte. */ |
||
17232 | if (base == 4) |
||
17233 | { |
||
17234 | FETCH_DATA (the_info, codep + 1); |
||
17235 | base = *codep & 7; |
||
17236 | /* When decoding the third source, don't increase |
||
17237 | bytes_before_imm as this has already been incremented |
||
17238 | by one in OP_E_memory while decoding the second |
||
17239 | source operand. */ |
||
17240 | if (opnum == 0) |
||
17241 | bytes_before_imm++; |
||
17242 | } |
||
17243 | |||
17244 | /* Don't increase bytes_before_imm when decoding the third source, |
||
17245 | it has already been incremented by OP_E_memory while decoding |
||
17246 | the second source operand. */ |
||
17247 | if (opnum == 0) |
||
17248 | { |
||
17249 | switch (modrm.mod) |
||
17250 | { |
||
17251 | case 0: |
||
17252 | /* When modrm.rm == 5 or modrm.rm == 4 and base in |
||
17253 | SIB == 5, there is a 4 byte displacement. */ |
||
17254 | if (base != 5) |
||
17255 | /* No displacement. */ |
||
17256 | break; |
||
17257 | case 2: |
||
17258 | /* 4 byte displacement. */ |
||
17259 | bytes_before_imm += 4; |
||
17260 | break; |
||
17261 | case 1: |
||
17262 | /* 1 byte displacement. */ |
||
17263 | bytes_before_imm++; |
||
17264 | break; |
||
17265 | } |
||
17266 | } |
||
17267 | } |
||
17268 | else |
||
17269 | { |
||
17270 | /* 16 bit address mode */ |
||
17271 | /* Don't increase bytes_before_imm when decoding the third source, |
||
17272 | it has already been incremented by OP_E_memory while decoding |
||
17273 | the second source operand. */ |
||
17274 | if (opnum == 0) |
||
17275 | { |
||
17276 | switch (modrm.mod) |
||
17277 | { |
||
17278 | case 0: |
||
17279 | /* When modrm.rm == 6, there is a 2 byte displacement. */ |
||
17280 | if (modrm.rm != 6) |
||
17281 | /* No displacement. */ |
||
17282 | break; |
||
17283 | case 2: |
||
17284 | /* 2 byte displacement. */ |
||
17285 | bytes_before_imm += 2; |
||
17286 | break; |
||
17287 | case 1: |
||
17288 | /* 1 byte displacement: when decoding the third source, |
||
17289 | don't increase bytes_before_imm as this has already |
||
17290 | been incremented by one in OP_E_memory while decoding |
||
17291 | the second source operand. */ |
||
17292 | if (opnum == 0) |
||
17293 | bytes_before_imm++; |
||
17294 | |||
17295 | break; |
||
17296 | } |
||
17297 | } |
||
17298 | } |
||
17299 | } |
||
17300 | |||
17301 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); |
||
17302 | return codep [bytes_before_imm]; |
||
17303 | } |
||
17304 | |||
17305 | static void |
||
17306 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) |
||
17307 | { |
||
17308 | const char **names; |
||
17309 | |||
17310 | if (reg == -1 && modrm.mod != 3) |
||
17311 | { |
||
17312 | OP_E_memory (bytemode, sizeflag); |
||
17313 | return; |
||
17314 | } |
||
17315 | else |
||
17316 | { |
||
17317 | if (reg == -1) |
||
17318 | { |
||
17319 | reg = modrm.rm; |
||
17320 | USED_REX (REX_B); |
||
17321 | if (rex & REX_B) |
||
17322 | reg += 8; |
||
17323 | } |
||
17324 | else if (reg > 7 && address_mode != mode_64bit) |
||
17325 | BadOp (); |
||
17326 | } |
||
17327 | |||
17328 | switch (vex.length) |
||
17329 | { |
||
17330 | case 128: |
||
17331 | names = names_xmm; |
||
17332 | break; |
||
17333 | case 256: |
||
17334 | names = names_ymm; |
||
17335 | break; |
||
17336 | default: |
||
17337 | abort (); |
||
17338 | } |
||
17339 | oappend (names[reg]); |
||
17340 | } |
||
17341 | |||
17342 | static void |
||
17343 | OP_EX_VexImmW (int bytemode, int sizeflag) |
||
17344 | { |
||
17345 | int reg = -1; |
||
17346 | static unsigned char vex_imm8; |
||
17347 | |||
17348 | if (vex_w_done == 0) |
||
17349 | { |
||
17350 | vex_w_done = 1; |
||
17351 | |||
17352 | /* Skip mod/rm byte. */ |
||
17353 | MODRM_CHECK; |
||
17354 | codep++; |
||
17355 | |||
17356 | vex_imm8 = get_vex_imm8 (sizeflag, 0); |
||
17357 | |||
17358 | if (vex.w) |
||
17359 | reg = vex_imm8 >> 4; |
||
17360 | |||
17361 | OP_EX_VexReg (bytemode, sizeflag, reg); |
||
17362 | } |
||
17363 | else if (vex_w_done == 1) |
||
17364 | { |
||
17365 | vex_w_done = 2; |
||
17366 | |||
17367 | if (!vex.w) |
||
17368 | reg = vex_imm8 >> 4; |
||
17369 | |||
17370 | OP_EX_VexReg (bytemode, sizeflag, reg); |
||
17371 | } |
||
17372 | else |
||
17373 | { |
||
17374 | /* Output the imm8 directly. */ |
||
17375 | scratchbuf[0] = '$'; |
||
17376 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); |
||
17377 | oappend_maybe_intel (scratchbuf); |
||
17378 | scratchbuf[0] = '\0'; |
||
17379 | codep++; |
||
17380 | } |
||
17381 | } |
||
17382 | |||
17383 | static void |
||
17384 | OP_Vex_2src (int bytemode, int sizeflag) |
||
17385 | { |
||
17386 | if (modrm.mod == 3) |
||
17387 | { |
||
17388 | int reg = modrm.rm; |
||
17389 | USED_REX (REX_B); |
||
17390 | if (rex & REX_B) |
||
17391 | reg += 8; |
||
17392 | oappend (names_xmm[reg]); |
||
17393 | } |
||
17394 | else |
||
17395 | { |
||
17396 | if (intel_syntax |
||
17397 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
||
17398 | { |
||
17399 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
||
17400 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
17401 | } |
||
17402 | OP_E (bytemode, sizeflag); |
||
17403 | } |
||
17404 | } |
||
17405 | |||
17406 | static void |
||
17407 | OP_Vex_2src_1 (int bytemode, int sizeflag) |
||
17408 | { |
||
17409 | if (modrm.mod == 3) |
||
17410 | { |
||
17411 | /* Skip mod/rm byte. */ |
||
17412 | MODRM_CHECK; |
||
17413 | codep++; |
||
17414 | } |
||
17415 | |||
17416 | if (vex.w) |
||
17417 | oappend (names_xmm[vex.register_specifier]); |
||
17418 | else |
||
17419 | OP_Vex_2src (bytemode, sizeflag); |
||
17420 | } |
||
17421 | |||
17422 | static void |
||
17423 | OP_Vex_2src_2 (int bytemode, int sizeflag) |
||
17424 | { |
||
17425 | if (vex.w) |
||
17426 | OP_Vex_2src (bytemode, sizeflag); |
||
17427 | else |
||
17428 | oappend (names_xmm[vex.register_specifier]); |
||
17429 | } |
||
17430 | |||
17431 | static void |
||
17432 | OP_EX_VexW (int bytemode, int sizeflag) |
||
17433 | { |
||
17434 | int reg = -1; |
||
17435 | |||
17436 | if (!vex_w_done) |
||
17437 | { |
||
17438 | vex_w_done = 1; |
||
17439 | |||
17440 | /* Skip mod/rm byte. */ |
||
17441 | MODRM_CHECK; |
||
17442 | codep++; |
||
17443 | |||
17444 | if (vex.w) |
||
17445 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
||
17446 | } |
||
17447 | else |
||
17448 | { |
||
17449 | if (!vex.w) |
||
17450 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
||
17451 | } |
||
17452 | |||
17453 | OP_EX_VexReg (bytemode, sizeflag, reg); |
||
17454 | } |
||
17455 | |||
17456 | static void |
||
17457 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, |
||
17458 | int sizeflag ATTRIBUTE_UNUSED) |
||
17459 | { |
||
17460 | /* Skip the immediate byte and check for invalid bits. */ |
||
17461 | FETCH_DATA (the_info, codep + 1); |
||
17462 | if (*codep++ & 0xf) |
||
17463 | BadOp (); |
||
17464 | } |
||
17465 | |||
17466 | static void |
||
17467 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
||
17468 | { |
||
17469 | int reg; |
||
17470 | const char **names; |
||
17471 | |||
17472 | FETCH_DATA (the_info, codep + 1); |
||
17473 | reg = *codep++; |
||
17474 | |||
17475 | if (bytemode != x_mode) |
||
17476 | abort (); |
||
17477 | |||
17478 | if (reg & 0xf) |
||
17479 | BadOp (); |
||
17480 | |||
17481 | reg >>= 4; |
||
17482 | if (reg > 7 && address_mode != mode_64bit) |
||
17483 | BadOp (); |
||
17484 | |||
17485 | switch (vex.length) |
||
17486 | { |
||
17487 | case 128: |
||
17488 | names = names_xmm; |
||
17489 | break; |
||
17490 | case 256: |
||
17491 | names = names_ymm; |
||
17492 | break; |
||
17493 | default: |
||
17494 | abort (); |
||
17495 | } |
||
17496 | oappend (names[reg]); |
||
17497 | } |
||
17498 | |||
17499 | static void |
||
17500 | OP_XMM_VexW (int bytemode, int sizeflag) |
||
17501 | { |
||
17502 | /* Turn off the REX.W bit since it is used for swapping operands |
||
17503 | now. */ |
||
17504 | rex &= ~REX_W; |
||
17505 | OP_XMM (bytemode, sizeflag); |
||
17506 | } |
||
17507 | |||
17508 | static void |
||
17509 | OP_EX_Vex (int bytemode, int sizeflag) |
||
17510 | { |
||
17511 | if (modrm.mod != 3) |
||
17512 | { |
||
17513 | if (vex.register_specifier != 0) |
||
17514 | BadOp (); |
||
17515 | need_vex_reg = 0; |
||
17516 | } |
||
17517 | OP_EX (bytemode, sizeflag); |
||
17518 | } |
||
17519 | |||
17520 | static void |
||
17521 | OP_XMM_Vex (int bytemode, int sizeflag) |
||
17522 | { |
||
17523 | if (modrm.mod != 3) |
||
17524 | { |
||
17525 | if (vex.register_specifier != 0) |
||
17526 | BadOp (); |
||
17527 | need_vex_reg = 0; |
||
17528 | } |
||
17529 | OP_XMM (bytemode, sizeflag); |
||
17530 | } |
||
17531 | |||
17532 | static void |
||
17533 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
17534 | { |
||
17535 | switch (vex.length) |
||
17536 | { |
||
17537 | case 128: |
||
17538 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
||
17539 | break; |
||
17540 | case 256: |
||
17541 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
||
17542 | break; |
||
17543 | default: |
||
17544 | abort (); |
||
17545 | } |
||
17546 | } |
||
17547 | |||
17548 | static struct op vex_cmp_op[] = |
||
17549 | { |
||
17550 | { STRING_COMMA_LEN ("eq") }, |
||
17551 | { STRING_COMMA_LEN ("lt") }, |
||
17552 | { STRING_COMMA_LEN ("le") }, |
||
17553 | { STRING_COMMA_LEN ("unord") }, |
||
17554 | { STRING_COMMA_LEN ("neq") }, |
||
17555 | { STRING_COMMA_LEN ("nlt") }, |
||
17556 | { STRING_COMMA_LEN ("nle") }, |
||
17557 | { STRING_COMMA_LEN ("ord") }, |
||
17558 | { STRING_COMMA_LEN ("eq_uq") }, |
||
17559 | { STRING_COMMA_LEN ("nge") }, |
||
17560 | { STRING_COMMA_LEN ("ngt") }, |
||
17561 | { STRING_COMMA_LEN ("false") }, |
||
17562 | { STRING_COMMA_LEN ("neq_oq") }, |
||
17563 | { STRING_COMMA_LEN ("ge") }, |
||
17564 | { STRING_COMMA_LEN ("gt") }, |
||
17565 | { STRING_COMMA_LEN ("true") }, |
||
17566 | { STRING_COMMA_LEN ("eq_os") }, |
||
17567 | { STRING_COMMA_LEN ("lt_oq") }, |
||
17568 | { STRING_COMMA_LEN ("le_oq") }, |
||
17569 | { STRING_COMMA_LEN ("unord_s") }, |
||
17570 | { STRING_COMMA_LEN ("neq_us") }, |
||
17571 | { STRING_COMMA_LEN ("nlt_uq") }, |
||
17572 | { STRING_COMMA_LEN ("nle_uq") }, |
||
17573 | { STRING_COMMA_LEN ("ord_s") }, |
||
17574 | { STRING_COMMA_LEN ("eq_us") }, |
||
17575 | { STRING_COMMA_LEN ("nge_uq") }, |
||
17576 | { STRING_COMMA_LEN ("ngt_uq") }, |
||
17577 | { STRING_COMMA_LEN ("false_os") }, |
||
17578 | { STRING_COMMA_LEN ("neq_os") }, |
||
17579 | { STRING_COMMA_LEN ("ge_oq") }, |
||
17580 | { STRING_COMMA_LEN ("gt_oq") }, |
||
17581 | { STRING_COMMA_LEN ("true_us") }, |
||
17582 | }; |
||
17583 | |||
17584 | static void |
||
17585 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
17586 | { |
||
17587 | unsigned int cmp_type; |
||
17588 | |||
17589 | FETCH_DATA (the_info, codep + 1); |
||
17590 | cmp_type = *codep++ & 0xff; |
||
17591 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) |
||
17592 | { |
||
17593 | char suffix [3]; |
||
17594 | char *p = mnemonicendp - 2; |
||
17595 | suffix[0] = p[0]; |
||
17596 | suffix[1] = p[1]; |
||
17597 | suffix[2] = '\0'; |
||
17598 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
||
17599 | mnemonicendp += vex_cmp_op[cmp_type].len; |
||
17600 | } |
||
17601 | else |
||
17602 | { |
||
17603 | /* We have a reserved extension byte. Output it directly. */ |
||
17604 | scratchbuf[0] = '$'; |
||
17605 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
||
17606 | oappend_maybe_intel (scratchbuf); |
||
17607 | scratchbuf[0] = '\0'; |
||
17608 | } |
||
17609 | } |
||
17610 | |||
17611 | static void |
||
17612 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, |
||
17613 | int sizeflag ATTRIBUTE_UNUSED) |
||
17614 | { |
||
17615 | unsigned int cmp_type; |
||
17616 | |||
17617 | if (!vex.evex) |
||
17618 | abort (); |
||
17619 | |||
17620 | FETCH_DATA (the_info, codep + 1); |
||
17621 | cmp_type = *codep++ & 0xff; |
||
17622 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. |
||
17623 | If it's the case, print suffix, otherwise - print the immediate. */ |
||
17624 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) |
||
17625 | && cmp_type != 3 |
||
17626 | && cmp_type != 7) |
||
17627 | { |
||
17628 | char suffix [3]; |
||
17629 | char *p = mnemonicendp - 2; |
||
17630 | |||
17631 | /* vpcmp* can have both one- and two-lettered suffix. */ |
||
17632 | if (p[0] == 'p') |
||
17633 | { |
||
17634 | p++; |
||
17635 | suffix[0] = p[0]; |
||
17636 | suffix[1] = '\0'; |
||
17637 | } |
||
17638 | else |
||
17639 | { |
||
17640 | suffix[0] = p[0]; |
||
17641 | suffix[1] = p[1]; |
||
17642 | suffix[2] = '\0'; |
||
17643 | } |
||
17644 | |||
17645 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
||
17646 | mnemonicendp += simd_cmp_op[cmp_type].len; |
||
17647 | } |
||
17648 | else |
||
17649 | { |
||
17650 | /* We have a reserved extension byte. Output it directly. */ |
||
17651 | scratchbuf[0] = '$'; |
||
17652 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
||
17653 | oappend_maybe_intel (scratchbuf); |
||
17654 | scratchbuf[0] = '\0'; |
||
17655 | } |
||
17656 | } |
||
17657 | |||
17658 | static const struct op pclmul_op[] = |
||
17659 | { |
||
17660 | { STRING_COMMA_LEN ("lql") }, |
||
17661 | { STRING_COMMA_LEN ("hql") }, |
||
17662 | { STRING_COMMA_LEN ("lqh") }, |
||
17663 | { STRING_COMMA_LEN ("hqh") } |
||
17664 | }; |
||
17665 | |||
17666 | static void |
||
17667 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, |
||
17668 | int sizeflag ATTRIBUTE_UNUSED) |
||
17669 | { |
||
17670 | unsigned int pclmul_type; |
||
17671 | |||
17672 | FETCH_DATA (the_info, codep + 1); |
||
17673 | pclmul_type = *codep++ & 0xff; |
||
17674 | switch (pclmul_type) |
||
17675 | { |
||
17676 | case 0x10: |
||
17677 | pclmul_type = 2; |
||
17678 | break; |
||
17679 | case 0x11: |
||
17680 | pclmul_type = 3; |
||
17681 | break; |
||
17682 | default: |
||
17683 | break; |
||
17684 | } |
||
17685 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
||
17686 | { |
||
17687 | char suffix [4]; |
||
17688 | char *p = mnemonicendp - 3; |
||
17689 | suffix[0] = p[0]; |
||
17690 | suffix[1] = p[1]; |
||
17691 | suffix[2] = p[2]; |
||
17692 | suffix[3] = '\0'; |
||
17693 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
||
17694 | mnemonicendp += pclmul_op[pclmul_type].len; |
||
17695 | } |
||
17696 | else |
||
17697 | { |
||
17698 | /* We have a reserved extension byte. Output it directly. */ |
||
17699 | scratchbuf[0] = '$'; |
||
17700 | print_operand_value (scratchbuf + 1, 1, pclmul_type); |
||
17701 | oappend_maybe_intel (scratchbuf); |
||
17702 | scratchbuf[0] = '\0'; |
||
17703 | } |
||
17704 | } |
||
17705 | |||
17706 | static void |
||
17707 | MOVBE_Fixup (int bytemode, int sizeflag) |
||
17708 | { |
||
17709 | /* Add proper suffix to "movbe". */ |
||
17710 | char *p = mnemonicendp; |
||
17711 | |||
17712 | switch (bytemode) |
||
17713 | { |
||
17714 | case v_mode: |
||
17715 | if (intel_syntax) |
||
17716 | goto skip; |
||
17717 | |||
17718 | USED_REX (REX_W); |
||
17719 | if (sizeflag & SUFFIX_ALWAYS) |
||
17720 | { |
||
17721 | if (rex & REX_W) |
||
17722 | *p++ = 'q'; |
||
17723 | else |
||
17724 | { |
||
17725 | if (sizeflag & DFLAG) |
||
17726 | *p++ = 'l'; |
||
17727 | else |
||
17728 | *p++ = 'w'; |
||
17729 | used_prefixes |= (prefixes & PREFIX_DATA); |
||
17730 | } |
||
17731 | } |
||
17732 | break; |
||
17733 | default: |
||
17734 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
||
17735 | break; |
||
17736 | } |
||
17737 | mnemonicendp = p; |
||
17738 | *p = '\0'; |
||
17739 | |||
17740 | skip: |
||
17741 | OP_M (bytemode, sizeflag); |
||
17742 | } |
||
17743 | |||
17744 | static void |
||
17745 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
17746 | { |
||
17747 | int reg; |
||
17748 | const char **names; |
||
17749 | |||
17750 | /* Skip mod/rm byte. */ |
||
17751 | MODRM_CHECK; |
||
17752 | codep++; |
||
17753 | |||
17754 | if (vex.w) |
||
17755 | names = names64; |
||
17756 | else |
||
17757 | names = names32; |
||
17758 | |||
17759 | reg = modrm.rm; |
||
17760 | USED_REX (REX_B); |
||
17761 | if (rex & REX_B) |
||
17762 | reg += 8; |
||
17763 | |||
17764 | oappend (names[reg]); |
||
17765 | } |
||
17766 | |||
17767 | static void |
||
17768 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
||
17769 | { |
||
17770 | const char **names; |
||
17771 | |||
17772 | if (vex.w) |
||
17773 | names = names64; |
||
17774 | else |
||
17775 | names = names32; |
||
17776 | |||
17777 | oappend (names[vex.register_specifier]); |
||
17778 | } |
||
17779 | |||
17780 | static void |
||
17781 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
||
17782 | { |
||
17783 | if (!vex.evex |
||
6324 | serge | 17784 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
5221 | serge | 17785 | abort (); |
17786 | |||
17787 | USED_REX (REX_R); |
||
17788 | if ((rex & REX_R) != 0 || !vex.r) |
||
17789 | { |
||
17790 | BadOp (); |
||
17791 | return; |
||
17792 | } |
||
17793 | |||
17794 | oappend (names_mask [modrm.reg]); |
||
17795 | } |
||
17796 | |||
17797 | static void |
||
17798 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
||
17799 | { |
||
17800 | if (!vex.evex |
||
17801 | || (bytemode != evex_rounding_mode |
||
17802 | && bytemode != evex_sae_mode)) |
||
17803 | abort (); |
||
17804 | if (modrm.mod == 3 && vex.b) |
||
17805 | switch (bytemode) |
||
17806 | { |
||
17807 | case evex_rounding_mode: |
||
17808 | oappend (names_rounding[vex.ll]); |
||
17809 | break; |
||
17810 | case evex_sae_mode: |
||
17811 | oappend ("{sae}"); |
||
17812 | break; |
||
17813 | default: |
||
17814 | break; |
||
17815 | } |
||
17816 | }>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=><=>>>>>>>>>>>>>>>>>>>>>><>><>><>><>><>=>=> |