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Rev | Author | Line No. | Line |
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5221 | serge | 1 | #ifdef NEED_OPCODE_TABLE |
2 | |||
3 | static const struct dis386 evex_table[][256] = { |
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4 | /* EVEX_0F */ |
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5 | { |
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6 | /* 00 */ |
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7 | { Bad_Opcode }, |
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8 | { Bad_Opcode }, |
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9 | { Bad_Opcode }, |
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10 | { Bad_Opcode }, |
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11 | { Bad_Opcode }, |
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12 | { Bad_Opcode }, |
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13 | { Bad_Opcode }, |
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14 | { Bad_Opcode }, |
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15 | /* 08 */ |
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16 | { Bad_Opcode }, |
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17 | { Bad_Opcode }, |
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18 | { Bad_Opcode }, |
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19 | { Bad_Opcode }, |
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20 | { Bad_Opcode }, |
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21 | { Bad_Opcode }, |
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22 | { Bad_Opcode }, |
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23 | { Bad_Opcode }, |
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24 | /* 10 */ |
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25 | { PREFIX_TABLE (PREFIX_EVEX_0F10) }, |
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26 | { PREFIX_TABLE (PREFIX_EVEX_0F11) }, |
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27 | { PREFIX_TABLE (PREFIX_EVEX_0F12) }, |
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28 | { PREFIX_TABLE (PREFIX_EVEX_0F13) }, |
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29 | { PREFIX_TABLE (PREFIX_EVEX_0F14) }, |
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30 | { PREFIX_TABLE (PREFIX_EVEX_0F15) }, |
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31 | { PREFIX_TABLE (PREFIX_EVEX_0F16) }, |
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32 | { PREFIX_TABLE (PREFIX_EVEX_0F17) }, |
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33 | /* 18 */ |
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34 | { Bad_Opcode }, |
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35 | { Bad_Opcode }, |
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36 | { Bad_Opcode }, |
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37 | { Bad_Opcode }, |
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38 | { Bad_Opcode }, |
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39 | { Bad_Opcode }, |
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40 | { Bad_Opcode }, |
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41 | { Bad_Opcode }, |
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42 | /* 20 */ |
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43 | { Bad_Opcode }, |
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44 | { Bad_Opcode }, |
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45 | { Bad_Opcode }, |
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46 | { Bad_Opcode }, |
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47 | { Bad_Opcode }, |
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48 | { Bad_Opcode }, |
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49 | { Bad_Opcode }, |
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50 | { Bad_Opcode }, |
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51 | /* 28 */ |
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52 | { PREFIX_TABLE (PREFIX_EVEX_0F28) }, |
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53 | { PREFIX_TABLE (PREFIX_EVEX_0F29) }, |
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54 | { PREFIX_TABLE (PREFIX_EVEX_0F2A) }, |
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55 | { PREFIX_TABLE (PREFIX_EVEX_0F2B) }, |
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56 | { PREFIX_TABLE (PREFIX_EVEX_0F2C) }, |
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57 | { PREFIX_TABLE (PREFIX_EVEX_0F2D) }, |
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58 | { PREFIX_TABLE (PREFIX_EVEX_0F2E) }, |
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59 | { PREFIX_TABLE (PREFIX_EVEX_0F2F) }, |
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60 | /* 30 */ |
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61 | { Bad_Opcode }, |
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62 | { Bad_Opcode }, |
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63 | { Bad_Opcode }, |
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64 | { Bad_Opcode }, |
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65 | { Bad_Opcode }, |
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66 | { Bad_Opcode }, |
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67 | { Bad_Opcode }, |
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68 | { Bad_Opcode }, |
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69 | /* 38 */ |
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70 | { Bad_Opcode }, |
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71 | { Bad_Opcode }, |
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72 | { Bad_Opcode }, |
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73 | { Bad_Opcode }, |
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74 | { Bad_Opcode }, |
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75 | { Bad_Opcode }, |
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76 | { Bad_Opcode }, |
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77 | { Bad_Opcode }, |
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78 | /* 40 */ |
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79 | { Bad_Opcode }, |
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80 | { Bad_Opcode }, |
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81 | { Bad_Opcode }, |
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82 | { Bad_Opcode }, |
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83 | { Bad_Opcode }, |
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84 | { Bad_Opcode }, |
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85 | { Bad_Opcode }, |
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86 | { Bad_Opcode }, |
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87 | /* 48 */ |
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88 | { Bad_Opcode }, |
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89 | { Bad_Opcode }, |
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90 | { Bad_Opcode }, |
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91 | { Bad_Opcode }, |
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92 | { Bad_Opcode }, |
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93 | { Bad_Opcode }, |
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94 | { Bad_Opcode }, |
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95 | { Bad_Opcode }, |
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96 | /* 50 */ |
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97 | { Bad_Opcode }, |
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98 | { PREFIX_TABLE (PREFIX_EVEX_0F51) }, |
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99 | { Bad_Opcode }, |
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100 | { Bad_Opcode }, |
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6324 | serge | 101 | { PREFIX_TABLE (PREFIX_EVEX_0F54) }, |
102 | { PREFIX_TABLE (PREFIX_EVEX_0F55) }, |
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103 | { PREFIX_TABLE (PREFIX_EVEX_0F56) }, |
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104 | { PREFIX_TABLE (PREFIX_EVEX_0F57) }, |
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5221 | serge | 105 | /* 58 */ |
106 | { PREFIX_TABLE (PREFIX_EVEX_0F58) }, |
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107 | { PREFIX_TABLE (PREFIX_EVEX_0F59) }, |
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108 | { PREFIX_TABLE (PREFIX_EVEX_0F5A) }, |
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109 | { PREFIX_TABLE (PREFIX_EVEX_0F5B) }, |
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110 | { PREFIX_TABLE (PREFIX_EVEX_0F5C) }, |
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111 | { PREFIX_TABLE (PREFIX_EVEX_0F5D) }, |
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112 | { PREFIX_TABLE (PREFIX_EVEX_0F5E) }, |
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113 | { PREFIX_TABLE (PREFIX_EVEX_0F5F) }, |
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114 | /* 60 */ |
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6324 | serge | 115 | { PREFIX_TABLE (PREFIX_EVEX_0F60) }, |
116 | { PREFIX_TABLE (PREFIX_EVEX_0F61) }, |
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5221 | serge | 117 | { PREFIX_TABLE (PREFIX_EVEX_0F62) }, |
6324 | serge | 118 | { PREFIX_TABLE (PREFIX_EVEX_0F63) }, |
119 | { PREFIX_TABLE (PREFIX_EVEX_0F64) }, |
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120 | { PREFIX_TABLE (PREFIX_EVEX_0F65) }, |
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5221 | serge | 121 | { PREFIX_TABLE (PREFIX_EVEX_0F66) }, |
6324 | serge | 122 | { PREFIX_TABLE (PREFIX_EVEX_0F67) }, |
5221 | serge | 123 | /* 68 */ |
6324 | serge | 124 | { PREFIX_TABLE (PREFIX_EVEX_0F68) }, |
125 | { PREFIX_TABLE (PREFIX_EVEX_0F69) }, |
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5221 | serge | 126 | { PREFIX_TABLE (PREFIX_EVEX_0F6A) }, |
6324 | serge | 127 | { PREFIX_TABLE (PREFIX_EVEX_0F6B) }, |
5221 | serge | 128 | { PREFIX_TABLE (PREFIX_EVEX_0F6C) }, |
129 | { PREFIX_TABLE (PREFIX_EVEX_0F6D) }, |
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130 | { PREFIX_TABLE (PREFIX_EVEX_0F6E) }, |
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131 | { PREFIX_TABLE (PREFIX_EVEX_0F6F) }, |
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132 | /* 70 */ |
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133 | { PREFIX_TABLE (PREFIX_EVEX_0F70) }, |
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6324 | serge | 134 | { REG_TABLE (REG_EVEX_0F71) }, |
5221 | serge | 135 | { REG_TABLE (REG_EVEX_0F72) }, |
136 | { REG_TABLE (REG_EVEX_0F73) }, |
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6324 | serge | 137 | { PREFIX_TABLE (PREFIX_EVEX_0F74) }, |
138 | { PREFIX_TABLE (PREFIX_EVEX_0F75) }, |
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5221 | serge | 139 | { PREFIX_TABLE (PREFIX_EVEX_0F76) }, |
140 | { Bad_Opcode }, |
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141 | /* 78 */ |
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142 | { PREFIX_TABLE (PREFIX_EVEX_0F78) }, |
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143 | { PREFIX_TABLE (PREFIX_EVEX_0F79) }, |
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144 | { PREFIX_TABLE (PREFIX_EVEX_0F7A) }, |
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145 | { PREFIX_TABLE (PREFIX_EVEX_0F7B) }, |
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146 | { Bad_Opcode }, |
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147 | { Bad_Opcode }, |
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148 | { PREFIX_TABLE (PREFIX_EVEX_0F7E) }, |
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149 | { PREFIX_TABLE (PREFIX_EVEX_0F7F) }, |
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150 | /* 80 */ |
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151 | { Bad_Opcode }, |
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152 | { Bad_Opcode }, |
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153 | { Bad_Opcode }, |
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154 | { Bad_Opcode }, |
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155 | { Bad_Opcode }, |
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156 | { Bad_Opcode }, |
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157 | { Bad_Opcode }, |
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158 | { Bad_Opcode }, |
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159 | /* 88 */ |
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160 | { Bad_Opcode }, |
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161 | { Bad_Opcode }, |
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162 | { Bad_Opcode }, |
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163 | { Bad_Opcode }, |
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164 | { Bad_Opcode }, |
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165 | { Bad_Opcode }, |
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166 | { Bad_Opcode }, |
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167 | { Bad_Opcode }, |
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168 | /* 90 */ |
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169 | { Bad_Opcode }, |
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170 | { Bad_Opcode }, |
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171 | { Bad_Opcode }, |
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172 | { Bad_Opcode }, |
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173 | { Bad_Opcode }, |
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174 | { Bad_Opcode }, |
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175 | { Bad_Opcode }, |
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176 | { Bad_Opcode }, |
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177 | /* 98 */ |
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178 | { Bad_Opcode }, |
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179 | { Bad_Opcode }, |
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180 | { Bad_Opcode }, |
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181 | { Bad_Opcode }, |
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182 | { Bad_Opcode }, |
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183 | { Bad_Opcode }, |
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184 | { Bad_Opcode }, |
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185 | { Bad_Opcode }, |
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186 | /* A0 */ |
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187 | { Bad_Opcode }, |
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188 | { Bad_Opcode }, |
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189 | { Bad_Opcode }, |
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190 | { Bad_Opcode }, |
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191 | { Bad_Opcode }, |
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192 | { Bad_Opcode }, |
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193 | { Bad_Opcode }, |
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194 | { Bad_Opcode }, |
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195 | /* A8 */ |
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196 | { Bad_Opcode }, |
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197 | { Bad_Opcode }, |
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198 | { Bad_Opcode }, |
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199 | { Bad_Opcode }, |
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200 | { Bad_Opcode }, |
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201 | { Bad_Opcode }, |
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202 | { Bad_Opcode }, |
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203 | { Bad_Opcode }, |
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204 | /* B0 */ |
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205 | { Bad_Opcode }, |
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206 | { Bad_Opcode }, |
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207 | { Bad_Opcode }, |
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208 | { Bad_Opcode }, |
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209 | { Bad_Opcode }, |
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210 | { Bad_Opcode }, |
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211 | { Bad_Opcode }, |
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212 | { Bad_Opcode }, |
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213 | /* B8 */ |
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214 | { Bad_Opcode }, |
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215 | { Bad_Opcode }, |
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216 | { Bad_Opcode }, |
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217 | { Bad_Opcode }, |
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218 | { Bad_Opcode }, |
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219 | { Bad_Opcode }, |
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220 | { Bad_Opcode }, |
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221 | { Bad_Opcode }, |
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222 | /* C0 */ |
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223 | { Bad_Opcode }, |
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224 | { Bad_Opcode }, |
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225 | { PREFIX_TABLE (PREFIX_EVEX_0FC2) }, |
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226 | { Bad_Opcode }, |
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6324 | serge | 227 | { PREFIX_TABLE (PREFIX_EVEX_0FC4) }, |
228 | { PREFIX_TABLE (PREFIX_EVEX_0FC5) }, |
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5221 | serge | 229 | { PREFIX_TABLE (PREFIX_EVEX_0FC6) }, |
230 | { Bad_Opcode }, |
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231 | /* C8 */ |
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232 | { Bad_Opcode }, |
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233 | { Bad_Opcode }, |
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234 | { Bad_Opcode }, |
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235 | { Bad_Opcode }, |
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236 | { Bad_Opcode }, |
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237 | { Bad_Opcode }, |
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238 | { Bad_Opcode }, |
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239 | { Bad_Opcode }, |
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240 | /* D0 */ |
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241 | { Bad_Opcode }, |
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6324 | serge | 242 | { PREFIX_TABLE (PREFIX_EVEX_0FD1) }, |
5221 | serge | 243 | { PREFIX_TABLE (PREFIX_EVEX_0FD2) }, |
244 | { PREFIX_TABLE (PREFIX_EVEX_0FD3) }, |
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245 | { PREFIX_TABLE (PREFIX_EVEX_0FD4) }, |
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6324 | serge | 246 | { PREFIX_TABLE (PREFIX_EVEX_0FD5) }, |
5221 | serge | 247 | { PREFIX_TABLE (PREFIX_EVEX_0FD6) }, |
248 | { Bad_Opcode }, |
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249 | /* D8 */ |
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6324 | serge | 250 | { PREFIX_TABLE (PREFIX_EVEX_0FD8) }, |
251 | { PREFIX_TABLE (PREFIX_EVEX_0FD9) }, |
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252 | { PREFIX_TABLE (PREFIX_EVEX_0FDA) }, |
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5221 | serge | 253 | { PREFIX_TABLE (PREFIX_EVEX_0FDB) }, |
6324 | serge | 254 | { PREFIX_TABLE (PREFIX_EVEX_0FDC) }, |
255 | { PREFIX_TABLE (PREFIX_EVEX_0FDD) }, |
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256 | { PREFIX_TABLE (PREFIX_EVEX_0FDE) }, |
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5221 | serge | 257 | { PREFIX_TABLE (PREFIX_EVEX_0FDF) }, |
258 | /* E0 */ |
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6324 | serge | 259 | { PREFIX_TABLE (PREFIX_EVEX_0FE0) }, |
260 | { PREFIX_TABLE (PREFIX_EVEX_0FE1) }, |
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5221 | serge | 261 | { PREFIX_TABLE (PREFIX_EVEX_0FE2) }, |
6324 | serge | 262 | { PREFIX_TABLE (PREFIX_EVEX_0FE3) }, |
263 | { PREFIX_TABLE (PREFIX_EVEX_0FE4) }, |
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264 | { PREFIX_TABLE (PREFIX_EVEX_0FE5) }, |
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5221 | serge | 265 | { PREFIX_TABLE (PREFIX_EVEX_0FE6) }, |
266 | { PREFIX_TABLE (PREFIX_EVEX_0FE7) }, |
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267 | /* E8 */ |
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6324 | serge | 268 | { PREFIX_TABLE (PREFIX_EVEX_0FE8) }, |
269 | { PREFIX_TABLE (PREFIX_EVEX_0FE9) }, |
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270 | { PREFIX_TABLE (PREFIX_EVEX_0FEA) }, |
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5221 | serge | 271 | { PREFIX_TABLE (PREFIX_EVEX_0FEB) }, |
6324 | serge | 272 | { PREFIX_TABLE (PREFIX_EVEX_0FEC) }, |
273 | { PREFIX_TABLE (PREFIX_EVEX_0FED) }, |
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274 | { PREFIX_TABLE (PREFIX_EVEX_0FEE) }, |
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5221 | serge | 275 | { PREFIX_TABLE (PREFIX_EVEX_0FEF) }, |
276 | /* F0 */ |
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277 | { Bad_Opcode }, |
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6324 | serge | 278 | { PREFIX_TABLE (PREFIX_EVEX_0FF1) }, |
5221 | serge | 279 | { PREFIX_TABLE (PREFIX_EVEX_0FF2) }, |
280 | { PREFIX_TABLE (PREFIX_EVEX_0FF3) }, |
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281 | { PREFIX_TABLE (PREFIX_EVEX_0FF4) }, |
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6324 | serge | 282 | { PREFIX_TABLE (PREFIX_EVEX_0FF5) }, |
283 | { PREFIX_TABLE (PREFIX_EVEX_0FF6) }, |
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5221 | serge | 284 | { Bad_Opcode }, |
285 | /* F8 */ |
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6324 | serge | 286 | { PREFIX_TABLE (PREFIX_EVEX_0FF8) }, |
287 | { PREFIX_TABLE (PREFIX_EVEX_0FF9) }, |
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5221 | serge | 288 | { PREFIX_TABLE (PREFIX_EVEX_0FFA) }, |
289 | { PREFIX_TABLE (PREFIX_EVEX_0FFB) }, |
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6324 | serge | 290 | { PREFIX_TABLE (PREFIX_EVEX_0FFC) }, |
291 | { PREFIX_TABLE (PREFIX_EVEX_0FFD) }, |
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5221 | serge | 292 | { PREFIX_TABLE (PREFIX_EVEX_0FFE) }, |
293 | { Bad_Opcode }, |
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294 | }, |
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295 | /* EVEX_0F38 */ |
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296 | { |
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297 | /* 00 */ |
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6324 | serge | 298 | { PREFIX_TABLE (PREFIX_EVEX_0F3800) }, |
5221 | serge | 299 | { Bad_Opcode }, |
300 | { Bad_Opcode }, |
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301 | { Bad_Opcode }, |
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6324 | serge | 302 | { PREFIX_TABLE (PREFIX_EVEX_0F3804) }, |
5221 | serge | 303 | { Bad_Opcode }, |
304 | { Bad_Opcode }, |
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305 | { Bad_Opcode }, |
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306 | /* 08 */ |
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307 | { Bad_Opcode }, |
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308 | { Bad_Opcode }, |
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309 | { Bad_Opcode }, |
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6324 | serge | 310 | { PREFIX_TABLE (PREFIX_EVEX_0F380B) }, |
5221 | serge | 311 | { PREFIX_TABLE (PREFIX_EVEX_0F380C) }, |
312 | { PREFIX_TABLE (PREFIX_EVEX_0F380D) }, |
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313 | { Bad_Opcode }, |
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314 | { Bad_Opcode }, |
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315 | /* 10 */ |
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6324 | serge | 316 | { PREFIX_TABLE (PREFIX_EVEX_0F3810) }, |
5221 | serge | 317 | { PREFIX_TABLE (PREFIX_EVEX_0F3811) }, |
318 | { PREFIX_TABLE (PREFIX_EVEX_0F3812) }, |
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319 | { PREFIX_TABLE (PREFIX_EVEX_0F3813) }, |
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320 | { PREFIX_TABLE (PREFIX_EVEX_0F3814) }, |
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321 | { PREFIX_TABLE (PREFIX_EVEX_0F3815) }, |
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322 | { PREFIX_TABLE (PREFIX_EVEX_0F3816) }, |
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323 | { Bad_Opcode }, |
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324 | /* 18 */ |
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325 | { PREFIX_TABLE (PREFIX_EVEX_0F3818) }, |
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326 | { PREFIX_TABLE (PREFIX_EVEX_0F3819) }, |
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327 | { PREFIX_TABLE (PREFIX_EVEX_0F381A) }, |
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328 | { PREFIX_TABLE (PREFIX_EVEX_0F381B) }, |
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6324 | serge | 329 | { PREFIX_TABLE (PREFIX_EVEX_0F381C) }, |
330 | { PREFIX_TABLE (PREFIX_EVEX_0F381D) }, |
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5221 | serge | 331 | { PREFIX_TABLE (PREFIX_EVEX_0F381E) }, |
332 | { PREFIX_TABLE (PREFIX_EVEX_0F381F) }, |
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333 | /* 20 */ |
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6324 | serge | 334 | { PREFIX_TABLE (PREFIX_EVEX_0F3820) }, |
5221 | serge | 335 | { PREFIX_TABLE (PREFIX_EVEX_0F3821) }, |
336 | { PREFIX_TABLE (PREFIX_EVEX_0F3822) }, |
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337 | { PREFIX_TABLE (PREFIX_EVEX_0F3823) }, |
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338 | { PREFIX_TABLE (PREFIX_EVEX_0F3824) }, |
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339 | { PREFIX_TABLE (PREFIX_EVEX_0F3825) }, |
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6324 | serge | 340 | { PREFIX_TABLE (PREFIX_EVEX_0F3826) }, |
5221 | serge | 341 | { PREFIX_TABLE (PREFIX_EVEX_0F3827) }, |
342 | /* 28 */ |
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343 | { PREFIX_TABLE (PREFIX_EVEX_0F3828) }, |
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344 | { PREFIX_TABLE (PREFIX_EVEX_0F3829) }, |
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345 | { PREFIX_TABLE (PREFIX_EVEX_0F382A) }, |
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6324 | serge | 346 | { PREFIX_TABLE (PREFIX_EVEX_0F382B) }, |
5221 | serge | 347 | { PREFIX_TABLE (PREFIX_EVEX_0F382C) }, |
348 | { PREFIX_TABLE (PREFIX_EVEX_0F382D) }, |
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349 | { Bad_Opcode }, |
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350 | { Bad_Opcode }, |
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351 | /* 30 */ |
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6324 | serge | 352 | { PREFIX_TABLE (PREFIX_EVEX_0F3830) }, |
5221 | serge | 353 | { PREFIX_TABLE (PREFIX_EVEX_0F3831) }, |
354 | { PREFIX_TABLE (PREFIX_EVEX_0F3832) }, |
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355 | { PREFIX_TABLE (PREFIX_EVEX_0F3833) }, |
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356 | { PREFIX_TABLE (PREFIX_EVEX_0F3834) }, |
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357 | { PREFIX_TABLE (PREFIX_EVEX_0F3835) }, |
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358 | { PREFIX_TABLE (PREFIX_EVEX_0F3836) }, |
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359 | { PREFIX_TABLE (PREFIX_EVEX_0F3837) }, |
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360 | /* 38 */ |
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6324 | serge | 361 | { PREFIX_TABLE (PREFIX_EVEX_0F3838) }, |
5221 | serge | 362 | { PREFIX_TABLE (PREFIX_EVEX_0F3839) }, |
363 | { PREFIX_TABLE (PREFIX_EVEX_0F383A) }, |
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364 | { PREFIX_TABLE (PREFIX_EVEX_0F383B) }, |
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6324 | serge | 365 | { PREFIX_TABLE (PREFIX_EVEX_0F383C) }, |
5221 | serge | 366 | { PREFIX_TABLE (PREFIX_EVEX_0F383D) }, |
6324 | serge | 367 | { PREFIX_TABLE (PREFIX_EVEX_0F383E) }, |
5221 | serge | 368 | { PREFIX_TABLE (PREFIX_EVEX_0F383F) }, |
369 | /* 40 */ |
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370 | { PREFIX_TABLE (PREFIX_EVEX_0F3840) }, |
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371 | { Bad_Opcode }, |
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372 | { PREFIX_TABLE (PREFIX_EVEX_0F3842) }, |
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373 | { PREFIX_TABLE (PREFIX_EVEX_0F3843) }, |
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374 | { PREFIX_TABLE (PREFIX_EVEX_0F3844) }, |
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375 | { PREFIX_TABLE (PREFIX_EVEX_0F3845) }, |
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376 | { PREFIX_TABLE (PREFIX_EVEX_0F3846) }, |
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377 | { PREFIX_TABLE (PREFIX_EVEX_0F3847) }, |
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378 | /* 48 */ |
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379 | { Bad_Opcode }, |
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380 | { Bad_Opcode }, |
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381 | { Bad_Opcode }, |
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382 | { Bad_Opcode }, |
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383 | { PREFIX_TABLE (PREFIX_EVEX_0F384C) }, |
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384 | { PREFIX_TABLE (PREFIX_EVEX_0F384D) }, |
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385 | { PREFIX_TABLE (PREFIX_EVEX_0F384E) }, |
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386 | { PREFIX_TABLE (PREFIX_EVEX_0F384F) }, |
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387 | /* 50 */ |
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388 | { Bad_Opcode }, |
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389 | { Bad_Opcode }, |
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390 | { Bad_Opcode }, |
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391 | { Bad_Opcode }, |
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392 | { Bad_Opcode }, |
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393 | { Bad_Opcode }, |
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394 | { Bad_Opcode }, |
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395 | { Bad_Opcode }, |
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396 | /* 58 */ |
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397 | { PREFIX_TABLE (PREFIX_EVEX_0F3858) }, |
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398 | { PREFIX_TABLE (PREFIX_EVEX_0F3859) }, |
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399 | { PREFIX_TABLE (PREFIX_EVEX_0F385A) }, |
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400 | { PREFIX_TABLE (PREFIX_EVEX_0F385B) }, |
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401 | { Bad_Opcode }, |
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402 | { Bad_Opcode }, |
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403 | { Bad_Opcode }, |
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404 | { Bad_Opcode }, |
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405 | /* 60 */ |
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406 | { Bad_Opcode }, |
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407 | { Bad_Opcode }, |
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408 | { Bad_Opcode }, |
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409 | { Bad_Opcode }, |
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410 | { PREFIX_TABLE (PREFIX_EVEX_0F3864) }, |
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411 | { PREFIX_TABLE (PREFIX_EVEX_0F3865) }, |
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6324 | serge | 412 | { PREFIX_TABLE (PREFIX_EVEX_0F3866) }, |
5221 | serge | 413 | { Bad_Opcode }, |
414 | /* 68 */ |
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415 | { Bad_Opcode }, |
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416 | { Bad_Opcode }, |
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417 | { Bad_Opcode }, |
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418 | { Bad_Opcode }, |
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419 | { Bad_Opcode }, |
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420 | { Bad_Opcode }, |
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421 | { Bad_Opcode }, |
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422 | { Bad_Opcode }, |
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423 | /* 70 */ |
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424 | { Bad_Opcode }, |
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425 | { Bad_Opcode }, |
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426 | { Bad_Opcode }, |
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427 | { Bad_Opcode }, |
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428 | { Bad_Opcode }, |
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6324 | serge | 429 | { PREFIX_TABLE (PREFIX_EVEX_0F3875) }, |
5221 | serge | 430 | { PREFIX_TABLE (PREFIX_EVEX_0F3876) }, |
431 | { PREFIX_TABLE (PREFIX_EVEX_0F3877) }, |
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432 | /* 78 */ |
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6324 | serge | 433 | { PREFIX_TABLE (PREFIX_EVEX_0F3878) }, |
434 | { PREFIX_TABLE (PREFIX_EVEX_0F3879) }, |
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435 | { PREFIX_TABLE (PREFIX_EVEX_0F387A) }, |
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436 | { PREFIX_TABLE (PREFIX_EVEX_0F387B) }, |
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5221 | serge | 437 | { PREFIX_TABLE (PREFIX_EVEX_0F387C) }, |
6324 | serge | 438 | { PREFIX_TABLE (PREFIX_EVEX_0F387D) }, |
5221 | serge | 439 | { PREFIX_TABLE (PREFIX_EVEX_0F387E) }, |
440 | { PREFIX_TABLE (PREFIX_EVEX_0F387F) }, |
||
441 | /* 80 */ |
||
442 | { Bad_Opcode }, |
||
443 | { Bad_Opcode }, |
||
444 | { Bad_Opcode }, |
||
6324 | serge | 445 | { PREFIX_TABLE (PREFIX_EVEX_0F3883) }, |
5221 | serge | 446 | { Bad_Opcode }, |
447 | { Bad_Opcode }, |
||
448 | { Bad_Opcode }, |
||
449 | { Bad_Opcode }, |
||
450 | /* 88 */ |
||
451 | { PREFIX_TABLE (PREFIX_EVEX_0F3888) }, |
||
452 | { PREFIX_TABLE (PREFIX_EVEX_0F3889) }, |
||
453 | { PREFIX_TABLE (PREFIX_EVEX_0F388A) }, |
||
454 | { PREFIX_TABLE (PREFIX_EVEX_0F388B) }, |
||
455 | { Bad_Opcode }, |
||
6324 | serge | 456 | { PREFIX_TABLE (PREFIX_EVEX_0F388D) }, |
5221 | serge | 457 | { Bad_Opcode }, |
458 | { Bad_Opcode }, |
||
459 | /* 90 */ |
||
460 | { PREFIX_TABLE (PREFIX_EVEX_0F3890) }, |
||
461 | { PREFIX_TABLE (PREFIX_EVEX_0F3891) }, |
||
462 | { PREFIX_TABLE (PREFIX_EVEX_0F3892) }, |
||
463 | { PREFIX_TABLE (PREFIX_EVEX_0F3893) }, |
||
464 | { Bad_Opcode }, |
||
465 | { Bad_Opcode }, |
||
466 | { PREFIX_TABLE (PREFIX_EVEX_0F3896) }, |
||
467 | { PREFIX_TABLE (PREFIX_EVEX_0F3897) }, |
||
468 | /* 98 */ |
||
469 | { PREFIX_TABLE (PREFIX_EVEX_0F3898) }, |
||
470 | { PREFIX_TABLE (PREFIX_EVEX_0F3899) }, |
||
471 | { PREFIX_TABLE (PREFIX_EVEX_0F389A) }, |
||
472 | { PREFIX_TABLE (PREFIX_EVEX_0F389B) }, |
||
473 | { PREFIX_TABLE (PREFIX_EVEX_0F389C) }, |
||
474 | { PREFIX_TABLE (PREFIX_EVEX_0F389D) }, |
||
475 | { PREFIX_TABLE (PREFIX_EVEX_0F389E) }, |
||
476 | { PREFIX_TABLE (PREFIX_EVEX_0F389F) }, |
||
477 | /* A0 */ |
||
478 | { PREFIX_TABLE (PREFIX_EVEX_0F38A0) }, |
||
479 | { PREFIX_TABLE (PREFIX_EVEX_0F38A1) }, |
||
480 | { PREFIX_TABLE (PREFIX_EVEX_0F38A2) }, |
||
481 | { PREFIX_TABLE (PREFIX_EVEX_0F38A3) }, |
||
482 | { Bad_Opcode }, |
||
483 | { Bad_Opcode }, |
||
484 | { PREFIX_TABLE (PREFIX_EVEX_0F38A6) }, |
||
485 | { PREFIX_TABLE (PREFIX_EVEX_0F38A7) }, |
||
486 | /* A8 */ |
||
487 | { PREFIX_TABLE (PREFIX_EVEX_0F38A8) }, |
||
488 | { PREFIX_TABLE (PREFIX_EVEX_0F38A9) }, |
||
489 | { PREFIX_TABLE (PREFIX_EVEX_0F38AA) }, |
||
490 | { PREFIX_TABLE (PREFIX_EVEX_0F38AB) }, |
||
491 | { PREFIX_TABLE (PREFIX_EVEX_0F38AC) }, |
||
492 | { PREFIX_TABLE (PREFIX_EVEX_0F38AD) }, |
||
493 | { PREFIX_TABLE (PREFIX_EVEX_0F38AE) }, |
||
494 | { PREFIX_TABLE (PREFIX_EVEX_0F38AF) }, |
||
495 | /* B0 */ |
||
496 | { Bad_Opcode }, |
||
497 | { Bad_Opcode }, |
||
498 | { Bad_Opcode }, |
||
499 | { Bad_Opcode }, |
||
6324 | serge | 500 | { PREFIX_TABLE (PREFIX_EVEX_0F38B4) }, |
501 | { PREFIX_TABLE (PREFIX_EVEX_0F38B5) }, |
||
5221 | serge | 502 | { PREFIX_TABLE (PREFIX_EVEX_0F38B6) }, |
503 | { PREFIX_TABLE (PREFIX_EVEX_0F38B7) }, |
||
504 | /* B8 */ |
||
505 | { PREFIX_TABLE (PREFIX_EVEX_0F38B8) }, |
||
506 | { PREFIX_TABLE (PREFIX_EVEX_0F38B9) }, |
||
507 | { PREFIX_TABLE (PREFIX_EVEX_0F38BA) }, |
||
508 | { PREFIX_TABLE (PREFIX_EVEX_0F38BB) }, |
||
509 | { PREFIX_TABLE (PREFIX_EVEX_0F38BC) }, |
||
510 | { PREFIX_TABLE (PREFIX_EVEX_0F38BD) }, |
||
511 | { PREFIX_TABLE (PREFIX_EVEX_0F38BE) }, |
||
512 | { PREFIX_TABLE (PREFIX_EVEX_0F38BF) }, |
||
513 | /* C0 */ |
||
514 | { Bad_Opcode }, |
||
515 | { Bad_Opcode }, |
||
516 | { Bad_Opcode }, |
||
517 | { Bad_Opcode }, |
||
518 | { PREFIX_TABLE (PREFIX_EVEX_0F38C4) }, |
||
519 | { Bad_Opcode }, |
||
520 | { REG_TABLE (REG_EVEX_0F38C6) }, |
||
521 | { REG_TABLE (REG_EVEX_0F38C7) }, |
||
522 | /* C8 */ |
||
523 | { PREFIX_TABLE (PREFIX_EVEX_0F38C8) }, |
||
524 | { Bad_Opcode }, |
||
525 | { PREFIX_TABLE (PREFIX_EVEX_0F38CA) }, |
||
526 | { PREFIX_TABLE (PREFIX_EVEX_0F38CB) }, |
||
527 | { PREFIX_TABLE (PREFIX_EVEX_0F38CC) }, |
||
528 | { PREFIX_TABLE (PREFIX_EVEX_0F38CD) }, |
||
529 | { Bad_Opcode }, |
||
530 | { Bad_Opcode }, |
||
531 | /* D0 */ |
||
532 | { Bad_Opcode }, |
||
533 | { Bad_Opcode }, |
||
534 | { Bad_Opcode }, |
||
535 | { Bad_Opcode }, |
||
536 | { Bad_Opcode }, |
||
537 | { Bad_Opcode }, |
||
538 | { Bad_Opcode }, |
||
539 | { Bad_Opcode }, |
||
540 | /* D8 */ |
||
541 | { Bad_Opcode }, |
||
542 | { Bad_Opcode }, |
||
543 | { Bad_Opcode }, |
||
544 | { Bad_Opcode }, |
||
545 | { Bad_Opcode }, |
||
546 | { Bad_Opcode }, |
||
547 | { Bad_Opcode }, |
||
548 | { Bad_Opcode }, |
||
549 | /* E0 */ |
||
550 | { Bad_Opcode }, |
||
551 | { Bad_Opcode }, |
||
552 | { Bad_Opcode }, |
||
553 | { Bad_Opcode }, |
||
554 | { Bad_Opcode }, |
||
555 | { Bad_Opcode }, |
||
556 | { Bad_Opcode }, |
||
557 | { Bad_Opcode }, |
||
558 | /* E8 */ |
||
559 | { Bad_Opcode }, |
||
560 | { Bad_Opcode }, |
||
561 | { Bad_Opcode }, |
||
562 | { Bad_Opcode }, |
||
563 | { Bad_Opcode }, |
||
564 | { Bad_Opcode }, |
||
565 | { Bad_Opcode }, |
||
566 | { Bad_Opcode }, |
||
567 | /* F0 */ |
||
568 | { Bad_Opcode }, |
||
569 | { Bad_Opcode }, |
||
570 | { Bad_Opcode }, |
||
571 | { Bad_Opcode }, |
||
572 | { Bad_Opcode }, |
||
573 | { Bad_Opcode }, |
||
574 | { Bad_Opcode }, |
||
575 | { Bad_Opcode }, |
||
576 | /* F8 */ |
||
577 | { Bad_Opcode }, |
||
578 | { Bad_Opcode }, |
||
579 | { Bad_Opcode }, |
||
580 | { Bad_Opcode }, |
||
581 | { Bad_Opcode }, |
||
582 | { Bad_Opcode }, |
||
583 | { Bad_Opcode }, |
||
584 | { Bad_Opcode }, |
||
585 | }, |
||
586 | /* EVEX_0F3A */ |
||
587 | { |
||
588 | /* 00 */ |
||
589 | { PREFIX_TABLE (PREFIX_EVEX_0F3A00) }, |
||
590 | { PREFIX_TABLE (PREFIX_EVEX_0F3A01) }, |
||
591 | { Bad_Opcode }, |
||
592 | { PREFIX_TABLE (PREFIX_EVEX_0F3A03) }, |
||
593 | { PREFIX_TABLE (PREFIX_EVEX_0F3A04) }, |
||
594 | { PREFIX_TABLE (PREFIX_EVEX_0F3A05) }, |
||
595 | { Bad_Opcode }, |
||
596 | { Bad_Opcode }, |
||
597 | /* 08 */ |
||
598 | { PREFIX_TABLE (PREFIX_EVEX_0F3A08) }, |
||
599 | { PREFIX_TABLE (PREFIX_EVEX_0F3A09) }, |
||
600 | { PREFIX_TABLE (PREFIX_EVEX_0F3A0A) }, |
||
601 | { PREFIX_TABLE (PREFIX_EVEX_0F3A0B) }, |
||
602 | { Bad_Opcode }, |
||
603 | { Bad_Opcode }, |
||
604 | { Bad_Opcode }, |
||
6324 | serge | 605 | { PREFIX_TABLE (PREFIX_EVEX_0F3A0F) }, |
5221 | serge | 606 | /* 10 */ |
607 | { Bad_Opcode }, |
||
608 | { Bad_Opcode }, |
||
609 | { Bad_Opcode }, |
||
610 | { Bad_Opcode }, |
||
6324 | serge | 611 | { PREFIX_TABLE (PREFIX_EVEX_0F3A14) }, |
612 | { PREFIX_TABLE (PREFIX_EVEX_0F3A15) }, |
||
613 | { PREFIX_TABLE (PREFIX_EVEX_0F3A16) }, |
||
5221 | serge | 614 | { PREFIX_TABLE (PREFIX_EVEX_0F3A17) }, |
615 | /* 18 */ |
||
616 | { PREFIX_TABLE (PREFIX_EVEX_0F3A18) }, |
||
617 | { PREFIX_TABLE (PREFIX_EVEX_0F3A19) }, |
||
618 | { PREFIX_TABLE (PREFIX_EVEX_0F3A1A) }, |
||
619 | { PREFIX_TABLE (PREFIX_EVEX_0F3A1B) }, |
||
620 | { Bad_Opcode }, |
||
621 | { PREFIX_TABLE (PREFIX_EVEX_0F3A1D) }, |
||
622 | { PREFIX_TABLE (PREFIX_EVEX_0F3A1E) }, |
||
623 | { PREFIX_TABLE (PREFIX_EVEX_0F3A1F) }, |
||
624 | /* 20 */ |
||
6324 | serge | 625 | { PREFIX_TABLE (PREFIX_EVEX_0F3A20) }, |
5221 | serge | 626 | { PREFIX_TABLE (PREFIX_EVEX_0F3A21) }, |
6324 | serge | 627 | { PREFIX_TABLE (PREFIX_EVEX_0F3A22) }, |
5221 | serge | 628 | { PREFIX_TABLE (PREFIX_EVEX_0F3A23) }, |
629 | { Bad_Opcode }, |
||
630 | { PREFIX_TABLE (PREFIX_EVEX_0F3A25) }, |
||
631 | { PREFIX_TABLE (PREFIX_EVEX_0F3A26) }, |
||
632 | { PREFIX_TABLE (PREFIX_EVEX_0F3A27) }, |
||
633 | /* 28 */ |
||
634 | { Bad_Opcode }, |
||
635 | { Bad_Opcode }, |
||
636 | { Bad_Opcode }, |
||
637 | { Bad_Opcode }, |
||
638 | { Bad_Opcode }, |
||
639 | { Bad_Opcode }, |
||
640 | { Bad_Opcode }, |
||
641 | { Bad_Opcode }, |
||
642 | /* 30 */ |
||
643 | { Bad_Opcode }, |
||
644 | { Bad_Opcode }, |
||
645 | { Bad_Opcode }, |
||
646 | { Bad_Opcode }, |
||
647 | { Bad_Opcode }, |
||
648 | { Bad_Opcode }, |
||
649 | { Bad_Opcode }, |
||
650 | { Bad_Opcode }, |
||
651 | /* 38 */ |
||
652 | { PREFIX_TABLE (PREFIX_EVEX_0F3A38) }, |
||
653 | { PREFIX_TABLE (PREFIX_EVEX_0F3A39) }, |
||
654 | { PREFIX_TABLE (PREFIX_EVEX_0F3A3A) }, |
||
655 | { PREFIX_TABLE (PREFIX_EVEX_0F3A3B) }, |
||
656 | { Bad_Opcode }, |
||
657 | { Bad_Opcode }, |
||
6324 | serge | 658 | { PREFIX_TABLE (PREFIX_EVEX_0F3A3E) }, |
659 | { PREFIX_TABLE (PREFIX_EVEX_0F3A3F) }, |
||
5221 | serge | 660 | /* 40 */ |
661 | { Bad_Opcode }, |
||
662 | { Bad_Opcode }, |
||
6324 | serge | 663 | { PREFIX_TABLE (PREFIX_EVEX_0F3A42) }, |
5221 | serge | 664 | { PREFIX_TABLE (PREFIX_EVEX_0F3A43) }, |
665 | { Bad_Opcode }, |
||
666 | { Bad_Opcode }, |
||
667 | { Bad_Opcode }, |
||
668 | { Bad_Opcode }, |
||
669 | /* 48 */ |
||
670 | { Bad_Opcode }, |
||
671 | { Bad_Opcode }, |
||
672 | { Bad_Opcode }, |
||
673 | { Bad_Opcode }, |
||
674 | { Bad_Opcode }, |
||
675 | { Bad_Opcode }, |
||
676 | { Bad_Opcode }, |
||
677 | { Bad_Opcode }, |
||
678 | /* 50 */ |
||
6324 | serge | 679 | { PREFIX_TABLE (PREFIX_EVEX_0F3A50) }, |
680 | { PREFIX_TABLE (PREFIX_EVEX_0F3A51) }, |
||
5221 | serge | 681 | { Bad_Opcode }, |
682 | { Bad_Opcode }, |
||
683 | { PREFIX_TABLE (PREFIX_EVEX_0F3A54) }, |
||
684 | { PREFIX_TABLE (PREFIX_EVEX_0F3A55) }, |
||
6324 | serge | 685 | { PREFIX_TABLE (PREFIX_EVEX_0F3A56) }, |
686 | { PREFIX_TABLE (PREFIX_EVEX_0F3A57) }, |
||
5221 | serge | 687 | /* 58 */ |
688 | { Bad_Opcode }, |
||
689 | { Bad_Opcode }, |
||
690 | { Bad_Opcode }, |
||
691 | { Bad_Opcode }, |
||
692 | { Bad_Opcode }, |
||
693 | { Bad_Opcode }, |
||
694 | { Bad_Opcode }, |
||
695 | { Bad_Opcode }, |
||
696 | /* 60 */ |
||
697 | { Bad_Opcode }, |
||
698 | { Bad_Opcode }, |
||
699 | { Bad_Opcode }, |
||
700 | { Bad_Opcode }, |
||
701 | { Bad_Opcode }, |
||
702 | { Bad_Opcode }, |
||
6324 | serge | 703 | { PREFIX_TABLE (PREFIX_EVEX_0F3A66) }, |
704 | { PREFIX_TABLE (PREFIX_EVEX_0F3A67) }, |
||
5221 | serge | 705 | /* 68 */ |
706 | { Bad_Opcode }, |
||
707 | { Bad_Opcode }, |
||
708 | { Bad_Opcode }, |
||
709 | { Bad_Opcode }, |
||
710 | { Bad_Opcode }, |
||
711 | { Bad_Opcode }, |
||
712 | { Bad_Opcode }, |
||
713 | { Bad_Opcode }, |
||
714 | /* 70 */ |
||
715 | { Bad_Opcode }, |
||
716 | { Bad_Opcode }, |
||
717 | { Bad_Opcode }, |
||
718 | { Bad_Opcode }, |
||
719 | { Bad_Opcode }, |
||
720 | { Bad_Opcode }, |
||
721 | { Bad_Opcode }, |
||
722 | { Bad_Opcode }, |
||
723 | /* 78 */ |
||
724 | { Bad_Opcode }, |
||
725 | { Bad_Opcode }, |
||
726 | { Bad_Opcode }, |
||
727 | { Bad_Opcode }, |
||
728 | { Bad_Opcode }, |
||
729 | { Bad_Opcode }, |
||
730 | { Bad_Opcode }, |
||
731 | { Bad_Opcode }, |
||
732 | /* 80 */ |
||
733 | { Bad_Opcode }, |
||
734 | { Bad_Opcode }, |
||
735 | { Bad_Opcode }, |
||
736 | { Bad_Opcode }, |
||
737 | { Bad_Opcode }, |
||
738 | { Bad_Opcode }, |
||
739 | { Bad_Opcode }, |
||
740 | { Bad_Opcode }, |
||
741 | /* 88 */ |
||
742 | { Bad_Opcode }, |
||
743 | { Bad_Opcode }, |
||
744 | { Bad_Opcode }, |
||
745 | { Bad_Opcode }, |
||
746 | { Bad_Opcode }, |
||
747 | { Bad_Opcode }, |
||
748 | { Bad_Opcode }, |
||
749 | { Bad_Opcode }, |
||
750 | /* 90 */ |
||
751 | { Bad_Opcode }, |
||
752 | { Bad_Opcode }, |
||
753 | { Bad_Opcode }, |
||
754 | { Bad_Opcode }, |
||
755 | { Bad_Opcode }, |
||
756 | { Bad_Opcode }, |
||
757 | { Bad_Opcode }, |
||
758 | { Bad_Opcode }, |
||
759 | /* 98 */ |
||
760 | { Bad_Opcode }, |
||
761 | { Bad_Opcode }, |
||
762 | { Bad_Opcode }, |
||
763 | { Bad_Opcode }, |
||
764 | { Bad_Opcode }, |
||
765 | { Bad_Opcode }, |
||
766 | { Bad_Opcode }, |
||
767 | { Bad_Opcode }, |
||
768 | /* A0 */ |
||
769 | { Bad_Opcode }, |
||
770 | { Bad_Opcode }, |
||
771 | { Bad_Opcode }, |
||
772 | { Bad_Opcode }, |
||
773 | { Bad_Opcode }, |
||
774 | { Bad_Opcode }, |
||
775 | { Bad_Opcode }, |
||
776 | { Bad_Opcode }, |
||
777 | /* A8 */ |
||
778 | { Bad_Opcode }, |
||
779 | { Bad_Opcode }, |
||
780 | { Bad_Opcode }, |
||
781 | { Bad_Opcode }, |
||
782 | { Bad_Opcode }, |
||
783 | { Bad_Opcode }, |
||
784 | { Bad_Opcode }, |
||
785 | { Bad_Opcode }, |
||
786 | /* B0 */ |
||
787 | { Bad_Opcode }, |
||
788 | { Bad_Opcode }, |
||
789 | { Bad_Opcode }, |
||
790 | { Bad_Opcode }, |
||
791 | { Bad_Opcode }, |
||
792 | { Bad_Opcode }, |
||
793 | { Bad_Opcode }, |
||
794 | { Bad_Opcode }, |
||
795 | /* B8 */ |
||
796 | { Bad_Opcode }, |
||
797 | { Bad_Opcode }, |
||
798 | { Bad_Opcode }, |
||
799 | { Bad_Opcode }, |
||
800 | { Bad_Opcode }, |
||
801 | { Bad_Opcode }, |
||
802 | { Bad_Opcode }, |
||
803 | { Bad_Opcode }, |
||
804 | /* C0 */ |
||
805 | { Bad_Opcode }, |
||
806 | { Bad_Opcode }, |
||
807 | { Bad_Opcode }, |
||
808 | { Bad_Opcode }, |
||
809 | { Bad_Opcode }, |
||
810 | { Bad_Opcode }, |
||
811 | { Bad_Opcode }, |
||
812 | { Bad_Opcode }, |
||
813 | /* C8 */ |
||
814 | { Bad_Opcode }, |
||
815 | { Bad_Opcode }, |
||
816 | { Bad_Opcode }, |
||
817 | { Bad_Opcode }, |
||
818 | { Bad_Opcode }, |
||
819 | { Bad_Opcode }, |
||
820 | { Bad_Opcode }, |
||
821 | { Bad_Opcode }, |
||
822 | /* D0 */ |
||
823 | { Bad_Opcode }, |
||
824 | { Bad_Opcode }, |
||
825 | { Bad_Opcode }, |
||
826 | { Bad_Opcode }, |
||
827 | { Bad_Opcode }, |
||
828 | { Bad_Opcode }, |
||
829 | { Bad_Opcode }, |
||
830 | { Bad_Opcode }, |
||
831 | /* D8 */ |
||
832 | { Bad_Opcode }, |
||
833 | { Bad_Opcode }, |
||
834 | { Bad_Opcode }, |
||
835 | { Bad_Opcode }, |
||
836 | { Bad_Opcode }, |
||
837 | { Bad_Opcode }, |
||
838 | { Bad_Opcode }, |
||
839 | { Bad_Opcode }, |
||
840 | /* E0 */ |
||
841 | { Bad_Opcode }, |
||
842 | { Bad_Opcode }, |
||
843 | { Bad_Opcode }, |
||
844 | { Bad_Opcode }, |
||
845 | { Bad_Opcode }, |
||
846 | { Bad_Opcode }, |
||
847 | { Bad_Opcode }, |
||
848 | { Bad_Opcode }, |
||
849 | /* E8 */ |
||
850 | { Bad_Opcode }, |
||
851 | { Bad_Opcode }, |
||
852 | { Bad_Opcode }, |
||
853 | { Bad_Opcode }, |
||
854 | { Bad_Opcode }, |
||
855 | { Bad_Opcode }, |
||
856 | { Bad_Opcode }, |
||
857 | { Bad_Opcode }, |
||
858 | /* F0 */ |
||
859 | { Bad_Opcode }, |
||
860 | { Bad_Opcode }, |
||
861 | { Bad_Opcode }, |
||
862 | { Bad_Opcode }, |
||
863 | { Bad_Opcode }, |
||
864 | { Bad_Opcode }, |
||
865 | { Bad_Opcode }, |
||
866 | { Bad_Opcode }, |
||
867 | /* F8 */ |
||
868 | { Bad_Opcode }, |
||
869 | { Bad_Opcode }, |
||
870 | { Bad_Opcode }, |
||
871 | { Bad_Opcode }, |
||
872 | { Bad_Opcode }, |
||
873 | { Bad_Opcode }, |
||
874 | { Bad_Opcode }, |
||
875 | { Bad_Opcode }, |
||
876 | }, |
||
877 | }; |
||
878 | #endif /* NEED_OPCODE_TABLE */ |
||
879 | |||
880 | #ifdef NEED_REG_TABLE |
||
6324 | serge | 881 | /* REG_EVEX_0F71 */ |
882 | { |
||
883 | { Bad_Opcode }, |
||
884 | { Bad_Opcode }, |
||
885 | { PREFIX_TABLE (PREFIX_EVEX_0F71_REG_2) }, |
||
886 | { Bad_Opcode }, |
||
887 | { PREFIX_TABLE (PREFIX_EVEX_0F71_REG_4) }, |
||
888 | { Bad_Opcode }, |
||
889 | { PREFIX_TABLE (PREFIX_EVEX_0F71_REG_6) }, |
||
890 | }, |
||
5221 | serge | 891 | /* REG_EVEX_0F72 */ |
892 | { |
||
893 | { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_0) }, |
||
894 | { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_1) }, |
||
895 | { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_2) }, |
||
896 | { Bad_Opcode }, |
||
897 | { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_4) }, |
||
898 | { Bad_Opcode }, |
||
899 | { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_6) }, |
||
900 | }, |
||
901 | /* REG_EVEX_0F73 */ |
||
902 | { |
||
903 | { Bad_Opcode }, |
||
904 | { Bad_Opcode }, |
||
905 | { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_2) }, |
||
6324 | serge | 906 | { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_3) }, |
5221 | serge | 907 | { Bad_Opcode }, |
908 | { Bad_Opcode }, |
||
909 | { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_6) }, |
||
6324 | serge | 910 | { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_7) }, |
5221 | serge | 911 | }, |
912 | /* REG_EVEX_0F38C6 */ |
||
913 | { |
||
914 | { Bad_Opcode }, |
||
915 | { MOD_TABLE (MOD_EVEX_0F38C6_REG_1) }, |
||
916 | { MOD_TABLE (MOD_EVEX_0F38C6_REG_2) }, |
||
917 | { Bad_Opcode }, |
||
918 | { Bad_Opcode }, |
||
919 | { MOD_TABLE (MOD_EVEX_0F38C6_REG_5) }, |
||
920 | { MOD_TABLE (MOD_EVEX_0F38C6_REG_6) }, |
||
921 | }, |
||
922 | /* REG_EVEX_0F38C7 */ |
||
923 | { |
||
924 | { Bad_Opcode }, |
||
925 | { MOD_TABLE (MOD_EVEX_0F38C7_REG_1) }, |
||
926 | { MOD_TABLE (MOD_EVEX_0F38C7_REG_2) }, |
||
927 | { Bad_Opcode }, |
||
928 | { Bad_Opcode }, |
||
929 | { MOD_TABLE (MOD_EVEX_0F38C7_REG_5) }, |
||
930 | { MOD_TABLE (MOD_EVEX_0F38C7_REG_6) }, |
||
931 | }, |
||
932 | #endif /* NEED_REG_TABLE */ |
||
933 | |||
934 | #ifdef NEED_PREFIX_TABLE |
||
935 | /* PREFIX_EVEX_0F10 */ |
||
936 | { |
||
937 | { VEX_W_TABLE (EVEX_W_0F10_P_0) }, |
||
938 | { MOD_TABLE (MOD_EVEX_0F10_PREFIX_1) }, |
||
939 | { VEX_W_TABLE (EVEX_W_0F10_P_2) }, |
||
940 | { MOD_TABLE (MOD_EVEX_0F10_PREFIX_3) }, |
||
941 | }, |
||
942 | /* PREFIX_EVEX_0F11 */ |
||
943 | { |
||
944 | { VEX_W_TABLE (EVEX_W_0F11_P_0) }, |
||
945 | { MOD_TABLE (MOD_EVEX_0F11_PREFIX_1) }, |
||
946 | { VEX_W_TABLE (EVEX_W_0F11_P_2) }, |
||
947 | { MOD_TABLE (MOD_EVEX_0F11_PREFIX_3) }, |
||
948 | }, |
||
949 | /* PREFIX_EVEX_0F12 */ |
||
950 | { |
||
951 | { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0) }, |
||
952 | { VEX_W_TABLE (EVEX_W_0F12_P_1) }, |
||
953 | { VEX_W_TABLE (EVEX_W_0F12_P_2) }, |
||
954 | { VEX_W_TABLE (EVEX_W_0F12_P_3) }, |
||
955 | }, |
||
956 | /* PREFIX_EVEX_0F13 */ |
||
957 | { |
||
958 | { VEX_W_TABLE (EVEX_W_0F13_P_0) }, |
||
959 | { Bad_Opcode }, |
||
960 | { VEX_W_TABLE (EVEX_W_0F13_P_2) }, |
||
961 | }, |
||
962 | /* PREFIX_EVEX_0F14 */ |
||
963 | { |
||
964 | { VEX_W_TABLE (EVEX_W_0F14_P_0) }, |
||
965 | { Bad_Opcode }, |
||
966 | { VEX_W_TABLE (EVEX_W_0F14_P_2) }, |
||
967 | }, |
||
968 | /* PREFIX_EVEX_0F15 */ |
||
969 | { |
||
970 | { VEX_W_TABLE (EVEX_W_0F15_P_0) }, |
||
971 | { Bad_Opcode }, |
||
972 | { VEX_W_TABLE (EVEX_W_0F15_P_2) }, |
||
973 | }, |
||
974 | /* PREFIX_EVEX_0F16 */ |
||
975 | { |
||
976 | { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0) }, |
||
977 | { VEX_W_TABLE (EVEX_W_0F16_P_1) }, |
||
978 | { VEX_W_TABLE (EVEX_W_0F16_P_2) }, |
||
979 | }, |
||
980 | /* PREFIX_EVEX_0F17 */ |
||
981 | { |
||
982 | { VEX_W_TABLE (EVEX_W_0F17_P_0) }, |
||
983 | { Bad_Opcode }, |
||
984 | { VEX_W_TABLE (EVEX_W_0F17_P_2) }, |
||
985 | }, |
||
986 | /* PREFIX_EVEX_0F28 */ |
||
987 | { |
||
988 | { VEX_W_TABLE (EVEX_W_0F28_P_0) }, |
||
989 | { Bad_Opcode }, |
||
990 | { VEX_W_TABLE (EVEX_W_0F28_P_2) }, |
||
991 | }, |
||
992 | /* PREFIX_EVEX_0F29 */ |
||
993 | { |
||
994 | { VEX_W_TABLE (EVEX_W_0F29_P_0) }, |
||
995 | { Bad_Opcode }, |
||
996 | { VEX_W_TABLE (EVEX_W_0F29_P_2) }, |
||
997 | }, |
||
998 | /* PREFIX_EVEX_0F2A */ |
||
999 | { |
||
1000 | { Bad_Opcode }, |
||
1001 | { VEX_W_TABLE (EVEX_W_0F2A_P_1) }, |
||
1002 | { Bad_Opcode }, |
||
1003 | { VEX_W_TABLE (EVEX_W_0F2A_P_3) }, |
||
1004 | }, |
||
1005 | /* PREFIX_EVEX_0F2B */ |
||
1006 | { |
||
1007 | { VEX_W_TABLE (EVEX_W_0F2B_P_0) }, |
||
1008 | { Bad_Opcode }, |
||
1009 | { VEX_W_TABLE (EVEX_W_0F2B_P_2) }, |
||
1010 | }, |
||
1011 | /* PREFIX_EVEX_0F2C */ |
||
1012 | { |
||
1013 | { Bad_Opcode }, |
||
6324 | serge | 1014 | { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 }, |
5221 | serge | 1015 | { Bad_Opcode }, |
6324 | serge | 1016 | { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 }, |
5221 | serge | 1017 | }, |
1018 | /* PREFIX_EVEX_0F2D */ |
||
1019 | { |
||
1020 | { Bad_Opcode }, |
||
6324 | serge | 1021 | { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 }, |
5221 | serge | 1022 | { Bad_Opcode }, |
6324 | serge | 1023 | { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 1024 | }, |
1025 | /* PREFIX_EVEX_0F2E */ |
||
1026 | { |
||
1027 | { VEX_W_TABLE (EVEX_W_0F2E_P_0) }, |
||
1028 | { Bad_Opcode }, |
||
1029 | { VEX_W_TABLE (EVEX_W_0F2E_P_2) }, |
||
1030 | }, |
||
1031 | /* PREFIX_EVEX_0F2F */ |
||
1032 | { |
||
1033 | { VEX_W_TABLE (EVEX_W_0F2F_P_0) }, |
||
1034 | { Bad_Opcode }, |
||
1035 | { VEX_W_TABLE (EVEX_W_0F2F_P_2) }, |
||
1036 | }, |
||
1037 | /* PREFIX_EVEX_0F51 */ |
||
1038 | { |
||
1039 | { VEX_W_TABLE (EVEX_W_0F51_P_0) }, |
||
1040 | { VEX_W_TABLE (EVEX_W_0F51_P_1) }, |
||
1041 | { VEX_W_TABLE (EVEX_W_0F51_P_2) }, |
||
1042 | { VEX_W_TABLE (EVEX_W_0F51_P_3) }, |
||
1043 | }, |
||
6324 | serge | 1044 | /* PREFIX_EVEX_0F54 */ |
1045 | { |
||
1046 | { VEX_W_TABLE (EVEX_W_0F54_P_0) }, |
||
1047 | { Bad_Opcode }, |
||
1048 | { VEX_W_TABLE (EVEX_W_0F54_P_2) }, |
||
1049 | }, |
||
1050 | /* PREFIX_EVEX_0F55 */ |
||
1051 | { |
||
1052 | { VEX_W_TABLE (EVEX_W_0F55_P_0) }, |
||
1053 | { Bad_Opcode }, |
||
1054 | { VEX_W_TABLE (EVEX_W_0F55_P_2) }, |
||
1055 | }, |
||
1056 | /* PREFIX_EVEX_0F56 */ |
||
1057 | { |
||
1058 | { VEX_W_TABLE (EVEX_W_0F56_P_0) }, |
||
1059 | { Bad_Opcode }, |
||
1060 | { VEX_W_TABLE (EVEX_W_0F56_P_2) }, |
||
1061 | }, |
||
1062 | /* PREFIX_EVEX_0F57 */ |
||
1063 | { |
||
1064 | { VEX_W_TABLE (EVEX_W_0F57_P_0) }, |
||
1065 | { Bad_Opcode }, |
||
1066 | { VEX_W_TABLE (EVEX_W_0F57_P_2) }, |
||
1067 | }, |
||
5221 | serge | 1068 | /* PREFIX_EVEX_0F58 */ |
1069 | { |
||
1070 | { VEX_W_TABLE (EVEX_W_0F58_P_0) }, |
||
1071 | { VEX_W_TABLE (EVEX_W_0F58_P_1) }, |
||
1072 | { VEX_W_TABLE (EVEX_W_0F58_P_2) }, |
||
1073 | { VEX_W_TABLE (EVEX_W_0F58_P_3) }, |
||
1074 | }, |
||
1075 | /* PREFIX_EVEX_0F59 */ |
||
1076 | { |
||
1077 | { VEX_W_TABLE (EVEX_W_0F59_P_0) }, |
||
1078 | { VEX_W_TABLE (EVEX_W_0F59_P_1) }, |
||
1079 | { VEX_W_TABLE (EVEX_W_0F59_P_2) }, |
||
1080 | { VEX_W_TABLE (EVEX_W_0F59_P_3) }, |
||
1081 | }, |
||
1082 | /* PREFIX_EVEX_0F5A */ |
||
1083 | { |
||
1084 | { VEX_W_TABLE (EVEX_W_0F5A_P_0) }, |
||
1085 | { VEX_W_TABLE (EVEX_W_0F5A_P_1) }, |
||
1086 | { VEX_W_TABLE (EVEX_W_0F5A_P_2) }, |
||
1087 | { VEX_W_TABLE (EVEX_W_0F5A_P_3) }, |
||
1088 | }, |
||
1089 | /* PREFIX_EVEX_0F5B */ |
||
1090 | { |
||
1091 | { VEX_W_TABLE (EVEX_W_0F5B_P_0) }, |
||
1092 | { VEX_W_TABLE (EVEX_W_0F5B_P_1) }, |
||
1093 | { VEX_W_TABLE (EVEX_W_0F5B_P_2) }, |
||
1094 | }, |
||
1095 | /* PREFIX_EVEX_0F5C */ |
||
1096 | { |
||
1097 | { VEX_W_TABLE (EVEX_W_0F5C_P_0) }, |
||
1098 | { VEX_W_TABLE (EVEX_W_0F5C_P_1) }, |
||
1099 | { VEX_W_TABLE (EVEX_W_0F5C_P_2) }, |
||
1100 | { VEX_W_TABLE (EVEX_W_0F5C_P_3) }, |
||
1101 | }, |
||
1102 | /* PREFIX_EVEX_0F5D */ |
||
1103 | { |
||
1104 | { VEX_W_TABLE (EVEX_W_0F5D_P_0) }, |
||
1105 | { VEX_W_TABLE (EVEX_W_0F5D_P_1) }, |
||
1106 | { VEX_W_TABLE (EVEX_W_0F5D_P_2) }, |
||
1107 | { VEX_W_TABLE (EVEX_W_0F5D_P_3) }, |
||
1108 | }, |
||
1109 | /* PREFIX_EVEX_0F5E */ |
||
1110 | { |
||
1111 | { VEX_W_TABLE (EVEX_W_0F5E_P_0) }, |
||
1112 | { VEX_W_TABLE (EVEX_W_0F5E_P_1) }, |
||
1113 | { VEX_W_TABLE (EVEX_W_0F5E_P_2) }, |
||
1114 | { VEX_W_TABLE (EVEX_W_0F5E_P_3) }, |
||
1115 | }, |
||
1116 | /* PREFIX_EVEX_0F5F */ |
||
1117 | { |
||
1118 | { VEX_W_TABLE (EVEX_W_0F5F_P_0) }, |
||
1119 | { VEX_W_TABLE (EVEX_W_0F5F_P_1) }, |
||
1120 | { VEX_W_TABLE (EVEX_W_0F5F_P_2) }, |
||
1121 | { VEX_W_TABLE (EVEX_W_0F5F_P_3) }, |
||
1122 | }, |
||
6324 | serge | 1123 | /* PREFIX_EVEX_0F60 */ |
1124 | { |
||
1125 | { Bad_Opcode }, |
||
1126 | { Bad_Opcode }, |
||
1127 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
||
1128 | }, |
||
1129 | /* PREFIX_EVEX_0F61 */ |
||
1130 | { |
||
1131 | { Bad_Opcode }, |
||
1132 | { Bad_Opcode }, |
||
1133 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
||
1134 | }, |
||
5221 | serge | 1135 | /* PREFIX_EVEX_0F62 */ |
1136 | { |
||
1137 | { Bad_Opcode }, |
||
1138 | { Bad_Opcode }, |
||
1139 | { VEX_W_TABLE (EVEX_W_0F62_P_2) }, |
||
1140 | }, |
||
6324 | serge | 1141 | /* PREFIX_EVEX_0F63 */ |
1142 | { |
||
1143 | { Bad_Opcode }, |
||
1144 | { Bad_Opcode }, |
||
1145 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
||
1146 | }, |
||
1147 | /* PREFIX_EVEX_0F64 */ |
||
1148 | { |
||
1149 | { Bad_Opcode }, |
||
1150 | { Bad_Opcode }, |
||
1151 | { "vpcmpgtb", { XMask, Vex, EXx }, 0 }, |
||
1152 | }, |
||
1153 | /* PREFIX_EVEX_0F65 */ |
||
1154 | { |
||
1155 | { Bad_Opcode }, |
||
1156 | { Bad_Opcode }, |
||
1157 | { "vpcmpgtw", { XMask, Vex, EXx }, 0 }, |
||
1158 | }, |
||
5221 | serge | 1159 | /* PREFIX_EVEX_0F66 */ |
1160 | { |
||
1161 | { Bad_Opcode }, |
||
1162 | { Bad_Opcode }, |
||
1163 | { VEX_W_TABLE (EVEX_W_0F66_P_2) }, |
||
1164 | }, |
||
6324 | serge | 1165 | /* PREFIX_EVEX_0F67 */ |
1166 | { |
||
1167 | { Bad_Opcode }, |
||
1168 | { Bad_Opcode }, |
||
1169 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
||
1170 | }, |
||
1171 | /* PREFIX_EVEX_0F68 */ |
||
1172 | { |
||
1173 | { Bad_Opcode }, |
||
1174 | { Bad_Opcode }, |
||
1175 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
||
1176 | }, |
||
1177 | /* PREFIX_EVEX_0F69 */ |
||
1178 | { |
||
1179 | { Bad_Opcode }, |
||
1180 | { Bad_Opcode }, |
||
1181 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
||
1182 | }, |
||
5221 | serge | 1183 | /* PREFIX_EVEX_0F6A */ |
1184 | { |
||
1185 | { Bad_Opcode }, |
||
1186 | { Bad_Opcode }, |
||
1187 | { VEX_W_TABLE (EVEX_W_0F6A_P_2) }, |
||
1188 | }, |
||
6324 | serge | 1189 | /* PREFIX_EVEX_0F6B */ |
1190 | { |
||
1191 | { Bad_Opcode }, |
||
1192 | { Bad_Opcode }, |
||
1193 | { VEX_W_TABLE (EVEX_W_0F6B_P_2) }, |
||
1194 | }, |
||
5221 | serge | 1195 | /* PREFIX_EVEX_0F6C */ |
1196 | { |
||
1197 | { Bad_Opcode }, |
||
1198 | { Bad_Opcode }, |
||
1199 | { VEX_W_TABLE (EVEX_W_0F6C_P_2) }, |
||
1200 | }, |
||
1201 | /* PREFIX_EVEX_0F6D */ |
||
1202 | { |
||
1203 | { Bad_Opcode }, |
||
1204 | { Bad_Opcode }, |
||
1205 | { VEX_W_TABLE (EVEX_W_0F6D_P_2) }, |
||
1206 | }, |
||
1207 | /* PREFIX_EVEX_0F6E */ |
||
1208 | { |
||
1209 | { Bad_Opcode }, |
||
1210 | { Bad_Opcode }, |
||
1211 | { VEX_W_TABLE (EVEX_W_0F6E_P_2) }, |
||
1212 | }, |
||
1213 | /* PREFIX_EVEX_0F6F */ |
||
1214 | { |
||
1215 | { Bad_Opcode }, |
||
1216 | { VEX_W_TABLE (EVEX_W_0F6F_P_1) }, |
||
1217 | { VEX_W_TABLE (EVEX_W_0F6F_P_2) }, |
||
6324 | serge | 1218 | { VEX_W_TABLE (EVEX_W_0F6F_P_3) }, |
5221 | serge | 1219 | }, |
1220 | /* PREFIX_EVEX_0F70 */ |
||
1221 | { |
||
1222 | { Bad_Opcode }, |
||
6324 | serge | 1223 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
5221 | serge | 1224 | { VEX_W_TABLE (EVEX_W_0F70_P_2) }, |
6324 | serge | 1225 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
5221 | serge | 1226 | }, |
6324 | serge | 1227 | /* PREFIX_EVEX_0F71_REG_2 */ |
1228 | { |
||
1229 | { Bad_Opcode }, |
||
1230 | { Bad_Opcode }, |
||
1231 | { "vpsrlw", { Vex, EXx, Ib }, 0 }, |
||
1232 | }, |
||
1233 | /* PREFIX_EVEX_0F71_REG_4 */ |
||
1234 | { |
||
1235 | { Bad_Opcode }, |
||
1236 | { Bad_Opcode }, |
||
1237 | { "vpsraw", { Vex, EXx, Ib }, 0 }, |
||
1238 | }, |
||
1239 | /* PREFIX_EVEX_0F71_REG_6 */ |
||
1240 | { |
||
1241 | { Bad_Opcode }, |
||
1242 | { Bad_Opcode }, |
||
1243 | { "vpsllw", { Vex, EXx, Ib }, 0 }, |
||
1244 | }, |
||
5221 | serge | 1245 | /* PREFIX_EVEX_0F72_REG_0 */ |
1246 | { |
||
1247 | { Bad_Opcode }, |
||
1248 | { Bad_Opcode }, |
||
6324 | serge | 1249 | { "vpror%LW", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 1250 | }, |
1251 | /* PREFIX_EVEX_0F72_REG_1 */ |
||
1252 | { |
||
1253 | { Bad_Opcode }, |
||
1254 | { Bad_Opcode }, |
||
6324 | serge | 1255 | { "vprol%LW", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 1256 | }, |
1257 | /* PREFIX_EVEX_0F72_REG_2 */ |
||
1258 | { |
||
1259 | { Bad_Opcode }, |
||
1260 | { Bad_Opcode }, |
||
1261 | { VEX_W_TABLE (EVEX_W_0F72_R_2_P_2) }, |
||
1262 | }, |
||
1263 | /* PREFIX_EVEX_0F72_REG_4 */ |
||
1264 | { |
||
1265 | { Bad_Opcode }, |
||
1266 | { Bad_Opcode }, |
||
6324 | serge | 1267 | { "vpsra%LW", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 1268 | }, |
1269 | /* PREFIX_EVEX_0F72_REG_6 */ |
||
1270 | { |
||
1271 | { Bad_Opcode }, |
||
1272 | { Bad_Opcode }, |
||
1273 | { VEX_W_TABLE (EVEX_W_0F72_R_6_P_2) }, |
||
1274 | }, |
||
1275 | /* PREFIX_EVEX_0F73_REG_2 */ |
||
1276 | { |
||
1277 | { Bad_Opcode }, |
||
1278 | { Bad_Opcode }, |
||
1279 | { VEX_W_TABLE (EVEX_W_0F73_R_2_P_2) }, |
||
1280 | }, |
||
6324 | serge | 1281 | /* PREFIX_EVEX_0F73_REG_3 */ |
1282 | { |
||
1283 | { Bad_Opcode }, |
||
1284 | { Bad_Opcode }, |
||
1285 | { "vpsrldq", { Vex, EXx, Ib }, 0 }, |
||
1286 | }, |
||
5221 | serge | 1287 | /* PREFIX_EVEX_0F73_REG_6 */ |
1288 | { |
||
1289 | { Bad_Opcode }, |
||
1290 | { Bad_Opcode }, |
||
1291 | { VEX_W_TABLE (EVEX_W_0F73_R_6_P_2) }, |
||
1292 | }, |
||
6324 | serge | 1293 | /* PREFIX_EVEX_0F73_REG_7 */ |
1294 | { |
||
1295 | { Bad_Opcode }, |
||
1296 | { Bad_Opcode }, |
||
1297 | { "vpslldq", { Vex, EXx, Ib }, 0 }, |
||
1298 | }, |
||
1299 | /* PREFIX_EVEX_0F74 */ |
||
1300 | { |
||
1301 | { Bad_Opcode }, |
||
1302 | { Bad_Opcode }, |
||
1303 | { "vpcmpeqb", { XMask, Vex, EXx }, 0 }, |
||
1304 | }, |
||
1305 | /* PREFIX_EVEX_0F75 */ |
||
1306 | { |
||
1307 | { Bad_Opcode }, |
||
1308 | { Bad_Opcode }, |
||
1309 | { "vpcmpeqw", { XMask, Vex, EXx }, 0 }, |
||
1310 | }, |
||
5221 | serge | 1311 | /* PREFIX_EVEX_0F76 */ |
1312 | { |
||
1313 | { Bad_Opcode }, |
||
1314 | { Bad_Opcode }, |
||
1315 | { VEX_W_TABLE (EVEX_W_0F76_P_2) }, |
||
1316 | }, |
||
1317 | /* PREFIX_EVEX_0F78 */ |
||
1318 | { |
||
1319 | { VEX_W_TABLE (EVEX_W_0F78_P_0) }, |
||
6324 | serge | 1320 | { "vcvttss2usi", { Gdq, EXxmm_md, EXxEVexS }, 0 }, |
1321 | { VEX_W_TABLE (EVEX_W_0F78_P_2) }, |
||
1322 | { "vcvttsd2usi", { Gdq, EXxmm_mq, EXxEVexS }, 0 }, |
||
5221 | serge | 1323 | }, |
1324 | /* PREFIX_EVEX_0F79 */ |
||
1325 | { |
||
1326 | { VEX_W_TABLE (EVEX_W_0F79_P_0) }, |
||
6324 | serge | 1327 | { "vcvtss2usi", { Gdq, EXxmm_md, EXxEVexR }, 0 }, |
1328 | { VEX_W_TABLE (EVEX_W_0F79_P_2) }, |
||
1329 | { "vcvtsd2usi", { Gdq, EXxmm_mq, EXxEVexR }, 0 }, |
||
5221 | serge | 1330 | }, |
1331 | /* PREFIX_EVEX_0F7A */ |
||
1332 | { |
||
1333 | { Bad_Opcode }, |
||
1334 | { VEX_W_TABLE (EVEX_W_0F7A_P_1) }, |
||
6324 | serge | 1335 | { VEX_W_TABLE (EVEX_W_0F7A_P_2) }, |
5221 | serge | 1336 | { VEX_W_TABLE (EVEX_W_0F7A_P_3) }, |
1337 | }, |
||
1338 | /* PREFIX_EVEX_0F7B */ |
||
1339 | { |
||
1340 | { Bad_Opcode }, |
||
1341 | { VEX_W_TABLE (EVEX_W_0F7B_P_1) }, |
||
6324 | serge | 1342 | { VEX_W_TABLE (EVEX_W_0F7B_P_2) }, |
5221 | serge | 1343 | { VEX_W_TABLE (EVEX_W_0F7B_P_3) }, |
1344 | }, |
||
1345 | /* PREFIX_EVEX_0F7E */ |
||
1346 | { |
||
1347 | { Bad_Opcode }, |
||
1348 | { VEX_W_TABLE (EVEX_W_0F7E_P_1) }, |
||
1349 | { VEX_W_TABLE (EVEX_W_0F7E_P_2) }, |
||
1350 | }, |
||
1351 | /* PREFIX_EVEX_0F7F */ |
||
1352 | { |
||
1353 | { Bad_Opcode }, |
||
1354 | { VEX_W_TABLE (EVEX_W_0F7F_P_1) }, |
||
1355 | { VEX_W_TABLE (EVEX_W_0F7F_P_2) }, |
||
6324 | serge | 1356 | { VEX_W_TABLE (EVEX_W_0F7F_P_3) }, |
5221 | serge | 1357 | }, |
1358 | /* PREFIX_EVEX_0FC2 */ |
||
1359 | { |
||
1360 | { VEX_W_TABLE (EVEX_W_0FC2_P_0) }, |
||
1361 | { VEX_W_TABLE (EVEX_W_0FC2_P_1) }, |
||
1362 | { VEX_W_TABLE (EVEX_W_0FC2_P_2) }, |
||
1363 | { VEX_W_TABLE (EVEX_W_0FC2_P_3) }, |
||
1364 | }, |
||
6324 | serge | 1365 | /* PREFIX_EVEX_0FC4 */ |
1366 | { |
||
1367 | { Bad_Opcode }, |
||
1368 | { Bad_Opcode }, |
||
1369 | { "vpinsrw", { XM, Vex128, Edw, Ib }, 0 }, |
||
1370 | }, |
||
1371 | /* PREFIX_EVEX_0FC5 */ |
||
1372 | { |
||
1373 | { Bad_Opcode }, |
||
1374 | { Bad_Opcode }, |
||
1375 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
||
1376 | }, |
||
5221 | serge | 1377 | /* PREFIX_EVEX_0FC6 */ |
1378 | { |
||
1379 | { VEX_W_TABLE (EVEX_W_0FC6_P_0) }, |
||
1380 | { Bad_Opcode }, |
||
1381 | { VEX_W_TABLE (EVEX_W_0FC6_P_2) }, |
||
1382 | }, |
||
6324 | serge | 1383 | /* PREFIX_EVEX_0FD1 */ |
1384 | { |
||
1385 | { Bad_Opcode }, |
||
1386 | { Bad_Opcode }, |
||
1387 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
||
1388 | }, |
||
5221 | serge | 1389 | /* PREFIX_EVEX_0FD2 */ |
1390 | { |
||
1391 | { Bad_Opcode }, |
||
1392 | { Bad_Opcode }, |
||
1393 | { VEX_W_TABLE (EVEX_W_0FD2_P_2) }, |
||
1394 | }, |
||
1395 | /* PREFIX_EVEX_0FD3 */ |
||
1396 | { |
||
1397 | { Bad_Opcode }, |
||
1398 | { Bad_Opcode }, |
||
1399 | { VEX_W_TABLE (EVEX_W_0FD3_P_2) }, |
||
1400 | }, |
||
1401 | /* PREFIX_EVEX_0FD4 */ |
||
1402 | { |
||
1403 | { Bad_Opcode }, |
||
1404 | { Bad_Opcode }, |
||
1405 | { VEX_W_TABLE (EVEX_W_0FD4_P_2) }, |
||
1406 | }, |
||
6324 | serge | 1407 | /* PREFIX_EVEX_0FD5 */ |
1408 | { |
||
1409 | { Bad_Opcode }, |
||
1410 | { Bad_Opcode }, |
||
1411 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
||
1412 | }, |
||
5221 | serge | 1413 | /* PREFIX_EVEX_0FD6 */ |
1414 | { |
||
1415 | { Bad_Opcode }, |
||
1416 | { Bad_Opcode }, |
||
1417 | { VEX_W_TABLE (EVEX_W_0FD6_P_2) }, |
||
1418 | }, |
||
6324 | serge | 1419 | /* PREFIX_EVEX_0FD8 */ |
1420 | { |
||
1421 | { Bad_Opcode }, |
||
1422 | { Bad_Opcode }, |
||
1423 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
||
1424 | }, |
||
1425 | /* PREFIX_EVEX_0FD9 */ |
||
1426 | { |
||
1427 | { Bad_Opcode }, |
||
1428 | { Bad_Opcode }, |
||
1429 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
||
1430 | }, |
||
1431 | /* PREFIX_EVEX_0FDA */ |
||
1432 | { |
||
1433 | { Bad_Opcode }, |
||
1434 | { Bad_Opcode }, |
||
1435 | { "vpminub", { XM, Vex, EXx }, 0 }, |
||
1436 | }, |
||
5221 | serge | 1437 | /* PREFIX_EVEX_0FDB */ |
1438 | { |
||
1439 | { Bad_Opcode }, |
||
1440 | { Bad_Opcode }, |
||
6324 | serge | 1441 | { "vpand%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1442 | }, |
6324 | serge | 1443 | /* PREFIX_EVEX_0FDC */ |
1444 | { |
||
1445 | { Bad_Opcode }, |
||
1446 | { Bad_Opcode }, |
||
1447 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
||
1448 | }, |
||
1449 | /* PREFIX_EVEX_0FDD */ |
||
1450 | { |
||
1451 | { Bad_Opcode }, |
||
1452 | { Bad_Opcode }, |
||
1453 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
||
1454 | }, |
||
1455 | /* PREFIX_EVEX_0FDE */ |
||
1456 | { |
||
1457 | { Bad_Opcode }, |
||
1458 | { Bad_Opcode }, |
||
1459 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
||
1460 | }, |
||
5221 | serge | 1461 | /* PREFIX_EVEX_0FDF */ |
1462 | { |
||
1463 | { Bad_Opcode }, |
||
1464 | { Bad_Opcode }, |
||
6324 | serge | 1465 | { "vpandn%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1466 | }, |
6324 | serge | 1467 | /* PREFIX_EVEX_0FE0 */ |
1468 | { |
||
1469 | { Bad_Opcode }, |
||
1470 | { Bad_Opcode }, |
||
1471 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
||
1472 | }, |
||
1473 | /* PREFIX_EVEX_0FE1 */ |
||
1474 | { |
||
1475 | { Bad_Opcode }, |
||
1476 | { Bad_Opcode }, |
||
1477 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
||
1478 | }, |
||
5221 | serge | 1479 | /* PREFIX_EVEX_0FE2 */ |
1480 | { |
||
1481 | { Bad_Opcode }, |
||
1482 | { Bad_Opcode }, |
||
6324 | serge | 1483 | { "vpsra%LW", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 1484 | }, |
6324 | serge | 1485 | /* PREFIX_EVEX_0FE3 */ |
1486 | { |
||
1487 | { Bad_Opcode }, |
||
1488 | { Bad_Opcode }, |
||
1489 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
||
1490 | }, |
||
1491 | /* PREFIX_EVEX_0FE4 */ |
||
1492 | { |
||
1493 | { Bad_Opcode }, |
||
1494 | { Bad_Opcode }, |
||
1495 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
||
1496 | }, |
||
1497 | /* PREFIX_EVEX_0FE5 */ |
||
1498 | { |
||
1499 | { Bad_Opcode }, |
||
1500 | { Bad_Opcode }, |
||
1501 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
||
1502 | }, |
||
5221 | serge | 1503 | /* PREFIX_EVEX_0FE6 */ |
1504 | { |
||
1505 | { Bad_Opcode }, |
||
1506 | { VEX_W_TABLE (EVEX_W_0FE6_P_1) }, |
||
1507 | { VEX_W_TABLE (EVEX_W_0FE6_P_2) }, |
||
1508 | { VEX_W_TABLE (EVEX_W_0FE6_P_3) }, |
||
1509 | }, |
||
1510 | /* PREFIX_EVEX_0FE7 */ |
||
1511 | { |
||
1512 | { Bad_Opcode }, |
||
1513 | { Bad_Opcode }, |
||
1514 | { VEX_W_TABLE (EVEX_W_0FE7_P_2) }, |
||
1515 | }, |
||
6324 | serge | 1516 | /* PREFIX_EVEX_0FE8 */ |
1517 | { |
||
1518 | { Bad_Opcode }, |
||
1519 | { Bad_Opcode }, |
||
1520 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
||
1521 | }, |
||
1522 | /* PREFIX_EVEX_0FE9 */ |
||
1523 | { |
||
1524 | { Bad_Opcode }, |
||
1525 | { Bad_Opcode }, |
||
1526 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
||
1527 | }, |
||
1528 | /* PREFIX_EVEX_0FEA */ |
||
1529 | { |
||
1530 | { Bad_Opcode }, |
||
1531 | { Bad_Opcode }, |
||
1532 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
||
1533 | }, |
||
5221 | serge | 1534 | /* PREFIX_EVEX_0FEB */ |
1535 | { |
||
1536 | { Bad_Opcode }, |
||
1537 | { Bad_Opcode }, |
||
6324 | serge | 1538 | { "vpor%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1539 | }, |
6324 | serge | 1540 | /* PREFIX_EVEX_0FEC */ |
1541 | { |
||
1542 | { Bad_Opcode }, |
||
1543 | { Bad_Opcode }, |
||
1544 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
||
1545 | }, |
||
1546 | /* PREFIX_EVEX_0FED */ |
||
1547 | { |
||
1548 | { Bad_Opcode }, |
||
1549 | { Bad_Opcode }, |
||
1550 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
||
1551 | }, |
||
1552 | /* PREFIX_EVEX_0FEE */ |
||
1553 | { |
||
1554 | { Bad_Opcode }, |
||
1555 | { Bad_Opcode }, |
||
1556 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
||
1557 | }, |
||
5221 | serge | 1558 | /* PREFIX_EVEX_0FEF */ |
1559 | { |
||
1560 | { Bad_Opcode }, |
||
1561 | { Bad_Opcode }, |
||
6324 | serge | 1562 | { "vpxor%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1563 | }, |
6324 | serge | 1564 | /* PREFIX_EVEX_0FF1 */ |
1565 | { |
||
1566 | { Bad_Opcode }, |
||
1567 | { Bad_Opcode }, |
||
1568 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
||
1569 | }, |
||
5221 | serge | 1570 | /* PREFIX_EVEX_0FF2 */ |
1571 | { |
||
1572 | { Bad_Opcode }, |
||
1573 | { Bad_Opcode }, |
||
1574 | { VEX_W_TABLE (EVEX_W_0FF2_P_2) }, |
||
1575 | }, |
||
1576 | /* PREFIX_EVEX_0FF3 */ |
||
1577 | { |
||
1578 | { Bad_Opcode }, |
||
1579 | { Bad_Opcode }, |
||
1580 | { VEX_W_TABLE (EVEX_W_0FF3_P_2) }, |
||
1581 | }, |
||
1582 | /* PREFIX_EVEX_0FF4 */ |
||
1583 | { |
||
1584 | { Bad_Opcode }, |
||
1585 | { Bad_Opcode }, |
||
1586 | { VEX_W_TABLE (EVEX_W_0FF4_P_2) }, |
||
1587 | }, |
||
6324 | serge | 1588 | /* PREFIX_EVEX_0FF5 */ |
1589 | { |
||
1590 | { Bad_Opcode }, |
||
1591 | { Bad_Opcode }, |
||
1592 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
||
1593 | }, |
||
1594 | /* PREFIX_EVEX_0FF6 */ |
||
1595 | { |
||
1596 | { Bad_Opcode }, |
||
1597 | { Bad_Opcode }, |
||
1598 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
||
1599 | }, |
||
1600 | /* PREFIX_EVEX_0FF8 */ |
||
1601 | { |
||
1602 | { Bad_Opcode }, |
||
1603 | { Bad_Opcode }, |
||
1604 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
||
1605 | }, |
||
1606 | /* PREFIX_EVEX_0FF9 */ |
||
1607 | { |
||
1608 | { Bad_Opcode }, |
||
1609 | { Bad_Opcode }, |
||
1610 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
||
1611 | }, |
||
5221 | serge | 1612 | /* PREFIX_EVEX_0FFA */ |
1613 | { |
||
1614 | { Bad_Opcode }, |
||
1615 | { Bad_Opcode }, |
||
1616 | { VEX_W_TABLE (EVEX_W_0FFA_P_2) }, |
||
1617 | }, |
||
1618 | /* PREFIX_EVEX_0FFB */ |
||
1619 | { |
||
1620 | { Bad_Opcode }, |
||
1621 | { Bad_Opcode }, |
||
1622 | { VEX_W_TABLE (EVEX_W_0FFB_P_2) }, |
||
1623 | }, |
||
6324 | serge | 1624 | /* PREFIX_EVEX_0FFC */ |
1625 | { |
||
1626 | { Bad_Opcode }, |
||
1627 | { Bad_Opcode }, |
||
1628 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
||
1629 | }, |
||
1630 | /* PREFIX_EVEX_0FFD */ |
||
1631 | { |
||
1632 | { Bad_Opcode }, |
||
1633 | { Bad_Opcode }, |
||
1634 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
||
1635 | }, |
||
5221 | serge | 1636 | /* PREFIX_EVEX_0FFE */ |
1637 | { |
||
1638 | { Bad_Opcode }, |
||
1639 | { Bad_Opcode }, |
||
1640 | { VEX_W_TABLE (EVEX_W_0FFE_P_2) }, |
||
1641 | }, |
||
6324 | serge | 1642 | /* PREFIX_EVEX_0F3800 */ |
1643 | { |
||
1644 | { Bad_Opcode }, |
||
1645 | { Bad_Opcode }, |
||
1646 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
||
1647 | }, |
||
1648 | /* PREFIX_EVEX_0F3804 */ |
||
1649 | { |
||
1650 | { Bad_Opcode }, |
||
1651 | { Bad_Opcode }, |
||
1652 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
||
1653 | }, |
||
1654 | /* PREFIX_EVEX_0F380B */ |
||
1655 | { |
||
1656 | { Bad_Opcode }, |
||
1657 | { Bad_Opcode }, |
||
1658 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
||
1659 | }, |
||
5221 | serge | 1660 | /* PREFIX_EVEX_0F380C */ |
1661 | { |
||
1662 | { Bad_Opcode }, |
||
1663 | { Bad_Opcode }, |
||
1664 | { VEX_W_TABLE (EVEX_W_0F380C_P_2) }, |
||
1665 | }, |
||
1666 | /* PREFIX_EVEX_0F380D */ |
||
1667 | { |
||
1668 | { Bad_Opcode }, |
||
1669 | { Bad_Opcode }, |
||
1670 | { VEX_W_TABLE (EVEX_W_0F380D_P_2) }, |
||
1671 | }, |
||
6324 | serge | 1672 | /* PREFIX_EVEX_0F3810 */ |
1673 | { |
||
1674 | { Bad_Opcode }, |
||
1675 | { VEX_W_TABLE (EVEX_W_0F3810_P_1) }, |
||
1676 | { VEX_W_TABLE (EVEX_W_0F3810_P_2) }, |
||
1677 | }, |
||
5221 | serge | 1678 | /* PREFIX_EVEX_0F3811 */ |
1679 | { |
||
1680 | { Bad_Opcode }, |
||
1681 | { VEX_W_TABLE (EVEX_W_0F3811_P_1) }, |
||
6324 | serge | 1682 | { VEX_W_TABLE (EVEX_W_0F3811_P_2) }, |
5221 | serge | 1683 | }, |
1684 | /* PREFIX_EVEX_0F3812 */ |
||
1685 | { |
||
1686 | { Bad_Opcode }, |
||
1687 | { VEX_W_TABLE (EVEX_W_0F3812_P_1) }, |
||
6324 | serge | 1688 | { VEX_W_TABLE (EVEX_W_0F3812_P_2) }, |
5221 | serge | 1689 | }, |
1690 | /* PREFIX_EVEX_0F3813 */ |
||
1691 | { |
||
1692 | { Bad_Opcode }, |
||
1693 | { VEX_W_TABLE (EVEX_W_0F3813_P_1) }, |
||
1694 | { VEX_W_TABLE (EVEX_W_0F3813_P_2) }, |
||
1695 | }, |
||
1696 | /* PREFIX_EVEX_0F3814 */ |
||
1697 | { |
||
1698 | { Bad_Opcode }, |
||
1699 | { VEX_W_TABLE (EVEX_W_0F3814_P_1) }, |
||
6324 | serge | 1700 | { "vprorv%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1701 | }, |
1702 | /* PREFIX_EVEX_0F3815 */ |
||
1703 | { |
||
1704 | { Bad_Opcode }, |
||
1705 | { VEX_W_TABLE (EVEX_W_0F3815_P_1) }, |
||
6324 | serge | 1706 | { "vprolv%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1707 | }, |
1708 | /* PREFIX_EVEX_0F3816 */ |
||
1709 | { |
||
1710 | { Bad_Opcode }, |
||
1711 | { Bad_Opcode }, |
||
6324 | serge | 1712 | { "vpermp%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1713 | }, |
1714 | /* PREFIX_EVEX_0F3818 */ |
||
1715 | { |
||
1716 | { Bad_Opcode }, |
||
1717 | { Bad_Opcode }, |
||
1718 | { VEX_W_TABLE (EVEX_W_0F3818_P_2) }, |
||
1719 | }, |
||
1720 | /* PREFIX_EVEX_0F3819 */ |
||
1721 | { |
||
1722 | { Bad_Opcode }, |
||
1723 | { Bad_Opcode }, |
||
1724 | { VEX_W_TABLE (EVEX_W_0F3819_P_2) }, |
||
1725 | }, |
||
1726 | /* PREFIX_EVEX_0F381A */ |
||
1727 | { |
||
1728 | { Bad_Opcode }, |
||
1729 | { Bad_Opcode }, |
||
1730 | { VEX_W_TABLE (EVEX_W_0F381A_P_2) }, |
||
1731 | }, |
||
1732 | /* PREFIX_EVEX_0F381B */ |
||
1733 | { |
||
1734 | { Bad_Opcode }, |
||
1735 | { Bad_Opcode }, |
||
1736 | { VEX_W_TABLE (EVEX_W_0F381B_P_2) }, |
||
1737 | }, |
||
6324 | serge | 1738 | /* PREFIX_EVEX_0F381C */ |
1739 | { |
||
1740 | { Bad_Opcode }, |
||
1741 | { Bad_Opcode }, |
||
1742 | { "vpabsb", { XM, EXx }, 0 }, |
||
1743 | }, |
||
1744 | /* PREFIX_EVEX_0F381D */ |
||
1745 | { |
||
1746 | { Bad_Opcode }, |
||
1747 | { Bad_Opcode }, |
||
1748 | { "vpabsw", { XM, EXx }, 0 }, |
||
1749 | }, |
||
5221 | serge | 1750 | /* PREFIX_EVEX_0F381E */ |
1751 | { |
||
1752 | { Bad_Opcode }, |
||
1753 | { Bad_Opcode }, |
||
1754 | { VEX_W_TABLE (EVEX_W_0F381E_P_2) }, |
||
1755 | }, |
||
1756 | /* PREFIX_EVEX_0F381F */ |
||
1757 | { |
||
1758 | { Bad_Opcode }, |
||
1759 | { Bad_Opcode }, |
||
1760 | { VEX_W_TABLE (EVEX_W_0F381F_P_2) }, |
||
1761 | }, |
||
6324 | serge | 1762 | /* PREFIX_EVEX_0F3820 */ |
1763 | { |
||
1764 | { Bad_Opcode }, |
||
1765 | { VEX_W_TABLE (EVEX_W_0F3820_P_1) }, |
||
1766 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
||
1767 | }, |
||
5221 | serge | 1768 | /* PREFIX_EVEX_0F3821 */ |
1769 | { |
||
1770 | { Bad_Opcode }, |
||
1771 | { VEX_W_TABLE (EVEX_W_0F3821_P_1) }, |
||
6324 | serge | 1772 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
5221 | serge | 1773 | }, |
1774 | /* PREFIX_EVEX_0F3822 */ |
||
1775 | { |
||
1776 | { Bad_Opcode }, |
||
1777 | { VEX_W_TABLE (EVEX_W_0F3822_P_1) }, |
||
6324 | serge | 1778 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
5221 | serge | 1779 | }, |
1780 | /* PREFIX_EVEX_0F3823 */ |
||
1781 | { |
||
1782 | { Bad_Opcode }, |
||
1783 | { VEX_W_TABLE (EVEX_W_0F3823_P_1) }, |
||
6324 | serge | 1784 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
5221 | serge | 1785 | }, |
1786 | /* PREFIX_EVEX_0F3824 */ |
||
1787 | { |
||
1788 | { Bad_Opcode }, |
||
1789 | { VEX_W_TABLE (EVEX_W_0F3824_P_1) }, |
||
6324 | serge | 1790 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
5221 | serge | 1791 | }, |
1792 | /* PREFIX_EVEX_0F3825 */ |
||
1793 | { |
||
1794 | { Bad_Opcode }, |
||
1795 | { VEX_W_TABLE (EVEX_W_0F3825_P_1) }, |
||
1796 | { VEX_W_TABLE (EVEX_W_0F3825_P_2) }, |
||
1797 | }, |
||
6324 | serge | 1798 | /* PREFIX_EVEX_0F3826 */ |
1799 | { |
||
1800 | { Bad_Opcode }, |
||
1801 | { VEX_W_TABLE (EVEX_W_0F3826_P_1) }, |
||
1802 | { VEX_W_TABLE (EVEX_W_0F3826_P_2) }, |
||
1803 | }, |
||
5221 | serge | 1804 | /* PREFIX_EVEX_0F3827 */ |
1805 | { |
||
1806 | { Bad_Opcode }, |
||
6324 | serge | 1807 | { "vptestnm%LW", { XMask, Vex, EXx }, 0 }, |
1808 | { "vptestm%LW", { XMask, Vex, EXx }, 0 }, |
||
5221 | serge | 1809 | }, |
1810 | /* PREFIX_EVEX_0F3828 */ |
||
1811 | { |
||
1812 | { Bad_Opcode }, |
||
6324 | serge | 1813 | { VEX_W_TABLE (EVEX_W_0F3828_P_1) }, |
5221 | serge | 1814 | { VEX_W_TABLE (EVEX_W_0F3828_P_2) }, |
1815 | }, |
||
1816 | /* PREFIX_EVEX_0F3829 */ |
||
1817 | { |
||
1818 | { Bad_Opcode }, |
||
6324 | serge | 1819 | { VEX_W_TABLE (EVEX_W_0F3829_P_1) }, |
5221 | serge | 1820 | { VEX_W_TABLE (EVEX_W_0F3829_P_2) }, |
1821 | }, |
||
1822 | /* PREFIX_EVEX_0F382A */ |
||
1823 | { |
||
1824 | { Bad_Opcode }, |
||
1825 | { VEX_W_TABLE (EVEX_W_0F382A_P_1) }, |
||
1826 | { VEX_W_TABLE (EVEX_W_0F382A_P_2) }, |
||
1827 | }, |
||
6324 | serge | 1828 | /* PREFIX_EVEX_0F382B */ |
1829 | { |
||
1830 | { Bad_Opcode }, |
||
1831 | { Bad_Opcode }, |
||
1832 | { VEX_W_TABLE (EVEX_W_0F382B_P_2) }, |
||
1833 | }, |
||
5221 | serge | 1834 | /* PREFIX_EVEX_0F382C */ |
1835 | { |
||
1836 | { Bad_Opcode }, |
||
1837 | { Bad_Opcode }, |
||
6324 | serge | 1838 | { "vscalefp%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 1839 | }, |
1840 | /* PREFIX_EVEX_0F382D */ |
||
1841 | { |
||
1842 | { Bad_Opcode }, |
||
1843 | { Bad_Opcode }, |
||
6324 | serge | 1844 | { "vscalefs%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 1845 | }, |
6324 | serge | 1846 | /* PREFIX_EVEX_0F3830 */ |
1847 | { |
||
1848 | { Bad_Opcode }, |
||
1849 | { VEX_W_TABLE (EVEX_W_0F3830_P_1) }, |
||
1850 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
||
1851 | }, |
||
5221 | serge | 1852 | /* PREFIX_EVEX_0F3831 */ |
1853 | { |
||
1854 | { Bad_Opcode }, |
||
1855 | { VEX_W_TABLE (EVEX_W_0F3831_P_1) }, |
||
6324 | serge | 1856 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
5221 | serge | 1857 | }, |
1858 | /* PREFIX_EVEX_0F3832 */ |
||
1859 | { |
||
1860 | { Bad_Opcode }, |
||
1861 | { VEX_W_TABLE (EVEX_W_0F3832_P_1) }, |
||
6324 | serge | 1862 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
5221 | serge | 1863 | }, |
1864 | /* PREFIX_EVEX_0F3833 */ |
||
1865 | { |
||
1866 | { Bad_Opcode }, |
||
1867 | { VEX_W_TABLE (EVEX_W_0F3833_P_1) }, |
||
6324 | serge | 1868 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
5221 | serge | 1869 | }, |
1870 | /* PREFIX_EVEX_0F3834 */ |
||
1871 | { |
||
1872 | { Bad_Opcode }, |
||
1873 | { VEX_W_TABLE (EVEX_W_0F3834_P_1) }, |
||
6324 | serge | 1874 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
5221 | serge | 1875 | }, |
1876 | /* PREFIX_EVEX_0F3835 */ |
||
1877 | { |
||
1878 | { Bad_Opcode }, |
||
1879 | { VEX_W_TABLE (EVEX_W_0F3835_P_1) }, |
||
1880 | { VEX_W_TABLE (EVEX_W_0F3835_P_2) }, |
||
1881 | }, |
||
1882 | /* PREFIX_EVEX_0F3836 */ |
||
1883 | { |
||
1884 | { Bad_Opcode }, |
||
1885 | { Bad_Opcode }, |
||
6324 | serge | 1886 | { "vperm%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1887 | }, |
1888 | /* PREFIX_EVEX_0F3837 */ |
||
1889 | { |
||
1890 | { Bad_Opcode }, |
||
1891 | { Bad_Opcode }, |
||
1892 | { VEX_W_TABLE (EVEX_W_0F3837_P_2) }, |
||
1893 | }, |
||
6324 | serge | 1894 | /* PREFIX_EVEX_0F3838 */ |
1895 | { |
||
1896 | { Bad_Opcode }, |
||
1897 | { VEX_W_TABLE (EVEX_W_0F3838_P_1) }, |
||
1898 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
||
1899 | }, |
||
5221 | serge | 1900 | /* PREFIX_EVEX_0F3839 */ |
1901 | { |
||
1902 | { Bad_Opcode }, |
||
6324 | serge | 1903 | { VEX_W_TABLE (EVEX_W_0F3839_P_1) }, |
1904 | { "vpmins%LW", { XM, Vex, EXx }, 0 }, |
||
5221 | serge | 1905 | }, |
1906 | /* PREFIX_EVEX_0F383A */ |
||
1907 | { |
||
1908 | { Bad_Opcode }, |
||
1909 | { VEX_W_TABLE (EVEX_W_0F383A_P_1) }, |
||
6324 | serge | 1910 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1911 | }, |
1912 | /* PREFIX_EVEX_0F383B */ |
||
1913 | { |
||
1914 | { Bad_Opcode }, |
||
1915 | { Bad_Opcode }, |
||
6324 | serge | 1916 | { "vpminu%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1917 | }, |
6324 | serge | 1918 | /* PREFIX_EVEX_0F383C */ |
1919 | { |
||
1920 | { Bad_Opcode }, |
||
1921 | { Bad_Opcode }, |
||
1922 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
||
1923 | }, |
||
5221 | serge | 1924 | /* PREFIX_EVEX_0F383D */ |
1925 | { |
||
1926 | { Bad_Opcode }, |
||
1927 | { Bad_Opcode }, |
||
6324 | serge | 1928 | { "vpmaxs%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1929 | }, |
6324 | serge | 1930 | /* PREFIX_EVEX_0F383E */ |
1931 | { |
||
1932 | { Bad_Opcode }, |
||
1933 | { Bad_Opcode }, |
||
1934 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
||
1935 | }, |
||
5221 | serge | 1936 | /* PREFIX_EVEX_0F383F */ |
1937 | { |
||
1938 | { Bad_Opcode }, |
||
1939 | { Bad_Opcode }, |
||
6324 | serge | 1940 | { "vpmaxu%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1941 | }, |
1942 | /* PREFIX_EVEX_0F3840 */ |
||
1943 | { |
||
1944 | { Bad_Opcode }, |
||
1945 | { Bad_Opcode }, |
||
1946 | { VEX_W_TABLE (EVEX_W_0F3840_P_2) }, |
||
1947 | }, |
||
1948 | /* PREFIX_EVEX_0F3842 */ |
||
1949 | { |
||
1950 | { Bad_Opcode }, |
||
1951 | { Bad_Opcode }, |
||
6324 | serge | 1952 | { "vgetexpp%XW", { XM, EXx, EXxEVexS }, 0 }, |
5221 | serge | 1953 | }, |
1954 | /* PREFIX_EVEX_0F3843 */ |
||
1955 | { |
||
1956 | { Bad_Opcode }, |
||
1957 | { Bad_Opcode }, |
||
6324 | serge | 1958 | { "vgetexps%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexS }, 0 }, |
5221 | serge | 1959 | }, |
1960 | /* PREFIX_EVEX_0F3844 */ |
||
1961 | { |
||
1962 | { Bad_Opcode }, |
||
1963 | { Bad_Opcode }, |
||
6324 | serge | 1964 | { "vplzcnt%LW", { XM, EXx }, 0 }, |
5221 | serge | 1965 | }, |
1966 | /* PREFIX_EVEX_0F3845 */ |
||
1967 | { |
||
1968 | { Bad_Opcode }, |
||
1969 | { Bad_Opcode }, |
||
6324 | serge | 1970 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1971 | }, |
1972 | /* PREFIX_EVEX_0F3846 */ |
||
1973 | { |
||
1974 | { Bad_Opcode }, |
||
1975 | { Bad_Opcode }, |
||
6324 | serge | 1976 | { "vpsrav%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1977 | }, |
1978 | /* PREFIX_EVEX_0F3847 */ |
||
1979 | { |
||
1980 | { Bad_Opcode }, |
||
1981 | { Bad_Opcode }, |
||
6324 | serge | 1982 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 1983 | }, |
1984 | /* PREFIX_EVEX_0F384C */ |
||
1985 | { |
||
1986 | { Bad_Opcode }, |
||
1987 | { Bad_Opcode }, |
||
6324 | serge | 1988 | { "vrcp14p%XW", { XM, EXx }, 0 }, |
5221 | serge | 1989 | }, |
1990 | /* PREFIX_EVEX_0F384D */ |
||
1991 | { |
||
1992 | { Bad_Opcode }, |
||
1993 | { Bad_Opcode }, |
||
6324 | serge | 1994 | { "vrcp14s%XW", { XMScalar, VexScalar, EXxmm_mdq }, 0 }, |
5221 | serge | 1995 | }, |
1996 | /* PREFIX_EVEX_0F384E */ |
||
1997 | { |
||
1998 | { Bad_Opcode }, |
||
1999 | { Bad_Opcode }, |
||
6324 | serge | 2000 | { "vrsqrt14p%XW", { XM, EXx }, 0 }, |
5221 | serge | 2001 | }, |
2002 | /* PREFIX_EVEX_0F384F */ |
||
2003 | { |
||
2004 | { Bad_Opcode }, |
||
2005 | { Bad_Opcode }, |
||
6324 | serge | 2006 | { "vrsqrt14s%XW", { XMScalar, VexScalar, EXxmm_mdq }, 0 }, |
5221 | serge | 2007 | }, |
2008 | /* PREFIX_EVEX_0F3858 */ |
||
2009 | { |
||
2010 | { Bad_Opcode }, |
||
2011 | { Bad_Opcode }, |
||
2012 | { VEX_W_TABLE (EVEX_W_0F3858_P_2) }, |
||
2013 | }, |
||
2014 | /* PREFIX_EVEX_0F3859 */ |
||
2015 | { |
||
2016 | { Bad_Opcode }, |
||
2017 | { Bad_Opcode }, |
||
2018 | { VEX_W_TABLE (EVEX_W_0F3859_P_2) }, |
||
2019 | }, |
||
2020 | /* PREFIX_EVEX_0F385A */ |
||
2021 | { |
||
2022 | { Bad_Opcode }, |
||
2023 | { Bad_Opcode }, |
||
2024 | { VEX_W_TABLE (EVEX_W_0F385A_P_2) }, |
||
2025 | }, |
||
2026 | /* PREFIX_EVEX_0F385B */ |
||
2027 | { |
||
2028 | { Bad_Opcode }, |
||
2029 | { Bad_Opcode }, |
||
2030 | { VEX_W_TABLE (EVEX_W_0F385B_P_2) }, |
||
2031 | }, |
||
2032 | /* PREFIX_EVEX_0F3864 */ |
||
2033 | { |
||
2034 | { Bad_Opcode }, |
||
2035 | { Bad_Opcode }, |
||
6324 | serge | 2036 | { "vpblendm%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2037 | }, |
2038 | /* PREFIX_EVEX_0F3865 */ |
||
2039 | { |
||
2040 | { Bad_Opcode }, |
||
2041 | { Bad_Opcode }, |
||
6324 | serge | 2042 | { "vblendmp%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2043 | }, |
6324 | serge | 2044 | /* PREFIX_EVEX_0F3866 */ |
2045 | { |
||
2046 | { Bad_Opcode }, |
||
2047 | { Bad_Opcode }, |
||
2048 | { VEX_W_TABLE (EVEX_W_0F3866_P_2) }, |
||
2049 | }, |
||
2050 | /* PREFIX_EVEX_0F3875 */ |
||
2051 | { |
||
2052 | { Bad_Opcode }, |
||
2053 | { Bad_Opcode }, |
||
2054 | { VEX_W_TABLE (EVEX_W_0F3875_P_2) }, |
||
2055 | }, |
||
5221 | serge | 2056 | /* PREFIX_EVEX_0F3876 */ |
2057 | { |
||
2058 | { Bad_Opcode }, |
||
2059 | { Bad_Opcode }, |
||
6324 | serge | 2060 | { "vpermi2%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2061 | }, |
2062 | /* PREFIX_EVEX_0F3877 */ |
||
2063 | { |
||
2064 | { Bad_Opcode }, |
||
2065 | { Bad_Opcode }, |
||
6324 | serge | 2066 | { "vpermi2p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2067 | }, |
6324 | serge | 2068 | /* PREFIX_EVEX_0F3878 */ |
2069 | { |
||
2070 | { Bad_Opcode }, |
||
2071 | { Bad_Opcode }, |
||
2072 | { VEX_W_TABLE (EVEX_W_0F3878_P_2) }, |
||
2073 | }, |
||
2074 | /* PREFIX_EVEX_0F3879 */ |
||
2075 | { |
||
2076 | { Bad_Opcode }, |
||
2077 | { Bad_Opcode }, |
||
2078 | { VEX_W_TABLE (EVEX_W_0F3879_P_2) }, |
||
2079 | }, |
||
2080 | /* PREFIX_EVEX_0F387A */ |
||
2081 | { |
||
2082 | { Bad_Opcode }, |
||
2083 | { Bad_Opcode }, |
||
2084 | { VEX_W_TABLE (EVEX_W_0F387A_P_2) }, |
||
2085 | }, |
||
2086 | /* PREFIX_EVEX_0F387B */ |
||
2087 | { |
||
2088 | { Bad_Opcode }, |
||
2089 | { Bad_Opcode }, |
||
2090 | { VEX_W_TABLE (EVEX_W_0F387B_P_2) }, |
||
2091 | }, |
||
5221 | serge | 2092 | /* PREFIX_EVEX_0F387C */ |
2093 | { |
||
2094 | { Bad_Opcode }, |
||
2095 | { Bad_Opcode }, |
||
6324 | serge | 2096 | { "vpbroadcast%LW", { XM, Rdq }, 0 }, |
5221 | serge | 2097 | }, |
6324 | serge | 2098 | /* PREFIX_EVEX_0F387D */ |
2099 | { |
||
2100 | { Bad_Opcode }, |
||
2101 | { Bad_Opcode }, |
||
2102 | { VEX_W_TABLE (EVEX_W_0F387D_P_2) }, |
||
2103 | }, |
||
5221 | serge | 2104 | /* PREFIX_EVEX_0F387E */ |
2105 | { |
||
2106 | { Bad_Opcode }, |
||
2107 | { Bad_Opcode }, |
||
6324 | serge | 2108 | { "vpermt2%LW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2109 | }, |
2110 | /* PREFIX_EVEX_0F387F */ |
||
2111 | { |
||
2112 | { Bad_Opcode }, |
||
2113 | { Bad_Opcode }, |
||
6324 | serge | 2114 | { "vpermt2p%XW", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2115 | }, |
6324 | serge | 2116 | /* PREFIX_EVEX_0F3883 */ |
2117 | { |
||
2118 | { Bad_Opcode }, |
||
2119 | { Bad_Opcode }, |
||
2120 | { VEX_W_TABLE (EVEX_W_0F3883_P_2) }, |
||
2121 | }, |
||
5221 | serge | 2122 | /* PREFIX_EVEX_0F3888 */ |
2123 | { |
||
2124 | { Bad_Opcode }, |
||
2125 | { Bad_Opcode }, |
||
6324 | serge | 2126 | { "vexpandp%XW", { XM, EXEvexXGscat }, 0 }, |
5221 | serge | 2127 | }, |
2128 | /* PREFIX_EVEX_0F3889 */ |
||
2129 | { |
||
2130 | { Bad_Opcode }, |
||
2131 | { Bad_Opcode }, |
||
6324 | serge | 2132 | { "vpexpand%LW", { XM, EXEvexXGscat }, 0 }, |
5221 | serge | 2133 | }, |
2134 | /* PREFIX_EVEX_0F388A */ |
||
2135 | { |
||
2136 | { Bad_Opcode }, |
||
2137 | { Bad_Opcode }, |
||
6324 | serge | 2138 | { "vcompressp%XW", { EXEvexXGscat, XM }, 0 }, |
5221 | serge | 2139 | }, |
2140 | /* PREFIX_EVEX_0F388B */ |
||
2141 | { |
||
2142 | { Bad_Opcode }, |
||
2143 | { Bad_Opcode }, |
||
6324 | serge | 2144 | { "vpcompress%LW", { EXEvexXGscat, XM }, 0 }, |
5221 | serge | 2145 | }, |
6324 | serge | 2146 | /* PREFIX_EVEX_0F388D */ |
2147 | { |
||
2148 | { Bad_Opcode }, |
||
2149 | { Bad_Opcode }, |
||
2150 | { VEX_W_TABLE (EVEX_W_0F388D_P_2) }, |
||
2151 | }, |
||
5221 | serge | 2152 | /* PREFIX_EVEX_0F3890 */ |
2153 | { |
||
2154 | { Bad_Opcode }, |
||
2155 | { Bad_Opcode }, |
||
6324 | serge | 2156 | { "vpgatherd%LW", { XM, MVexVSIBDWpX }, 0 }, |
5221 | serge | 2157 | }, |
2158 | /* PREFIX_EVEX_0F3891 */ |
||
2159 | { |
||
2160 | { Bad_Opcode }, |
||
2161 | { Bad_Opcode }, |
||
2162 | { VEX_W_TABLE (EVEX_W_0F3891_P_2) }, |
||
2163 | }, |
||
2164 | /* PREFIX_EVEX_0F3892 */ |
||
2165 | { |
||
2166 | { Bad_Opcode }, |
||
2167 | { Bad_Opcode }, |
||
6324 | serge | 2168 | { "vgatherdp%XW", { XM, MVexVSIBDWpX}, 0 }, |
5221 | serge | 2169 | }, |
2170 | /* PREFIX_EVEX_0F3893 */ |
||
2171 | { |
||
2172 | { Bad_Opcode }, |
||
2173 | { Bad_Opcode }, |
||
2174 | { VEX_W_TABLE (EVEX_W_0F3893_P_2) }, |
||
2175 | }, |
||
2176 | /* PREFIX_EVEX_0F3896 */ |
||
2177 | { |
||
2178 | { Bad_Opcode }, |
||
2179 | { Bad_Opcode }, |
||
6324 | serge | 2180 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2181 | }, |
2182 | /* PREFIX_EVEX_0F3897 */ |
||
2183 | { |
||
2184 | { Bad_Opcode }, |
||
2185 | { Bad_Opcode }, |
||
6324 | serge | 2186 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2187 | }, |
2188 | /* PREFIX_EVEX_0F3898 */ |
||
2189 | { |
||
2190 | { Bad_Opcode }, |
||
2191 | { Bad_Opcode }, |
||
6324 | serge | 2192 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2193 | }, |
2194 | /* PREFIX_EVEX_0F3899 */ |
||
2195 | { |
||
2196 | { Bad_Opcode }, |
||
2197 | { Bad_Opcode }, |
||
6324 | serge | 2198 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2199 | }, |
2200 | /* PREFIX_EVEX_0F389A */ |
||
2201 | { |
||
2202 | { Bad_Opcode }, |
||
2203 | { Bad_Opcode }, |
||
6324 | serge | 2204 | { "vfmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2205 | }, |
2206 | /* PREFIX_EVEX_0F389B */ |
||
2207 | { |
||
2208 | { Bad_Opcode }, |
||
2209 | { Bad_Opcode }, |
||
6324 | serge | 2210 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2211 | }, |
2212 | /* PREFIX_EVEX_0F389C */ |
||
2213 | { |
||
2214 | { Bad_Opcode }, |
||
2215 | { Bad_Opcode }, |
||
6324 | serge | 2216 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2217 | }, |
2218 | /* PREFIX_EVEX_0F389D */ |
||
2219 | { |
||
2220 | { Bad_Opcode }, |
||
2221 | { Bad_Opcode }, |
||
6324 | serge | 2222 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2223 | }, |
2224 | /* PREFIX_EVEX_0F389E */ |
||
2225 | { |
||
2226 | { Bad_Opcode }, |
||
2227 | { Bad_Opcode }, |
||
6324 | serge | 2228 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2229 | }, |
2230 | /* PREFIX_EVEX_0F389F */ |
||
2231 | { |
||
2232 | { Bad_Opcode }, |
||
2233 | { Bad_Opcode }, |
||
6324 | serge | 2234 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2235 | }, |
2236 | /* PREFIX_EVEX_0F38A0 */ |
||
2237 | { |
||
2238 | { Bad_Opcode }, |
||
2239 | { Bad_Opcode }, |
||
6324 | serge | 2240 | { "vpscatterd%LW", { MVexVSIBDWpX, XM }, 0 }, |
5221 | serge | 2241 | }, |
2242 | /* PREFIX_EVEX_0F38A1 */ |
||
2243 | { |
||
2244 | { Bad_Opcode }, |
||
2245 | { Bad_Opcode }, |
||
2246 | { VEX_W_TABLE (EVEX_W_0F38A1_P_2) }, |
||
2247 | }, |
||
2248 | /* PREFIX_EVEX_0F38A2 */ |
||
2249 | { |
||
2250 | { Bad_Opcode }, |
||
2251 | { Bad_Opcode }, |
||
6324 | serge | 2252 | { "vscatterdp%XW", { MVexVSIBDWpX, XM }, 0 }, |
5221 | serge | 2253 | }, |
2254 | /* PREFIX_EVEX_0F38A3 */ |
||
2255 | { |
||
2256 | { Bad_Opcode }, |
||
2257 | { Bad_Opcode }, |
||
2258 | { VEX_W_TABLE (EVEX_W_0F38A3_P_2) }, |
||
2259 | }, |
||
2260 | /* PREFIX_EVEX_0F38A6 */ |
||
2261 | { |
||
2262 | { Bad_Opcode }, |
||
2263 | { Bad_Opcode }, |
||
6324 | serge | 2264 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2265 | }, |
2266 | /* PREFIX_EVEX_0F38A7 */ |
||
2267 | { |
||
2268 | { Bad_Opcode }, |
||
2269 | { Bad_Opcode }, |
||
6324 | serge | 2270 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2271 | }, |
2272 | /* PREFIX_EVEX_0F38A8 */ |
||
2273 | { |
||
2274 | { Bad_Opcode }, |
||
2275 | { Bad_Opcode }, |
||
6324 | serge | 2276 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2277 | }, |
2278 | /* PREFIX_EVEX_0F38A9 */ |
||
2279 | { |
||
2280 | { Bad_Opcode }, |
||
2281 | { Bad_Opcode }, |
||
6324 | serge | 2282 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2283 | }, |
2284 | /* PREFIX_EVEX_0F38AA */ |
||
2285 | { |
||
2286 | { Bad_Opcode }, |
||
2287 | { Bad_Opcode }, |
||
6324 | serge | 2288 | { "vfmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2289 | }, |
2290 | /* PREFIX_EVEX_0F38AB */ |
||
2291 | { |
||
2292 | { Bad_Opcode }, |
||
2293 | { Bad_Opcode }, |
||
6324 | serge | 2294 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2295 | }, |
2296 | /* PREFIX_EVEX_0F38AC */ |
||
2297 | { |
||
2298 | { Bad_Opcode }, |
||
2299 | { Bad_Opcode }, |
||
6324 | serge | 2300 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2301 | }, |
2302 | /* PREFIX_EVEX_0F38AD */ |
||
2303 | { |
||
2304 | { Bad_Opcode }, |
||
2305 | { Bad_Opcode }, |
||
6324 | serge | 2306 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2307 | }, |
2308 | /* PREFIX_EVEX_0F38AE */ |
||
2309 | { |
||
2310 | { Bad_Opcode }, |
||
2311 | { Bad_Opcode }, |
||
6324 | serge | 2312 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2313 | }, |
2314 | /* PREFIX_EVEX_0F38AF */ |
||
2315 | { |
||
2316 | { Bad_Opcode }, |
||
2317 | { Bad_Opcode }, |
||
6324 | serge | 2318 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2319 | }, |
6324 | serge | 2320 | /* PREFIX_EVEX_0F38B4 */ |
2321 | { |
||
2322 | { Bad_Opcode }, |
||
2323 | { Bad_Opcode }, |
||
2324 | { "vpmadd52luq", { XM, Vex, EXx }, 0 }, |
||
2325 | }, |
||
2326 | /* PREFIX_EVEX_0F38B5 */ |
||
2327 | { |
||
2328 | { Bad_Opcode }, |
||
2329 | { Bad_Opcode }, |
||
2330 | { "vpmadd52huq", { XM, Vex, EXx }, 0 }, |
||
2331 | }, |
||
5221 | serge | 2332 | /* PREFIX_EVEX_0F38B6 */ |
2333 | { |
||
2334 | { Bad_Opcode }, |
||
2335 | { Bad_Opcode }, |
||
6324 | serge | 2336 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2337 | }, |
2338 | /* PREFIX_EVEX_0F38B7 */ |
||
2339 | { |
||
2340 | { Bad_Opcode }, |
||
2341 | { Bad_Opcode }, |
||
6324 | serge | 2342 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2343 | }, |
2344 | /* PREFIX_EVEX_0F38B8 */ |
||
2345 | { |
||
2346 | { Bad_Opcode }, |
||
2347 | { Bad_Opcode }, |
||
6324 | serge | 2348 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2349 | }, |
2350 | /* PREFIX_EVEX_0F38B9 */ |
||
2351 | { |
||
2352 | { Bad_Opcode }, |
||
2353 | { Bad_Opcode }, |
||
6324 | serge | 2354 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2355 | }, |
2356 | /* PREFIX_EVEX_0F38BA */ |
||
2357 | { |
||
2358 | { Bad_Opcode }, |
||
2359 | { Bad_Opcode }, |
||
6324 | serge | 2360 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2361 | }, |
2362 | /* PREFIX_EVEX_0F38BB */ |
||
2363 | { |
||
2364 | { Bad_Opcode }, |
||
2365 | { Bad_Opcode }, |
||
6324 | serge | 2366 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2367 | }, |
2368 | /* PREFIX_EVEX_0F38BC */ |
||
2369 | { |
||
2370 | { Bad_Opcode }, |
||
2371 | { Bad_Opcode }, |
||
6324 | serge | 2372 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2373 | }, |
2374 | /* PREFIX_EVEX_0F38BD */ |
||
2375 | { |
||
2376 | { Bad_Opcode }, |
||
2377 | { Bad_Opcode }, |
||
6324 | serge | 2378 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2379 | }, |
2380 | /* PREFIX_EVEX_0F38BE */ |
||
2381 | { |
||
2382 | { Bad_Opcode }, |
||
2383 | { Bad_Opcode }, |
||
6324 | serge | 2384 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2385 | }, |
2386 | /* PREFIX_EVEX_0F38BF */ |
||
2387 | { |
||
2388 | { Bad_Opcode }, |
||
2389 | { Bad_Opcode }, |
||
6324 | serge | 2390 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR }, 0 }, |
5221 | serge | 2391 | }, |
2392 | /* PREFIX_EVEX_0F38C4 */ |
||
2393 | { |
||
2394 | { Bad_Opcode }, |
||
2395 | { Bad_Opcode }, |
||
6324 | serge | 2396 | { "vpconflict%LW", { XM, EXx }, 0 }, |
5221 | serge | 2397 | }, |
2398 | /* PREFIX_EVEX_0F38C6_REG_1 */ |
||
2399 | { |
||
2400 | { Bad_Opcode }, |
||
2401 | { Bad_Opcode }, |
||
6324 | serge | 2402 | { "vgatherpf0dp%XW", { MVexVSIBDWpX }, 0 }, |
5221 | serge | 2403 | }, |
2404 | /* PREFIX_EVEX_0F38C6_REG_2 */ |
||
2405 | { |
||
2406 | { Bad_Opcode }, |
||
2407 | { Bad_Opcode }, |
||
6324 | serge | 2408 | { "vgatherpf1dp%XW", { MVexVSIBDWpX }, 0 }, |
5221 | serge | 2409 | }, |
2410 | /* PREFIX_EVEX_0F38C6_REG_5 */ |
||
2411 | { |
||
2412 | { Bad_Opcode }, |
||
2413 | { Bad_Opcode }, |
||
6324 | serge | 2414 | { "vscatterpf0dp%XW", { MVexVSIBDWpX }, 0 }, |
5221 | serge | 2415 | }, |
2416 | /* PREFIX_EVEX_0F38C6_REG_6 */ |
||
2417 | { |
||
2418 | { Bad_Opcode }, |
||
2419 | { Bad_Opcode }, |
||
6324 | serge | 2420 | { "vscatterpf1dp%XW", { MVexVSIBDWpX }, 0 }, |
5221 | serge | 2421 | }, |
2422 | /* PREFIX_EVEX_0F38C7_REG_1 */ |
||
2423 | { |
||
2424 | { Bad_Opcode }, |
||
2425 | { Bad_Opcode }, |
||
2426 | { VEX_W_TABLE (EVEX_W_0F38C7_R_1_P_2) }, |
||
2427 | }, |
||
2428 | /* PREFIX_EVEX_0F38C7_REG_2 */ |
||
2429 | { |
||
2430 | { Bad_Opcode }, |
||
2431 | { Bad_Opcode }, |
||
2432 | { VEX_W_TABLE (EVEX_W_0F38C7_R_2_P_2) }, |
||
2433 | }, |
||
2434 | /* PREFIX_EVEX_0F38C7_REG_5 */ |
||
2435 | { |
||
2436 | { Bad_Opcode }, |
||
2437 | { Bad_Opcode }, |
||
2438 | { VEX_W_TABLE (EVEX_W_0F38C7_R_5_P_2) }, |
||
2439 | }, |
||
2440 | /* PREFIX_EVEX_0F38C7_REG_6 */ |
||
2441 | { |
||
2442 | { Bad_Opcode }, |
||
2443 | { Bad_Opcode }, |
||
2444 | { VEX_W_TABLE (EVEX_W_0F38C7_R_6_P_2) }, |
||
2445 | }, |
||
2446 | /* PREFIX_EVEX_0F38C8 */ |
||
2447 | { |
||
2448 | { Bad_Opcode }, |
||
2449 | { Bad_Opcode }, |
||
6324 | serge | 2450 | { "vexp2p%XW", { XM, EXx, EXxEVexS }, 0 }, |
5221 | serge | 2451 | }, |
2452 | /* PREFIX_EVEX_0F38CA */ |
||
2453 | { |
||
2454 | { Bad_Opcode }, |
||
2455 | { Bad_Opcode }, |
||
6324 | serge | 2456 | { "vrcp28p%XW", { XM, EXx, EXxEVexS }, 0 }, |
5221 | serge | 2457 | }, |
2458 | /* PREFIX_EVEX_0F38CB */ |
||
2459 | { |
||
2460 | { Bad_Opcode }, |
||
2461 | { Bad_Opcode }, |
||
6324 | serge | 2462 | { "vrcp28s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexS }, 0 }, |
5221 | serge | 2463 | }, |
2464 | /* PREFIX_EVEX_0F38CC */ |
||
2465 | { |
||
2466 | { Bad_Opcode }, |
||
2467 | { Bad_Opcode }, |
||
6324 | serge | 2468 | { "vrsqrt28p%XW", { XM, EXx, EXxEVexS }, 0 }, |
5221 | serge | 2469 | }, |
2470 | /* PREFIX_EVEX_0F38CD */ |
||
2471 | { |
||
2472 | { Bad_Opcode }, |
||
2473 | { Bad_Opcode }, |
||
6324 | serge | 2474 | { "vrsqrt28s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexS }, 0 }, |
5221 | serge | 2475 | }, |
2476 | /* PREFIX_EVEX_0F3A00 */ |
||
2477 | { |
||
2478 | { Bad_Opcode }, |
||
2479 | { Bad_Opcode }, |
||
2480 | { VEX_W_TABLE (EVEX_W_0F3A00_P_2) }, |
||
2481 | }, |
||
2482 | /* PREFIX_EVEX_0F3A01 */ |
||
2483 | { |
||
2484 | { Bad_Opcode }, |
||
2485 | { Bad_Opcode }, |
||
2486 | { VEX_W_TABLE (EVEX_W_0F3A01_P_2) }, |
||
2487 | }, |
||
2488 | /* PREFIX_EVEX_0F3A03 */ |
||
2489 | { |
||
2490 | { Bad_Opcode }, |
||
2491 | { Bad_Opcode }, |
||
6324 | serge | 2492 | { "valign%LW", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 2493 | }, |
2494 | /* PREFIX_EVEX_0F3A04 */ |
||
2495 | { |
||
2496 | { Bad_Opcode }, |
||
2497 | { Bad_Opcode }, |
||
2498 | { VEX_W_TABLE (EVEX_W_0F3A04_P_2) }, |
||
2499 | }, |
||
2500 | /* PREFIX_EVEX_0F3A05 */ |
||
2501 | { |
||
2502 | { Bad_Opcode }, |
||
2503 | { Bad_Opcode }, |
||
2504 | { VEX_W_TABLE (EVEX_W_0F3A05_P_2) }, |
||
2505 | }, |
||
2506 | /* PREFIX_EVEX_0F3A08 */ |
||
2507 | { |
||
2508 | { Bad_Opcode }, |
||
2509 | { Bad_Opcode }, |
||
2510 | { VEX_W_TABLE (EVEX_W_0F3A08_P_2) }, |
||
2511 | }, |
||
2512 | /* PREFIX_EVEX_0F3A09 */ |
||
2513 | { |
||
2514 | { Bad_Opcode }, |
||
2515 | { Bad_Opcode }, |
||
2516 | { VEX_W_TABLE (EVEX_W_0F3A09_P_2) }, |
||
2517 | }, |
||
2518 | /* PREFIX_EVEX_0F3A0A */ |
||
2519 | { |
||
2520 | { Bad_Opcode }, |
||
2521 | { Bad_Opcode }, |
||
2522 | { VEX_W_TABLE (EVEX_W_0F3A0A_P_2) }, |
||
2523 | }, |
||
2524 | /* PREFIX_EVEX_0F3A0B */ |
||
2525 | { |
||
2526 | { Bad_Opcode }, |
||
2527 | { Bad_Opcode }, |
||
2528 | { VEX_W_TABLE (EVEX_W_0F3A0B_P_2) }, |
||
2529 | }, |
||
6324 | serge | 2530 | /* PREFIX_EVEX_0F3A0F */ |
2531 | { |
||
2532 | { Bad_Opcode }, |
||
2533 | { Bad_Opcode }, |
||
2534 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
||
2535 | }, |
||
2536 | /* PREFIX_EVEX_0F3A14 */ |
||
2537 | { |
||
2538 | { Bad_Opcode }, |
||
2539 | { Bad_Opcode }, |
||
2540 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
||
2541 | }, |
||
2542 | /* PREFIX_EVEX_0F3A15 */ |
||
2543 | { |
||
2544 | { Bad_Opcode }, |
||
2545 | { Bad_Opcode }, |
||
2546 | { "vpextrw", { EdqwS, XM, Ib }, 0 }, |
||
2547 | }, |
||
2548 | /* PREFIX_EVEX_0F3A16 */ |
||
2549 | { |
||
2550 | { Bad_Opcode }, |
||
2551 | { Bad_Opcode }, |
||
2552 | { VEX_W_TABLE (EVEX_W_0F3A16_P_2) }, |
||
2553 | }, |
||
5221 | serge | 2554 | /* PREFIX_EVEX_0F3A17 */ |
2555 | { |
||
2556 | { Bad_Opcode }, |
||
2557 | { Bad_Opcode }, |
||
6324 | serge | 2558 | { "vextractps", { Edqd, XMM, Ib }, 0 }, |
5221 | serge | 2559 | }, |
2560 | /* PREFIX_EVEX_0F3A18 */ |
||
2561 | { |
||
2562 | { Bad_Opcode }, |
||
2563 | { Bad_Opcode }, |
||
2564 | { VEX_W_TABLE (EVEX_W_0F3A18_P_2) }, |
||
2565 | }, |
||
2566 | /* PREFIX_EVEX_0F3A19 */ |
||
2567 | { |
||
2568 | { Bad_Opcode }, |
||
2569 | { Bad_Opcode }, |
||
2570 | { VEX_W_TABLE (EVEX_W_0F3A19_P_2) }, |
||
2571 | }, |
||
2572 | /* PREFIX_EVEX_0F3A1A */ |
||
2573 | { |
||
2574 | { Bad_Opcode }, |
||
2575 | { Bad_Opcode }, |
||
2576 | { VEX_W_TABLE (EVEX_W_0F3A1A_P_2) }, |
||
2577 | }, |
||
2578 | /* PREFIX_EVEX_0F3A1B */ |
||
2579 | { |
||
2580 | { Bad_Opcode }, |
||
2581 | { Bad_Opcode }, |
||
2582 | { VEX_W_TABLE (EVEX_W_0F3A1B_P_2) }, |
||
2583 | }, |
||
2584 | /* PREFIX_EVEX_0F3A1D */ |
||
2585 | { |
||
2586 | { Bad_Opcode }, |
||
2587 | { Bad_Opcode }, |
||
2588 | { VEX_W_TABLE (EVEX_W_0F3A1D_P_2) }, |
||
2589 | }, |
||
2590 | /* PREFIX_EVEX_0F3A1E */ |
||
2591 | { |
||
2592 | { Bad_Opcode }, |
||
2593 | { Bad_Opcode }, |
||
6324 | serge | 2594 | { "vpcmpu%LW", { XMask, Vex, EXx, VPCMP }, 0 }, |
5221 | serge | 2595 | }, |
2596 | /* PREFIX_EVEX_0F3A1F */ |
||
2597 | { |
||
2598 | { Bad_Opcode }, |
||
2599 | { Bad_Opcode }, |
||
6324 | serge | 2600 | { "vpcmp%LW", { XMask, Vex, EXx, VPCMP }, 0 }, |
5221 | serge | 2601 | }, |
6324 | serge | 2602 | /* PREFIX_EVEX_0F3A20 */ |
2603 | { |
||
2604 | { Bad_Opcode }, |
||
2605 | { Bad_Opcode }, |
||
2606 | { "vpinsrb", { XM, Vex128, Edb, Ib }, 0 }, |
||
2607 | }, |
||
5221 | serge | 2608 | /* PREFIX_EVEX_0F3A21 */ |
2609 | { |
||
2610 | { Bad_Opcode }, |
||
2611 | { Bad_Opcode }, |
||
2612 | { VEX_W_TABLE (EVEX_W_0F3A21_P_2) }, |
||
2613 | }, |
||
6324 | serge | 2614 | /* PREFIX_EVEX_0F3A22 */ |
2615 | { |
||
2616 | { Bad_Opcode }, |
||
2617 | { Bad_Opcode }, |
||
2618 | { VEX_W_TABLE (EVEX_W_0F3A22_P_2) }, |
||
2619 | }, |
||
5221 | serge | 2620 | /* PREFIX_EVEX_0F3A23 */ |
2621 | { |
||
2622 | { Bad_Opcode }, |
||
2623 | { Bad_Opcode }, |
||
2624 | { VEX_W_TABLE (EVEX_W_0F3A23_P_2) }, |
||
2625 | }, |
||
2626 | /* PREFIX_EVEX_0F3A25 */ |
||
2627 | { |
||
2628 | { Bad_Opcode }, |
||
2629 | { Bad_Opcode }, |
||
6324 | serge | 2630 | { "vpternlog%LW", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 2631 | }, |
2632 | /* PREFIX_EVEX_0F3A26 */ |
||
2633 | { |
||
2634 | { Bad_Opcode }, |
||
2635 | { Bad_Opcode }, |
||
6324 | serge | 2636 | { "vgetmantp%XW", { XM, EXx, EXxEVexS, Ib }, 0 }, |
5221 | serge | 2637 | }, |
2638 | /* PREFIX_EVEX_0F3A27 */ |
||
2639 | { |
||
2640 | { Bad_Opcode }, |
||
2641 | { Bad_Opcode }, |
||
6324 | serge | 2642 | { "vgetmants%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexS, Ib }, 0 }, |
5221 | serge | 2643 | }, |
2644 | /* PREFIX_EVEX_0F3A38 */ |
||
2645 | { |
||
2646 | { Bad_Opcode }, |
||
2647 | { Bad_Opcode }, |
||
2648 | { VEX_W_TABLE (EVEX_W_0F3A38_P_2) }, |
||
2649 | }, |
||
2650 | /* PREFIX_EVEX_0F3A39 */ |
||
2651 | { |
||
2652 | { Bad_Opcode }, |
||
2653 | { Bad_Opcode }, |
||
2654 | { VEX_W_TABLE (EVEX_W_0F3A39_P_2) }, |
||
2655 | }, |
||
2656 | /* PREFIX_EVEX_0F3A3A */ |
||
2657 | { |
||
2658 | { Bad_Opcode }, |
||
2659 | { Bad_Opcode }, |
||
2660 | { VEX_W_TABLE (EVEX_W_0F3A3A_P_2) }, |
||
2661 | }, |
||
2662 | /* PREFIX_EVEX_0F3A3B */ |
||
2663 | { |
||
2664 | { Bad_Opcode }, |
||
2665 | { Bad_Opcode }, |
||
2666 | { VEX_W_TABLE (EVEX_W_0F3A3B_P_2) }, |
||
2667 | }, |
||
6324 | serge | 2668 | /* PREFIX_EVEX_0F3A3E */ |
2669 | { |
||
2670 | { Bad_Opcode }, |
||
2671 | { Bad_Opcode }, |
||
2672 | { VEX_W_TABLE (EVEX_W_0F3A3E_P_2) }, |
||
2673 | }, |
||
2674 | /* PREFIX_EVEX_0F3A3F */ |
||
2675 | { |
||
2676 | { Bad_Opcode }, |
||
2677 | { Bad_Opcode }, |
||
2678 | { VEX_W_TABLE (EVEX_W_0F3A3F_P_2) }, |
||
2679 | }, |
||
2680 | /* PREFIX_EVEX_0F3A42 */ |
||
2681 | { |
||
2682 | { Bad_Opcode }, |
||
2683 | { Bad_Opcode }, |
||
2684 | { VEX_W_TABLE (EVEX_W_0F3A42_P_2) }, |
||
2685 | }, |
||
5221 | serge | 2686 | /* PREFIX_EVEX_0F3A43 */ |
2687 | { |
||
2688 | { Bad_Opcode }, |
||
2689 | { Bad_Opcode }, |
||
2690 | { VEX_W_TABLE (EVEX_W_0F3A43_P_2) }, |
||
2691 | }, |
||
6324 | serge | 2692 | /* PREFIX_EVEX_0F3A50 */ |
2693 | { |
||
2694 | { Bad_Opcode }, |
||
2695 | { Bad_Opcode }, |
||
2696 | { VEX_W_TABLE (EVEX_W_0F3A50_P_2) }, |
||
2697 | }, |
||
2698 | /* PREFIX_EVEX_0F3A51 */ |
||
2699 | { |
||
2700 | { Bad_Opcode }, |
||
2701 | { Bad_Opcode }, |
||
2702 | { VEX_W_TABLE (EVEX_W_0F3A51_P_2) }, |
||
2703 | }, |
||
5221 | serge | 2704 | /* PREFIX_EVEX_0F3A54 */ |
2705 | { |
||
2706 | { Bad_Opcode }, |
||
2707 | { Bad_Opcode }, |
||
6324 | serge | 2708 | { "vfixupimmp%XW", { XM, Vex, EXx, EXxEVexS, Ib }, 0 }, |
5221 | serge | 2709 | }, |
2710 | /* PREFIX_EVEX_0F3A55 */ |
||
2711 | { |
||
2712 | { Bad_Opcode }, |
||
2713 | { Bad_Opcode }, |
||
6324 | serge | 2714 | { "vfixupimms%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexS, Ib }, 0 }, |
5221 | serge | 2715 | }, |
6324 | serge | 2716 | /* PREFIX_EVEX_0F3A56 */ |
2717 | { |
||
2718 | { Bad_Opcode }, |
||
2719 | { Bad_Opcode }, |
||
2720 | { VEX_W_TABLE (EVEX_W_0F3A56_P_2) }, |
||
2721 | }, |
||
2722 | /* PREFIX_EVEX_0F3A57 */ |
||
2723 | { |
||
2724 | { Bad_Opcode }, |
||
2725 | { Bad_Opcode }, |
||
2726 | { VEX_W_TABLE (EVEX_W_0F3A57_P_2) }, |
||
2727 | }, |
||
2728 | /* PREFIX_EVEX_0F3A66 */ |
||
2729 | { |
||
2730 | { Bad_Opcode }, |
||
2731 | { Bad_Opcode }, |
||
2732 | { VEX_W_TABLE (EVEX_W_0F3A66_P_2) }, |
||
2733 | }, |
||
2734 | /* PREFIX_EVEX_0F3A67 */ |
||
2735 | { |
||
2736 | { Bad_Opcode }, |
||
2737 | { Bad_Opcode }, |
||
2738 | { VEX_W_TABLE (EVEX_W_0F3A67_P_2) }, |
||
2739 | }, |
||
5221 | serge | 2740 | #endif /* NEED_PREFIX_TABLE */ |
2741 | |||
2742 | #ifdef NEED_VEX_W_TABLE |
||
2743 | /* EVEX_W_0F10_P_0 */ |
||
2744 | { |
||
6324 | serge | 2745 | { "vmovups", { XM, EXEvexXNoBcst }, 0 }, |
5221 | serge | 2746 | }, |
2747 | /* EVEX_W_0F10_P_1_M_0 */ |
||
2748 | { |
||
6324 | serge | 2749 | { "vmovss", { XMScalar, EXdScalar }, 0 }, |
5221 | serge | 2750 | }, |
2751 | /* EVEX_W_0F10_P_1_M_1 */ |
||
2752 | { |
||
6324 | serge | 2753 | { "vmovss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
5221 | serge | 2754 | }, |
2755 | /* EVEX_W_0F10_P_2 */ |
||
2756 | { |
||
2757 | { Bad_Opcode }, |
||
6324 | serge | 2758 | { "vmovupd", { XM, EXEvexXNoBcst }, 0 }, |
5221 | serge | 2759 | }, |
2760 | /* EVEX_W_0F10_P_3_M_0 */ |
||
2761 | { |
||
2762 | { Bad_Opcode }, |
||
6324 | serge | 2763 | { "vmovsd", { XMScalar, EXqScalar }, 0 }, |
5221 | serge | 2764 | }, |
2765 | /* EVEX_W_0F10_P_3_M_1 */ |
||
2766 | { |
||
2767 | { Bad_Opcode }, |
||
6324 | serge | 2768 | { "vmovsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
5221 | serge | 2769 | }, |
2770 | /* EVEX_W_0F11_P_0 */ |
||
2771 | { |
||
6324 | serge | 2772 | { "vmovups", { EXxS, XM }, 0 }, |
5221 | serge | 2773 | }, |
2774 | /* EVEX_W_0F11_P_1_M_0 */ |
||
2775 | { |
||
6324 | serge | 2776 | { "vmovss", { EXdScalarS, XMScalar }, 0 }, |
5221 | serge | 2777 | }, |
2778 | /* EVEX_W_0F11_P_1_M_1 */ |
||
2779 | { |
||
6324 | serge | 2780 | { "vmovss", { EXxS, Vex, XMScalar }, 0 }, |
5221 | serge | 2781 | }, |
2782 | /* EVEX_W_0F11_P_2 */ |
||
2783 | { |
||
2784 | { Bad_Opcode }, |
||
6324 | serge | 2785 | { "vmovupd", { EXxS, XM }, 0 }, |
5221 | serge | 2786 | }, |
2787 | /* EVEX_W_0F11_P_3_M_0 */ |
||
2788 | { |
||
2789 | { Bad_Opcode }, |
||
6324 | serge | 2790 | { "vmovsd", { EXqScalarS, XMScalar }, 0 }, |
5221 | serge | 2791 | }, |
2792 | /* EVEX_W_0F11_P_3_M_1 */ |
||
2793 | { |
||
2794 | { Bad_Opcode }, |
||
6324 | serge | 2795 | { "vmovsd", { EXxS, Vex, XMScalar }, 0 }, |
5221 | serge | 2796 | }, |
2797 | /* EVEX_W_0F12_P_0_M_0 */ |
||
2798 | { |
||
6324 | serge | 2799 | { "vmovlps", { XMM, Vex, EXxmm_mq }, 0 }, |
5221 | serge | 2800 | }, |
2801 | /* EVEX_W_0F12_P_0_M_1 */ |
||
2802 | { |
||
6324 | serge | 2803 | { "vmovhlps", { XMM, Vex, EXxmm_mq }, 0 }, |
5221 | serge | 2804 | }, |
2805 | /* EVEX_W_0F12_P_1 */ |
||
2806 | { |
||
6324 | serge | 2807 | { "vmovsldup", { XM, EXEvexXNoBcst }, 0 }, |
5221 | serge | 2808 | }, |
2809 | /* EVEX_W_0F12_P_2 */ |
||
2810 | { |
||
2811 | { Bad_Opcode }, |
||
6324 | serge | 2812 | { "vmovlpd", { XMM, Vex, EXxmm_mq }, 0 }, |
5221 | serge | 2813 | }, |
2814 | /* EVEX_W_0F12_P_3 */ |
||
2815 | { |
||
2816 | { Bad_Opcode }, |
||
6324 | serge | 2817 | { "vmovddup", { XM, EXymmq }, 0 }, |
5221 | serge | 2818 | }, |
2819 | /* EVEX_W_0F13_P_0 */ |
||
2820 | { |
||
6324 | serge | 2821 | { "vmovlps", { EXxmm_mq, XMM }, 0 }, |
5221 | serge | 2822 | }, |
2823 | /* EVEX_W_0F13_P_2 */ |
||
2824 | { |
||
2825 | { Bad_Opcode }, |
||
6324 | serge | 2826 | { "vmovlpd", { EXxmm_mq, XMM }, 0 }, |
5221 | serge | 2827 | }, |
2828 | /* EVEX_W_0F14_P_0 */ |
||
2829 | { |
||
6324 | serge | 2830 | { "vunpcklps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2831 | }, |
2832 | /* EVEX_W_0F14_P_2 */ |
||
2833 | { |
||
2834 | { Bad_Opcode }, |
||
6324 | serge | 2835 | { "vunpcklpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2836 | }, |
2837 | /* EVEX_W_0F15_P_0 */ |
||
2838 | { |
||
6324 | serge | 2839 | { "vunpckhps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2840 | }, |
2841 | /* EVEX_W_0F15_P_2 */ |
||
2842 | { |
||
2843 | { Bad_Opcode }, |
||
6324 | serge | 2844 | { "vunpckhpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 2845 | }, |
2846 | /* EVEX_W_0F16_P_0_M_0 */ |
||
2847 | { |
||
6324 | serge | 2848 | { "vmovhps", { XMM, Vex, EXxmm_mq }, 0 }, |
5221 | serge | 2849 | }, |
2850 | /* EVEX_W_0F16_P_0_M_1 */ |
||
2851 | { |
||
6324 | serge | 2852 | { "vmovlhps", { XMM, Vex, EXx }, 0 }, |
5221 | serge | 2853 | }, |
2854 | /* EVEX_W_0F16_P_1 */ |
||
2855 | { |
||
6324 | serge | 2856 | { "vmovshdup", { XM, EXx }, 0 }, |
5221 | serge | 2857 | }, |
2858 | /* EVEX_W_0F16_P_2 */ |
||
2859 | { |
||
2860 | { Bad_Opcode }, |
||
6324 | serge | 2861 | { "vmovhpd", { XMM, Vex, EXxmm_mq }, 0 }, |
5221 | serge | 2862 | }, |
2863 | /* EVEX_W_0F17_P_0 */ |
||
2864 | { |
||
6324 | serge | 2865 | { "vmovhps", { EXxmm_mq, XMM }, 0 }, |
5221 | serge | 2866 | }, |
2867 | /* EVEX_W_0F17_P_2 */ |
||
2868 | { |
||
2869 | { Bad_Opcode }, |
||
6324 | serge | 2870 | { "vmovhpd", { EXxmm_mq, XMM }, 0 }, |
5221 | serge | 2871 | }, |
2872 | /* EVEX_W_0F28_P_0 */ |
||
2873 | { |
||
6324 | serge | 2874 | { "vmovaps", { XM, EXx }, 0 }, |
5221 | serge | 2875 | }, |
2876 | /* EVEX_W_0F28_P_2 */ |
||
2877 | { |
||
2878 | { Bad_Opcode }, |
||
6324 | serge | 2879 | { "vmovapd", { XM, EXx }, 0 }, |
5221 | serge | 2880 | }, |
2881 | /* EVEX_W_0F29_P_0 */ |
||
2882 | { |
||
6324 | serge | 2883 | { "vmovaps", { EXxS, XM }, 0 }, |
5221 | serge | 2884 | }, |
2885 | /* EVEX_W_0F29_P_2 */ |
||
2886 | { |
||
2887 | { Bad_Opcode }, |
||
6324 | serge | 2888 | { "vmovapd", { EXxS, XM }, 0 }, |
5221 | serge | 2889 | }, |
2890 | /* EVEX_W_0F2A_P_1 */ |
||
2891 | { |
||
6324 | serge | 2892 | { "vcvtsi2ss", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, |
2893 | { "vcvtsi2ss", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, |
||
5221 | serge | 2894 | }, |
2895 | /* EVEX_W_0F2A_P_3 */ |
||
2896 | { |
||
6324 | serge | 2897 | { "vcvtsi2sd", { XMScalar, VexScalar, Ed }, 0 }, |
2898 | { "vcvtsi2sd", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, |
||
5221 | serge | 2899 | }, |
2900 | /* EVEX_W_0F2B_P_0 */ |
||
2901 | { |
||
6324 | serge | 2902 | { "vmovntps", { EXx, XM }, 0 }, |
5221 | serge | 2903 | }, |
2904 | /* EVEX_W_0F2B_P_2 */ |
||
2905 | { |
||
2906 | { Bad_Opcode }, |
||
6324 | serge | 2907 | { "vmovntpd", { EXx, XM }, 0 }, |
5221 | serge | 2908 | }, |
2909 | /* EVEX_W_0F2E_P_0 */ |
||
2910 | { |
||
6324 | serge | 2911 | { "vucomiss", { XMScalar, EXxmm_md, EXxEVexS }, 0 }, |
5221 | serge | 2912 | }, |
2913 | /* EVEX_W_0F2E_P_2 */ |
||
2914 | { |
||
2915 | { Bad_Opcode }, |
||
6324 | serge | 2916 | { "vucomisd", { XMScalar, EXxmm_mq, EXxEVexS }, 0 }, |
5221 | serge | 2917 | }, |
2918 | /* EVEX_W_0F2F_P_0 */ |
||
2919 | { |
||
6324 | serge | 2920 | { "vcomiss", { XMScalar, EXxmm_md, EXxEVexS }, 0 }, |
5221 | serge | 2921 | }, |
2922 | /* EVEX_W_0F2F_P_2 */ |
||
2923 | { |
||
2924 | { Bad_Opcode }, |
||
6324 | serge | 2925 | { "vcomisd", { XMScalar, EXxmm_mq, EXxEVexS }, 0 }, |
5221 | serge | 2926 | }, |
2927 | /* EVEX_W_0F51_P_0 */ |
||
2928 | { |
||
6324 | serge | 2929 | { "vsqrtps", { XM, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2930 | }, |
2931 | /* EVEX_W_0F51_P_1 */ |
||
2932 | { |
||
6324 | serge | 2933 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 }, |
5221 | serge | 2934 | }, |
2935 | /* EVEX_W_0F51_P_2 */ |
||
2936 | { |
||
2937 | { Bad_Opcode }, |
||
6324 | serge | 2938 | { "vsqrtpd", { XM, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2939 | }, |
2940 | /* EVEX_W_0F51_P_3 */ |
||
2941 | { |
||
2942 | { Bad_Opcode }, |
||
6324 | serge | 2943 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 2944 | }, |
6324 | serge | 2945 | /* EVEX_W_0F54_P_0 */ |
2946 | { |
||
2947 | { "vandps", { XM, Vex, EXx }, 0 }, |
||
2948 | }, |
||
2949 | /* EVEX_W_0F54_P_2 */ |
||
2950 | { |
||
2951 | { Bad_Opcode }, |
||
2952 | { "vandpd", { XM, Vex, EXx }, 0 }, |
||
2953 | }, |
||
2954 | /* EVEX_W_0F55_P_0 */ |
||
2955 | { |
||
2956 | { "vandnps", { XM, Vex, EXx }, 0 }, |
||
2957 | }, |
||
2958 | /* EVEX_W_0F55_P_2 */ |
||
2959 | { |
||
2960 | { Bad_Opcode }, |
||
2961 | { "vandnpd", { XM, Vex, EXx }, 0 }, |
||
2962 | }, |
||
2963 | /* EVEX_W_0F56_P_0 */ |
||
2964 | { |
||
2965 | { "vorps", { XM, Vex, EXx }, 0 }, |
||
2966 | }, |
||
2967 | /* EVEX_W_0F56_P_2 */ |
||
2968 | { |
||
2969 | { Bad_Opcode }, |
||
2970 | { "vorpd", { XM, Vex, EXx }, 0 }, |
||
2971 | }, |
||
2972 | /* EVEX_W_0F57_P_0 */ |
||
2973 | { |
||
2974 | { "vxorps", { XM, Vex, EXx }, 0 }, |
||
2975 | }, |
||
2976 | /* EVEX_W_0F57_P_2 */ |
||
2977 | { |
||
2978 | { Bad_Opcode }, |
||
2979 | { "vxorpd", { XM, Vex, EXx }, 0 }, |
||
2980 | }, |
||
5221 | serge | 2981 | /* EVEX_W_0F58_P_0 */ |
2982 | { |
||
6324 | serge | 2983 | { "vaddps", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2984 | }, |
2985 | /* EVEX_W_0F58_P_1 */ |
||
2986 | { |
||
6324 | serge | 2987 | { "vaddss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 }, |
5221 | serge | 2988 | }, |
2989 | /* EVEX_W_0F58_P_2 */ |
||
2990 | { |
||
2991 | { Bad_Opcode }, |
||
6324 | serge | 2992 | { "vaddpd", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 2993 | }, |
2994 | /* EVEX_W_0F58_P_3 */ |
||
2995 | { |
||
2996 | { Bad_Opcode }, |
||
6324 | serge | 2997 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 2998 | }, |
2999 | /* EVEX_W_0F59_P_0 */ |
||
3000 | { |
||
6324 | serge | 3001 | { "vmulps", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3002 | }, |
3003 | /* EVEX_W_0F59_P_1 */ |
||
3004 | { |
||
6324 | serge | 3005 | { "vmulss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 }, |
5221 | serge | 3006 | }, |
3007 | /* EVEX_W_0F59_P_2 */ |
||
3008 | { |
||
3009 | { Bad_Opcode }, |
||
6324 | serge | 3010 | { "vmulpd", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3011 | }, |
3012 | /* EVEX_W_0F59_P_3 */ |
||
3013 | { |
||
3014 | { Bad_Opcode }, |
||
6324 | serge | 3015 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 3016 | }, |
3017 | /* EVEX_W_0F5A_P_0 */ |
||
3018 | { |
||
6324 | serge | 3019 | { "vcvtps2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, |
5221 | serge | 3020 | }, |
3021 | /* EVEX_W_0F5A_P_1 */ |
||
3022 | { |
||
6324 | serge | 3023 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 }, |
5221 | serge | 3024 | }, |
3025 | /* EVEX_W_0F5A_P_2 */ |
||
3026 | { |
||
3027 | { Bad_Opcode }, |
||
6324 | serge | 3028 | { "vcvtpd2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3029 | }, |
3030 | /* EVEX_W_0F5A_P_3 */ |
||
3031 | { |
||
3032 | { Bad_Opcode }, |
||
6324 | serge | 3033 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 3034 | }, |
3035 | /* EVEX_W_0F5B_P_0 */ |
||
3036 | { |
||
6324 | serge | 3037 | { "vcvtdq2ps", { XM, EXx, EXxEVexR }, 0 }, |
3038 | { "vcvtqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, |
||
5221 | serge | 3039 | }, |
3040 | /* EVEX_W_0F5B_P_1 */ |
||
3041 | { |
||
6324 | serge | 3042 | { "vcvttps2dq", { XM, EXx, EXxEVexS }, 0 }, |
5221 | serge | 3043 | }, |
3044 | /* EVEX_W_0F5B_P_2 */ |
||
3045 | { |
||
6324 | serge | 3046 | { "vcvtps2dq", { XM, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3047 | }, |
3048 | /* EVEX_W_0F5C_P_0 */ |
||
3049 | { |
||
6324 | serge | 3050 | { "vsubps", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3051 | }, |
3052 | /* EVEX_W_0F5C_P_1 */ |
||
3053 | { |
||
6324 | serge | 3054 | { "vsubss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 }, |
5221 | serge | 3055 | }, |
3056 | /* EVEX_W_0F5C_P_2 */ |
||
3057 | { |
||
3058 | { Bad_Opcode }, |
||
6324 | serge | 3059 | { "vsubpd", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3060 | }, |
3061 | /* EVEX_W_0F5C_P_3 */ |
||
3062 | { |
||
3063 | { Bad_Opcode }, |
||
6324 | serge | 3064 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 3065 | }, |
3066 | /* EVEX_W_0F5D_P_0 */ |
||
3067 | { |
||
6324 | serge | 3068 | { "vminps", { XM, Vex, EXx, EXxEVexS }, 0 }, |
5221 | serge | 3069 | }, |
3070 | /* EVEX_W_0F5D_P_1 */ |
||
3071 | { |
||
6324 | serge | 3072 | { "vminss", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 }, |
5221 | serge | 3073 | }, |
3074 | /* EVEX_W_0F5D_P_2 */ |
||
3075 | { |
||
3076 | { Bad_Opcode }, |
||
6324 | serge | 3077 | { "vminpd", { XM, Vex, EXx, EXxEVexS }, 0 }, |
5221 | serge | 3078 | }, |
3079 | /* EVEX_W_0F5D_P_3 */ |
||
3080 | { |
||
3081 | { Bad_Opcode }, |
||
6324 | serge | 3082 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS }, 0 }, |
5221 | serge | 3083 | }, |
3084 | /* EVEX_W_0F5E_P_0 */ |
||
3085 | { |
||
6324 | serge | 3086 | { "vdivps", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3087 | }, |
3088 | /* EVEX_W_0F5E_P_1 */ |
||
3089 | { |
||
6324 | serge | 3090 | { "vdivss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 }, |
5221 | serge | 3091 | }, |
3092 | /* EVEX_W_0F5E_P_2 */ |
||
3093 | { |
||
3094 | { Bad_Opcode }, |
||
6324 | serge | 3095 | { "vdivpd", { XM, Vex, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3096 | }, |
3097 | /* EVEX_W_0F5E_P_3 */ |
||
3098 | { |
||
3099 | { Bad_Opcode }, |
||
6324 | serge | 3100 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 }, |
5221 | serge | 3101 | }, |
3102 | /* EVEX_W_0F5F_P_0 */ |
||
3103 | { |
||
6324 | serge | 3104 | { "vmaxps", { XM, Vex, EXx, EXxEVexS }, 0 }, |
5221 | serge | 3105 | }, |
3106 | /* EVEX_W_0F5F_P_1 */ |
||
3107 | { |
||
6324 | serge | 3108 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 }, |
5221 | serge | 3109 | }, |
3110 | /* EVEX_W_0F5F_P_2 */ |
||
3111 | { |
||
3112 | { Bad_Opcode }, |
||
6324 | serge | 3113 | { "vmaxpd", { XM, Vex, EXx, EXxEVexS }, 0 }, |
5221 | serge | 3114 | }, |
3115 | /* EVEX_W_0F5F_P_3 */ |
||
3116 | { |
||
3117 | { Bad_Opcode }, |
||
6324 | serge | 3118 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS }, 0 }, |
5221 | serge | 3119 | }, |
3120 | /* EVEX_W_0F62_P_2 */ |
||
3121 | { |
||
6324 | serge | 3122 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3123 | }, |
3124 | /* EVEX_W_0F66_P_2 */ |
||
3125 | { |
||
6324 | serge | 3126 | { "vpcmpgtd", { XMask, Vex, EXx }, 0 }, |
5221 | serge | 3127 | }, |
3128 | /* EVEX_W_0F6A_P_2 */ |
||
3129 | { |
||
6324 | serge | 3130 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3131 | }, |
6324 | serge | 3132 | /* EVEX_W_0F6B_P_2 */ |
3133 | { |
||
3134 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
||
3135 | }, |
||
5221 | serge | 3136 | /* EVEX_W_0F6C_P_2 */ |
3137 | { |
||
3138 | { Bad_Opcode }, |
||
6324 | serge | 3139 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3140 | }, |
3141 | /* EVEX_W_0F6D_P_2 */ |
||
3142 | { |
||
3143 | { Bad_Opcode }, |
||
6324 | serge | 3144 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3145 | }, |
3146 | /* EVEX_W_0F6E_P_2 */ |
||
3147 | { |
||
6324 | serge | 3148 | { "vmovd", { XMScalar, Ed }, 0 }, |
3149 | { "vmovq", { XMScalar, Eq }, 0 }, |
||
5221 | serge | 3150 | }, |
3151 | /* EVEX_W_0F6F_P_1 */ |
||
3152 | { |
||
6324 | serge | 3153 | { "vmovdqu32", { XM, EXEvexXNoBcst }, 0 }, |
3154 | { "vmovdqu64", { XM, EXEvexXNoBcst }, 0 }, |
||
5221 | serge | 3155 | }, |
3156 | /* EVEX_W_0F6F_P_2 */ |
||
3157 | { |
||
6324 | serge | 3158 | { "vmovdqa32", { XM, EXEvexXNoBcst }, 0 }, |
3159 | { "vmovdqa64", { XM, EXEvexXNoBcst }, 0 }, |
||
5221 | serge | 3160 | }, |
6324 | serge | 3161 | /* EVEX_W_0F6F_P_3 */ |
3162 | { |
||
3163 | { "vmovdqu8", { XM, EXx }, 0 }, |
||
3164 | { "vmovdqu16", { XM, EXx }, 0 }, |
||
3165 | }, |
||
5221 | serge | 3166 | /* EVEX_W_0F70_P_2 */ |
3167 | { |
||
6324 | serge | 3168 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 3169 | }, |
3170 | /* EVEX_W_0F72_R_2_P_2 */ |
||
3171 | { |
||
6324 | serge | 3172 | { "vpsrld", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 3173 | }, |
3174 | /* EVEX_W_0F72_R_6_P_2 */ |
||
3175 | { |
||
6324 | serge | 3176 | { "vpslld", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 3177 | }, |
3178 | /* EVEX_W_0F73_R_2_P_2 */ |
||
3179 | { |
||
3180 | { Bad_Opcode }, |
||
6324 | serge | 3181 | { "vpsrlq", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 3182 | }, |
3183 | /* EVEX_W_0F73_R_6_P_2 */ |
||
3184 | { |
||
3185 | { Bad_Opcode }, |
||
6324 | serge | 3186 | { "vpsllq", { Vex, EXx, Ib }, 0 }, |
5221 | serge | 3187 | }, |
3188 | /* EVEX_W_0F76_P_2 */ |
||
3189 | { |
||
6324 | serge | 3190 | { "vpcmpeqd", { XMask, Vex, EXx }, 0 }, |
5221 | serge | 3191 | }, |
3192 | /* EVEX_W_0F78_P_0 */ |
||
3193 | { |
||
6324 | serge | 3194 | { "vcvttps2udq", { XM, EXx, EXxEVexS }, 0 }, |
3195 | { "vcvttpd2udq%XY", { XMxmmq, EXx, EXxEVexS }, 0 }, |
||
5221 | serge | 3196 | }, |
6324 | serge | 3197 | /* EVEX_W_0F78_P_2 */ |
3198 | { |
||
3199 | { "vcvttps2uqq", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, |
||
3200 | { "vcvttpd2uqq", { XM, EXx, EXxEVexS }, 0 }, |
||
3201 | }, |
||
5221 | serge | 3202 | /* EVEX_W_0F79_P_0 */ |
3203 | { |
||
6324 | serge | 3204 | { "vcvtps2udq", { XM, EXx, EXxEVexR }, 0 }, |
3205 | { "vcvtpd2udq%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, |
||
5221 | serge | 3206 | }, |
6324 | serge | 3207 | /* EVEX_W_0F79_P_2 */ |
3208 | { |
||
3209 | { "vcvtps2uqq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 }, |
||
3210 | { "vcvtpd2uqq", { XM, EXx, EXxEVexR }, 0 }, |
||
3211 | }, |
||
5221 | serge | 3212 | /* EVEX_W_0F7A_P_1 */ |
3213 | { |
||
6324 | serge | 3214 | { "vcvtudq2pd", { XM, EXEvexHalfBcstXmmq }, 0 }, |
3215 | { "vcvtuqq2pd", { XM, EXx, EXxEVexR }, 0 }, |
||
5221 | serge | 3216 | }, |
6324 | serge | 3217 | /* EVEX_W_0F7A_P_2 */ |
3218 | { |
||
3219 | { "vcvttps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, |
||
3220 | { "vcvttpd2qq", { XM, EXx, EXxEVexS }, 0 }, |
||
3221 | }, |
||
5221 | serge | 3222 | /* EVEX_W_0F7A_P_3 */ |
3223 | { |
||
6324 | serge | 3224 | { "vcvtudq2ps", { XM, EXx, EXxEVexR }, 0 }, |
3225 | { "vcvtuqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, |
||
5221 | serge | 3226 | }, |
3227 | /* EVEX_W_0F7B_P_1 */ |
||
3228 | { |
||
6324 | serge | 3229 | { "vcvtusi2ss", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, |
3230 | { "vcvtusi2ss", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, |
||
5221 | serge | 3231 | }, |
6324 | serge | 3232 | /* EVEX_W_0F7B_P_2 */ |
3233 | { |
||
3234 | { "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 }, |
||
3235 | { "vcvtpd2qq", { XM, EXx, EXxEVexR }, 0 }, |
||
3236 | }, |
||
5221 | serge | 3237 | /* EVEX_W_0F7B_P_3 */ |
3238 | { |
||
6324 | serge | 3239 | { "vcvtusi2sd", { XMScalar, VexScalar, Ed }, 0 }, |
3240 | { "vcvtusi2sd", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, |
||
5221 | serge | 3241 | }, |
3242 | /* EVEX_W_0F7E_P_1 */ |
||
3243 | { |
||
3244 | { Bad_Opcode }, |
||
6324 | serge | 3245 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
5221 | serge | 3246 | }, |
3247 | /* EVEX_W_0F7E_P_2 */ |
||
3248 | { |
||
6324 | serge | 3249 | { "vmovd", { Ed, XMScalar }, 0 }, |
3250 | { "vmovq", { Eq, XMScalar }, 0 }, |
||
5221 | serge | 3251 | }, |
3252 | /* EVEX_W_0F7F_P_1 */ |
||
3253 | { |
||
6324 | serge | 3254 | { "vmovdqu32", { EXxS, XM }, 0 }, |
3255 | { "vmovdqu64", { EXxS, XM }, 0 }, |
||
5221 | serge | 3256 | }, |
3257 | /* EVEX_W_0F7F_P_2 */ |
||
3258 | { |
||
6324 | serge | 3259 | { "vmovdqa32", { EXxS, XM }, 0 }, |
3260 | { "vmovdqa64", { EXxS, XM }, 0 }, |
||
5221 | serge | 3261 | }, |
6324 | serge | 3262 | /* EVEX_W_0F7F_P_3 */ |
3263 | { |
||
3264 | { "vmovdqu8", { EXxS, XM }, 0 }, |
||
3265 | { "vmovdqu16", { EXxS, XM }, 0 }, |
||
3266 | }, |
||
5221 | serge | 3267 | /* EVEX_W_0FC2_P_0 */ |
3268 | { |
||
6324 | serge | 3269 | { "vcmpps", { XMask, Vex, EXx, EXxEVexS, VCMP }, 0 }, |
5221 | serge | 3270 | }, |
3271 | /* EVEX_W_0FC2_P_1 */ |
||
3272 | { |
||
6324 | serge | 3273 | { "vcmpss", { XMask, VexScalar, EXxmm_md, EXxEVexS, VCMP }, 0 }, |
5221 | serge | 3274 | }, |
3275 | /* EVEX_W_0FC2_P_2 */ |
||
3276 | { |
||
3277 | { Bad_Opcode }, |
||
6324 | serge | 3278 | { "vcmppd", { XMask, Vex, EXx, EXxEVexS, VCMP }, 0 }, |
5221 | serge | 3279 | }, |
3280 | /* EVEX_W_0FC2_P_3 */ |
||
3281 | { |
||
3282 | { Bad_Opcode }, |
||
6324 | serge | 3283 | { "vcmpsd", { XMask, VexScalar, EXxmm_mq, EXxEVexS, VCMP }, 0 }, |
5221 | serge | 3284 | }, |
3285 | /* EVEX_W_0FC6_P_0 */ |
||
3286 | { |
||
6324 | serge | 3287 | { "vshufps", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 3288 | }, |
3289 | /* EVEX_W_0FC6_P_2 */ |
||
3290 | { |
||
3291 | { Bad_Opcode }, |
||
6324 | serge | 3292 | { "vshufpd", { XM, Vex, EXx, Ib }, 0 }, |
5221 | serge | 3293 | }, |
3294 | /* EVEX_W_0FD2_P_2 */ |
||
3295 | { |
||
6324 | serge | 3296 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 3297 | }, |
3298 | /* EVEX_W_0FD3_P_2 */ |
||
3299 | { |
||
3300 | { Bad_Opcode }, |
||
6324 | serge | 3301 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 3302 | }, |
3303 | /* EVEX_W_0FD4_P_2 */ |
||
3304 | { |
||
3305 | { Bad_Opcode }, |
||
6324 | serge | 3306 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3307 | }, |
3308 | /* EVEX_W_0FD6_P_2 */ |
||
3309 | { |
||
3310 | { Bad_Opcode }, |
||
6324 | serge | 3311 | { "vmovq", { EXxmm_mq, XMScalar }, 0 }, |
5221 | serge | 3312 | }, |
3313 | /* EVEX_W_0FE6_P_1 */ |
||
3314 | { |
||
6324 | serge | 3315 | { "vcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 }, |
3316 | { "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 }, |
||
5221 | serge | 3317 | }, |
3318 | /* EVEX_W_0FE6_P_2 */ |
||
3319 | { |
||
3320 | { Bad_Opcode }, |
||
6324 | serge | 3321 | { "vcvttpd2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 }, |
5221 | serge | 3322 | }, |
3323 | /* EVEX_W_0FE6_P_3 */ |
||
3324 | { |
||
3325 | { Bad_Opcode }, |
||
6324 | serge | 3326 | { "vcvtpd2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, |
5221 | serge | 3327 | }, |
3328 | /* EVEX_W_0FE7_P_2 */ |
||
3329 | { |
||
6324 | serge | 3330 | { "vmovntdq", { EXEvexXNoBcst, XM }, 0 }, |
5221 | serge | 3331 | }, |
3332 | /* EVEX_W_0FF2_P_2 */ |
||
3333 | { |
||
6324 | serge | 3334 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 3335 | }, |
3336 | /* EVEX_W_0FF3_P_2 */ |
||
3337 | { |
||
3338 | { Bad_Opcode }, |
||
6324 | serge | 3339 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
5221 | serge | 3340 | }, |
3341 | /* EVEX_W_0FF4_P_2 */ |
||
3342 | { |
||
3343 | { Bad_Opcode }, |
||
6324 | serge | 3344 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3345 | }, |
3346 | /* EVEX_W_0FFA_P_2 */ |
||
3347 | { |
||
6324 | serge | 3348 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3349 | }, |
3350 | /* EVEX_W_0FFB_P_2 */ |
||
3351 | { |
||
3352 | { Bad_Opcode }, |
||
6324 | serge | 3353 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3354 | }, |
3355 | /* EVEX_W_0FFE_P_2 */ |
||
3356 | { |
||
6324 | serge | 3357 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3358 | }, |
3359 | /* EVEX_W_0F380C_P_2 */ |
||
3360 | { |
||
6324 | serge | 3361 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3362 | }, |
3363 | /* EVEX_W_0F380D_P_2 */ |
||
3364 | { |
||
3365 | { Bad_Opcode }, |
||
6324 | serge | 3366 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3367 | }, |
6324 | serge | 3368 | /* EVEX_W_0F3810_P_1 */ |
3369 | { |
||
3370 | { "vpmovuswb", { EXxmmq, XM }, 0 }, |
||
3371 | }, |
||
3372 | /* EVEX_W_0F3810_P_2 */ |
||
3373 | { |
||
3374 | { Bad_Opcode }, |
||
3375 | { "vpsrlvw", { XM, Vex, EXx }, 0 }, |
||
3376 | }, |
||
5221 | serge | 3377 | /* EVEX_W_0F3811_P_1 */ |
3378 | { |
||
6324 | serge | 3379 | { "vpmovusdb", { EXxmmqd, XM }, 0 }, |
5221 | serge | 3380 | }, |
6324 | serge | 3381 | /* EVEX_W_0F3811_P_2 */ |
3382 | { |
||
3383 | { Bad_Opcode }, |
||
3384 | { "vpsravw", { XM, Vex, EXx }, 0 }, |
||
3385 | }, |
||
5221 | serge | 3386 | /* EVEX_W_0F3812_P_1 */ |
3387 | { |
||
6324 | serge | 3388 | { "vpmovusqb", { EXxmmdw, XM }, 0 }, |
5221 | serge | 3389 | }, |
6324 | serge | 3390 | /* EVEX_W_0F3812_P_2 */ |
3391 | { |
||
3392 | { Bad_Opcode }, |
||
3393 | { "vpsllvw", { XM, Vex, EXx }, 0 }, |
||
3394 | }, |
||
5221 | serge | 3395 | /* EVEX_W_0F3813_P_1 */ |
3396 | { |
||
6324 | serge | 3397 | { "vpmovusdw", { EXxmmq, XM }, 0 }, |
5221 | serge | 3398 | }, |
3399 | /* EVEX_W_0F3813_P_2 */ |
||
3400 | { |
||
6324 | serge | 3401 | { "vcvtph2ps", { XM, EXxmmq, EXxEVexS }, 0 }, |
5221 | serge | 3402 | }, |
3403 | /* EVEX_W_0F3814_P_1 */ |
||
3404 | { |
||
6324 | serge | 3405 | { "vpmovusqw", { EXxmmqd, XM }, 0 }, |
5221 | serge | 3406 | }, |
3407 | /* EVEX_W_0F3815_P_1 */ |
||
3408 | { |
||
6324 | serge | 3409 | { "vpmovusqd", { EXxmmq, XM }, 0 }, |
5221 | serge | 3410 | }, |
3411 | /* EVEX_W_0F3818_P_2 */ |
||
3412 | { |
||
6324 | serge | 3413 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
5221 | serge | 3414 | }, |
3415 | /* EVEX_W_0F3819_P_2 */ |
||
3416 | { |
||
6324 | serge | 3417 | { "vbroadcastf32x2", { XM, EXxmm_mq }, 0 }, |
3418 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
||
5221 | serge | 3419 | }, |
3420 | /* EVEX_W_0F381A_P_2 */ |
||
3421 | { |
||
6324 | serge | 3422 | { "vbroadcastf32x4", { XM, EXxmm }, 0 }, |
3423 | { "vbroadcastf64x2", { XM, EXxmm }, 0 }, |
||
5221 | serge | 3424 | }, |
3425 | /* EVEX_W_0F381B_P_2 */ |
||
3426 | { |
||
6324 | serge | 3427 | { "vbroadcastf32x8", { XM, EXxmmq }, 0 }, |
3428 | { "vbroadcastf64x4", { XM, EXymm }, 0 }, |
||
5221 | serge | 3429 | }, |
3430 | /* EVEX_W_0F381E_P_2 */ |
||
3431 | { |
||
6324 | serge | 3432 | { "vpabsd", { XM, EXx }, 0 }, |
5221 | serge | 3433 | }, |
3434 | /* EVEX_W_0F381F_P_2 */ |
||
3435 | { |
||
3436 | { Bad_Opcode }, |
||
6324 | serge | 3437 | { "vpabsq", { XM, EXx }, 0 }, |
5221 | serge | 3438 | }, |
6324 | serge | 3439 | /* EVEX_W_0F3820_P_1 */ |
3440 | { |
||
3441 | { "vpmovswb", { EXxmmq, XM }, 0 }, |
||
3442 | }, |
||
5221 | serge | 3443 | /* EVEX_W_0F3821_P_1 */ |
3444 | { |
||
6324 | serge | 3445 | { "vpmovsdb", { EXxmmqd, XM }, 0 }, |
5221 | serge | 3446 | }, |
3447 | /* EVEX_W_0F3822_P_1 */ |
||
3448 | { |
||
6324 | serge | 3449 | { "vpmovsqb", { EXxmmdw, XM }, 0 }, |
5221 | serge | 3450 | }, |
3451 | /* EVEX_W_0F3823_P_1 */ |
||
3452 | { |
||
6324 | serge | 3453 | { "vpmovsdw", { EXxmmq, XM }, 0 }, |
5221 | serge | 3454 | }, |
3455 | /* EVEX_W_0F3824_P_1 */ |
||
3456 | { |
||
6324 | serge | 3457 | { "vpmovsqw", { EXxmmqd, XM }, 0 }, |
5221 | serge | 3458 | }, |
3459 | /* EVEX_W_0F3825_P_1 */ |
||
3460 | { |
||
6324 | serge | 3461 | { "vpmovsqd", { EXxmmq, XM }, 0 }, |
5221 | serge | 3462 | }, |
3463 | /* EVEX_W_0F3825_P_2 */ |
||
3464 | { |
||
6324 | serge | 3465 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
5221 | serge | 3466 | }, |
6324 | serge | 3467 | /* EVEX_W_0F3826_P_1 */ |
3468 | { |
||
3469 | { "vptestnmb", { XMask, Vex, EXx }, 0 }, |
||
3470 | { "vptestnmw", { XMask, Vex, EXx }, 0 }, |
||
3471 | }, |
||
3472 | /* EVEX_W_0F3826_P_2 */ |
||
3473 | { |
||
3474 | { "vptestmb", { XMask, Vex, EXx }, 0 }, |
||
3475 | { "vptestmw", { XMask, Vex, EXx }, 0 }, |
||
3476 | }, |
||
3477 | /* EVEX_W_0F3828_P_1 */ |
||
3478 | { |
||
3479 | { "vpmovm2b", { XM, MaskR }, 0 }, |
||
3480 | { "vpmovm2w", { XM, MaskR }, 0 }, |
||
3481 | }, |
||
5221 | serge | 3482 | /* EVEX_W_0F3828_P_2 */ |
3483 | { |
||
3484 | { Bad_Opcode }, |
||
6324 | serge | 3485 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3486 | }, |
6324 | serge | 3487 | /* EVEX_W_0F3829_P_1 */ |
3488 | { |
||
3489 | { "vpmovb2m", { XMask, EXx }, 0 }, |
||
3490 | { "vpmovw2m", { XMask, EXx }, 0 }, |
||
3491 | }, |
||
5221 | serge | 3492 | /* EVEX_W_0F3829_P_2 */ |
3493 | { |
||
3494 | { Bad_Opcode }, |
||
6324 | serge | 3495 | { "vpcmpeqq", { XMask, Vex, EXx }, 0 }, |
5221 | serge | 3496 | }, |
3497 | /* EVEX_W_0F382A_P_1 */ |
||
3498 | { |
||
3499 | { Bad_Opcode }, |
||
6324 | serge | 3500 | { "vpbroadcastmb2q", { XM, MaskR }, 0 }, |
5221 | serge | 3501 | }, |
3502 | /* EVEX_W_0F382A_P_2 */ |
||
3503 | { |
||
6324 | serge | 3504 | { "vmovntdqa", { XM, EXEvexXNoBcst }, 0 }, |
5221 | serge | 3505 | }, |
6324 | serge | 3506 | /* EVEX_W_0F382B_P_2 */ |
3507 | { |
||
3508 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
||
3509 | }, |
||
3510 | /* EVEX_W_0F3830_P_1 */ |
||
3511 | { |
||
3512 | { "vpmovwb", { EXxmmq, XM }, 0 }, |
||
3513 | }, |
||
5221 | serge | 3514 | /* EVEX_W_0F3831_P_1 */ |
3515 | { |
||
6324 | serge | 3516 | { "vpmovdb", { EXxmmqd, XM }, 0 }, |
5221 | serge | 3517 | }, |
3518 | /* EVEX_W_0F3832_P_1 */ |
||
3519 | { |
||
6324 | serge | 3520 | { "vpmovqb", { EXxmmdw, XM }, 0 }, |
5221 | serge | 3521 | }, |
3522 | /* EVEX_W_0F3833_P_1 */ |
||
3523 | { |
||
6324 | serge | 3524 | { "vpmovdw", { EXxmmq, XM }, 0 }, |
5221 | serge | 3525 | }, |
3526 | /* EVEX_W_0F3834_P_1 */ |
||
3527 | { |
||
6324 | serge | 3528 | { "vpmovqw", { EXxmmqd, XM }, 0 }, |
5221 | serge | 3529 | }, |
3530 | /* EVEX_W_0F3835_P_1 */ |
||
3531 | { |
||
6324 | serge | 3532 | { "vpmovqd", { EXxmmq, XM }, 0 }, |
5221 | serge | 3533 | }, |
3534 | /* EVEX_W_0F3835_P_2 */ |
||
3535 | { |
||
6324 | serge | 3536 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
5221 | serge | 3537 | }, |
3538 | /* EVEX_W_0F3837_P_2 */ |
||
3539 | { |
||
3540 | { Bad_Opcode }, |
||
6324 | serge | 3541 | { "vpcmpgtq", { XMask, Vex, EXx }, 0 }, |
5221 | serge | 3542 | }, |
6324 | serge | 3543 | /* EVEX_W_0F3838_P_1 */ |
3544 | { |
||
3545 | { "vpmovm2d", { XM, MaskR }, 0 }, |
||
3546 | { "vpmovm2q", { XM, MaskR }, 0 }, |
||
3547 | }, |
||
3548 | /* EVEX_W_0F3839_P_1 */ |
||
3549 | { |
||
3550 | { "vpmovd2m", { XMask, EXx }, 0 }, |
||
3551 | { "vpmovq2m", { XMask, EXx }, 0 }, |
||
3552 | }, |
||
5221 | serge | 3553 | /* EVEX_W_0F383A_P_1 */ |
3554 | { |
||
6324 | serge | 3555 | { "vpbroadcastmw2d", { XM, MaskR }, 0 }, |
5221 | serge | 3556 | }, |
3557 | /* EVEX_W_0F3840_P_2 */ |
||
3558 | { |
||
6324 | serge | 3559 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
3560 | { "vpmullq", { XM, Vex, EXx }, 0 }, |
||
5221 | serge | 3561 | }, |
3562 | /* EVEX_W_0F3858_P_2 */ |
||
3563 | { |
||
6324 | serge | 3564 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
5221 | serge | 3565 | }, |
3566 | /* EVEX_W_0F3859_P_2 */ |
||
3567 | { |
||
6324 | serge | 3568 | { "vbroadcasti32x2", { XM, EXxmm_mq }, 0 }, |
3569 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
||
5221 | serge | 3570 | }, |
3571 | /* EVEX_W_0F385A_P_2 */ |
||
3572 | { |
||
6324 | serge | 3573 | { "vbroadcasti32x4", { XM, EXxmm }, 0 }, |
3574 | { "vbroadcasti64x2", { XM, EXxmm }, 0 }, |
||
5221 | serge | 3575 | }, |
3576 | /* EVEX_W_0F385B_P_2 */ |
||
3577 | { |
||
6324 | serge | 3578 | { "vbroadcasti32x8", { XM, EXxmmq }, 0 }, |
3579 | { "vbroadcasti64x4", { XM, EXymm }, 0 }, |
||
3580 | }, |
||
3581 | /* EVEX_W_0F3866_P_2 */ |
||
3582 | { |
||
3583 | { "vpblendmb", { XM, Vex, EXx }, 0 }, |
||
3584 | { "vpblendmw", { XM, Vex, EXx }, 0 }, |
||
3585 | }, |
||
3586 | /* EVEX_W_0F3875_P_2 */ |
||
3587 | { |
||
3588 | { "vpermi2b", { XM, Vex, EXx }, 0 }, |
||
3589 | { "vpermi2w", { XM, Vex, EXx }, 0 }, |
||
3590 | }, |
||
3591 | /* EVEX_W_0F3878_P_2 */ |
||
3592 | { |
||
3593 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
||
3594 | }, |
||
3595 | /* EVEX_W_0F3879_P_2 */ |
||
3596 | { |
||
3597 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
||
3598 | }, |
||
3599 | /* EVEX_W_0F387A_P_2 */ |
||
3600 | { |
||
3601 | { "vpbroadcastb", { XM, Rd }, 0 }, |
||
3602 | }, |
||
3603 | /* EVEX_W_0F387B_P_2 */ |
||
3604 | { |
||
3605 | { "vpbroadcastw", { XM, Rd }, 0 }, |
||
3606 | }, |
||
3607 | /* EVEX_W_0F387D_P_2 */ |
||
3608 | { |
||
3609 | { "vpermt2b", { XM, Vex, EXx }, 0 }, |
||
3610 | { "vpermt2w", { XM, Vex, EXx }, 0 }, |
||
3611 | }, |
||
3612 | /* EVEX_W_0F3883_P_2 */ |
||
3613 | { |
||
5221 | serge | 3614 | { Bad_Opcode }, |
6324 | serge | 3615 | { "vpmultishiftqb", { XM, Vex, EXx }, 0 }, |
5221 | serge | 3616 | }, |
6324 | serge | 3617 | /* EVEX_W_0F388D_P_2 */ |
3618 | { |
||
3619 | { "vpermb", { XM, Vex, EXx }, 0 }, |
||
3620 | { "vpermw", { XM, Vex, EXx }, 0 }, |
||
3621 | }, |
||
5221 | serge | 3622 | /* EVEX_W_0F3891_P_2 */ |
3623 | { |
||
6324 | serge | 3624 | { "vpgatherqd", { XMxmmq, MVexVSIBQDWpX }, 0 }, |
3625 | { "vpgatherqq", { XM, MVexVSIBQWpX }, 0 }, |
||
5221 | serge | 3626 | }, |
3627 | /* EVEX_W_0F3893_P_2 */ |
||
3628 | { |
||
6324 | serge | 3629 | { "vgatherqps", { XMxmmq, MVexVSIBQDWpX }, 0 }, |
3630 | { "vgatherqpd", { XM, MVexVSIBQWpX }, 0 }, |
||
5221 | serge | 3631 | }, |
3632 | /* EVEX_W_0F38A1_P_2 */ |
||
3633 | { |
||
6324 | serge | 3634 | { "vpscatterqd", { MVexVSIBQDWpX, XMxmmq }, 0 }, |
3635 | { "vpscatterqq", { MVexVSIBQWpX, XM }, 0 }, |
||
5221 | serge | 3636 | }, |
3637 | /* EVEX_W_0F38A3_P_2 */ |
||
3638 | { |
||
6324 | serge | 3639 | { "vscatterqps", { MVexVSIBQDWpX, XMxmmq }, 0 }, |
3640 | { "vscatterqpd", { MVexVSIBQWpX, XM }, 0 }, |
||
5221 | serge | 3641 | }, |
3642 | /* EVEX_W_0F38C7_R_1_P_2 */ |
||
3643 | { |
||
6324 | serge | 3644 | { "vgatherpf0qps", { MVexVSIBDQWpX }, 0 }, |
3645 | { "vgatherpf0qpd", { MVexVSIBQWpX }, 0 }, |
||
5221 | serge | 3646 | }, |
3647 | /* EVEX_W_0F38C7_R_2_P_2 */ |
||
3648 | { |
||
6324 | serge | 3649 | { "vgatherpf1qps", { MVexVSIBDQWpX }, 0 }, |
3650 | { "vgatherpf1qpd", { MVexVSIBQWpX }, 0 }, |
||
5221 | serge | 3651 | }, |
3652 | /* EVEX_W_0F38C7_R_5_P_2 */ |
||
3653 | { |
||
6324 | serge | 3654 | { "vscatterpf0qps", { MVexVSIBDQWpX }, 0 }, |
3655 | { "vscatterpf0qpd", { MVexVSIBQWpX }, 0 }, |
||
5221 | serge | 3656 | }, |
3657 | /* EVEX_W_0F38C7_R_6_P_2 */ |
||
3658 | { |
||
6324 | serge | 3659 | { "vscatterpf1qps", { MVexVSIBDQWpX }, 0 }, |
3660 | { "vscatterpf1qpd", { MVexVSIBQWpX }, 0 }, |
||
5221 | serge | 3661 | }, |
3662 | /* EVEX_W_0F3A00_P_2 */ |
||
3663 | { |
||
3664 | { Bad_Opcode }, |
||
6324 | serge | 3665 | { "vpermq", { XM, EXx, Ib }, 0 }, |
5221 | serge | 3666 | }, |
3667 | /* EVEX_W_0F3A01_P_2 */ |
||
3668 | { |
||
3669 | { Bad_Opcode }, |
||
6324 | serge | 3670 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 3671 | }, |
3672 | /* EVEX_W_0F3A04_P_2 */ |
||
3673 | { |
||
6324 | serge | 3674 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
5221 | serge | 3675 | }, |
3676 | /* EVEX_W_0F3A05_P_2 */ |
||
3677 | { |
||
3678 | { Bad_Opcode }, |
||
6324 | serge | 3679 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
5221 | serge | 3680 | }, |
3681 | /* EVEX_W_0F3A08_P_2 */ |
||
3682 | { |
||
6324 | serge | 3683 | { "vrndscaleps", { XM, EXx, EXxEVexS, Ib }, 0 }, |
5221 | serge | 3684 | }, |
3685 | /* EVEX_W_0F3A09_P_2 */ |
||
3686 | { |
||
3687 | { Bad_Opcode }, |
||
6324 | serge | 3688 | { "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, 0 }, |
5221 | serge | 3689 | }, |
3690 | /* EVEX_W_0F3A0A_P_2 */ |
||
3691 | { |
||
6324 | serge | 3692 | { "vrndscaless", { XMScalar, VexScalar, EXxmm_md, EXxEVexS, Ib }, 0 }, |
5221 | serge | 3693 | }, |
3694 | /* EVEX_W_0F3A0B_P_2 */ |
||
3695 | { |
||
3696 | { Bad_Opcode }, |
||
6324 | serge | 3697 | { "vrndscalesd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS, Ib }, 0 }, |
5221 | serge | 3698 | }, |
6324 | serge | 3699 | /* EVEX_W_0F3A16_P_2 */ |
3700 | { |
||
3701 | { "vpextrd", { Edqd, XM, Ib }, 0 }, |
||
3702 | { "vpextrq", { Eq, XM, Ib }, 0 }, |
||
3703 | }, |
||
5221 | serge | 3704 | /* EVEX_W_0F3A18_P_2 */ |
3705 | { |
||
6324 | serge | 3706 | { "vinsertf32x4", { XM, Vex, EXxmm, Ib }, 0 }, |
3707 | { "vinsertf64x2", { XM, Vex, EXxmm, Ib }, 0 }, |
||
5221 | serge | 3708 | }, |
3709 | /* EVEX_W_0F3A19_P_2 */ |
||
3710 | { |
||
6324 | serge | 3711 | { "vextractf32x4", { EXxmm, XM, Ib }, 0 }, |
3712 | { "vextractf64x2", { EXxmm, XM, Ib }, 0 }, |
||
5221 | serge | 3713 | }, |
3714 | /* EVEX_W_0F3A1A_P_2 */ |
||
3715 | { |
||
6324 | serge | 3716 | { "vinsertf32x8", { XM, Vex, EXxmmq, Ib }, 0 }, |
3717 | { "vinsertf64x4", { XM, Vex, EXxmmq, Ib }, 0 }, |
||
5221 | serge | 3718 | }, |
3719 | /* EVEX_W_0F3A1B_P_2 */ |
||
3720 | { |
||
6324 | serge | 3721 | { "vextractf32x8", { EXxmmq, XM, Ib }, 0 }, |
3722 | { "vextractf64x4", { EXxmmq, XM, Ib }, 0 }, |
||
5221 | serge | 3723 | }, |
3724 | /* EVEX_W_0F3A1D_P_2 */ |
||
3725 | { |
||
6324 | serge | 3726 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, |
5221 | serge | 3727 | }, |
3728 | /* EVEX_W_0F3A21_P_2 */ |
||
3729 | { |
||
6324 | serge | 3730 | { "vinsertps", { XMM, Vex, EXxmm_md, Ib }, 0 }, |
5221 | serge | 3731 | }, |
6324 | serge | 3732 | /* EVEX_W_0F3A22_P_2 */ |
3733 | { |
||
3734 | { "vpinsrd", { XM, Vex128, Edqd, Ib }, 0 }, |
||
3735 | { "vpinsrq", { XM, Vex128, Eq, Ib }, 0 }, |
||
3736 | }, |
||
5221 | serge | 3737 | /* EVEX_W_0F3A23_P_2 */ |
3738 | { |
||
6324 | serge | 3739 | { "vshuff32x4", { XM, Vex, EXx, Ib }, 0 }, |
3740 | { "vshuff64x2", { XM, Vex, EXx, Ib }, 0 }, |
||
5221 | serge | 3741 | }, |
3742 | /* EVEX_W_0F3A38_P_2 */ |
||
3743 | { |
||
6324 | serge | 3744 | { "vinserti32x4", { XM, Vex, EXxmm, Ib }, 0 }, |
3745 | { "vinserti64x2", { XM, Vex, EXxmm, Ib }, 0 }, |
||
5221 | serge | 3746 | }, |
3747 | /* EVEX_W_0F3A39_P_2 */ |
||
3748 | { |
||
6324 | serge | 3749 | { "vextracti32x4", { EXxmm, XM, Ib }, 0 }, |
3750 | { "vextracti64x2", { EXxmm, XM, Ib }, 0 }, |
||
5221 | serge | 3751 | }, |
3752 | /* EVEX_W_0F3A3A_P_2 */ |
||
3753 | { |
||
6324 | serge | 3754 | { "vinserti32x8", { XM, Vex, EXxmmq, Ib }, 0 }, |
3755 | { "vinserti64x4", { XM, Vex, EXxmmq, Ib }, 0 }, |
||
5221 | serge | 3756 | }, |
3757 | /* EVEX_W_0F3A3B_P_2 */ |
||
3758 | { |
||
6324 | serge | 3759 | { "vextracti32x8", { EXxmmq, XM, Ib }, 0 }, |
3760 | { "vextracti64x4", { EXxmmq, XM, Ib }, 0 }, |
||
5221 | serge | 3761 | }, |
6324 | serge | 3762 | /* EVEX_W_0F3A3E_P_2 */ |
3763 | { |
||
3764 | { "vpcmpub", { XMask, Vex, EXx, Ib }, 0 }, |
||
3765 | { "vpcmpuw", { XMask, Vex, EXx, Ib }, 0 }, |
||
3766 | }, |
||
3767 | /* EVEX_W_0F3A3F_P_2 */ |
||
3768 | { |
||
3769 | { "vpcmpb", { XMask, Vex, EXx, Ib }, 0 }, |
||
3770 | { "vpcmpw", { XMask, Vex, EXx, Ib }, 0 }, |
||
3771 | }, |
||
3772 | /* EVEX_W_0F3A42_P_2 */ |
||
3773 | { |
||
3774 | { "vdbpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
||
3775 | }, |
||
5221 | serge | 3776 | /* EVEX_W_0F3A43_P_2 */ |
3777 | { |
||
6324 | serge | 3778 | { "vshufi32x4", { XM, Vex, EXx, Ib }, 0 }, |
3779 | { "vshufi64x2", { XM, Vex, EXx, Ib }, 0 }, |
||
5221 | serge | 3780 | }, |
6324 | serge | 3781 | /* EVEX_W_0F3A50_P_2 */ |
3782 | { |
||
3783 | { "vrangeps", { XM, Vex, EXx, EXxEVexS, Ib }, 0 }, |
||
3784 | { "vrangepd", { XM, Vex, EXx, EXxEVexS, Ib }, 0 }, |
||
3785 | }, |
||
3786 | /* EVEX_W_0F3A51_P_2 */ |
||
3787 | { |
||
3788 | { "vrangess", { XMScalar, VexScalar, EXxmm_md, EXxEVexS, Ib }, 0 }, |
||
3789 | { "vrangesd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS, Ib }, 0 }, |
||
3790 | }, |
||
3791 | /* EVEX_W_0F3A56_P_2 */ |
||
3792 | { |
||
3793 | { "vreduceps", { XM, EXx, EXxEVexS, Ib }, 0 }, |
||
3794 | { "vreducepd", { XM, EXx, EXxEVexS, Ib }, 0 }, |
||
3795 | }, |
||
3796 | /* EVEX_W_0F3A57_P_2 */ |
||
3797 | { |
||
3798 | { "vreducess", { XMScalar, VexScalar, EXxmm_md, EXxEVexS, Ib }, 0 }, |
||
3799 | { "vreducesd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS, Ib }, 0 }, |
||
3800 | }, |
||
3801 | /* EVEX_W_0F3A66_P_2 */ |
||
3802 | { |
||
3803 | { "vfpclassps%XZ", { XMask, EXx, Ib }, 0 }, |
||
3804 | { "vfpclasspd%XZ", { XMask, EXx, Ib }, 0 }, |
||
3805 | }, |
||
3806 | /* EVEX_W_0F3A67_P_2 */ |
||
3807 | { |
||
3808 | { "vfpclassss", { XMask, EXxmm_md, Ib }, 0 }, |
||
3809 | { "vfpclasssd", { XMask, EXxmm_mq, Ib }, 0 }, |
||
3810 | }, |
||
5221 | serge | 3811 | #endif /* NEED_VEX_W_TABLE */ |
3812 | #ifdef NEED_MOD_TABLE |
||
3813 | { |
||
3814 | /* MOD_EVEX_0F10_PREFIX_1 */ |
||
3815 | { VEX_W_TABLE (EVEX_W_0F10_P_1_M_0) }, |
||
3816 | { VEX_W_TABLE (EVEX_W_0F10_P_1_M_1) }, |
||
3817 | }, |
||
3818 | { |
||
3819 | /* MOD_EVEX_0F10_PREFIX_3 */ |
||
3820 | { VEX_W_TABLE (EVEX_W_0F10_P_3_M_0) }, |
||
3821 | { VEX_W_TABLE (EVEX_W_0F10_P_3_M_1) }, |
||
3822 | }, |
||
3823 | { |
||
3824 | /* MOD_EVEX_0F11_PREFIX_1 */ |
||
3825 | { VEX_W_TABLE (EVEX_W_0F11_P_1_M_0) }, |
||
3826 | { VEX_W_TABLE (EVEX_W_0F11_P_1_M_1) }, |
||
3827 | }, |
||
3828 | { |
||
3829 | /* MOD_EVEX_0F11_PREFIX_3 */ |
||
3830 | { VEX_W_TABLE (EVEX_W_0F11_P_3_M_0) }, |
||
3831 | { VEX_W_TABLE (EVEX_W_0F11_P_3_M_1) }, |
||
3832 | }, |
||
3833 | { |
||
3834 | /* MOD_EVEX_0F12_PREFIX_0 */ |
||
3835 | { VEX_W_TABLE (EVEX_W_0F12_P_0_M_0) }, |
||
3836 | { VEX_W_TABLE (EVEX_W_0F12_P_0_M_1) }, |
||
3837 | }, |
||
3838 | { |
||
3839 | /* MOD_EVEX_0F16_PREFIX_0 */ |
||
3840 | { VEX_W_TABLE (EVEX_W_0F16_P_0_M_0) }, |
||
3841 | { VEX_W_TABLE (EVEX_W_0F16_P_0_M_1) }, |
||
3842 | }, |
||
3843 | { |
||
3844 | /* MOD_EVEX_0F38C6_REG_1 */ |
||
3845 | { PREFIX_TABLE (PREFIX_EVEX_0F38C6_REG_1) }, |
||
3846 | }, |
||
3847 | { |
||
3848 | /* MOD_EVEX_0F38C6_REG_2 */ |
||
3849 | { PREFIX_TABLE (PREFIX_EVEX_0F38C6_REG_2) }, |
||
3850 | }, |
||
3851 | { |
||
3852 | /* MOD_EVEX_0F38C6_REG_5 */ |
||
3853 | { PREFIX_TABLE (PREFIX_EVEX_0F38C6_REG_5) }, |
||
3854 | }, |
||
3855 | { |
||
3856 | /* MOD_EVEX_0F38C6_REG_6 */ |
||
3857 | { PREFIX_TABLE (PREFIX_EVEX_0F38C6_REG_6) }, |
||
3858 | }, |
||
3859 | { |
||
3860 | /* MOD_EVEX_0F38C7_REG_1 */ |
||
3861 | { PREFIX_TABLE (PREFIX_EVEX_0F38C7_REG_1) }, |
||
3862 | }, |
||
3863 | { |
||
3864 | /* MOD_EVEX_0F38C7_REG_2 */ |
||
3865 | { PREFIX_TABLE (PREFIX_EVEX_0F38C7_REG_2) }, |
||
3866 | }, |
||
3867 | { |
||
3868 | /* MOD_EVEX_0F38C7_REG_5 */ |
||
3869 | { PREFIX_TABLE (PREFIX_EVEX_0F38C7_REG_5) }, |
||
3870 | }, |
||
3871 | { |
||
3872 | /* MOD_EVEX_0F38C7_REG_6 */ |
||
3873 | { PREFIX_TABLE (PREFIX_EVEX_0F38C7_REG_6) }, |
||
3874 | }, |
||
3875 | #endif /* NEED_MOD_TABLE */ |