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5191 serge 1
/* Opcode decoder for the Renesas RL78
6324 serge 2
   Copyright (C) 2011-2015 Free Software Foundation, Inc.
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   Written by DJ Delorie 
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   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, write to the Free Software
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   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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   02110-1301, USA.  */
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/* The RL78 decoder in libopcodes is used by the simulator, gdb's
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   analyzer, and the disassembler.  Given an opcode data source, it
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   decodes the next opcode into the following structures.  */
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#ifndef RL78_OPCODES_H_INCLUDED
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#define RL78_OPCODES_H_INCLUDED
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6324 serge 29
#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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  RL78_ISA_DEFAULT,
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  RL78_ISA_G10,
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  RL78_ISA_G13,
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  RL78_ISA_G14,
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} RL78_Dis_Isa;
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5191 serge 40
/* For the purposes of these structures, the RL78 registers are as
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   follows, despite most of these being memory-mapped and
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   bank-switched:  */
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typedef enum {
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  RL78_Reg_None,
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  /* The order of these matches the encodings.  */
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  RL78_Reg_X,
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  RL78_Reg_A,
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  RL78_Reg_C,
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  RL78_Reg_B,
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  RL78_Reg_E,
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  RL78_Reg_D,
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  RL78_Reg_L,
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  RL78_Reg_H,
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  /* The order of these matches the encodings.  */
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  RL78_Reg_AX,
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  RL78_Reg_BC,
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  RL78_Reg_DE,
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  RL78_Reg_HL,
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  /* Unordered.  */
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  RL78_Reg_SP,
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  RL78_Reg_PSW,
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  RL78_Reg_CS,
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  RL78_Reg_ES,
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  RL78_Reg_PMC,
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  RL78_Reg_MEM
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} RL78_Register;
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typedef enum
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{
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  RL78_Byte = 0,
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  RL78_Word
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} RL78_Size;
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typedef enum {
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  RL78_Condition_T,
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  RL78_Condition_F,
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  RL78_Condition_C,
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  RL78_Condition_NC,
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  RL78_Condition_H,
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  RL78_Condition_NH,
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  RL78_Condition_Z,
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  RL78_Condition_NZ
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} RL78_Condition;
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typedef enum {
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  RL78_Operand_None = 0,
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  RL78_Operand_Immediate,	/* #addend */
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  RL78_Operand_Register,	/* reg */
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  RL78_Operand_Indirect,	/* [reg + reg2 + addend] */
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  RL78_Operand_Bit,		/* reg.bit */
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  RL78_Operand_BitIndirect,	/* [reg+reg2+addend].bit */
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  RL78_Operand_PreDec,		/* [--reg] = push */
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  RL78_Operand_PostInc		/* [reg++] = pop */
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} RL78_Operand_Type;
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typedef enum
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{
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  RLO_unknown,
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  RLO_add,			/* d += s */
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  RLO_addc,			/* d += s + CY */
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  RLO_and,			/* d &= s (byte, word, bit) */
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  RLO_branch,			/* pc = d */
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  RLO_branch_cond,		/* pc = d if cond(src) */
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  RLO_branch_cond_clear,	/* pc = d if cond(src), and clear(src) */
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  RLO_break,			/* BRK */
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  RLO_call,			/* call */
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  RLO_cmp,			/* cmp d, s */
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  RLO_divhu,			/* DIVHU */
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  RLO_divwu,			/* DIVWU */
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  RLO_halt,			/* HALT */
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  RLO_mov,			/* d = s */
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  RLO_mach,			/* MACH */
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  RLO_machu,			/* MACHU */
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  RLO_mulu,			/* MULU */
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  RLO_mulh,			/* MULH */
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  RLO_mulhu,			/* MULHU */
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  RLO_nop,			/* NOP */
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  RLO_or,			/* d |= s */
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  RLO_ret,			/* RET */
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  RLO_reti,			/* RETI */
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  RLO_rol,			/* d <<= s, MSB to LSB and CY */
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  RLO_rolc,			/* d <<= s, MSB to CY, CY, to LSB */
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  RLO_ror,			/* d >>= s, LSB to MSB and CY */
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  RLO_rorc,			/* d >>= s, LSB to CY, CY, to MSB */
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  RLO_sar,			/* d >>= s, signed */
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  RLO_sel,			/* rb = s */
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  RLO_shr,			/* d >>= s, unsigned */
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  RLO_shl,			/* d <<= s */
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  RLO_skip,			/* skip next insn is cond(s) */
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  RLO_stop,			/* STOP */
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  RLO_sub,			/* d -= s */
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  RLO_subc,			/* d -= s - CY */
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  RLO_xch,			/* swap d, s  */
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  RLO_xor,			/* d ^= s */
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} RL78_Opcode_ID;
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typedef struct {
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  RL78_Operand_Type  type;
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  int              addend;
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  RL78_Register	   reg : 8;
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  RL78_Register	   reg2 : 8;
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  unsigned char	   bit_number : 4;
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  unsigned char	   condition : 3;
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  unsigned char	   use_es : 1;
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} RL78_Opcode_Operand;
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/* PSW flag bits */
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#define RL78_PSW_IE	0x80
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#define RL78_PSW_Z	0x40
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#define RL78_PSW_RBS1	0x20
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#define RL78_PSW_AC	0x10
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#define	RL78_PSW_RBS0	0x08
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#define	RL78_PSW_ISP1	0x04
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#define	RL78_PSW_ISP0	0x02
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#define RL78_PSW_CY	0x01
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#define	RL78_SFR_SP	0xffff8
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#define	RL78_SFR_PSW	0xffffa
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#define	RL78_SFR_CS	0xffffc
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#define	RL78_SFR_ES	0xffffd
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#define	RL78_SFR_PMC	0xffffe
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#define	RL78_SFR_MEM	0xfffff
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typedef struct
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{
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  int lineno;
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  RL78_Opcode_ID	id:24;
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  unsigned		flags:8; /* PSW mask, for side effects only */
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  int			n_bytes;
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  char *		syntax;
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  RL78_Size		size;
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  /* By convention, these are destination, source.  */
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  RL78_Opcode_Operand	op[2];
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} RL78_Opcode_Decoded;
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int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa);
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#ifdef __cplusplus
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}
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#endif
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#endif