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5191 | serge | 1 | /* Opcode decoder for the Renesas RL78 |
6324 | serge | 2 | Copyright (C) 2011-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Written by DJ Delorie |
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5 | This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. |
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6 | |||
7 | This program is free software; you can redistribute it and/or modify |
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8 | it under the terms of the GNU General Public License as published by |
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9 | the Free Software Foundation; either version 3 of the License, or |
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10 | (at your option) any later version. |
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11 | |||
12 | This program is distributed in the hope that it will be useful, |
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13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this program; if not, write to the Free Software |
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19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
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20 | 02110-1301, USA. */ |
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21 | |||
22 | /* The RL78 decoder in libopcodes is used by the simulator, gdb's |
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23 | analyzer, and the disassembler. Given an opcode data source, it |
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24 | decodes the next opcode into the following structures. */ |
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25 | |||
26 | #ifndef RL78_OPCODES_H_INCLUDED |
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27 | #define RL78_OPCODES_H_INCLUDED |
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28 | |||
6324 | serge | 29 | #ifdef __cplusplus |
30 | extern "C" { |
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31 | #endif |
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32 | |||
33 | typedef enum { |
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34 | RL78_ISA_DEFAULT, |
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35 | RL78_ISA_G10, |
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36 | RL78_ISA_G13, |
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37 | RL78_ISA_G14, |
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38 | } RL78_Dis_Isa; |
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39 | |||
5191 | serge | 40 | /* For the purposes of these structures, the RL78 registers are as |
41 | follows, despite most of these being memory-mapped and |
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42 | bank-switched: */ |
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43 | typedef enum { |
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44 | RL78_Reg_None, |
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45 | /* The order of these matches the encodings. */ |
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46 | RL78_Reg_X, |
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47 | RL78_Reg_A, |
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48 | RL78_Reg_C, |
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49 | RL78_Reg_B, |
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50 | RL78_Reg_E, |
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51 | RL78_Reg_D, |
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52 | RL78_Reg_L, |
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53 | RL78_Reg_H, |
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54 | /* The order of these matches the encodings. */ |
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55 | RL78_Reg_AX, |
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56 | RL78_Reg_BC, |
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57 | RL78_Reg_DE, |
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58 | RL78_Reg_HL, |
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59 | /* Unordered. */ |
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60 | RL78_Reg_SP, |
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61 | RL78_Reg_PSW, |
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62 | RL78_Reg_CS, |
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63 | RL78_Reg_ES, |
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64 | RL78_Reg_PMC, |
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65 | RL78_Reg_MEM |
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66 | } RL78_Register; |
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67 | |||
68 | typedef enum |
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69 | { |
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70 | RL78_Byte = 0, |
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71 | RL78_Word |
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72 | } RL78_Size; |
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73 | |||
74 | typedef enum { |
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75 | RL78_Condition_T, |
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76 | RL78_Condition_F, |
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77 | RL78_Condition_C, |
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78 | RL78_Condition_NC, |
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79 | RL78_Condition_H, |
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80 | RL78_Condition_NH, |
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81 | RL78_Condition_Z, |
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82 | RL78_Condition_NZ |
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83 | } RL78_Condition; |
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84 | |||
85 | typedef enum { |
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86 | RL78_Operand_None = 0, |
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87 | RL78_Operand_Immediate, /* #addend */ |
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88 | RL78_Operand_Register, /* reg */ |
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89 | RL78_Operand_Indirect, /* [reg + reg2 + addend] */ |
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90 | RL78_Operand_Bit, /* reg.bit */ |
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91 | RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */ |
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92 | RL78_Operand_PreDec, /* [--reg] = push */ |
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93 | RL78_Operand_PostInc /* [reg++] = pop */ |
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94 | } RL78_Operand_Type; |
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95 | |||
96 | typedef enum |
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97 | { |
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98 | RLO_unknown, |
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99 | RLO_add, /* d += s */ |
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100 | RLO_addc, /* d += s + CY */ |
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101 | RLO_and, /* d &= s (byte, word, bit) */ |
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102 | RLO_branch, /* pc = d */ |
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103 | RLO_branch_cond, /* pc = d if cond(src) */ |
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104 | RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */ |
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105 | RLO_break, /* BRK */ |
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106 | RLO_call, /* call */ |
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107 | RLO_cmp, /* cmp d, s */ |
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108 | RLO_divhu, /* DIVHU */ |
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109 | RLO_divwu, /* DIVWU */ |
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110 | RLO_halt, /* HALT */ |
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111 | RLO_mov, /* d = s */ |
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112 | RLO_mach, /* MACH */ |
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113 | RLO_machu, /* MACHU */ |
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114 | RLO_mulu, /* MULU */ |
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115 | RLO_mulh, /* MULH */ |
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116 | RLO_mulhu, /* MULHU */ |
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117 | RLO_nop, /* NOP */ |
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118 | RLO_or, /* d |= s */ |
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119 | RLO_ret, /* RET */ |
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120 | RLO_reti, /* RETI */ |
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121 | RLO_rol, /* d <<= s, MSB to LSB and CY */ |
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122 | RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */ |
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123 | RLO_ror, /* d >>= s, LSB to MSB and CY */ |
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124 | RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */ |
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125 | RLO_sar, /* d >>= s, signed */ |
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126 | RLO_sel, /* rb = s */ |
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127 | RLO_shr, /* d >>= s, unsigned */ |
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128 | RLO_shl, /* d <<= s */ |
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129 | RLO_skip, /* skip next insn is cond(s) */ |
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130 | RLO_stop, /* STOP */ |
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131 | RLO_sub, /* d -= s */ |
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132 | RLO_subc, /* d -= s - CY */ |
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133 | RLO_xch, /* swap d, s */ |
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134 | RLO_xor, /* d ^= s */ |
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135 | } RL78_Opcode_ID; |
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136 | |||
137 | typedef struct { |
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138 | RL78_Operand_Type type; |
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139 | int addend; |
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140 | RL78_Register reg : 8; |
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141 | RL78_Register reg2 : 8; |
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142 | unsigned char bit_number : 4; |
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143 | unsigned char condition : 3; |
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144 | unsigned char use_es : 1; |
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145 | } RL78_Opcode_Operand; |
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146 | |||
147 | /* PSW flag bits */ |
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148 | #define RL78_PSW_IE 0x80 |
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149 | #define RL78_PSW_Z 0x40 |
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150 | #define RL78_PSW_RBS1 0x20 |
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151 | #define RL78_PSW_AC 0x10 |
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152 | #define RL78_PSW_RBS0 0x08 |
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153 | #define RL78_PSW_ISP1 0x04 |
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154 | #define RL78_PSW_ISP0 0x02 |
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155 | #define RL78_PSW_CY 0x01 |
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156 | |||
157 | #define RL78_SFR_SP 0xffff8 |
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158 | #define RL78_SFR_PSW 0xffffa |
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159 | #define RL78_SFR_CS 0xffffc |
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160 | #define RL78_SFR_ES 0xffffd |
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161 | #define RL78_SFR_PMC 0xffffe |
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162 | #define RL78_SFR_MEM 0xfffff |
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163 | |||
164 | typedef struct |
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165 | { |
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166 | int lineno; |
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167 | RL78_Opcode_ID id:24; |
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168 | unsigned flags:8; /* PSW mask, for side effects only */ |
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169 | int n_bytes; |
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170 | char * syntax; |
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171 | RL78_Size size; |
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172 | /* By convention, these are destination, source. */ |
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173 | RL78_Opcode_Operand op[2]; |
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174 | } RL78_Opcode_Decoded; |
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175 | |||
6324 | serge | 176 | int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa); |
5191 | serge | 177 | |
6324 | serge | 178 | #ifdef __cplusplus |
179 | } |
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5191 | serge | 180 | #endif |
6324 | serge | 181 | |
182 | #endif=><=>=><=>=><=> |