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5191 | serge | 1 | /* ppc.h -- Header file for PowerPC opcode table |
6324 | serge | 2 | Copyright (C) 1994-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Written by Ian Lance Taylor, Cygnus Support |
4 | |||
5 | This file is part of GDB, GAS, and the GNU binutils. |
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6 | |||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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8 | them and/or modify them under the terms of the GNU General Public |
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9 | License as published by the Free Software Foundation; either version 3, |
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10 | or (at your option) any later version. |
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11 | |||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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15 | the GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this file; see the file COPYING3. If not, write to the Free |
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19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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20 | MA 02110-1301, USA. */ |
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21 | |||
22 | #ifndef PPC_H |
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23 | #define PPC_H |
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24 | |||
25 | #include "bfd_stdint.h" |
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26 | |||
27 | typedef uint64_t ppc_cpu_t; |
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28 | |||
29 | /* The opcode table is an array of struct powerpc_opcode. */ |
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30 | |||
31 | struct powerpc_opcode |
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32 | { |
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33 | /* The opcode name. */ |
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34 | const char *name; |
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35 | |||
36 | /* The opcode itself. Those bits which will be filled in with |
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37 | operands are zeroes. */ |
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38 | unsigned long opcode; |
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39 | |||
40 | /* The opcode mask. This is used by the disassembler. This is a |
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41 | mask containing ones indicating those bits which must match the |
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42 | opcode field, and zeroes indicating those bits which need not |
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43 | match (and are presumably filled in by operands). */ |
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44 | unsigned long mask; |
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45 | |||
46 | /* One bit flags for the opcode. These are used to indicate which |
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47 | specific processors support the instructions. The defined values |
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48 | are listed below. */ |
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49 | ppc_cpu_t flags; |
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50 | |||
51 | /* One bit flags for the opcode. These are used to indicate which |
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52 | specific processors no longer support the instructions. The defined |
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53 | values are listed below. */ |
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54 | ppc_cpu_t deprecated; |
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55 | |||
56 | /* An array of operand codes. Each code is an index into the |
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57 | operand table. They appear in the order which the operands must |
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58 | appear in assembly code, and are terminated by a zero. */ |
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59 | unsigned char operands[8]; |
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60 | }; |
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61 | |||
62 | /* The table itself is sorted by major opcode number, and is otherwise |
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63 | in the order in which the disassembler should consider |
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64 | instructions. */ |
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65 | extern const struct powerpc_opcode powerpc_opcodes[]; |
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66 | extern const int powerpc_num_opcodes; |
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67 | extern const struct powerpc_opcode vle_opcodes[]; |
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68 | extern const int vle_num_opcodes; |
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69 | |||
70 | /* Values defined for the flags field of a struct powerpc_opcode. */ |
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71 | |||
72 | /* Opcode is defined for the PowerPC architecture. */ |
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73 | #define PPC_OPCODE_PPC 1 |
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74 | |||
75 | /* Opcode is defined for the POWER (RS/6000) architecture. */ |
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76 | #define PPC_OPCODE_POWER 2 |
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77 | |||
78 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ |
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79 | #define PPC_OPCODE_POWER2 4 |
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80 | |||
81 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
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82 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, |
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83 | but it also supports many additional POWER instructions. */ |
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84 | #define PPC_OPCODE_601 8 |
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85 | |||
86 | /* Opcode is supported in both the Power and PowerPC architectures |
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87 | (ie, compiler's -mcpu=common or assembler's -mcom). More than just |
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88 | the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER |
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89 | and PPC_OPCODE_POWER2 because many instructions changed mnemonics |
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90 | between POWER and POWERPC. */ |
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91 | #define PPC_OPCODE_COMMON 0x10 |
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92 | |||
93 | /* Opcode is supported for any Power or PowerPC platform (this is |
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94 | for the assembler's -many option, and it eliminates duplicates). */ |
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95 | #define PPC_OPCODE_ANY 0x20 |
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96 | |||
97 | /* Opcode is only defined on 64 bit architectures. */ |
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98 | #define PPC_OPCODE_64 0x40 |
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99 | |||
100 | /* Opcode is supported as part of the 64-bit bridge. */ |
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101 | #define PPC_OPCODE_64_BRIDGE 0x80 |
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102 | |||
103 | /* Opcode is supported by Altivec Vector Unit */ |
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104 | #define PPC_OPCODE_ALTIVEC 0x100 |
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105 | |||
106 | /* Opcode is supported by PowerPC 403 processor. */ |
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107 | #define PPC_OPCODE_403 0x200 |
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108 | |||
109 | /* Opcode is supported by PowerPC BookE processor. */ |
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110 | #define PPC_OPCODE_BOOKE 0x400 |
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111 | |||
112 | /* Opcode is supported by PowerPC 440 processor. */ |
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113 | #define PPC_OPCODE_440 0x800 |
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114 | |||
115 | /* Opcode is only supported by Power4 architecture. */ |
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116 | #define PPC_OPCODE_POWER4 0x1000 |
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117 | |||
118 | /* Opcode is only supported by Power7 architecture. */ |
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119 | #define PPC_OPCODE_POWER7 0x2000 |
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120 | |||
121 | /* Opcode is only supported by e500x2 Core. */ |
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122 | #define PPC_OPCODE_SPE 0x4000 |
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123 | |||
124 | /* Opcode is supported by e500x2 Integer select APU. */ |
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125 | #define PPC_OPCODE_ISEL 0x8000 |
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126 | |||
127 | /* Opcode is an e500 SPE floating point instruction. */ |
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128 | #define PPC_OPCODE_EFS 0x10000 |
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129 | |||
130 | /* Opcode is supported by branch locking APU. */ |
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131 | #define PPC_OPCODE_BRLOCK 0x20000 |
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132 | |||
133 | /* Opcode is supported by performance monitor APU. */ |
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134 | #define PPC_OPCODE_PMR 0x40000 |
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135 | |||
136 | /* Opcode is supported by cache locking APU. */ |
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137 | #define PPC_OPCODE_CACHELCK 0x80000 |
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138 | |||
139 | /* Opcode is supported by machine check APU. */ |
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140 | #define PPC_OPCODE_RFMCI 0x100000 |
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141 | |||
142 | /* Opcode is only supported by Power5 architecture. */ |
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143 | #define PPC_OPCODE_POWER5 0x200000 |
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144 | |||
145 | /* Opcode is supported by PowerPC e300 family. */ |
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146 | #define PPC_OPCODE_E300 0x400000 |
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147 | |||
148 | /* Opcode is only supported by Power6 architecture. */ |
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149 | #define PPC_OPCODE_POWER6 0x800000 |
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150 | |||
151 | /* Opcode is only supported by PowerPC Cell family. */ |
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152 | #define PPC_OPCODE_CELL 0x1000000 |
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153 | |||
154 | /* Opcode is supported by CPUs with paired singles support. */ |
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155 | #define PPC_OPCODE_PPCPS 0x2000000 |
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156 | |||
157 | /* Opcode is supported by Power E500MC */ |
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158 | #define PPC_OPCODE_E500MC 0x4000000 |
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159 | |||
160 | /* Opcode is supported by PowerPC 405 processor. */ |
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161 | #define PPC_OPCODE_405 0x8000000 |
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162 | |||
163 | /* Opcode is supported by Vector-Scalar (VSX) Unit */ |
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164 | #define PPC_OPCODE_VSX 0x10000000 |
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165 | |||
166 | /* Opcode is supported by A2. */ |
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167 | #define PPC_OPCODE_A2 0x20000000 |
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168 | |||
169 | /* Opcode is supported by PowerPC 476 processor. */ |
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170 | #define PPC_OPCODE_476 0x40000000 |
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171 | |||
172 | /* Opcode is supported by AppliedMicro Titan core */ |
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173 | #define PPC_OPCODE_TITAN 0x80000000 |
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174 | |||
175 | /* Opcode which is supported by the e500 family */ |
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176 | #define PPC_OPCODE_E500 0x100000000ull |
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177 | |||
178 | /* Opcode is supported by Extended Altivec Vector Unit */ |
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179 | #define PPC_OPCODE_ALTIVEC2 0x200000000ull |
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180 | |||
181 | /* Opcode is supported by Power E6500 */ |
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182 | #define PPC_OPCODE_E6500 0x400000000ull |
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183 | |||
184 | /* Opcode is supported by Thread management APU */ |
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185 | #define PPC_OPCODE_TMR 0x800000000ull |
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186 | |||
187 | /* Opcode which is supported by the VLE extension. */ |
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188 | #define PPC_OPCODE_VLE 0x1000000000ull |
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189 | |||
190 | /* Opcode is only supported by Power8 architecture. */ |
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191 | #define PPC_OPCODE_POWER8 0x2000000000ull |
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192 | |||
193 | /* Opcode which is supported by the Hardware Transactional Memory extension. */ |
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194 | /* Currently, this is the same as the POWER8 mask. If another cpu comes out |
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195 | that isn't a superset of POWER8, we can define this to its own mask. */ |
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196 | #define PPC_OPCODE_HTM PPC_OPCODE_POWER8 |
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197 | |||
6324 | serge | 198 | /* Opcode is supported by ppc750cl. */ |
199 | #define PPC_OPCODE_750 0x4000000000ull |
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200 | |||
201 | /* Opcode is supported by ppc7450. */ |
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202 | #define PPC_OPCODE_7450 0x8000000000ull |
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203 | |||
204 | /* Opcode is supported by ppc821/850/860. */ |
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205 | #define PPC_OPCODE_860 0x10000000000ull |
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206 | |||
207 | /* Opcode is only supported by Power9 architecture. */ |
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208 | #define PPC_OPCODE_POWER9 0x20000000000ull |
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209 | |||
210 | /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */ |
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211 | #define PPC_OPCODE_VSX3 0x40000000000ull |
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212 | |||
5191 | serge | 213 | /* A macro to extract the major opcode from an instruction. */ |
214 | #define PPC_OP(i) (((i) >> 26) & 0x3f) |
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215 | |||
216 | /* A macro to determine if the instruction is a 2-byte VLE insn. */ |
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217 | #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) |
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218 | |||
219 | /* A macro to extract the major opcode from a VLE instruction. */ |
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220 | #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) |
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221 | |||
222 | /* A macro to convert a VLE opcode to a VLE opcode segment. */ |
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223 | #define VLE_OP_TO_SEG(i) ((i) >> 1) |
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224 | |||
225 | /* The operands table is an array of struct powerpc_operand. */ |
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226 | |||
227 | struct powerpc_operand |
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228 | { |
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229 | /* A bitmask of bits in the operand. */ |
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230 | unsigned int bitm; |
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231 | |||
232 | /* The shift operation to be applied to the operand. No shift |
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233 | is made if this is zero. For positive values, the operand |
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234 | is shifted left by SHIFT. For negative values, the operand |
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235 | is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate |
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236 | that BITM and SHIFT cannot be used to determine where the |
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237 | operand goes in the insn. */ |
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238 | int shift; |
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239 | |||
240 | /* Insertion function. This is used by the assembler. To insert an |
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241 | operand value into an instruction, check this field. |
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242 | |||
243 | If it is NULL, execute |
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244 | if (o->shift >= 0) |
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245 | i |= (op & o->bitm) << o->shift; |
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246 | else |
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247 | i |= (op & o->bitm) >> -o->shift; |
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248 | (i is the instruction which we are filling in, o is a pointer to |
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249 | this structure, and op is the operand value). |
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250 | |||
251 | If this field is not NULL, then simply call it with the |
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252 | instruction and the operand value. It will return the new value |
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253 | of the instruction. If the ERRMSG argument is not NULL, then if |
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254 | the operand value is illegal, *ERRMSG will be set to a warning |
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255 | string (the operand will be inserted in any case). If the |
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256 | operand value is legal, *ERRMSG will be unchanged (most operands |
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257 | can accept any value). */ |
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258 | unsigned long (*insert) |
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259 | (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); |
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260 | |||
261 | /* Extraction function. This is used by the disassembler. To |
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262 | extract this operand type from an instruction, check this field. |
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263 | |||
264 | If it is NULL, compute |
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265 | if (o->shift >= 0) |
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266 | op = (i >> o->shift) & o->bitm; |
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267 | else |
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268 | op = (i << -o->shift) & o->bitm; |
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269 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
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270 | sign_extend (op); |
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271 | (i is the instruction, o is a pointer to this structure, and op |
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272 | is the result). |
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273 | |||
274 | If this field is not NULL, then simply call it with the |
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275 | instruction value. It will return the value of the operand. If |
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276 | the INVALID argument is not NULL, *INVALID will be set to |
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277 | non-zero if this operand type can not actually be extracted from |
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278 | this operand (i.e., the instruction does not match). If the |
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279 | operand is valid, *INVALID will not be changed. */ |
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280 | long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); |
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281 | |||
282 | /* One bit syntax flags. */ |
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283 | unsigned long flags; |
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284 | }; |
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285 | |||
286 | /* Elements in the table are retrieved by indexing with values from |
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287 | the operands field of the powerpc_opcodes table. */ |
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288 | |||
289 | extern const struct powerpc_operand powerpc_operands[]; |
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290 | extern const unsigned int num_powerpc_operands; |
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291 | |||
292 | /* Use with the shift field of a struct powerpc_operand to indicate |
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293 | that BITM and SHIFT cannot be used to determine where the operand |
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294 | goes in the insn. */ |
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6324 | serge | 295 | #define PPC_OPSHIFT_INV (-1U << 31) |
5191 | serge | 296 | |
297 | /* Values defined for the flags field of a struct powerpc_operand. */ |
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298 | |||
299 | /* This operand takes signed values. */ |
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300 | #define PPC_OPERAND_SIGNED (0x1) |
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301 | |||
302 | /* This operand takes signed values, but also accepts a full positive |
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303 | range of values when running in 32 bit mode. That is, if bits is |
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304 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, |
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305 | this flag is ignored. */ |
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306 | #define PPC_OPERAND_SIGNOPT (0x2) |
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307 | |||
308 | /* This operand does not actually exist in the assembler input. This |
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309 | is used to support extended mnemonics such as mr, for which two |
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310 | operands fields are identical. The assembler should call the |
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311 | insert function with any op value. The disassembler should call |
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312 | the extract function, ignore the return value, and check the value |
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313 | placed in the valid argument. */ |
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314 | #define PPC_OPERAND_FAKE (0x4) |
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315 | |||
316 | /* The next operand should be wrapped in parentheses rather than |
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317 | separated from this one by a comma. This is used for the load and |
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318 | store instructions which want their operands to look like |
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319 | reg,displacement(reg) |
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320 | */ |
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321 | #define PPC_OPERAND_PARENS (0x8) |
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322 | |||
323 | /* This operand may use the symbolic names for the CR fields, which |
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324 | are |
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325 | lt 0 gt 1 eq 2 so 3 un 3 |
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326 | cr0 0 cr1 1 cr2 2 cr3 3 |
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327 | cr4 4 cr5 5 cr6 6 cr7 7 |
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328 | These may be combined arithmetically, as in cr2*4+gt. These are |
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329 | only supported on the PowerPC, not the POWER. */ |
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330 | #define PPC_OPERAND_CR_BIT (0x10) |
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331 | |||
332 | /* This operand names a register. The disassembler uses this to print |
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333 | register names with a leading 'r'. */ |
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334 | #define PPC_OPERAND_GPR (0x20) |
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335 | |||
336 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
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337 | #define PPC_OPERAND_GPR_0 (0x40) |
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338 | |||
339 | /* This operand names a floating point register. The disassembler |
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340 | prints these with a leading 'f'. */ |
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341 | #define PPC_OPERAND_FPR (0x80) |
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342 | |||
343 | /* This operand is a relative branch displacement. The disassembler |
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344 | prints these symbolically if possible. */ |
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345 | #define PPC_OPERAND_RELATIVE (0x100) |
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346 | |||
347 | /* This operand is an absolute branch address. The disassembler |
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348 | prints these symbolically if possible. */ |
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349 | #define PPC_OPERAND_ABSOLUTE (0x200) |
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350 | |||
351 | /* This operand is optional, and is zero if omitted. This is used for |
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352 | example, in the optional BF field in the comparison instructions. The |
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353 | assembler must count the number of operands remaining on the line, |
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354 | and the number of operands remaining for the opcode, and decide |
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355 | whether this operand is present or not. The disassembler should |
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356 | print this operand out only if it is not zero. */ |
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357 | #define PPC_OPERAND_OPTIONAL (0x400) |
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358 | |||
359 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
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360 | is omitted, then for the next operand use this operand value plus |
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361 | 1, ignoring the next operand field for the opcode. This wretched |
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362 | hack is needed because the Power rotate instructions can take |
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363 | either 4 or 5 operands. The disassembler should print this operand |
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364 | out regardless of the PPC_OPERAND_OPTIONAL field. */ |
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365 | #define PPC_OPERAND_NEXT (0x800) |
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366 | |||
367 | /* This operand should be regarded as a negative number for the |
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368 | purposes of overflow checking (i.e., the normal most negative |
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369 | number is disallowed and one more than the normal most positive |
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370 | number is allowed). This flag will only be set for a signed |
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371 | operand. */ |
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372 | #define PPC_OPERAND_NEGATIVE (0x1000) |
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373 | |||
374 | /* This operand names a vector unit register. The disassembler |
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375 | prints these with a leading 'v'. */ |
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376 | #define PPC_OPERAND_VR (0x2000) |
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377 | |||
378 | /* This operand is for the DS field in a DS form instruction. */ |
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379 | #define PPC_OPERAND_DS (0x4000) |
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380 | |||
381 | /* This operand is for the DQ field in a DQ form instruction. */ |
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382 | #define PPC_OPERAND_DQ (0x8000) |
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383 | |||
384 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
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385 | #define PPC_OPERAND_PLUS1 (0x10000) |
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386 | |||
387 | /* Xilinx APU and FSL related operands */ |
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388 | #define PPC_OPERAND_FSL (0x20000) |
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389 | #define PPC_OPERAND_FCR (0x40000) |
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390 | #define PPC_OPERAND_UDI (0x80000) |
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391 | |||
392 | /* This operand names a vector-scalar unit register. The disassembler |
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393 | prints these with a leading 'vs'. */ |
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394 | #define PPC_OPERAND_VSR (0x100000) |
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395 | |||
396 | /* This is a CR FIELD that does not use symbolic names. */ |
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397 | #define PPC_OPERAND_CR_REG (0x200000) |
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6324 | serge | 398 | |
399 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
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400 | is omitted, then the value it should use for the operand is stored |
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401 | in the SHIFT field of the immediatly following operand field. */ |
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402 | #define PPC_OPERAND_OPTIONAL_VALUE (0x400000) |
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5191 | serge | 403 | |
404 | /* The POWER and PowerPC assemblers use a few macros. We keep them |
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405 | with the operands table for simplicity. The macro table is an |
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406 | array of struct powerpc_macro. */ |
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407 | |||
408 | struct powerpc_macro |
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409 | { |
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410 | /* The macro name. */ |
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411 | const char *name; |
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412 | |||
413 | /* The number of operands the macro takes. */ |
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414 | unsigned int operands; |
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415 | |||
416 | /* One bit flags for the opcode. These are used to indicate which |
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417 | specific processors support the instructions. The values are the |
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418 | same as those for the struct powerpc_opcode flags field. */ |
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419 | ppc_cpu_t flags; |
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420 | |||
421 | /* A format string to turn the macro into a normal instruction. |
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422 | Each %N in the string is replaced with operand number N (zero |
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423 | based). */ |
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424 | const char *format; |
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425 | }; |
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426 | |||
427 | extern const struct powerpc_macro powerpc_macros[]; |
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428 | extern const int powerpc_num_macros; |
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429 | |||
430 | extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
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431 | |||
6324 | serge | 432 | static inline long |
433 | ppc_optional_operand_value (const struct powerpc_operand *operand) |
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434 | { |
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435 | if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) |
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436 | return (operand+1)->shift; |
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437 | return 0; |
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438 | } |
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439 | |||
5191 | serge | 440 | #endif /* PPC_H */><>><>><>=>=> |