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5191 | serge | 1 | /* d10v.h -- Header file for D10V opcode table |
6324 | serge | 2 | Copyright (C) 1996-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Written by Martin Hunt (hunt@cygnus.com), Cygnus Support |
4 | |||
5 | This file is part of GDB, GAS, and the GNU binutils. |
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6 | |||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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8 | them and/or modify them under the terms of the GNU General Public |
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9 | License as published by the Free Software Foundation; either version 3, |
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10 | or (at your option) any later version. |
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11 | |||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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15 | the GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this file; see the file COPYING3. If not, write to the Free |
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19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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20 | MA 02110-1301, USA. */ |
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21 | |||
22 | #ifndef D10V_H |
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23 | #define D10V_H |
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24 | |||
25 | /* Format Specifier */ |
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26 | #define FM00 0 |
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27 | #define FM01 0x40000000 |
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28 | #define FM10 0x80000000 |
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29 | #define FM11 0xC0000000 |
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30 | |||
31 | #define NOP 0x5e00 |
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32 | #define OPCODE_DIVS 0x14002800 |
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33 | |||
34 | /* The opcode table is an array of struct d10v_opcode. */ |
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35 | |||
36 | struct d10v_opcode |
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37 | { |
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38 | /* The opcode name. */ |
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39 | const char *name; |
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40 | |||
41 | /* the opcode format */ |
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42 | int format; |
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43 | |||
44 | /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ |
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45 | #define SHORT_OPCODE 1 |
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46 | #define LONG_OPCODE 8 |
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47 | #define SHORT_2 1 /* short with 2 operands */ |
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48 | #define SHORT_B 3 /* short with 8-bit branch */ |
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49 | #define LONG_B 8 /* long with 16-bit branch */ |
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50 | #define LONG_L 10 /* long with 3 operands */ |
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51 | #define LONG_R 12 /* reserved */ |
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52 | |||
53 | /* just a placeholder for variable-length instructions */ |
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54 | /* for example, "bra" will be a fake for "bra.s" and bra.l" */ |
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55 | /* which will immediately follow in the opcode table. */ |
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56 | #define OPCODE_FAKE 32 |
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57 | |||
58 | /* the number of cycles */ |
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59 | int cycles; |
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60 | |||
61 | /* the execution unit(s) used */ |
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62 | int unit; |
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63 | #define EITHER 0 |
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64 | #define IU 1 |
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65 | #define MU 2 |
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66 | #define BOTH 3 |
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67 | |||
68 | /* execution type; parallel or sequential */ |
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69 | /* this field is used to decide if two instructions */ |
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70 | /* can be executed in parallel */ |
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71 | int exec_type; |
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72 | #define PARONLY 1 /* parallel only */ |
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73 | #define SEQ 2 /* must be sequential */ |
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74 | #define PAR 4 /* may be parallel */ |
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75 | #define BRANCH_LINK 8 /* subroutine call. must be aligned */ |
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76 | #define RMEM 16 /* reads memory */ |
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77 | #define WMEM 32 /* writes memory */ |
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78 | #define RF0 64 /* reads f0 */ |
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79 | #define WF0 128 /* modifies f0 */ |
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80 | #define WCAR 256 /* write Carry */ |
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81 | #define BRANCH 512 /* branch, no link */ |
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82 | #define ALONE 1024 /* short but pack with a NOP if on asm line alone */ |
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83 | |||
84 | /* the opcode */ |
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85 | long opcode; |
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86 | |||
87 | /* mask. if( (i & mask) == opcode ) then match */ |
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88 | long mask; |
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89 | |||
90 | /* An array of operand codes. Each code is an index into the |
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91 | operand table. They appear in the order which the operands must |
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92 | appear in assembly code, and are terminated by a zero. */ |
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93 | unsigned char operands[6]; |
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94 | }; |
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95 | |||
96 | /* The table itself is sorted by major opcode number, and is otherwise |
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97 | in the order in which the disassembler should consider |
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98 | instructions. */ |
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99 | extern const struct d10v_opcode d10v_opcodes[]; |
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100 | extern const int d10v_num_opcodes; |
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101 | |||
102 | /* The operands table is an array of struct d10v_operand. */ |
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103 | struct d10v_operand |
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104 | { |
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105 | /* The number of bits in the operand. */ |
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106 | int bits; |
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107 | |||
108 | /* How far the operand is left shifted in the instruction. */ |
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109 | int shift; |
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110 | |||
111 | /* One bit syntax flags. */ |
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112 | int flags; |
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113 | }; |
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114 | |||
115 | /* Elements in the table are retrieved by indexing with values from |
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116 | the operands field of the d10v_opcodes table. */ |
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117 | |||
118 | extern const struct d10v_operand d10v_operands[]; |
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119 | |||
120 | /* Values defined for the flags field of a struct d10v_operand. */ |
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121 | |||
122 | /* the operand must be an even number */ |
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123 | #define OPERAND_EVEN (1) |
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124 | |||
125 | /* the operand must be an odd number */ |
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126 | #define OPERAND_ODD (2) |
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127 | |||
128 | /* this is the destination register; it will be modified */ |
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129 | /* this is used by the optimizer */ |
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130 | #define OPERAND_DEST (4) |
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131 | |||
132 | /* number or symbol */ |
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133 | #define OPERAND_NUM (8) |
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134 | |||
135 | /* address or label */ |
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136 | #define OPERAND_ADDR (0x10) |
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137 | |||
138 | /* register */ |
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139 | #define OPERAND_REG (0x20) |
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140 | |||
141 | /* postincrement + */ |
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142 | #define OPERAND_PLUS (0x40) |
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143 | |||
144 | /* postdecrement - */ |
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145 | #define OPERAND_MINUS (0x80) |
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146 | |||
147 | /* @ */ |
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148 | #define OPERAND_ATSIGN (0x100) |
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149 | |||
150 | /* @( */ |
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151 | #define OPERAND_ATPAR (0x200) |
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152 | |||
153 | /* accumulator 0 */ |
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154 | #define OPERAND_ACC0 (0x400) |
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155 | |||
156 | /* accumulator 1 */ |
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157 | #define OPERAND_ACC1 (0x800) |
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158 | |||
159 | /* f0 / f1 flag register */ |
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160 | #define OPERAND_FFLAG (0x1000) |
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161 | |||
162 | /* c flag register */ |
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163 | #define OPERAND_CFLAG (0x2000) |
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164 | |||
165 | /* control register */ |
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166 | #define OPERAND_CONTROL (0x4000) |
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167 | |||
168 | /* predecrement mode '@-sp' */ |
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169 | #define OPERAND_ATMINUS (0x8000) |
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170 | |||
171 | /* signed number */ |
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172 | #define OPERAND_SIGNED (0x10000) |
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173 | |||
174 | /* special accumulator shifts need a 4-bit number */ |
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175 | /* 1 <= x <= 16 */ |
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176 | #define OPERAND_SHIFT (0x20000) |
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177 | |||
178 | /* general purpose register */ |
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179 | #define OPERAND_GPR (0x40000) |
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180 | |||
181 | /* special imm3 values with range restricted to -2 <= imm3 <= 3 */ |
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182 | /* needed for rac/rachi */ |
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183 | #define RESTRICTED_NUM3 (0x80000) |
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184 | |||
185 | /* Pre-decrement is only supported for SP. */ |
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186 | #define OPERAND_SP (0x100000) |
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187 | |||
188 | /* Post-decrement is not supported for SP. Like OPERAND_EVEN, and |
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189 | unlike OPERAND_SP, this flag doesn't prevent the instruction from |
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190 | matching, it only fails validation later on. */ |
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191 | #define OPERAND_NOSP (0x200000) |
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192 | |||
193 | /* Structure to hold information about predefined registers. */ |
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194 | struct pd_reg |
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195 | { |
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196 | char *name; /* name to recognize */ |
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197 | char *pname; /* name to print for this register */ |
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198 | int value; |
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199 | }; |
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200 | |||
201 | extern const struct pd_reg d10v_predefined_registers[]; |
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202 | int d10v_reg_name_cnt (void); |
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203 | |||
204 | /* an expressionS only has one register type, so we fake it */ |
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205 | /* by setting high bits to indicate type */ |
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206 | #define REGISTER_MASK 0xFF |
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207 | |||
208 | #endif /* D10V_H */=>=>=>=> |